1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * Copyright (c) 1994 John S. Dyson 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91 37 * from: FreeBSD: src/sys/i386/include/vmparam.h,v 1.33 2000/03/30 38 * $FreeBSD$ 39 */ 40 41 #ifndef _MACHINE_VMPARAM_H_ 42 #define _MACHINE_VMPARAM_H_ 43 44 /* 45 * Virtual memory related constants, all in bytes 46 */ 47 #ifndef MAXTSIZ 48 #define MAXTSIZ (1*1024*1024*1024) /* max text size */ 49 #endif 50 #ifndef DFLDSIZ 51 #define DFLDSIZ (128*1024*1024) /* initial data size limit */ 52 #endif 53 #ifndef MAXDSIZ 54 #define MAXDSIZ (1*1024*1024*1024) /* max data size */ 55 #endif 56 #ifndef DFLSSIZ 57 #define DFLSSIZ (128*1024*1024) /* initial stack size limit */ 58 #endif 59 #ifndef MAXSSIZ 60 #define MAXSSIZ (1*1024*1024*1024) /* max stack size */ 61 #endif 62 #ifndef SGROWSIZ 63 #define SGROWSIZ (128*1024) /* amount to grow stack */ 64 #endif 65 66 /* 67 * The physical address space is sparsely populated. 68 */ 69 #define VM_PHYSSEG_SPARSE 70 71 /* 72 * The number of PHYSSEG entries must be one greater than the number 73 * of phys_avail entries because the phys_avail entry that spans the 74 * largest physical address that is accessible by ISA DMA is split 75 * into two PHYSSEG entries. 76 */ 77 #define VM_PHYSSEG_MAX 64 78 79 /* 80 * Create two free page pools: VM_FREEPOOL_DEFAULT is the default pool 81 * from which physical pages are allocated and VM_FREEPOOL_DIRECT is 82 * the pool from which physical pages for small UMA objects are 83 * allocated. 84 */ 85 #define VM_NFREEPOOL 2 86 #define VM_FREEPOOL_DEFAULT 0 87 #define VM_FREEPOOL_DIRECT 1 88 89 /* 90 * Create two free page lists: VM_FREELIST_DEFAULT is for physical 91 * pages that are above the largest physical address that is 92 * accessible by ISA DMA and VM_FREELIST_ISADMA is for physical pages 93 * that are below that address. 94 */ 95 #define VM_NFREELIST 2 96 #define VM_FREELIST_DEFAULT 0 97 #define VM_FREELIST_ISADMA 1 98 99 /* 100 * An allocation size of 16MB is supported in order to optimize the 101 * use of the direct map by UMA. Specifically, a cache line contains 102 * at most four TTEs, collectively mapping 16MB of physical memory. 103 * By reducing the number of distinct 16MB "pages" that are used by UMA, 104 * the physical memory allocator reduces the likelihood of both 4MB 105 * page TLB misses and cache misses caused by 4MB page TLB misses. 106 */ 107 #define VM_NFREEORDER 12 108 109 /* 110 * Enable superpage reservations: 1 level. 111 */ 112 #ifndef VM_NRESERVLEVEL 113 #define VM_NRESERVLEVEL 1 114 #endif 115 116 /* 117 * Level 0 reservations consist of 512 pages. 118 */ 119 #ifndef VM_LEVEL_0_ORDER 120 #define VM_LEVEL_0_ORDER 9 121 #endif 122 123 /** 124 * Address space layout. 125 * 126 * UltraSPARC I and II implement a 44 bit virtual address space. The address 127 * space is split into 2 regions at each end of the 64 bit address space, with 128 * an out of range "hole" in the middle. UltraSPARC III implements the full 129 * 64 bit virtual address space, but we don't really have any use for it and 130 * 43 bits of user address space is considered to be "enough", so we ignore it. 131 * 132 * Upper region: 0xffffffffffffffff 133 * 0xfffff80000000000 134 * 135 * Hole: 0xfffff7ffffffffff 136 * 0x0000080000000000 137 * 138 * Lower region: 0x000007ffffffffff 139 * 0x0000000000000000 140 * 141 * In general we ignore the upper region, and use the lower region as mappable 142 * space. 143 * 144 * We define some interesting address constants: 145 * 146 * VM_MIN_ADDRESS and VM_MAX_ADDRESS define the start and end of the entire 147 * 64 bit address space, mostly just for convenience. 148 * 149 * VM_MIN_DIRECT_ADDRESS and VM_MAX_DIRECT_ADDRESS define the start and end 150 * of the direct mapped region. This maps virtual addresses to physical 151 * addresses directly using 4mb tlb entries, with the physical address encoded 152 * in the lower 43 bits of virtual address. These mappings are convenient 153 * because they do not require page tables, and because they never change they 154 * do not require tlb flushes. However, since these mappings are cacheable, 155 * we must ensure that all pages accessed this way are either not double 156 * mapped, or that all other mappings have virtual color equal to physical 157 * color, in order to avoid creating illegal aliases in the data cache. 158 * 159 * VM_MIN_KERNEL_ADDRESS and VM_MAX_KERNEL_ADDRESS define the start and end of 160 * mappable kernel virtual address space. VM_MIN_KERNEL_ADDRESS is basically 161 * arbitrary, a convenient address is chosen which allows both the kernel text 162 * and data and the prom's address space to be mapped with 1 4mb tsb page. 163 * VM_MAX_KERNEL_ADDRESS is variable, computed at startup time based on the 164 * amount of physical memory available. Each 4mb tsb page provides 1g of 165 * virtual address space, with the only practical limit being available 166 * phsyical memory. 167 * 168 * VM_MIN_PROM_ADDRESS and VM_MAX_PROM_ADDRESS define the start and end of the 169 * prom address space. On startup the prom's mappings are duplicated in the 170 * kernel tsb, to allow prom memory to be accessed normally by the kernel. 171 * 172 * VM_MIN_USER_ADDRESS and VM_MAX_USER_ADDRESS define the start and end of the 173 * user address space. There are some hardware errata about using addresses 174 * at the boundary of the va hole, so we allow just under 43 bits of user 175 * address space. Note that the kernel and user address spaces overlap, but 176 * this doesn't matter because they use different tlb contexts, and because 177 * the kernel address space is not mapped into each process' address space. 178 */ 179 #define VM_MIN_ADDRESS (0x0000000000000000UL) 180 #define VM_MAX_ADDRESS (0xffffffffffffffffUL) 181 182 #define VM_MIN_DIRECT_ADDRESS (0xfffff80000000000UL) 183 #define VM_MAX_DIRECT_ADDRESS (VM_MAX_ADDRESS) 184 185 #define VM_MIN_KERNEL_ADDRESS (0x00000000c0000000UL) 186 #define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address) 187 188 #define VM_MIN_PROM_ADDRESS (0x00000000f0000000UL) 189 #define VM_MAX_PROM_ADDRESS (0x00000000ffffffffUL) 190 191 #define VM_MIN_USER_ADDRESS (0x0000000000000000UL) 192 #define VM_MAX_USER_ADDRESS (0x000007fe00000000UL) 193 194 #define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS) 195 #define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS) 196 197 #define KERNBASE (VM_MIN_KERNEL_ADDRESS) 198 #define PROMBASE (VM_MIN_PROM_ADDRESS) 199 #define USRSTACK (VM_MAX_USER_ADDRESS) 200 201 /* 202 * How many physical pages per kmem arena virtual page. 203 */ 204 #ifndef VM_KMEM_SIZE_SCALE 205 #define VM_KMEM_SIZE_SCALE (tsb_kernel_ldd_phys == 0 ? 3 : 2) 206 #endif 207 208 /* 209 * Optional floor (in bytes) on the size of the kmem arena. 210 */ 211 #ifndef VM_KMEM_SIZE_MIN 212 #define VM_KMEM_SIZE_MIN (16 * 1024 * 1024) 213 #endif 214 215 /* 216 * Optional ceiling (in bytes) on the size of the kmem arena: 60% of the 217 * kernel map. 218 */ 219 #ifndef VM_KMEM_SIZE_MAX 220 #define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \ 221 VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5) 222 #endif 223 224 /* 225 * Initial pagein size of beginning of executable file. 226 */ 227 #ifndef VM_INITIAL_PAGEIN 228 #define VM_INITIAL_PAGEIN 16 229 #endif 230 231 #define UMA_MD_SMALL_ALLOC 232 233 extern u_int tsb_kernel_ldd_phys; 234 extern vm_offset_t vm_max_kernel_address; 235 236 /* 237 * Older sparc64 machines have a virtually indexed L1 data cache of 16KB. 238 * Consequently, mapping the same physical page multiple times may have 239 * caching disabled. 240 */ 241 #define ZERO_REGION_SIZE PAGE_SIZE 242 243 #include <machine/tlb.h> 244 245 #define SFBUF 246 #define SFBUF_MAP 247 248 #define PMAP_HAS_DMAP dcache_color_ignore 249 #define PHYS_TO_DMAP(x) (TLB_PHYS_TO_DIRECT(x)) 250 251 #endif /* !_MACHINE_VMPARAM_H_ */ 252