1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <[email protected]> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/sockio.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/kobj.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #if defined(__i386__) || defined(__amd64__) 92 #include <sys/memdesc.h> 93 #include <machine/bus.h> 94 #include <machine/md_var.h> 95 #include <machine/specialreg.h> 96 #include <x86/include/busdma_impl.h> 97 #include <x86/iommu/busdma_dmar.h> 98 #endif 99 100 #include <sys/bitstring.h> 101 /* 102 * enable accounting of every mbuf as it comes in to and goes out of 103 * iflib's software descriptor references 104 */ 105 #define MEMORY_LOGGING 0 106 /* 107 * Enable mbuf vectors for compressing long mbuf chains 108 */ 109 110 /* 111 * NB: 112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 113 * we prefetch needs to be determined by the time spent in m_free vis a vis 114 * the cost of a prefetch. This will of course vary based on the workload: 115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 116 * is quite expensive, thus suggesting very little prefetch. 117 * - small packet forwarding which is just returning a single mbuf to 118 * UMA will typically be very fast vis a vis the cost of a memory 119 * access. 120 */ 121 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct mtx ifc_mtx; 167 168 uint16_t ifc_nhwtxqs; 169 uint16_t ifc_nhwrxqs; 170 171 iflib_txq_t ifc_txqs; 172 iflib_rxq_t ifc_rxqs; 173 uint32_t ifc_if_flags; 174 uint32_t ifc_flags; 175 uint32_t ifc_max_fl_buf_size; 176 int ifc_in_detach; 177 178 int ifc_link_state; 179 int ifc_link_irq; 180 int ifc_watchdog_events; 181 struct cdev *ifc_led_dev; 182 struct resource *ifc_msix_mem; 183 184 struct if_irq ifc_legacy_irq; 185 struct grouptask ifc_admin_task; 186 struct grouptask ifc_vflr_task; 187 struct iflib_filter_info ifc_filter_info; 188 struct ifmedia ifc_media; 189 190 struct sysctl_oid *ifc_sysctl_node; 191 uint16_t ifc_sysctl_ntxqs; 192 uint16_t ifc_sysctl_nrxqs; 193 uint16_t ifc_sysctl_qs_eq_override; 194 uint16_t ifc_sysctl_rx_budget; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 uint8_t ifc_mac[ETHER_ADDR_LEN]; 212 char ifc_mtx_name[16]; 213 }; 214 215 216 void * 217 iflib_get_softc(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_softc); 221 } 222 223 device_t 224 iflib_get_dev(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_dev); 228 } 229 230 if_t 231 iflib_get_ifp(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_ifp); 235 } 236 237 struct ifmedia * 238 iflib_get_media(if_ctx_t ctx) 239 { 240 241 return (&ctx->ifc_media); 242 } 243 244 void 245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 246 { 247 248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 249 } 250 251 if_softc_ctx_t 252 iflib_get_softc_ctx(if_ctx_t ctx) 253 { 254 255 return (&ctx->ifc_softc_ctx); 256 } 257 258 if_shared_ctx_t 259 iflib_get_sctx(if_ctx_t ctx) 260 { 261 262 return (ctx->ifc_sctx); 263 } 264 265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 268 269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 271 272 #define RX_SW_DESC_MAP_CREATED (1 << 0) 273 #define TX_SW_DESC_MAP_CREATED (1 << 1) 274 #define RX_SW_DESC_INUSE (1 << 3) 275 #define TX_SW_DESC_MAPPED (1 << 4) 276 277 #define M_TOOBIG M_PROTO1 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 uint8_t *ifsd_flags; 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 struct mbuf **ifsd_m; /* pkthdr mbufs */ 289 uint8_t *ifsd_flags; 290 } if_txsd_vec_t; 291 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 /* bnxt supports 64 with hardware LRO enabled */ 296 #define IFLIB_MAX_RX_SEGS 64 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define IFC_LEGACY 0x001 314 #define IFC_QFLUSH 0x002 315 #define IFC_MULTISEG 0x004 316 #define IFC_DMAR 0x008 317 #define IFC_SC_ALLOCATED 0x010 318 #define IFC_INIT_DONE 0x020 319 #define IFC_PREFETCH 0x040 320 #define IFC_DO_RESET 0x080 321 #define IFC_CHECK_HUNG 0x100 322 323 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 324 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 325 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 326 struct iflib_txq { 327 qidx_t ift_in_use; 328 qidx_t ift_cidx; 329 qidx_t ift_cidx_processed; 330 qidx_t ift_pidx; 331 uint8_t ift_gen; 332 uint8_t ift_br_offset; 333 uint16_t ift_npending; 334 uint16_t ift_db_pending; 335 uint16_t ift_rs_pending; 336 /* implicit pad */ 337 uint8_t ift_txd_size[8]; 338 uint64_t ift_processed; 339 uint64_t ift_cleaned; 340 uint64_t ift_cleaned_prev; 341 #if MEMORY_LOGGING 342 uint64_t ift_enqueued; 343 uint64_t ift_dequeued; 344 #endif 345 uint64_t ift_no_tx_dma_setup; 346 uint64_t ift_no_desc_avail; 347 uint64_t ift_mbuf_defrag_failed; 348 uint64_t ift_mbuf_defrag; 349 uint64_t ift_map_failed; 350 uint64_t ift_txd_encap_efbig; 351 uint64_t ift_pullups; 352 353 struct mtx ift_mtx; 354 struct mtx ift_db_mtx; 355 356 /* constant values */ 357 if_ctx_t ift_ctx; 358 struct ifmp_ring *ift_br; 359 struct grouptask ift_task; 360 qidx_t ift_size; 361 uint16_t ift_id; 362 struct callout ift_timer; 363 364 if_txsd_vec_t ift_sds; 365 uint8_t ift_qstatus; 366 uint8_t ift_closed; 367 uint8_t ift_update_freq; 368 struct iflib_filter_info ift_filter_info; 369 bus_dma_tag_t ift_desc_tag; 370 bus_dma_tag_t ift_tso_desc_tag; 371 iflib_dma_info_t ift_ifdi; 372 #define MTX_NAME_LEN 16 373 char ift_mtx_name[MTX_NAME_LEN]; 374 char ift_db_mtx_name[MTX_NAME_LEN]; 375 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 376 #ifdef IFLIB_DIAGNOSTICS 377 uint64_t ift_cpu_exec_count[256]; 378 #endif 379 } __aligned(CACHE_LINE_SIZE); 380 381 struct iflib_fl { 382 qidx_t ifl_cidx; 383 qidx_t ifl_pidx; 384 qidx_t ifl_credits; 385 uint8_t ifl_gen; 386 uint8_t ifl_rxd_size; 387 #if MEMORY_LOGGING 388 uint64_t ifl_m_enqueued; 389 uint64_t ifl_m_dequeued; 390 uint64_t ifl_cl_enqueued; 391 uint64_t ifl_cl_dequeued; 392 #endif 393 /* implicit pad */ 394 395 bitstr_t *ifl_rx_bitmap; 396 qidx_t ifl_fragidx; 397 /* constant */ 398 qidx_t ifl_size; 399 uint16_t ifl_buf_size; 400 uint16_t ifl_cltype; 401 uma_zone_t ifl_zone; 402 iflib_rxsd_array_t ifl_sds; 403 iflib_rxq_t ifl_rxq; 404 uint8_t ifl_id; 405 bus_dma_tag_t ifl_desc_tag; 406 iflib_dma_info_t ifl_ifdi; 407 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 408 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 409 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 410 } __aligned(CACHE_LINE_SIZE); 411 412 static inline qidx_t 413 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 414 { 415 qidx_t used; 416 417 if (pidx > cidx) 418 used = pidx - cidx; 419 else if (pidx < cidx) 420 used = size - cidx + pidx; 421 else if (gen == 0 && pidx == cidx) 422 used = 0; 423 else if (gen == 1 && pidx == cidx) 424 used = size; 425 else 426 panic("bad state"); 427 428 return (used); 429 } 430 431 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 432 433 #define IDXDIFF(head, tail, wrap) \ 434 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 435 436 struct iflib_rxq { 437 /* If there is a separate completion queue - 438 * these are the cq cidx and pidx. Otherwise 439 * these are unused. 440 */ 441 qidx_t ifr_size; 442 qidx_t ifr_cq_cidx; 443 qidx_t ifr_cq_pidx; 444 uint8_t ifr_cq_gen; 445 uint8_t ifr_fl_offset; 446 447 if_ctx_t ifr_ctx; 448 iflib_fl_t ifr_fl; 449 uint64_t ifr_rx_irq; 450 uint16_t ifr_id; 451 uint8_t ifr_lro_enabled; 452 uint8_t ifr_nfl; 453 uint8_t ifr_ntxqirq; 454 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 455 struct lro_ctrl ifr_lc; 456 struct grouptask ifr_task; 457 struct iflib_filter_info ifr_filter_info; 458 iflib_dma_info_t ifr_ifdi; 459 460 /* dynamically allocate if any drivers need a value substantially larger than this */ 461 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 462 #ifdef IFLIB_DIAGNOSTICS 463 uint64_t ifr_cpu_exec_count[256]; 464 #endif 465 } __aligned(CACHE_LINE_SIZE); 466 467 typedef struct if_rxsd { 468 caddr_t *ifsd_cl; 469 struct mbuf **ifsd_m; 470 iflib_fl_t ifsd_fl; 471 qidx_t ifsd_cidx; 472 } *if_rxsd_t; 473 474 /* multiple of word size */ 475 #ifdef __LP64__ 476 #define PKT_INFO_SIZE 6 477 #define RXD_INFO_SIZE 5 478 #define PKT_TYPE uint64_t 479 #else 480 #define PKT_INFO_SIZE 11 481 #define RXD_INFO_SIZE 8 482 #define PKT_TYPE uint32_t 483 #endif 484 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 485 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 486 487 typedef struct if_pkt_info_pad { 488 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 489 } *if_pkt_info_pad_t; 490 typedef struct if_rxd_info_pad { 491 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 492 } *if_rxd_info_pad_t; 493 494 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 495 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 496 497 498 static inline void 499 pkt_info_zero(if_pkt_info_t pi) 500 { 501 if_pkt_info_pad_t pi_pad; 502 503 pi_pad = (if_pkt_info_pad_t)pi; 504 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 505 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 506 #ifndef __LP64__ 507 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 508 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 509 #endif 510 } 511 512 static inline void 513 rxd_info_zero(if_rxd_info_t ri) 514 { 515 if_rxd_info_pad_t ri_pad; 516 int i; 517 518 ri_pad = (if_rxd_info_pad_t)ri; 519 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 520 ri_pad->rxd_val[i] = 0; 521 ri_pad->rxd_val[i+1] = 0; 522 ri_pad->rxd_val[i+2] = 0; 523 ri_pad->rxd_val[i+3] = 0; 524 } 525 #ifdef __LP64__ 526 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 527 #endif 528 } 529 530 /* 531 * Only allow a single packet to take up most 1/nth of the tx ring 532 */ 533 #define MAX_SINGLE_PACKET_FRACTION 12 534 #define IF_BAD_DMA (bus_addr_t)-1 535 536 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 537 538 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 539 540 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 541 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 542 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 543 544 545 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 546 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 547 548 549 /* Our boot-time initialization hook */ 550 static int iflib_module_event_handler(module_t, int, void *); 551 552 static moduledata_t iflib_moduledata = { 553 "iflib", 554 iflib_module_event_handler, 555 NULL 556 }; 557 558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 559 MODULE_VERSION(iflib, 1); 560 561 MODULE_DEPEND(iflib, pci, 1, 1, 1); 562 MODULE_DEPEND(iflib, ether, 1, 1, 1); 563 564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 566 567 #ifndef IFLIB_DEBUG_COUNTERS 568 #ifdef INVARIANTS 569 #define IFLIB_DEBUG_COUNTERS 1 570 #else 571 #define IFLIB_DEBUG_COUNTERS 0 572 #endif /* !INVARIANTS */ 573 #endif 574 575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 576 "iflib driver parameters"); 577 578 /* 579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 580 */ 581 static int iflib_min_tx_latency = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 584 static int iflib_no_tx_batch = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 587 588 589 #if IFLIB_DEBUG_COUNTERS 590 591 static int iflib_tx_seen; 592 static int iflib_tx_sent; 593 static int iflib_tx_encap; 594 static int iflib_rx_allocs; 595 static int iflib_fl_refills; 596 static int iflib_fl_refills_large; 597 static int iflib_tx_frees; 598 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 600 &iflib_tx_seen, 0, "# tx mbufs seen"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 602 &iflib_tx_sent, 0, "# tx mbufs sent"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 604 &iflib_tx_encap, 0, "# tx mbufs encapped"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 606 &iflib_tx_frees, 0, "# tx frees"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 608 &iflib_rx_allocs, 0, "# rx allocations"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 610 &iflib_fl_refills, 0, "# refills"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 612 &iflib_fl_refills_large, 0, "# large refills"); 613 614 615 static int iflib_txq_drain_flushing; 616 static int iflib_txq_drain_oactive; 617 static int iflib_txq_drain_notready; 618 static int iflib_txq_drain_encapfail; 619 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 621 &iflib_txq_drain_flushing, 0, "# drain flushes"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 623 &iflib_txq_drain_oactive, 0, "# drain oactives"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 625 &iflib_txq_drain_notready, 0, "# drain notready"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 627 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 628 629 630 static int iflib_encap_load_mbuf_fail; 631 static int iflib_encap_pad_mbuf_fail; 632 static int iflib_encap_txq_avail_fail; 633 static int iflib_encap_txd_encap_fail; 634 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 636 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 638 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 640 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 642 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 643 644 static int iflib_task_fn_rxs; 645 static int iflib_rx_intr_enables; 646 static int iflib_fast_intrs; 647 static int iflib_intr_link; 648 static int iflib_intr_msix; 649 static int iflib_rx_unavail; 650 static int iflib_rx_ctx_inactive; 651 static int iflib_rx_zero_len; 652 static int iflib_rx_if_input; 653 static int iflib_rx_mbuf_null; 654 static int iflib_rxd_flush; 655 656 static int iflib_verbose_debug; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 659 &iflib_intr_link, 0, "# intr link calls"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 661 &iflib_intr_msix, 0, "# intr msix calls"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 665 &iflib_rx_intr_enables, 0, "# rx intr enables"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 667 &iflib_fast_intrs, 0, "# fast_intr calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 669 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 673 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 675 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 677 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 679 &iflib_rxd_flush, 0, "# times rxd_flush called"); 680 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 681 &iflib_verbose_debug, 0, "enable verbose debugging"); 682 683 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 684 static void 685 iflib_debug_reset(void) 686 { 687 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 688 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 689 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 690 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 691 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 692 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 693 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 694 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 695 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 696 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 697 } 698 699 #else 700 #define DBG_COUNTER_INC(name) 701 static void iflib_debug_reset(void) {} 702 #endif 703 704 705 706 #define IFLIB_DEBUG 0 707 708 static void iflib_tx_structures_free(if_ctx_t ctx); 709 static void iflib_rx_structures_free(if_ctx_t ctx); 710 static int iflib_queues_alloc(if_ctx_t ctx); 711 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 712 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 713 static int iflib_qset_structures_setup(if_ctx_t ctx); 714 static int iflib_msix_init(if_ctx_t ctx); 715 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 716 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 717 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 718 static int iflib_register(if_ctx_t); 719 static void iflib_init_locked(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 722 static void iflib_ifmp_purge(iflib_txq_t txq); 723 static void _iflib_pre_assert(if_softc_ctx_t scctx); 724 static void iflib_stop(if_ctx_t ctx); 725 static void iflib_if_init_locked(if_ctx_t ctx); 726 #ifndef __NO_STRICT_ALIGNMENT 727 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 728 #endif 729 730 #ifdef DEV_NETMAP 731 #include <sys/selinfo.h> 732 #include <net/netmap.h> 733 #include <dev/netmap/netmap_kern.h> 734 735 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 736 737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 738 739 /* 740 * device-specific sysctl variables: 741 * 742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 743 * During regular operations the CRC is stripped, but on some 744 * hardware reception of frames not multiple of 64 is slower, 745 * so using crcstrip=0 helps in benchmarks. 746 * 747 * iflib_rx_miss, iflib_rx_miss_bufs: 748 * count packets that might be missed due to lost interrupts. 749 */ 750 SYSCTL_DECL(_dev_netmap); 751 /* 752 * The xl driver by default strips CRCs and we do not override it. 753 */ 754 755 int iflib_crcstrip = 1; 756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 758 759 int iflib_rx_miss, iflib_rx_miss_bufs; 760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 764 765 /* 766 * Register/unregister. We are already under netmap lock. 767 * Only called on the first register or the last unregister. 768 */ 769 static int 770 iflib_netmap_register(struct netmap_adapter *na, int onoff) 771 { 772 struct ifnet *ifp = na->ifp; 773 if_ctx_t ctx = ifp->if_softc; 774 int status; 775 776 CTX_LOCK(ctx); 777 IFDI_INTR_DISABLE(ctx); 778 779 /* Tell the stack that the interface is no longer active */ 780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 781 782 if (!CTX_IS_VF(ctx)) 783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 784 785 /* enable or disable flags and callbacks in na and ifp */ 786 if (onoff) { 787 nm_set_native_flags(na); 788 } else { 789 nm_clear_native_flags(na); 790 } 791 iflib_stop(ctx); 792 iflib_init_locked(ctx); 793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 795 if (status) 796 nm_clear_native_flags(na); 797 CTX_UNLOCK(ctx); 798 return (status); 799 } 800 801 static int 802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 803 { 804 struct netmap_adapter *na = kring->na; 805 u_int const lim = kring->nkr_num_slots - 1; 806 u_int head = kring->rhead; 807 struct netmap_ring *ring = kring->ring; 808 bus_dmamap_t *map; 809 struct if_rxd_update iru; 810 if_ctx_t ctx = rxq->ifr_ctx; 811 iflib_fl_t fl = &rxq->ifr_fl[0]; 812 uint32_t refill_pidx, nic_i; 813 814 if (nm_i == head && __predict_true(!init)) 815 return 0; 816 iru_init(&iru, rxq, 0 /* flid */); 817 map = fl->ifl_sds.ifsd_map; 818 refill_pidx = netmap_idx_k2n(kring, nm_i); 819 /* 820 * IMPORTANT: we must leave one free slot in the ring, 821 * so move head back by one unit 822 */ 823 head = nm_prev(head, lim); 824 while (nm_i != head) { 825 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 826 struct netmap_slot *slot = &ring->slot[nm_i]; 827 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 828 uint32_t nic_i_dma = refill_pidx; 829 nic_i = netmap_idx_k2n(kring, nm_i); 830 831 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 832 833 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 834 return netmap_ring_reinit(kring); 835 836 fl->ifl_vm_addrs[tmp_pidx] = addr; 837 if (__predict_false(init) && map) { 838 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 839 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 840 /* buffer has changed, reload map */ 841 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 842 } 843 slot->flags &= ~NS_BUF_CHANGED; 844 845 nm_i = nm_next(nm_i, lim); 846 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 847 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 848 continue; 849 850 iru.iru_pidx = refill_pidx; 851 iru.iru_count = tmp_pidx+1; 852 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 853 854 refill_pidx = nic_i; 855 if (map == NULL) 856 continue; 857 858 for (int n = 0; n < iru.iru_count; n++) { 859 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 860 BUS_DMASYNC_PREREAD); 861 /* XXX - change this to not use the netmap func*/ 862 nic_i_dma = nm_next(nic_i_dma, lim); 863 } 864 } 865 } 866 kring->nr_hwcur = head; 867 868 if (map) 869 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 870 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 871 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 872 return (0); 873 } 874 875 /* 876 * Reconcile kernel and user view of the transmit ring. 877 * 878 * All information is in the kring. 879 * Userspace wants to send packets up to the one before kring->rhead, 880 * kernel knows kring->nr_hwcur is the first unsent packet. 881 * 882 * Here we push packets out (as many as possible), and possibly 883 * reclaim buffers from previously completed transmission. 884 * 885 * The caller (netmap) guarantees that there is only one instance 886 * running at any time. Any interference with other driver 887 * methods should be handled by the individual drivers. 888 */ 889 static int 890 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 891 { 892 struct netmap_adapter *na = kring->na; 893 struct ifnet *ifp = na->ifp; 894 struct netmap_ring *ring = kring->ring; 895 u_int nm_i; /* index into the netmap ring */ 896 u_int nic_i; /* index into the NIC ring */ 897 u_int n; 898 u_int const lim = kring->nkr_num_slots - 1; 899 u_int const head = kring->rhead; 900 struct if_pkt_info pi; 901 902 /* 903 * interrupts on every tx packet are expensive so request 904 * them every half ring, or where NS_REPORT is set 905 */ 906 u_int report_frequency = kring->nkr_num_slots >> 1; 907 /* device-specific */ 908 if_ctx_t ctx = ifp->if_softc; 909 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 910 911 if (txq->ift_sds.ifsd_map) 912 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 913 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 914 915 916 /* 917 * First part: process new packets to send. 918 * nm_i is the current index in the netmap ring, 919 * nic_i is the corresponding index in the NIC ring. 920 * 921 * If we have packets to send (nm_i != head) 922 * iterate over the netmap ring, fetch length and update 923 * the corresponding slot in the NIC ring. Some drivers also 924 * need to update the buffer's physical address in the NIC slot 925 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 926 * 927 * The netmap_reload_map() calls is especially expensive, 928 * even when (as in this case) the tag is 0, so do only 929 * when the buffer has actually changed. 930 * 931 * If possible do not set the report/intr bit on all slots, 932 * but only a few times per ring or when NS_REPORT is set. 933 * 934 * Finally, on 10G and faster drivers, it might be useful 935 * to prefetch the next slot and txr entry. 936 */ 937 938 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 939 pkt_info_zero(&pi); 940 pi.ipi_segs = txq->ift_segs; 941 pi.ipi_qsidx = kring->ring_id; 942 if (nm_i != head) { /* we have new packets to send */ 943 nic_i = netmap_idx_k2n(kring, nm_i); 944 945 __builtin_prefetch(&ring->slot[nm_i]); 946 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 947 if (txq->ift_sds.ifsd_map) 948 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 949 950 for (n = 0; nm_i != head; n++) { 951 struct netmap_slot *slot = &ring->slot[nm_i]; 952 u_int len = slot->len; 953 uint64_t paddr; 954 void *addr = PNMB(na, slot, &paddr); 955 int flags = (slot->flags & NS_REPORT || 956 nic_i == 0 || nic_i == report_frequency) ? 957 IPI_TX_INTR : 0; 958 959 /* device-specific */ 960 pi.ipi_len = len; 961 pi.ipi_segs[0].ds_addr = paddr; 962 pi.ipi_segs[0].ds_len = len; 963 pi.ipi_nsegs = 1; 964 pi.ipi_ndescs = 0; 965 pi.ipi_pidx = nic_i; 966 pi.ipi_flags = flags; 967 968 /* Fill the slot in the NIC ring. */ 969 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 970 971 /* prefetch for next round */ 972 __builtin_prefetch(&ring->slot[nm_i + 1]); 973 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 974 if (txq->ift_sds.ifsd_map) { 975 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 976 977 NM_CHECK_ADDR_LEN(na, addr, len); 978 979 if (slot->flags & NS_BUF_CHANGED) { 980 /* buffer has changed, reload map */ 981 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 982 } 983 /* make sure changes to the buffer are synced */ 984 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 985 BUS_DMASYNC_PREWRITE); 986 } 987 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 988 nm_i = nm_next(nm_i, lim); 989 nic_i = nm_next(nic_i, lim); 990 } 991 kring->nr_hwcur = head; 992 993 /* synchronize the NIC ring */ 994 if (txq->ift_sds.ifsd_map) 995 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 997 998 /* (re)start the tx unit up to slot nic_i (excluded) */ 999 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1000 } 1001 1002 /* 1003 * Second part: reclaim buffers for completed transmissions. 1004 */ 1005 if (iflib_tx_credits_update(ctx, txq)) { 1006 /* some tx completed, increment avail */ 1007 nic_i = txq->ift_cidx_processed; 1008 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1009 } 1010 return (0); 1011 } 1012 1013 /* 1014 * Reconcile kernel and user view of the receive ring. 1015 * Same as for the txsync, this routine must be efficient. 1016 * The caller guarantees a single invocations, but races against 1017 * the rest of the driver should be handled here. 1018 * 1019 * On call, kring->rhead is the first packet that userspace wants 1020 * to keep, and kring->rcur is the wakeup point. 1021 * The kernel has previously reported packets up to kring->rtail. 1022 * 1023 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1024 * of whether or not we received an interrupt. 1025 */ 1026 static int 1027 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1028 { 1029 struct netmap_adapter *na = kring->na; 1030 struct netmap_ring *ring = kring->ring; 1031 uint32_t nm_i; /* index into the netmap ring */ 1032 uint32_t nic_i; /* index into the NIC ring */ 1033 u_int i, n; 1034 u_int const lim = kring->nkr_num_slots - 1; 1035 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1036 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1037 struct if_rxd_info ri; 1038 1039 struct ifnet *ifp = na->ifp; 1040 if_ctx_t ctx = ifp->if_softc; 1041 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1042 iflib_fl_t fl = rxq->ifr_fl; 1043 if (head > lim) 1044 return netmap_ring_reinit(kring); 1045 1046 /* XXX check sync modes */ 1047 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1048 if (fl->ifl_sds.ifsd_map == NULL) 1049 continue; 1050 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1051 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1052 } 1053 /* 1054 * First part: import newly received packets. 1055 * 1056 * nm_i is the index of the next free slot in the netmap ring, 1057 * nic_i is the index of the next received packet in the NIC ring, 1058 * and they may differ in case if_init() has been called while 1059 * in netmap mode. For the receive ring we have 1060 * 1061 * nic_i = rxr->next_check; 1062 * nm_i = kring->nr_hwtail (previous) 1063 * and 1064 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1065 * 1066 * rxr->next_check is set to 0 on a ring reinit 1067 */ 1068 if (netmap_no_pendintr || force_update) { 1069 int crclen = iflib_crcstrip ? 0 : 4; 1070 int error, avail; 1071 uint16_t slot_flags = kring->nkr_slot_flags; 1072 1073 for (i = 0; i < rxq->ifr_nfl; i++) { 1074 fl = &rxq->ifr_fl[i]; 1075 nic_i = fl->ifl_cidx; 1076 nm_i = netmap_idx_n2k(kring, nic_i); 1077 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1078 for (n = 0; avail > 0; n++, avail--) { 1079 rxd_info_zero(&ri); 1080 ri.iri_frags = rxq->ifr_frags; 1081 ri.iri_qsidx = kring->ring_id; 1082 ri.iri_ifp = ctx->ifc_ifp; 1083 ri.iri_cidx = nic_i; 1084 1085 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1086 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1087 ring->slot[nm_i].flags = slot_flags; 1088 if (fl->ifl_sds.ifsd_map) 1089 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1090 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1091 nm_i = nm_next(nm_i, lim); 1092 nic_i = nm_next(nic_i, lim); 1093 } 1094 if (n) { /* update the state variables */ 1095 if (netmap_no_pendintr && !force_update) { 1096 /* diagnostics */ 1097 iflib_rx_miss ++; 1098 iflib_rx_miss_bufs += n; 1099 } 1100 fl->ifl_cidx = nic_i; 1101 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1102 } 1103 kring->nr_kflags &= ~NKR_PENDINTR; 1104 } 1105 } 1106 /* 1107 * Second part: skip past packets that userspace has released. 1108 * (kring->nr_hwcur to head excluded), 1109 * and make the buffers available for reception. 1110 * As usual nm_i is the index in the netmap ring, 1111 * nic_i is the index in the NIC ring, and 1112 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1113 */ 1114 /* XXX not sure how this will work with multiple free lists */ 1115 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1116 1117 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1118 } 1119 1120 static void 1121 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1122 { 1123 struct ifnet *ifp = na->ifp; 1124 if_ctx_t ctx = ifp->if_softc; 1125 1126 CTX_LOCK(ctx); 1127 if (onoff) { 1128 IFDI_INTR_ENABLE(ctx); 1129 } else { 1130 IFDI_INTR_DISABLE(ctx); 1131 } 1132 CTX_UNLOCK(ctx); 1133 } 1134 1135 1136 static int 1137 iflib_netmap_attach(if_ctx_t ctx) 1138 { 1139 struct netmap_adapter na; 1140 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1141 1142 bzero(&na, sizeof(na)); 1143 1144 na.ifp = ctx->ifc_ifp; 1145 na.na_flags = NAF_BDG_MAYSLEEP; 1146 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1147 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1148 1149 na.num_tx_desc = scctx->isc_ntxd[0]; 1150 na.num_rx_desc = scctx->isc_nrxd[0]; 1151 na.nm_txsync = iflib_netmap_txsync; 1152 na.nm_rxsync = iflib_netmap_rxsync; 1153 na.nm_register = iflib_netmap_register; 1154 na.nm_intr = iflib_netmap_intr; 1155 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1156 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1157 return (netmap_attach(&na)); 1158 } 1159 1160 static void 1161 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1162 { 1163 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1164 struct netmap_slot *slot; 1165 1166 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1167 if (slot == NULL) 1168 return; 1169 if (txq->ift_sds.ifsd_map == NULL) 1170 return; 1171 1172 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1173 1174 /* 1175 * In netmap mode, set the map for the packet buffer. 1176 * NOTE: Some drivers (not this one) also need to set 1177 * the physical buffer address in the NIC ring. 1178 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1179 * netmap slot index, si 1180 */ 1181 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1182 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1183 } 1184 } 1185 1186 static void 1187 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1188 { 1189 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1190 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1191 struct netmap_slot *slot; 1192 uint32_t nm_i; 1193 1194 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1195 if (slot == NULL) 1196 return; 1197 nm_i = netmap_idx_n2k(kring, 0); 1198 netmap_fl_refill(rxq, kring, nm_i, true); 1199 } 1200 1201 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1202 1203 #else 1204 #define iflib_netmap_txq_init(ctx, txq) 1205 #define iflib_netmap_rxq_init(ctx, rxq) 1206 #define iflib_netmap_detach(ifp) 1207 1208 #define iflib_netmap_attach(ctx) (0) 1209 #define netmap_rx_irq(ifp, qid, budget) (0) 1210 #define netmap_tx_irq(ifp, qid) do {} while (0) 1211 1212 #endif 1213 1214 #if defined(__i386__) || defined(__amd64__) 1215 static __inline void 1216 prefetch(void *x) 1217 { 1218 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1219 } 1220 static __inline void 1221 prefetch2cachelines(void *x) 1222 { 1223 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1224 #if (CACHE_LINE_SIZE < 128) 1225 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1226 #endif 1227 } 1228 #else 1229 #define prefetch(x) 1230 #define prefetch2cachelines(x) 1231 #endif 1232 1233 static void 1234 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1235 { 1236 iflib_fl_t fl; 1237 1238 fl = &rxq->ifr_fl[flid]; 1239 iru->iru_paddrs = fl->ifl_bus_addrs; 1240 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1241 iru->iru_idxs = fl->ifl_rxd_idxs; 1242 iru->iru_qsidx = rxq->ifr_id; 1243 iru->iru_buf_size = fl->ifl_buf_size; 1244 iru->iru_flidx = fl->ifl_id; 1245 } 1246 1247 static void 1248 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1249 { 1250 if (err) 1251 return; 1252 *(bus_addr_t *) arg = segs[0].ds_addr; 1253 } 1254 1255 int 1256 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1257 { 1258 int err; 1259 if_shared_ctx_t sctx = ctx->ifc_sctx; 1260 device_t dev = ctx->ifc_dev; 1261 1262 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1263 1264 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1265 sctx->isc_q_align, 0, /* alignment, bounds */ 1266 BUS_SPACE_MAXADDR, /* lowaddr */ 1267 BUS_SPACE_MAXADDR, /* highaddr */ 1268 NULL, NULL, /* filter, filterarg */ 1269 size, /* maxsize */ 1270 1, /* nsegments */ 1271 size, /* maxsegsize */ 1272 BUS_DMA_ALLOCNOW, /* flags */ 1273 NULL, /* lockfunc */ 1274 NULL, /* lockarg */ 1275 &dma->idi_tag); 1276 if (err) { 1277 device_printf(dev, 1278 "%s: bus_dma_tag_create failed: %d\n", 1279 __func__, err); 1280 goto fail_0; 1281 } 1282 1283 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1284 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1285 if (err) { 1286 device_printf(dev, 1287 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1288 __func__, (uintmax_t)size, err); 1289 goto fail_1; 1290 } 1291 1292 dma->idi_paddr = IF_BAD_DMA; 1293 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1294 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1295 if (err || dma->idi_paddr == IF_BAD_DMA) { 1296 device_printf(dev, 1297 "%s: bus_dmamap_load failed: %d\n", 1298 __func__, err); 1299 goto fail_2; 1300 } 1301 1302 dma->idi_size = size; 1303 return (0); 1304 1305 fail_2: 1306 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1307 fail_1: 1308 bus_dma_tag_destroy(dma->idi_tag); 1309 fail_0: 1310 dma->idi_tag = NULL; 1311 1312 return (err); 1313 } 1314 1315 int 1316 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1317 { 1318 int i, err; 1319 iflib_dma_info_t *dmaiter; 1320 1321 dmaiter = dmalist; 1322 for (i = 0; i < count; i++, dmaiter++) { 1323 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1324 break; 1325 } 1326 if (err) 1327 iflib_dma_free_multi(dmalist, i); 1328 return (err); 1329 } 1330 1331 void 1332 iflib_dma_free(iflib_dma_info_t dma) 1333 { 1334 if (dma->idi_tag == NULL) 1335 return; 1336 if (dma->idi_paddr != IF_BAD_DMA) { 1337 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1339 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1340 dma->idi_paddr = IF_BAD_DMA; 1341 } 1342 if (dma->idi_vaddr != NULL) { 1343 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1344 dma->idi_vaddr = NULL; 1345 } 1346 bus_dma_tag_destroy(dma->idi_tag); 1347 dma->idi_tag = NULL; 1348 } 1349 1350 void 1351 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1352 { 1353 int i; 1354 iflib_dma_info_t *dmaiter = dmalist; 1355 1356 for (i = 0; i < count; i++, dmaiter++) 1357 iflib_dma_free(*dmaiter); 1358 } 1359 1360 #ifdef EARLY_AP_STARTUP 1361 static const int iflib_started = 1; 1362 #else 1363 /* 1364 * We used to abuse the smp_started flag to decide if the queues have been 1365 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1366 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1367 * is set. Run a SYSINIT() strictly after that to just set a usable 1368 * completion flag. 1369 */ 1370 1371 static int iflib_started; 1372 1373 static void 1374 iflib_record_started(void *arg) 1375 { 1376 iflib_started = 1; 1377 } 1378 1379 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1380 iflib_record_started, NULL); 1381 #endif 1382 1383 static int 1384 iflib_fast_intr(void *arg) 1385 { 1386 iflib_filter_info_t info = arg; 1387 struct grouptask *gtask = info->ifi_task; 1388 if (!iflib_started) 1389 return (FILTER_HANDLED); 1390 1391 DBG_COUNTER_INC(fast_intrs); 1392 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1393 return (FILTER_HANDLED); 1394 1395 GROUPTASK_ENQUEUE(gtask); 1396 return (FILTER_HANDLED); 1397 } 1398 1399 static int 1400 iflib_fast_intr_rxtx(void *arg) 1401 { 1402 iflib_filter_info_t info = arg; 1403 struct grouptask *gtask = info->ifi_task; 1404 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1405 if_ctx_t ctx; 1406 int i, cidx; 1407 1408 if (!iflib_started) 1409 return (FILTER_HANDLED); 1410 1411 DBG_COUNTER_INC(fast_intrs); 1412 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1413 return (FILTER_HANDLED); 1414 1415 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1416 qidx_t txqid = rxq->ifr_txqid[i]; 1417 1418 ctx = rxq->ifr_ctx; 1419 1420 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1421 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1422 continue; 1423 } 1424 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1425 } 1426 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1427 cidx = rxq->ifr_cq_cidx; 1428 else 1429 cidx = rxq->ifr_fl[0].ifl_cidx; 1430 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1431 GROUPTASK_ENQUEUE(gtask); 1432 else 1433 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1434 return (FILTER_HANDLED); 1435 } 1436 1437 1438 static int 1439 iflib_fast_intr_ctx(void *arg) 1440 { 1441 iflib_filter_info_t info = arg; 1442 struct grouptask *gtask = info->ifi_task; 1443 1444 if (!iflib_started) 1445 return (FILTER_HANDLED); 1446 1447 DBG_COUNTER_INC(fast_intrs); 1448 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1449 return (FILTER_HANDLED); 1450 1451 GROUPTASK_ENQUEUE(gtask); 1452 return (FILTER_HANDLED); 1453 } 1454 1455 static int 1456 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1457 driver_filter_t filter, driver_intr_t handler, void *arg, 1458 char *name) 1459 { 1460 int rc, flags; 1461 struct resource *res; 1462 void *tag = NULL; 1463 device_t dev = ctx->ifc_dev; 1464 1465 flags = RF_ACTIVE; 1466 if (ctx->ifc_flags & IFC_LEGACY) 1467 flags |= RF_SHAREABLE; 1468 MPASS(rid < 512); 1469 irq->ii_rid = rid; 1470 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1471 if (res == NULL) { 1472 device_printf(dev, 1473 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1474 return (ENOMEM); 1475 } 1476 irq->ii_res = res; 1477 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1478 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1479 filter, handler, arg, &tag); 1480 if (rc != 0) { 1481 device_printf(dev, 1482 "failed to setup interrupt for rid %d, name %s: %d\n", 1483 rid, name ? name : "unknown", rc); 1484 return (rc); 1485 } else if (name) 1486 bus_describe_intr(dev, res, tag, "%s", name); 1487 1488 irq->ii_tag = tag; 1489 return (0); 1490 } 1491 1492 1493 /********************************************************************* 1494 * 1495 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1496 * the information needed to transmit a packet on the wire. This is 1497 * called only once at attach, setup is done every reset. 1498 * 1499 **********************************************************************/ 1500 1501 static int 1502 iflib_txsd_alloc(iflib_txq_t txq) 1503 { 1504 if_ctx_t ctx = txq->ift_ctx; 1505 if_shared_ctx_t sctx = ctx->ifc_sctx; 1506 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1507 device_t dev = ctx->ifc_dev; 1508 int err, nsegments, ntsosegments; 1509 1510 nsegments = scctx->isc_tx_nsegments; 1511 ntsosegments = scctx->isc_tx_tso_segments_max; 1512 MPASS(scctx->isc_ntxd[0] > 0); 1513 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1514 MPASS(nsegments > 0); 1515 MPASS(ntsosegments > 0); 1516 /* 1517 * Setup DMA descriptor areas. 1518 */ 1519 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1520 1, 0, /* alignment, bounds */ 1521 BUS_SPACE_MAXADDR, /* lowaddr */ 1522 BUS_SPACE_MAXADDR, /* highaddr */ 1523 NULL, NULL, /* filter, filterarg */ 1524 sctx->isc_tx_maxsize, /* maxsize */ 1525 nsegments, /* nsegments */ 1526 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1527 0, /* flags */ 1528 NULL, /* lockfunc */ 1529 NULL, /* lockfuncarg */ 1530 &txq->ift_desc_tag))) { 1531 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1532 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1533 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1534 goto fail; 1535 } 1536 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1537 1, 0, /* alignment, bounds */ 1538 BUS_SPACE_MAXADDR, /* lowaddr */ 1539 BUS_SPACE_MAXADDR, /* highaddr */ 1540 NULL, NULL, /* filter, filterarg */ 1541 scctx->isc_tx_tso_size_max, /* maxsize */ 1542 ntsosegments, /* nsegments */ 1543 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1544 0, /* flags */ 1545 NULL, /* lockfunc */ 1546 NULL, /* lockfuncarg */ 1547 &txq->ift_tso_desc_tag))) { 1548 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1549 1550 goto fail; 1551 } 1552 if (!(txq->ift_sds.ifsd_flags = 1553 (uint8_t *) mallocarray(scctx->isc_ntxd[txq->ift_br_offset], 1554 sizeof(uint8_t), M_IFLIB, M_NOWAIT | M_ZERO))) { 1555 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1556 err = ENOMEM; 1557 goto fail; 1558 } 1559 if (!(txq->ift_sds.ifsd_m = 1560 (struct mbuf **) mallocarray(scctx->isc_ntxd[txq->ift_br_offset], 1561 sizeof(struct mbuf *), M_IFLIB, M_NOWAIT | M_ZERO))) { 1562 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1563 err = ENOMEM; 1564 goto fail; 1565 } 1566 1567 /* Create the descriptor buffer dma maps */ 1568 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1569 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1570 return (0); 1571 1572 if (!(txq->ift_sds.ifsd_map = 1573 (bus_dmamap_t *) mallocarray(scctx->isc_ntxd[txq->ift_br_offset], 1574 sizeof(bus_dmamap_t), M_IFLIB, M_NOWAIT | M_ZERO))) { 1575 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1576 err = ENOMEM; 1577 goto fail; 1578 } 1579 1580 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1581 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1582 if (err != 0) { 1583 device_printf(dev, "Unable to create TX DMA map\n"); 1584 goto fail; 1585 } 1586 } 1587 #endif 1588 return (0); 1589 fail: 1590 /* We free all, it handles case where we are in the middle */ 1591 iflib_tx_structures_free(ctx); 1592 return (err); 1593 } 1594 1595 static void 1596 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1597 { 1598 bus_dmamap_t map; 1599 1600 map = NULL; 1601 if (txq->ift_sds.ifsd_map != NULL) 1602 map = txq->ift_sds.ifsd_map[i]; 1603 if (map != NULL) { 1604 bus_dmamap_unload(txq->ift_desc_tag, map); 1605 bus_dmamap_destroy(txq->ift_desc_tag, map); 1606 txq->ift_sds.ifsd_map[i] = NULL; 1607 } 1608 } 1609 1610 static void 1611 iflib_txq_destroy(iflib_txq_t txq) 1612 { 1613 if_ctx_t ctx = txq->ift_ctx; 1614 1615 for (int i = 0; i < txq->ift_size; i++) 1616 iflib_txsd_destroy(ctx, txq, i); 1617 if (txq->ift_sds.ifsd_map != NULL) { 1618 free(txq->ift_sds.ifsd_map, M_IFLIB); 1619 txq->ift_sds.ifsd_map = NULL; 1620 } 1621 if (txq->ift_sds.ifsd_m != NULL) { 1622 free(txq->ift_sds.ifsd_m, M_IFLIB); 1623 txq->ift_sds.ifsd_m = NULL; 1624 } 1625 if (txq->ift_sds.ifsd_flags != NULL) { 1626 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1627 txq->ift_sds.ifsd_flags = NULL; 1628 } 1629 if (txq->ift_desc_tag != NULL) { 1630 bus_dma_tag_destroy(txq->ift_desc_tag); 1631 txq->ift_desc_tag = NULL; 1632 } 1633 if (txq->ift_tso_desc_tag != NULL) { 1634 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1635 txq->ift_tso_desc_tag = NULL; 1636 } 1637 } 1638 1639 static void 1640 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1641 { 1642 struct mbuf **mp; 1643 1644 mp = &txq->ift_sds.ifsd_m[i]; 1645 if (*mp == NULL) 1646 return; 1647 1648 if (txq->ift_sds.ifsd_map != NULL) { 1649 bus_dmamap_sync(txq->ift_desc_tag, 1650 txq->ift_sds.ifsd_map[i], 1651 BUS_DMASYNC_POSTWRITE); 1652 bus_dmamap_unload(txq->ift_desc_tag, 1653 txq->ift_sds.ifsd_map[i]); 1654 } 1655 m_free(*mp); 1656 DBG_COUNTER_INC(tx_frees); 1657 *mp = NULL; 1658 } 1659 1660 static int 1661 iflib_txq_setup(iflib_txq_t txq) 1662 { 1663 if_ctx_t ctx = txq->ift_ctx; 1664 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1665 iflib_dma_info_t di; 1666 int i; 1667 1668 /* Set number of descriptors available */ 1669 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1670 /* XXX make configurable */ 1671 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1672 1673 /* Reset indices */ 1674 txq->ift_cidx_processed = 0; 1675 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1676 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1677 1678 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1679 bzero((void *)di->idi_vaddr, di->idi_size); 1680 1681 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1682 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1683 bus_dmamap_sync(di->idi_tag, di->idi_map, 1684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1685 return (0); 1686 } 1687 1688 /********************************************************************* 1689 * 1690 * Allocate memory for rx_buffer structures. Since we use one 1691 * rx_buffer per received packet, the maximum number of rx_buffer's 1692 * that we'll need is equal to the number of receive descriptors 1693 * that we've allocated. 1694 * 1695 **********************************************************************/ 1696 static int 1697 iflib_rxsd_alloc(iflib_rxq_t rxq) 1698 { 1699 if_ctx_t ctx = rxq->ifr_ctx; 1700 if_shared_ctx_t sctx = ctx->ifc_sctx; 1701 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1702 device_t dev = ctx->ifc_dev; 1703 iflib_fl_t fl; 1704 int err; 1705 1706 MPASS(scctx->isc_nrxd[0] > 0); 1707 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1708 1709 fl = rxq->ifr_fl; 1710 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1711 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1712 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1713 1, 0, /* alignment, bounds */ 1714 BUS_SPACE_MAXADDR, /* lowaddr */ 1715 BUS_SPACE_MAXADDR, /* highaddr */ 1716 NULL, NULL, /* filter, filterarg */ 1717 sctx->isc_rx_maxsize, /* maxsize */ 1718 sctx->isc_rx_nsegments, /* nsegments */ 1719 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1720 0, /* flags */ 1721 NULL, /* lockfunc */ 1722 NULL, /* lockarg */ 1723 &fl->ifl_desc_tag); 1724 if (err) { 1725 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1726 __func__, err); 1727 goto fail; 1728 } 1729 if (!(fl->ifl_sds.ifsd_flags = 1730 (uint8_t *) mallocarray(scctx->isc_nrxd[rxq->ifr_fl_offset], 1731 sizeof(uint8_t), M_IFLIB, M_NOWAIT | M_ZERO))) { 1732 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1733 err = ENOMEM; 1734 goto fail; 1735 } 1736 if (!(fl->ifl_sds.ifsd_m = 1737 (struct mbuf **) mallocarray(scctx->isc_nrxd[rxq->ifr_fl_offset], 1738 sizeof(struct mbuf *), M_IFLIB, M_NOWAIT | M_ZERO))) { 1739 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1740 err = ENOMEM; 1741 goto fail; 1742 } 1743 if (!(fl->ifl_sds.ifsd_cl = 1744 (caddr_t *) mallocarray(scctx->isc_nrxd[rxq->ifr_fl_offset], 1745 sizeof(caddr_t), M_IFLIB, M_NOWAIT | M_ZERO))) { 1746 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1747 err = ENOMEM; 1748 goto fail; 1749 } 1750 1751 /* Create the descriptor buffer dma maps */ 1752 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1753 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1754 continue; 1755 1756 if (!(fl->ifl_sds.ifsd_map = 1757 (bus_dmamap_t *) mallocarray(scctx->isc_nrxd[rxq->ifr_fl_offset], 1758 sizeof(bus_dmamap_t), M_IFLIB, M_NOWAIT | M_ZERO))) { 1759 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1760 err = ENOMEM; 1761 goto fail; 1762 } 1763 1764 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1765 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1766 if (err != 0) { 1767 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1768 goto fail; 1769 } 1770 } 1771 #endif 1772 } 1773 return (0); 1774 1775 fail: 1776 iflib_rx_structures_free(ctx); 1777 return (err); 1778 } 1779 1780 1781 /* 1782 * Internal service routines 1783 */ 1784 1785 struct rxq_refill_cb_arg { 1786 int error; 1787 bus_dma_segment_t seg; 1788 int nseg; 1789 }; 1790 1791 static void 1792 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1793 { 1794 struct rxq_refill_cb_arg *cb_arg = arg; 1795 1796 cb_arg->error = error; 1797 cb_arg->seg = segs[0]; 1798 cb_arg->nseg = nseg; 1799 } 1800 1801 1802 #ifdef ACPI_DMAR 1803 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1804 #else 1805 #define IS_DMAR(ctx) (0) 1806 #endif 1807 1808 /** 1809 * rxq_refill - refill an rxq free-buffer list 1810 * @ctx: the iflib context 1811 * @rxq: the free-list to refill 1812 * @n: the number of new buffers to allocate 1813 * 1814 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1815 * The caller must assure that @n does not exceed the queue's capacity. 1816 */ 1817 static void 1818 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1819 { 1820 struct mbuf *m; 1821 int idx, frag_idx = fl->ifl_fragidx; 1822 int pidx = fl->ifl_pidx; 1823 caddr_t cl, *sd_cl; 1824 struct mbuf **sd_m; 1825 uint8_t *sd_flags; 1826 struct if_rxd_update iru; 1827 bus_dmamap_t *sd_map; 1828 int n, i = 0; 1829 uint64_t bus_addr; 1830 int err; 1831 qidx_t credits; 1832 1833 sd_m = fl->ifl_sds.ifsd_m; 1834 sd_map = fl->ifl_sds.ifsd_map; 1835 sd_cl = fl->ifl_sds.ifsd_cl; 1836 sd_flags = fl->ifl_sds.ifsd_flags; 1837 idx = pidx; 1838 credits = fl->ifl_credits; 1839 1840 n = count; 1841 MPASS(n > 0); 1842 MPASS(credits + n <= fl->ifl_size); 1843 1844 if (pidx < fl->ifl_cidx) 1845 MPASS(pidx + n <= fl->ifl_cidx); 1846 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1847 MPASS(fl->ifl_gen == 0); 1848 if (pidx > fl->ifl_cidx) 1849 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1850 1851 DBG_COUNTER_INC(fl_refills); 1852 if (n > 8) 1853 DBG_COUNTER_INC(fl_refills_large); 1854 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1855 while (n--) { 1856 /* 1857 * We allocate an uninitialized mbuf + cluster, mbuf is 1858 * initialized after rx. 1859 * 1860 * If the cluster is still set then we know a minimum sized packet was received 1861 */ 1862 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1863 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1864 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1865 if ((cl = sd_cl[frag_idx]) == NULL) { 1866 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1867 break; 1868 #if MEMORY_LOGGING 1869 fl->ifl_cl_enqueued++; 1870 #endif 1871 } 1872 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1873 break; 1874 } 1875 #if MEMORY_LOGGING 1876 fl->ifl_m_enqueued++; 1877 #endif 1878 1879 DBG_COUNTER_INC(rx_allocs); 1880 #if defined(__i386__) || defined(__amd64__) 1881 if (!IS_DMAR(ctx)) { 1882 bus_addr = pmap_kextract((vm_offset_t)cl); 1883 } else 1884 #endif 1885 { 1886 struct rxq_refill_cb_arg cb_arg; 1887 iflib_rxq_t q; 1888 1889 cb_arg.error = 0; 1890 q = fl->ifl_rxq; 1891 MPASS(sd_map != NULL); 1892 MPASS(sd_map[frag_idx] != NULL); 1893 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1894 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1895 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1896 BUS_DMASYNC_PREREAD); 1897 1898 if (err != 0 || cb_arg.error) { 1899 /* 1900 * !zone_pack ? 1901 */ 1902 if (fl->ifl_zone == zone_pack) 1903 uma_zfree(fl->ifl_zone, cl); 1904 m_free(m); 1905 n = 0; 1906 goto done; 1907 } 1908 bus_addr = cb_arg.seg.ds_addr; 1909 } 1910 bit_set(fl->ifl_rx_bitmap, frag_idx); 1911 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1912 1913 MPASS(sd_m[frag_idx] == NULL); 1914 sd_cl[frag_idx] = cl; 1915 sd_m[frag_idx] = m; 1916 fl->ifl_rxd_idxs[i] = frag_idx; 1917 fl->ifl_bus_addrs[i] = bus_addr; 1918 fl->ifl_vm_addrs[i] = cl; 1919 credits++; 1920 i++; 1921 MPASS(credits <= fl->ifl_size); 1922 if (++idx == fl->ifl_size) { 1923 fl->ifl_gen = 1; 1924 idx = 0; 1925 } 1926 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1927 iru.iru_pidx = pidx; 1928 iru.iru_count = i; 1929 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1930 i = 0; 1931 pidx = idx; 1932 fl->ifl_pidx = idx; 1933 fl->ifl_credits = credits; 1934 } 1935 1936 } 1937 done: 1938 if (i) { 1939 iru.iru_pidx = pidx; 1940 iru.iru_count = i; 1941 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1942 fl->ifl_pidx = idx; 1943 fl->ifl_credits = credits; 1944 } 1945 DBG_COUNTER_INC(rxd_flush); 1946 if (fl->ifl_pidx == 0) 1947 pidx = fl->ifl_size - 1; 1948 else 1949 pidx = fl->ifl_pidx - 1; 1950 1951 if (sd_map) 1952 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1953 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1954 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1955 fl->ifl_fragidx = frag_idx; 1956 } 1957 1958 static __inline void 1959 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1960 { 1961 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1962 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1963 #ifdef INVARIANTS 1964 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1965 #endif 1966 1967 MPASS(fl->ifl_credits <= fl->ifl_size); 1968 MPASS(reclaimable == delta); 1969 1970 if (reclaimable > 0) 1971 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1972 } 1973 1974 static void 1975 iflib_fl_bufs_free(iflib_fl_t fl) 1976 { 1977 iflib_dma_info_t idi = fl->ifl_ifdi; 1978 uint32_t i; 1979 1980 for (i = 0; i < fl->ifl_size; i++) { 1981 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1982 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1983 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1984 1985 if (*sd_flags & RX_SW_DESC_INUSE) { 1986 if (fl->ifl_sds.ifsd_map != NULL) { 1987 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1988 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1989 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1990 } 1991 if (*sd_m != NULL) { 1992 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1993 uma_zfree(zone_mbuf, *sd_m); 1994 } 1995 if (*sd_cl != NULL) 1996 uma_zfree(fl->ifl_zone, *sd_cl); 1997 *sd_flags = 0; 1998 } else { 1999 MPASS(*sd_cl == NULL); 2000 MPASS(*sd_m == NULL); 2001 } 2002 #if MEMORY_LOGGING 2003 fl->ifl_m_dequeued++; 2004 fl->ifl_cl_dequeued++; 2005 #endif 2006 *sd_cl = NULL; 2007 *sd_m = NULL; 2008 } 2009 #ifdef INVARIANTS 2010 for (i = 0; i < fl->ifl_size; i++) { 2011 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2012 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2013 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2014 } 2015 #endif 2016 /* 2017 * Reset free list values 2018 */ 2019 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2020 bzero(idi->idi_vaddr, idi->idi_size); 2021 } 2022 2023 /********************************************************************* 2024 * 2025 * Initialize a receive ring and its buffers. 2026 * 2027 **********************************************************************/ 2028 static int 2029 iflib_fl_setup(iflib_fl_t fl) 2030 { 2031 iflib_rxq_t rxq = fl->ifl_rxq; 2032 if_ctx_t ctx = rxq->ifr_ctx; 2033 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2034 2035 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2036 /* 2037 ** Free current RX buffer structs and their mbufs 2038 */ 2039 iflib_fl_bufs_free(fl); 2040 /* Now replenish the mbufs */ 2041 MPASS(fl->ifl_credits == 0); 2042 /* 2043 * XXX don't set the max_frame_size to larger 2044 * than the hardware can handle 2045 */ 2046 if (sctx->isc_max_frame_size <= 2048) 2047 fl->ifl_buf_size = MCLBYTES; 2048 #ifndef CONTIGMALLOC_WORKS 2049 else 2050 fl->ifl_buf_size = MJUMPAGESIZE; 2051 #else 2052 else if (sctx->isc_max_frame_size <= 4096) 2053 fl->ifl_buf_size = MJUMPAGESIZE; 2054 else if (sctx->isc_max_frame_size <= 9216) 2055 fl->ifl_buf_size = MJUM9BYTES; 2056 else 2057 fl->ifl_buf_size = MJUM16BYTES; 2058 #endif 2059 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2060 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2061 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2062 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2063 2064 2065 /* avoid pre-allocating zillions of clusters to an idle card 2066 * potentially speeding up attach 2067 */ 2068 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2069 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2070 if (min(128, fl->ifl_size) != fl->ifl_credits) 2071 return (ENOBUFS); 2072 /* 2073 * handle failure 2074 */ 2075 MPASS(rxq != NULL); 2076 MPASS(fl->ifl_ifdi != NULL); 2077 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2078 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2079 return (0); 2080 } 2081 2082 /********************************************************************* 2083 * 2084 * Free receive ring data structures 2085 * 2086 **********************************************************************/ 2087 static void 2088 iflib_rx_sds_free(iflib_rxq_t rxq) 2089 { 2090 iflib_fl_t fl; 2091 int i; 2092 2093 if (rxq->ifr_fl != NULL) { 2094 for (i = 0; i < rxq->ifr_nfl; i++) { 2095 fl = &rxq->ifr_fl[i]; 2096 if (fl->ifl_desc_tag != NULL) { 2097 bus_dma_tag_destroy(fl->ifl_desc_tag); 2098 fl->ifl_desc_tag = NULL; 2099 } 2100 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2101 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2102 /* XXX destroy maps first */ 2103 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2104 fl->ifl_sds.ifsd_m = NULL; 2105 fl->ifl_sds.ifsd_cl = NULL; 2106 fl->ifl_sds.ifsd_map = NULL; 2107 } 2108 free(rxq->ifr_fl, M_IFLIB); 2109 rxq->ifr_fl = NULL; 2110 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2111 } 2112 } 2113 2114 /* 2115 * MI independent logic 2116 * 2117 */ 2118 static void 2119 iflib_timer(void *arg) 2120 { 2121 iflib_txq_t txq = arg; 2122 if_ctx_t ctx = txq->ift_ctx; 2123 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2124 2125 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2126 return; 2127 /* 2128 ** Check on the state of the TX queue(s), this 2129 ** can be done without the lock because its RO 2130 ** and the HUNG state will be static if set. 2131 */ 2132 IFDI_TIMER(ctx, txq->ift_id); 2133 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2134 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2135 (sctx->isc_pause_frames == 0))) 2136 goto hung; 2137 2138 if (ifmp_ring_is_stalled(txq->ift_br)) 2139 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2140 txq->ift_cleaned_prev = txq->ift_cleaned; 2141 /* handle any laggards */ 2142 if (txq->ift_db_pending) 2143 GROUPTASK_ENQUEUE(&txq->ift_task); 2144 2145 sctx->isc_pause_frames = 0; 2146 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2147 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2148 return; 2149 hung: 2150 CTX_LOCK(ctx); 2151 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2152 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2153 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2154 2155 IFDI_WATCHDOG_RESET(ctx); 2156 ctx->ifc_watchdog_events++; 2157 2158 ctx->ifc_flags |= IFC_DO_RESET; 2159 iflib_admin_intr_deferred(ctx); 2160 CTX_UNLOCK(ctx); 2161 } 2162 2163 static void 2164 iflib_init_locked(if_ctx_t ctx) 2165 { 2166 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2167 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2168 if_t ifp = ctx->ifc_ifp; 2169 iflib_fl_t fl; 2170 iflib_txq_t txq; 2171 iflib_rxq_t rxq; 2172 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2173 2174 2175 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2176 IFDI_INTR_DISABLE(ctx); 2177 2178 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2179 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2180 /* Set hardware offload abilities */ 2181 if_clearhwassist(ifp); 2182 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2183 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2184 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2185 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2186 if (if_getcapenable(ifp) & IFCAP_TSO4) 2187 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2188 if (if_getcapenable(ifp) & IFCAP_TSO6) 2189 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2190 2191 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2192 CALLOUT_LOCK(txq); 2193 callout_stop(&txq->ift_timer); 2194 CALLOUT_UNLOCK(txq); 2195 iflib_netmap_txq_init(ctx, txq); 2196 } 2197 #ifdef INVARIANTS 2198 i = if_getdrvflags(ifp); 2199 #endif 2200 IFDI_INIT(ctx); 2201 MPASS(if_getdrvflags(ifp) == i); 2202 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2203 /* XXX this should really be done on a per-queue basis */ 2204 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2205 MPASS(rxq->ifr_id == i); 2206 iflib_netmap_rxq_init(ctx, rxq); 2207 continue; 2208 } 2209 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2210 if (iflib_fl_setup(fl)) { 2211 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2212 goto done; 2213 } 2214 } 2215 } 2216 done: 2217 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2218 IFDI_INTR_ENABLE(ctx); 2219 txq = ctx->ifc_txqs; 2220 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2221 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2222 txq->ift_timer.c_cpu); 2223 } 2224 2225 static int 2226 iflib_media_change(if_t ifp) 2227 { 2228 if_ctx_t ctx = if_getsoftc(ifp); 2229 int err; 2230 2231 CTX_LOCK(ctx); 2232 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2233 iflib_init_locked(ctx); 2234 CTX_UNLOCK(ctx); 2235 return (err); 2236 } 2237 2238 static void 2239 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2240 { 2241 if_ctx_t ctx = if_getsoftc(ifp); 2242 2243 CTX_LOCK(ctx); 2244 IFDI_UPDATE_ADMIN_STATUS(ctx); 2245 IFDI_MEDIA_STATUS(ctx, ifmr); 2246 CTX_UNLOCK(ctx); 2247 } 2248 2249 static void 2250 iflib_stop(if_ctx_t ctx) 2251 { 2252 iflib_txq_t txq = ctx->ifc_txqs; 2253 iflib_rxq_t rxq = ctx->ifc_rxqs; 2254 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2255 iflib_dma_info_t di; 2256 iflib_fl_t fl; 2257 int i, j; 2258 2259 /* Tell the stack that the interface is no longer active */ 2260 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2261 2262 IFDI_INTR_DISABLE(ctx); 2263 DELAY(1000); 2264 IFDI_STOP(ctx); 2265 DELAY(1000); 2266 2267 iflib_debug_reset(); 2268 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2269 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2270 /* make sure all transmitters have completed before proceeding XXX */ 2271 2272 /* clean any enqueued buffers */ 2273 iflib_ifmp_purge(txq); 2274 /* Free any existing tx buffers. */ 2275 for (j = 0; j < txq->ift_size; j++) { 2276 iflib_txsd_free(ctx, txq, j); 2277 } 2278 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2279 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2280 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2281 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2282 txq->ift_pullups = 0; 2283 ifmp_ring_reset_stats(txq->ift_br); 2284 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2285 bzero((void *)di->idi_vaddr, di->idi_size); 2286 } 2287 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2288 /* make sure all transmitters have completed before proceeding XXX */ 2289 2290 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2291 bzero((void *)di->idi_vaddr, di->idi_size); 2292 /* also resets the free lists pidx/cidx */ 2293 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2294 iflib_fl_bufs_free(fl); 2295 } 2296 } 2297 2298 static inline caddr_t 2299 calc_next_rxd(iflib_fl_t fl, int cidx) 2300 { 2301 qidx_t size; 2302 int nrxd; 2303 caddr_t start, end, cur, next; 2304 2305 nrxd = fl->ifl_size; 2306 size = fl->ifl_rxd_size; 2307 start = fl->ifl_ifdi->idi_vaddr; 2308 2309 if (__predict_false(size == 0)) 2310 return (start); 2311 cur = start + size*cidx; 2312 end = start + size*nrxd; 2313 next = CACHE_PTR_NEXT(cur); 2314 return (next < end ? next : start); 2315 } 2316 2317 static inline void 2318 prefetch_pkts(iflib_fl_t fl, int cidx) 2319 { 2320 int nextptr; 2321 int nrxd = fl->ifl_size; 2322 caddr_t next_rxd; 2323 2324 2325 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2326 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2327 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2328 next_rxd = calc_next_rxd(fl, cidx); 2329 prefetch(next_rxd); 2330 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2331 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2332 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2333 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2334 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2335 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2336 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2337 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2338 } 2339 2340 static void 2341 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2342 { 2343 int flid, cidx; 2344 bus_dmamap_t map; 2345 iflib_fl_t fl; 2346 iflib_dma_info_t di; 2347 int next; 2348 2349 map = NULL; 2350 flid = irf->irf_flid; 2351 cidx = irf->irf_idx; 2352 fl = &rxq->ifr_fl[flid]; 2353 sd->ifsd_fl = fl; 2354 sd->ifsd_cidx = cidx; 2355 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2356 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2357 fl->ifl_credits--; 2358 #if MEMORY_LOGGING 2359 fl->ifl_m_dequeued++; 2360 #endif 2361 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2362 prefetch_pkts(fl, cidx); 2363 if (fl->ifl_sds.ifsd_map != NULL) { 2364 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2365 prefetch(&fl->ifl_sds.ifsd_map[next]); 2366 map = fl->ifl_sds.ifsd_map[cidx]; 2367 di = fl->ifl_ifdi; 2368 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2369 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2370 bus_dmamap_sync(di->idi_tag, di->idi_map, 2371 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2372 2373 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2374 MPASS(fl->ifl_cidx == cidx); 2375 if (unload) 2376 bus_dmamap_unload(fl->ifl_desc_tag, map); 2377 } 2378 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2379 if (__predict_false(fl->ifl_cidx == 0)) 2380 fl->ifl_gen = 0; 2381 if (map != NULL) 2382 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2383 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2384 bit_clear(fl->ifl_rx_bitmap, cidx); 2385 } 2386 2387 static struct mbuf * 2388 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2389 { 2390 int i, padlen , flags; 2391 struct mbuf *m, *mh, *mt; 2392 caddr_t cl; 2393 2394 i = 0; 2395 mh = NULL; 2396 do { 2397 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2398 2399 MPASS(*sd->ifsd_cl != NULL); 2400 MPASS(*sd->ifsd_m != NULL); 2401 2402 /* Don't include zero-length frags */ 2403 if (ri->iri_frags[i].irf_len == 0) { 2404 /* XXX we can save the cluster here, but not the mbuf */ 2405 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2406 m_free(*sd->ifsd_m); 2407 *sd->ifsd_m = NULL; 2408 continue; 2409 } 2410 m = *sd->ifsd_m; 2411 *sd->ifsd_m = NULL; 2412 if (mh == NULL) { 2413 flags = M_PKTHDR|M_EXT; 2414 mh = mt = m; 2415 padlen = ri->iri_pad; 2416 } else { 2417 flags = M_EXT; 2418 mt->m_next = m; 2419 mt = m; 2420 /* assuming padding is only on the first fragment */ 2421 padlen = 0; 2422 } 2423 cl = *sd->ifsd_cl; 2424 *sd->ifsd_cl = NULL; 2425 2426 /* Can these two be made one ? */ 2427 m_init(m, M_NOWAIT, MT_DATA, flags); 2428 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2429 /* 2430 * These must follow m_init and m_cljset 2431 */ 2432 m->m_data += padlen; 2433 ri->iri_len -= padlen; 2434 m->m_len = ri->iri_frags[i].irf_len; 2435 } while (++i < ri->iri_nfrags); 2436 2437 return (mh); 2438 } 2439 2440 /* 2441 * Process one software descriptor 2442 */ 2443 static struct mbuf * 2444 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2445 { 2446 struct if_rxsd sd; 2447 struct mbuf *m; 2448 2449 /* should I merge this back in now that the two paths are basically duplicated? */ 2450 if (ri->iri_nfrags == 1 && 2451 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2452 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2453 m = *sd.ifsd_m; 2454 *sd.ifsd_m = NULL; 2455 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2456 #ifndef __NO_STRICT_ALIGNMENT 2457 if (!IP_ALIGNED(m)) 2458 m->m_data += 2; 2459 #endif 2460 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2461 m->m_len = ri->iri_frags[0].irf_len; 2462 } else { 2463 m = assemble_segments(rxq, ri, &sd); 2464 } 2465 m->m_pkthdr.len = ri->iri_len; 2466 m->m_pkthdr.rcvif = ri->iri_ifp; 2467 m->m_flags |= ri->iri_flags; 2468 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2469 m->m_pkthdr.flowid = ri->iri_flowid; 2470 M_HASHTYPE_SET(m, ri->iri_rsstype); 2471 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2472 m->m_pkthdr.csum_data = ri->iri_csum_data; 2473 return (m); 2474 } 2475 2476 #if defined(INET6) || defined(INET) 2477 static void 2478 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2479 { 2480 CURVNET_SET(lc->ifp->if_vnet); 2481 #if defined(INET6) 2482 *v6 = VNET(ip6_forwarding); 2483 #endif 2484 #if defined(INET) 2485 *v4 = VNET(ipforwarding); 2486 #endif 2487 CURVNET_RESTORE(); 2488 } 2489 2490 /* 2491 * Returns true if it's possible this packet could be LROed. 2492 * if it returns false, it is guaranteed that tcp_lro_rx() 2493 * would not return zero. 2494 */ 2495 static bool 2496 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2497 { 2498 struct ether_header *eh; 2499 uint16_t eh_type; 2500 2501 eh = mtod(m, struct ether_header *); 2502 eh_type = ntohs(eh->ether_type); 2503 switch (eh_type) { 2504 #if defined(INET6) 2505 case ETHERTYPE_IPV6: 2506 return !v6_forwarding; 2507 #endif 2508 #if defined (INET) 2509 case ETHERTYPE_IP: 2510 return !v4_forwarding; 2511 #endif 2512 } 2513 2514 return false; 2515 } 2516 #else 2517 static void 2518 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2519 { 2520 } 2521 #endif 2522 2523 static bool 2524 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2525 { 2526 if_ctx_t ctx = rxq->ifr_ctx; 2527 if_shared_ctx_t sctx = ctx->ifc_sctx; 2528 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2529 int avail, i; 2530 qidx_t *cidxp; 2531 struct if_rxd_info ri; 2532 int err, budget_left, rx_bytes, rx_pkts; 2533 iflib_fl_t fl; 2534 struct ifnet *ifp; 2535 int lro_enabled; 2536 bool lro_possible = false; 2537 bool v4_forwarding, v6_forwarding; 2538 2539 /* 2540 * XXX early demux data packets so that if_input processing only handles 2541 * acks in interrupt context 2542 */ 2543 struct mbuf *m, *mh, *mt, *mf; 2544 2545 ifp = ctx->ifc_ifp; 2546 mh = mt = NULL; 2547 MPASS(budget > 0); 2548 rx_pkts = rx_bytes = 0; 2549 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2550 cidxp = &rxq->ifr_cq_cidx; 2551 else 2552 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2553 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2554 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2555 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2556 DBG_COUNTER_INC(rx_unavail); 2557 return (false); 2558 } 2559 2560 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2561 if (__predict_false(!CTX_ACTIVE(ctx))) { 2562 DBG_COUNTER_INC(rx_ctx_inactive); 2563 break; 2564 } 2565 /* 2566 * Reset client set fields to their default values 2567 */ 2568 rxd_info_zero(&ri); 2569 ri.iri_qsidx = rxq->ifr_id; 2570 ri.iri_cidx = *cidxp; 2571 ri.iri_ifp = ifp; 2572 ri.iri_frags = rxq->ifr_frags; 2573 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2574 2575 if (err) 2576 goto err; 2577 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2578 *cidxp = ri.iri_cidx; 2579 /* Update our consumer index */ 2580 /* XXX NB: shurd - check if this is still safe */ 2581 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2582 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2583 rxq->ifr_cq_gen = 0; 2584 } 2585 /* was this only a completion queue message? */ 2586 if (__predict_false(ri.iri_nfrags == 0)) 2587 continue; 2588 } 2589 MPASS(ri.iri_nfrags != 0); 2590 MPASS(ri.iri_len != 0); 2591 2592 /* will advance the cidx on the corresponding free lists */ 2593 m = iflib_rxd_pkt_get(rxq, &ri); 2594 if (avail == 0 && budget_left) 2595 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2596 2597 if (__predict_false(m == NULL)) { 2598 DBG_COUNTER_INC(rx_mbuf_null); 2599 continue; 2600 } 2601 /* imm_pkt: -- cxgb */ 2602 if (mh == NULL) 2603 mh = mt = m; 2604 else { 2605 mt->m_nextpkt = m; 2606 mt = m; 2607 } 2608 } 2609 /* make sure that we can refill faster than drain */ 2610 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2611 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2612 2613 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2614 if (lro_enabled) 2615 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2616 mt = mf = NULL; 2617 while (mh != NULL) { 2618 m = mh; 2619 mh = mh->m_nextpkt; 2620 m->m_nextpkt = NULL; 2621 #ifndef __NO_STRICT_ALIGNMENT 2622 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2623 continue; 2624 #endif 2625 rx_bytes += m->m_pkthdr.len; 2626 rx_pkts++; 2627 #if defined(INET6) || defined(INET) 2628 if (lro_enabled) { 2629 if (!lro_possible) { 2630 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2631 if (lro_possible && mf != NULL) { 2632 ifp->if_input(ifp, mf); 2633 DBG_COUNTER_INC(rx_if_input); 2634 mt = mf = NULL; 2635 } 2636 } 2637 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2638 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2639 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2640 continue; 2641 } 2642 } 2643 #endif 2644 if (lro_possible) { 2645 ifp->if_input(ifp, m); 2646 DBG_COUNTER_INC(rx_if_input); 2647 continue; 2648 } 2649 2650 if (mf == NULL) 2651 mf = m; 2652 if (mt != NULL) 2653 mt->m_nextpkt = m; 2654 mt = m; 2655 } 2656 if (mf != NULL) { 2657 ifp->if_input(ifp, mf); 2658 DBG_COUNTER_INC(rx_if_input); 2659 } 2660 2661 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2662 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2663 2664 /* 2665 * Flush any outstanding LRO work 2666 */ 2667 #if defined(INET6) || defined(INET) 2668 tcp_lro_flush_all(&rxq->ifr_lc); 2669 #endif 2670 if (avail) 2671 return true; 2672 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2673 err: 2674 CTX_LOCK(ctx); 2675 ctx->ifc_flags |= IFC_DO_RESET; 2676 iflib_admin_intr_deferred(ctx); 2677 CTX_UNLOCK(ctx); 2678 return (false); 2679 } 2680 2681 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2682 static inline qidx_t 2683 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2684 { 2685 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2686 qidx_t minthresh = txq->ift_size / 8; 2687 if (in_use > 4*minthresh) 2688 return (notify_count); 2689 if (in_use > 2*minthresh) 2690 return (notify_count >> 1); 2691 if (in_use > minthresh) 2692 return (notify_count >> 3); 2693 return (0); 2694 } 2695 2696 static inline qidx_t 2697 txq_max_rs_deferred(iflib_txq_t txq) 2698 { 2699 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2700 qidx_t minthresh = txq->ift_size / 8; 2701 if (txq->ift_in_use > 4*minthresh) 2702 return (notify_count); 2703 if (txq->ift_in_use > 2*minthresh) 2704 return (notify_count >> 1); 2705 if (txq->ift_in_use > minthresh) 2706 return (notify_count >> 2); 2707 return (2); 2708 } 2709 2710 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2711 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2712 2713 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2714 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2715 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2716 2717 /* forward compatibility for cxgb */ 2718 #define FIRST_QSET(ctx) 0 2719 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2720 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2721 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2722 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2723 2724 /* XXX we should be setting this to something other than zero */ 2725 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2726 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2727 2728 static inline bool 2729 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2730 { 2731 qidx_t dbval, max; 2732 bool rang; 2733 2734 rang = false; 2735 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2736 if (ring || txq->ift_db_pending >= max) { 2737 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2738 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2739 txq->ift_db_pending = txq->ift_npending = 0; 2740 rang = true; 2741 } 2742 return (rang); 2743 } 2744 2745 #ifdef PKT_DEBUG 2746 static void 2747 print_pkt(if_pkt_info_t pi) 2748 { 2749 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2750 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2751 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2752 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2753 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2754 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2755 } 2756 #endif 2757 2758 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2759 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2760 2761 static int 2762 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2763 { 2764 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2765 struct ether_vlan_header *eh; 2766 struct mbuf *m, *n; 2767 2768 n = m = *mp; 2769 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2770 M_WRITABLE(m) == 0) { 2771 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2772 return (ENOMEM); 2773 } else { 2774 m_freem(*mp); 2775 n = *mp = m; 2776 } 2777 } 2778 2779 /* 2780 * Determine where frame payload starts. 2781 * Jump over vlan headers if already present, 2782 * helpful for QinQ too. 2783 */ 2784 if (__predict_false(m->m_len < sizeof(*eh))) { 2785 txq->ift_pullups++; 2786 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2787 return (ENOMEM); 2788 } 2789 eh = mtod(m, struct ether_vlan_header *); 2790 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2791 pi->ipi_etype = ntohs(eh->evl_proto); 2792 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2793 } else { 2794 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2795 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2796 } 2797 2798 switch (pi->ipi_etype) { 2799 #ifdef INET 2800 case ETHERTYPE_IP: 2801 { 2802 struct ip *ip = NULL; 2803 struct tcphdr *th = NULL; 2804 int minthlen; 2805 2806 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2807 if (__predict_false(m->m_len < minthlen)) { 2808 /* 2809 * if this code bloat is causing too much of a hit 2810 * move it to a separate function and mark it noinline 2811 */ 2812 if (m->m_len == pi->ipi_ehdrlen) { 2813 n = m->m_next; 2814 MPASS(n); 2815 if (n->m_len >= sizeof(*ip)) { 2816 ip = (struct ip *)n->m_data; 2817 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2818 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2819 } else { 2820 txq->ift_pullups++; 2821 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2822 return (ENOMEM); 2823 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2824 } 2825 } else { 2826 txq->ift_pullups++; 2827 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2828 return (ENOMEM); 2829 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2830 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2831 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2832 } 2833 } else { 2834 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2835 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2836 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2837 } 2838 pi->ipi_ip_hlen = ip->ip_hl << 2; 2839 pi->ipi_ipproto = ip->ip_p; 2840 pi->ipi_flags |= IPI_TX_IPV4; 2841 2842 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2843 ip->ip_sum = 0; 2844 2845 if (IS_TSO4(pi)) { 2846 if (pi->ipi_ipproto == IPPROTO_TCP) { 2847 if (__predict_false(th == NULL)) { 2848 txq->ift_pullups++; 2849 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2850 return (ENOMEM); 2851 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2852 } 2853 pi->ipi_tcp_hflags = th->th_flags; 2854 pi->ipi_tcp_hlen = th->th_off << 2; 2855 pi->ipi_tcp_seq = th->th_seq; 2856 } 2857 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2858 return (ENXIO); 2859 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2860 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2861 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2862 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2863 ip->ip_sum = 0; 2864 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2865 } 2866 } 2867 break; 2868 } 2869 #endif 2870 #ifdef INET6 2871 case ETHERTYPE_IPV6: 2872 { 2873 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2874 struct tcphdr *th; 2875 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2876 2877 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2878 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2879 return (ENOMEM); 2880 } 2881 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2882 2883 /* XXX-BZ this will go badly in case of ext hdrs. */ 2884 pi->ipi_ipproto = ip6->ip6_nxt; 2885 pi->ipi_flags |= IPI_TX_IPV6; 2886 2887 if (IS_TSO6(pi)) { 2888 if (pi->ipi_ipproto == IPPROTO_TCP) { 2889 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2890 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2891 return (ENOMEM); 2892 } 2893 pi->ipi_tcp_hflags = th->th_flags; 2894 pi->ipi_tcp_hlen = th->th_off << 2; 2895 } 2896 2897 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2898 return (ENXIO); 2899 /* 2900 * The corresponding flag is set by the stack in the IPv4 2901 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2902 * So, set it here because the rest of the flow requires it. 2903 */ 2904 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2905 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2906 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2907 } 2908 break; 2909 } 2910 #endif 2911 default: 2912 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2913 pi->ipi_ip_hlen = 0; 2914 break; 2915 } 2916 *mp = m; 2917 2918 return (0); 2919 } 2920 2921 static __noinline struct mbuf * 2922 collapse_pkthdr(struct mbuf *m0) 2923 { 2924 struct mbuf *m, *m_next, *tmp; 2925 2926 m = m0; 2927 m_next = m->m_next; 2928 while (m_next != NULL && m_next->m_len == 0) { 2929 m = m_next; 2930 m->m_next = NULL; 2931 m_free(m); 2932 m_next = m_next->m_next; 2933 } 2934 m = m0; 2935 m->m_next = m_next; 2936 if ((m_next->m_flags & M_EXT) == 0) { 2937 m = m_defrag(m, M_NOWAIT); 2938 } else { 2939 tmp = m_next->m_next; 2940 memcpy(m_next, m, MPKTHSIZE); 2941 m = m_next; 2942 m->m_next = tmp; 2943 } 2944 return (m); 2945 } 2946 2947 /* 2948 * If dodgy hardware rejects the scatter gather chain we've handed it 2949 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2950 * m_defrag'd mbufs 2951 */ 2952 static __noinline struct mbuf * 2953 iflib_remove_mbuf(iflib_txq_t txq) 2954 { 2955 int ntxd, i, pidx; 2956 struct mbuf *m, *mh, **ifsd_m; 2957 2958 pidx = txq->ift_pidx; 2959 ifsd_m = txq->ift_sds.ifsd_m; 2960 ntxd = txq->ift_size; 2961 mh = m = ifsd_m[pidx]; 2962 ifsd_m[pidx] = NULL; 2963 #if MEMORY_LOGGING 2964 txq->ift_dequeued++; 2965 #endif 2966 i = 1; 2967 2968 while (m) { 2969 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2970 #if MEMORY_LOGGING 2971 txq->ift_dequeued++; 2972 #endif 2973 m = m->m_next; 2974 i++; 2975 } 2976 return (mh); 2977 } 2978 2979 static int 2980 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2981 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2982 int max_segs, int flags) 2983 { 2984 if_ctx_t ctx; 2985 if_shared_ctx_t sctx; 2986 if_softc_ctx_t scctx; 2987 int i, next, pidx, err, ntxd, count; 2988 struct mbuf *m, *tmp, **ifsd_m; 2989 2990 m = *m0; 2991 2992 /* 2993 * Please don't ever do this 2994 */ 2995 if (__predict_false(m->m_len == 0)) 2996 *m0 = m = collapse_pkthdr(m); 2997 2998 ctx = txq->ift_ctx; 2999 sctx = ctx->ifc_sctx; 3000 scctx = &ctx->ifc_softc_ctx; 3001 ifsd_m = txq->ift_sds.ifsd_m; 3002 ntxd = txq->ift_size; 3003 pidx = txq->ift_pidx; 3004 if (map != NULL) { 3005 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3006 3007 err = bus_dmamap_load_mbuf_sg(tag, map, 3008 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3009 if (err) 3010 return (err); 3011 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3012 count = 0; 3013 m = *m0; 3014 do { 3015 if (__predict_false(m->m_len <= 0)) { 3016 tmp = m; 3017 m = m->m_next; 3018 tmp->m_next = NULL; 3019 m_free(tmp); 3020 continue; 3021 } 3022 m = m->m_next; 3023 count++; 3024 } while (m != NULL); 3025 if (count > *nsegs) { 3026 ifsd_m[pidx] = *m0; 3027 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3028 return (0); 3029 } 3030 m = *m0; 3031 count = 0; 3032 do { 3033 next = (pidx + count) & (ntxd-1); 3034 MPASS(ifsd_m[next] == NULL); 3035 ifsd_m[next] = m; 3036 count++; 3037 tmp = m; 3038 m = m->m_next; 3039 } while (m != NULL); 3040 } else { 3041 int buflen, sgsize, maxsegsz, max_sgsize; 3042 vm_offset_t vaddr; 3043 vm_paddr_t curaddr; 3044 3045 count = i = 0; 3046 m = *m0; 3047 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3048 maxsegsz = scctx->isc_tx_tso_segsize_max; 3049 else 3050 maxsegsz = sctx->isc_tx_maxsegsize; 3051 3052 do { 3053 if (__predict_false(m->m_len <= 0)) { 3054 tmp = m; 3055 m = m->m_next; 3056 tmp->m_next = NULL; 3057 m_free(tmp); 3058 continue; 3059 } 3060 buflen = m->m_len; 3061 vaddr = (vm_offset_t)m->m_data; 3062 /* 3063 * see if we can't be smarter about physically 3064 * contiguous mappings 3065 */ 3066 next = (pidx + count) & (ntxd-1); 3067 MPASS(ifsd_m[next] == NULL); 3068 #if MEMORY_LOGGING 3069 txq->ift_enqueued++; 3070 #endif 3071 ifsd_m[next] = m; 3072 while (buflen > 0) { 3073 if (i >= max_segs) 3074 goto err; 3075 max_sgsize = MIN(buflen, maxsegsz); 3076 curaddr = pmap_kextract(vaddr); 3077 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3078 sgsize = MIN(sgsize, max_sgsize); 3079 segs[i].ds_addr = curaddr; 3080 segs[i].ds_len = sgsize; 3081 vaddr += sgsize; 3082 buflen -= sgsize; 3083 i++; 3084 } 3085 count++; 3086 tmp = m; 3087 m = m->m_next; 3088 } while (m != NULL); 3089 *nsegs = i; 3090 } 3091 return (0); 3092 err: 3093 *m0 = iflib_remove_mbuf(txq); 3094 return (EFBIG); 3095 } 3096 3097 static inline caddr_t 3098 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3099 { 3100 qidx_t size; 3101 int ntxd; 3102 caddr_t start, end, cur, next; 3103 3104 ntxd = txq->ift_size; 3105 size = txq->ift_txd_size[qid]; 3106 start = txq->ift_ifdi[qid].idi_vaddr; 3107 3108 if (__predict_false(size == 0)) 3109 return (start); 3110 cur = start + size*cidx; 3111 end = start + size*ntxd; 3112 next = CACHE_PTR_NEXT(cur); 3113 return (next < end ? next : start); 3114 } 3115 3116 /* 3117 * Pad an mbuf to ensure a minimum ethernet frame size. 3118 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3119 */ 3120 static __noinline int 3121 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3122 { 3123 /* 3124 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3125 * and ARP message is the smallest common payload I can think of 3126 */ 3127 static char pad[18]; /* just zeros */ 3128 int n; 3129 struct mbuf *new_head; 3130 3131 if (!M_WRITABLE(*m_head)) { 3132 new_head = m_dup(*m_head, M_NOWAIT); 3133 if (new_head == NULL) { 3134 m_freem(*m_head); 3135 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3136 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3137 return ENOMEM; 3138 } 3139 m_freem(*m_head); 3140 *m_head = new_head; 3141 } 3142 3143 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3144 n > 0; n -= sizeof(pad)) 3145 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3146 break; 3147 3148 if (n > 0) { 3149 m_freem(*m_head); 3150 device_printf(dev, "cannot pad short frame\n"); 3151 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3152 return (ENOBUFS); 3153 } 3154 3155 return 0; 3156 } 3157 3158 static int 3159 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3160 { 3161 if_ctx_t ctx; 3162 if_shared_ctx_t sctx; 3163 if_softc_ctx_t scctx; 3164 bus_dma_segment_t *segs; 3165 struct mbuf *m_head; 3166 void *next_txd; 3167 bus_dmamap_t map; 3168 struct if_pkt_info pi; 3169 int remap = 0; 3170 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3171 bus_dma_tag_t desc_tag; 3172 3173 segs = txq->ift_segs; 3174 ctx = txq->ift_ctx; 3175 sctx = ctx->ifc_sctx; 3176 scctx = &ctx->ifc_softc_ctx; 3177 segs = txq->ift_segs; 3178 ntxd = txq->ift_size; 3179 m_head = *m_headp; 3180 map = NULL; 3181 3182 /* 3183 * If we're doing TSO the next descriptor to clean may be quite far ahead 3184 */ 3185 cidx = txq->ift_cidx; 3186 pidx = txq->ift_pidx; 3187 if (ctx->ifc_flags & IFC_PREFETCH) { 3188 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3189 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3190 next_txd = calc_next_txd(txq, cidx, 0); 3191 prefetch(next_txd); 3192 } 3193 3194 /* prefetch the next cache line of mbuf pointers and flags */ 3195 prefetch(&txq->ift_sds.ifsd_m[next]); 3196 if (txq->ift_sds.ifsd_map != NULL) { 3197 prefetch(&txq->ift_sds.ifsd_map[next]); 3198 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3199 prefetch(&txq->ift_sds.ifsd_flags[next]); 3200 } 3201 } else if (txq->ift_sds.ifsd_map != NULL) 3202 map = txq->ift_sds.ifsd_map[pidx]; 3203 3204 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3205 desc_tag = txq->ift_tso_desc_tag; 3206 max_segs = scctx->isc_tx_tso_segments_max; 3207 } else { 3208 desc_tag = txq->ift_desc_tag; 3209 max_segs = scctx->isc_tx_nsegments; 3210 } 3211 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3212 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3213 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3214 if (err) 3215 return err; 3216 } 3217 m_head = *m_headp; 3218 3219 pkt_info_zero(&pi); 3220 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3221 pi.ipi_pidx = pidx; 3222 pi.ipi_qsidx = txq->ift_id; 3223 pi.ipi_len = m_head->m_pkthdr.len; 3224 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3225 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3226 3227 /* deliberate bitwise OR to make one condition */ 3228 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3229 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3230 return (err); 3231 m_head = *m_headp; 3232 } 3233 3234 retry: 3235 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3236 defrag: 3237 if (__predict_false(err)) { 3238 switch (err) { 3239 case EFBIG: 3240 /* try collapse once and defrag once */ 3241 if (remap == 0) 3242 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3243 if (remap == 1) 3244 m_head = m_defrag(*m_headp, M_NOWAIT); 3245 remap++; 3246 if (__predict_false(m_head == NULL)) 3247 goto defrag_failed; 3248 txq->ift_mbuf_defrag++; 3249 *m_headp = m_head; 3250 goto retry; 3251 break; 3252 case ENOMEM: 3253 txq->ift_no_tx_dma_setup++; 3254 break; 3255 default: 3256 txq->ift_no_tx_dma_setup++; 3257 m_freem(*m_headp); 3258 DBG_COUNTER_INC(tx_frees); 3259 *m_headp = NULL; 3260 break; 3261 } 3262 txq->ift_map_failed++; 3263 DBG_COUNTER_INC(encap_load_mbuf_fail); 3264 return (err); 3265 } 3266 3267 /* 3268 * XXX assumes a 1 to 1 relationship between segments and 3269 * descriptors - this does not hold true on all drivers, e.g. 3270 * cxgb 3271 */ 3272 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3273 txq->ift_no_desc_avail++; 3274 if (map != NULL) 3275 bus_dmamap_unload(desc_tag, map); 3276 DBG_COUNTER_INC(encap_txq_avail_fail); 3277 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3278 GROUPTASK_ENQUEUE(&txq->ift_task); 3279 return (ENOBUFS); 3280 } 3281 /* 3282 * On Intel cards we can greatly reduce the number of TX interrupts 3283 * we see by only setting report status on every Nth descriptor. 3284 * However, this also means that the driver will need to keep track 3285 * of the descriptors that RS was set on to check them for the DD bit. 3286 */ 3287 txq->ift_rs_pending += nsegs + 1; 3288 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3289 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3290 pi.ipi_flags |= IPI_TX_INTR; 3291 txq->ift_rs_pending = 0; 3292 } 3293 3294 pi.ipi_segs = segs; 3295 pi.ipi_nsegs = nsegs; 3296 3297 MPASS(pidx >= 0 && pidx < txq->ift_size); 3298 #ifdef PKT_DEBUG 3299 print_pkt(&pi); 3300 #endif 3301 if (map != NULL) 3302 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3303 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3304 if (map != NULL) 3305 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3306 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3307 DBG_COUNTER_INC(tx_encap); 3308 MPASS(pi.ipi_new_pidx < txq->ift_size); 3309 3310 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3311 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3312 ndesc += txq->ift_size; 3313 txq->ift_gen = 1; 3314 } 3315 /* 3316 * drivers can need as many as 3317 * two sentinels 3318 */ 3319 MPASS(ndesc <= pi.ipi_nsegs + 2); 3320 MPASS(pi.ipi_new_pidx != pidx); 3321 MPASS(ndesc > 0); 3322 txq->ift_in_use += ndesc; 3323 3324 /* 3325 * We update the last software descriptor again here because there may 3326 * be a sentinel and/or there may be more mbufs than segments 3327 */ 3328 txq->ift_pidx = pi.ipi_new_pidx; 3329 txq->ift_npending += pi.ipi_ndescs; 3330 } else if (__predict_false(err == EFBIG && remap < 2)) { 3331 *m_headp = m_head = iflib_remove_mbuf(txq); 3332 remap = 1; 3333 txq->ift_txd_encap_efbig++; 3334 goto defrag; 3335 } else 3336 DBG_COUNTER_INC(encap_txd_encap_fail); 3337 return (err); 3338 3339 defrag_failed: 3340 txq->ift_mbuf_defrag_failed++; 3341 txq->ift_map_failed++; 3342 m_freem(*m_headp); 3343 DBG_COUNTER_INC(tx_frees); 3344 *m_headp = NULL; 3345 return (ENOMEM); 3346 } 3347 3348 static void 3349 iflib_tx_desc_free(iflib_txq_t txq, int n) 3350 { 3351 int hasmap; 3352 uint32_t qsize, cidx, mask, gen; 3353 struct mbuf *m, **ifsd_m; 3354 uint8_t *ifsd_flags; 3355 bus_dmamap_t *ifsd_map; 3356 bool do_prefetch; 3357 3358 cidx = txq->ift_cidx; 3359 gen = txq->ift_gen; 3360 qsize = txq->ift_size; 3361 mask = qsize-1; 3362 hasmap = txq->ift_sds.ifsd_map != NULL; 3363 ifsd_flags = txq->ift_sds.ifsd_flags; 3364 ifsd_m = txq->ift_sds.ifsd_m; 3365 ifsd_map = txq->ift_sds.ifsd_map; 3366 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3367 3368 while (n--) { 3369 if (do_prefetch) { 3370 prefetch(ifsd_m[(cidx + 3) & mask]); 3371 prefetch(ifsd_m[(cidx + 4) & mask]); 3372 } 3373 if (ifsd_m[cidx] != NULL) { 3374 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3375 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3376 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3377 /* 3378 * does it matter if it's not the TSO tag? If so we'll 3379 * have to add the type to flags 3380 */ 3381 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3382 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3383 } 3384 if ((m = ifsd_m[cidx]) != NULL) { 3385 /* XXX we don't support any drivers that batch packets yet */ 3386 MPASS(m->m_nextpkt == NULL); 3387 /* if the number of clusters exceeds the number of segments 3388 * there won't be space on the ring to save a pointer to each 3389 * cluster so we simply free the list here 3390 */ 3391 if (m->m_flags & M_TOOBIG) { 3392 m_freem(m); 3393 } else { 3394 m_free(m); 3395 } 3396 ifsd_m[cidx] = NULL; 3397 #if MEMORY_LOGGING 3398 txq->ift_dequeued++; 3399 #endif 3400 DBG_COUNTER_INC(tx_frees); 3401 } 3402 } 3403 if (__predict_false(++cidx == qsize)) { 3404 cidx = 0; 3405 gen = 0; 3406 } 3407 } 3408 txq->ift_cidx = cidx; 3409 txq->ift_gen = gen; 3410 } 3411 3412 static __inline int 3413 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3414 { 3415 int reclaim; 3416 if_ctx_t ctx = txq->ift_ctx; 3417 3418 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3419 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3420 3421 /* 3422 * Need a rate-limiting check so that this isn't called every time 3423 */ 3424 iflib_tx_credits_update(ctx, txq); 3425 reclaim = DESC_RECLAIMABLE(txq); 3426 3427 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3428 #ifdef INVARIANTS 3429 if (iflib_verbose_debug) { 3430 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3431 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3432 reclaim, thresh); 3433 3434 } 3435 #endif 3436 return (0); 3437 } 3438 iflib_tx_desc_free(txq, reclaim); 3439 txq->ift_cleaned += reclaim; 3440 txq->ift_in_use -= reclaim; 3441 3442 return (reclaim); 3443 } 3444 3445 static struct mbuf ** 3446 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3447 { 3448 int next, size; 3449 struct mbuf **items; 3450 3451 size = r->size; 3452 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3453 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3454 3455 prefetch(items[(cidx + offset) & (size-1)]); 3456 if (remaining > 1) { 3457 prefetch2cachelines(&items[next]); 3458 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3459 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3460 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3461 } 3462 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3463 } 3464 3465 static void 3466 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3467 { 3468 3469 ifmp_ring_check_drainage(txq->ift_br, budget); 3470 } 3471 3472 static uint32_t 3473 iflib_txq_can_drain(struct ifmp_ring *r) 3474 { 3475 iflib_txq_t txq = r->cookie; 3476 if_ctx_t ctx = txq->ift_ctx; 3477 3478 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3479 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3480 } 3481 3482 static uint32_t 3483 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3484 { 3485 iflib_txq_t txq = r->cookie; 3486 if_ctx_t ctx = txq->ift_ctx; 3487 struct ifnet *ifp = ctx->ifc_ifp; 3488 struct mbuf **mp, *m; 3489 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3490 int reclaimed, err, in_use_prev, desc_used; 3491 bool do_prefetch, ring, rang; 3492 3493 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3494 !LINK_ACTIVE(ctx))) { 3495 DBG_COUNTER_INC(txq_drain_notready); 3496 return (0); 3497 } 3498 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3499 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3500 avail = IDXDIFF(pidx, cidx, r->size); 3501 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3502 DBG_COUNTER_INC(txq_drain_flushing); 3503 for (i = 0; i < avail; i++) { 3504 m_free(r->items[(cidx + i) & (r->size-1)]); 3505 r->items[(cidx + i) & (r->size-1)] = NULL; 3506 } 3507 return (avail); 3508 } 3509 3510 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3511 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3512 CALLOUT_LOCK(txq); 3513 callout_stop(&txq->ift_timer); 3514 CALLOUT_UNLOCK(txq); 3515 DBG_COUNTER_INC(txq_drain_oactive); 3516 return (0); 3517 } 3518 if (reclaimed) 3519 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3520 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3521 count = MIN(avail, TX_BATCH_SIZE); 3522 #ifdef INVARIANTS 3523 if (iflib_verbose_debug) 3524 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3525 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3526 #endif 3527 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3528 avail = TXQ_AVAIL(txq); 3529 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3530 int pidx_prev, rem = do_prefetch ? count - i : 0; 3531 3532 mp = _ring_peek_one(r, cidx, i, rem); 3533 MPASS(mp != NULL && *mp != NULL); 3534 if (__predict_false(*mp == (struct mbuf *)txq)) { 3535 consumed++; 3536 reclaimed++; 3537 continue; 3538 } 3539 in_use_prev = txq->ift_in_use; 3540 pidx_prev = txq->ift_pidx; 3541 err = iflib_encap(txq, mp); 3542 if (__predict_false(err)) { 3543 DBG_COUNTER_INC(txq_drain_encapfail); 3544 /* no room - bail out */ 3545 if (err == ENOBUFS) 3546 break; 3547 consumed++; 3548 DBG_COUNTER_INC(txq_drain_encapfail); 3549 /* we can't send this packet - skip it */ 3550 continue; 3551 } 3552 consumed++; 3553 pkt_sent++; 3554 m = *mp; 3555 DBG_COUNTER_INC(tx_sent); 3556 bytes_sent += m->m_pkthdr.len; 3557 mcast_sent += !!(m->m_flags & M_MCAST); 3558 avail = TXQ_AVAIL(txq); 3559 3560 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3561 desc_used += (txq->ift_in_use - in_use_prev); 3562 ETHER_BPF_MTAP(ifp, m); 3563 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3564 break; 3565 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3566 } 3567 3568 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3569 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3570 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3571 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3572 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3573 if (mcast_sent) 3574 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3575 #ifdef INVARIANTS 3576 if (iflib_verbose_debug) 3577 printf("consumed=%d\n", consumed); 3578 #endif 3579 return (consumed); 3580 } 3581 3582 static uint32_t 3583 iflib_txq_drain_always(struct ifmp_ring *r) 3584 { 3585 return (1); 3586 } 3587 3588 static uint32_t 3589 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3590 { 3591 int i, avail; 3592 struct mbuf **mp; 3593 iflib_txq_t txq; 3594 3595 txq = r->cookie; 3596 3597 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3598 CALLOUT_LOCK(txq); 3599 callout_stop(&txq->ift_timer); 3600 CALLOUT_UNLOCK(txq); 3601 3602 avail = IDXDIFF(pidx, cidx, r->size); 3603 for (i = 0; i < avail; i++) { 3604 mp = _ring_peek_one(r, cidx, i, avail - i); 3605 if (__predict_false(*mp == (struct mbuf *)txq)) 3606 continue; 3607 m_freem(*mp); 3608 } 3609 MPASS(ifmp_ring_is_stalled(r) == 0); 3610 return (avail); 3611 } 3612 3613 static void 3614 iflib_ifmp_purge(iflib_txq_t txq) 3615 { 3616 struct ifmp_ring *r; 3617 3618 r = txq->ift_br; 3619 r->drain = iflib_txq_drain_free; 3620 r->can_drain = iflib_txq_drain_always; 3621 3622 ifmp_ring_check_drainage(r, r->size); 3623 3624 r->drain = iflib_txq_drain; 3625 r->can_drain = iflib_txq_can_drain; 3626 } 3627 3628 static void 3629 _task_fn_tx(void *context) 3630 { 3631 iflib_txq_t txq = context; 3632 if_ctx_t ctx = txq->ift_ctx; 3633 struct ifnet *ifp = ctx->ifc_ifp; 3634 int rc; 3635 3636 #ifdef IFLIB_DIAGNOSTICS 3637 txq->ift_cpu_exec_count[curcpu]++; 3638 #endif 3639 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3640 return; 3641 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3642 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3643 netmap_tx_irq(ifp, txq->ift_id); 3644 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3645 return; 3646 } 3647 if (txq->ift_db_pending) 3648 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3649 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3650 if (ctx->ifc_flags & IFC_LEGACY) 3651 IFDI_INTR_ENABLE(ctx); 3652 else { 3653 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3654 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3655 } 3656 } 3657 3658 static void 3659 _task_fn_rx(void *context) 3660 { 3661 iflib_rxq_t rxq = context; 3662 if_ctx_t ctx = rxq->ifr_ctx; 3663 bool more; 3664 int rc; 3665 uint16_t budget; 3666 3667 #ifdef IFLIB_DIAGNOSTICS 3668 rxq->ifr_cpu_exec_count[curcpu]++; 3669 #endif 3670 DBG_COUNTER_INC(task_fn_rxs); 3671 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3672 return; 3673 more = true; 3674 #ifdef DEV_NETMAP 3675 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3676 u_int work = 0; 3677 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3678 more = false; 3679 } 3680 } 3681 #endif 3682 budget = ctx->ifc_sysctl_rx_budget; 3683 if (budget == 0) 3684 budget = 16; /* XXX */ 3685 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3686 if (ctx->ifc_flags & IFC_LEGACY) 3687 IFDI_INTR_ENABLE(ctx); 3688 else { 3689 DBG_COUNTER_INC(rx_intr_enables); 3690 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3691 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3692 } 3693 } 3694 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3695 return; 3696 if (more) 3697 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3698 } 3699 3700 static void 3701 _task_fn_admin(void *context) 3702 { 3703 if_ctx_t ctx = context; 3704 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3705 iflib_txq_t txq; 3706 int i; 3707 3708 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3709 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3710 return; 3711 } 3712 } 3713 3714 CTX_LOCK(ctx); 3715 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3716 CALLOUT_LOCK(txq); 3717 callout_stop(&txq->ift_timer); 3718 CALLOUT_UNLOCK(txq); 3719 } 3720 IFDI_UPDATE_ADMIN_STATUS(ctx); 3721 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3722 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3723 IFDI_LINK_INTR_ENABLE(ctx); 3724 if (ctx->ifc_flags & IFC_DO_RESET) { 3725 ctx->ifc_flags &= ~IFC_DO_RESET; 3726 iflib_if_init_locked(ctx); 3727 } 3728 CTX_UNLOCK(ctx); 3729 3730 if (LINK_ACTIVE(ctx) == 0) 3731 return; 3732 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3733 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3734 } 3735 3736 3737 static void 3738 _task_fn_iov(void *context) 3739 { 3740 if_ctx_t ctx = context; 3741 3742 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3743 return; 3744 3745 CTX_LOCK(ctx); 3746 IFDI_VFLR_HANDLE(ctx); 3747 CTX_UNLOCK(ctx); 3748 } 3749 3750 static int 3751 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3752 { 3753 int err; 3754 if_int_delay_info_t info; 3755 if_ctx_t ctx; 3756 3757 info = (if_int_delay_info_t)arg1; 3758 ctx = info->iidi_ctx; 3759 info->iidi_req = req; 3760 info->iidi_oidp = oidp; 3761 CTX_LOCK(ctx); 3762 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3763 CTX_UNLOCK(ctx); 3764 return (err); 3765 } 3766 3767 /********************************************************************* 3768 * 3769 * IFNET FUNCTIONS 3770 * 3771 **********************************************************************/ 3772 3773 static void 3774 iflib_if_init_locked(if_ctx_t ctx) 3775 { 3776 iflib_stop(ctx); 3777 iflib_init_locked(ctx); 3778 } 3779 3780 3781 static void 3782 iflib_if_init(void *arg) 3783 { 3784 if_ctx_t ctx = arg; 3785 3786 CTX_LOCK(ctx); 3787 iflib_if_init_locked(ctx); 3788 CTX_UNLOCK(ctx); 3789 } 3790 3791 static int 3792 iflib_if_transmit(if_t ifp, struct mbuf *m) 3793 { 3794 if_ctx_t ctx = if_getsoftc(ifp); 3795 3796 iflib_txq_t txq; 3797 int err, qidx; 3798 3799 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3800 DBG_COUNTER_INC(tx_frees); 3801 m_freem(m); 3802 return (ENOBUFS); 3803 } 3804 3805 MPASS(m->m_nextpkt == NULL); 3806 qidx = 0; 3807 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3808 qidx = QIDX(ctx, m); 3809 /* 3810 * XXX calculate buf_ring based on flowid (divvy up bits?) 3811 */ 3812 txq = &ctx->ifc_txqs[qidx]; 3813 3814 #ifdef DRIVER_BACKPRESSURE 3815 if (txq->ift_closed) { 3816 while (m != NULL) { 3817 next = m->m_nextpkt; 3818 m->m_nextpkt = NULL; 3819 m_freem(m); 3820 m = next; 3821 } 3822 return (ENOBUFS); 3823 } 3824 #endif 3825 #ifdef notyet 3826 qidx = count = 0; 3827 mp = marr; 3828 next = m; 3829 do { 3830 count++; 3831 next = next->m_nextpkt; 3832 } while (next != NULL); 3833 3834 if (count > nitems(marr)) 3835 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3836 /* XXX check nextpkt */ 3837 m_freem(m); 3838 /* XXX simplify for now */ 3839 DBG_COUNTER_INC(tx_frees); 3840 return (ENOBUFS); 3841 } 3842 for (next = m, i = 0; next != NULL; i++) { 3843 mp[i] = next; 3844 next = next->m_nextpkt; 3845 mp[i]->m_nextpkt = NULL; 3846 } 3847 #endif 3848 DBG_COUNTER_INC(tx_seen); 3849 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3850 3851 GROUPTASK_ENQUEUE(&txq->ift_task); 3852 if (err) { 3853 /* support forthcoming later */ 3854 #ifdef DRIVER_BACKPRESSURE 3855 txq->ift_closed = TRUE; 3856 #endif 3857 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3858 m_freem(m); 3859 } 3860 3861 return (err); 3862 } 3863 3864 static void 3865 iflib_if_qflush(if_t ifp) 3866 { 3867 if_ctx_t ctx = if_getsoftc(ifp); 3868 iflib_txq_t txq = ctx->ifc_txqs; 3869 int i; 3870 3871 CTX_LOCK(ctx); 3872 ctx->ifc_flags |= IFC_QFLUSH; 3873 CTX_UNLOCK(ctx); 3874 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3875 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3876 iflib_txq_check_drain(txq, 0); 3877 CTX_LOCK(ctx); 3878 ctx->ifc_flags &= ~IFC_QFLUSH; 3879 CTX_UNLOCK(ctx); 3880 3881 if_qflush(ifp); 3882 } 3883 3884 3885 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3886 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3887 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3888 3889 static int 3890 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3891 { 3892 if_ctx_t ctx = if_getsoftc(ifp); 3893 struct ifreq *ifr = (struct ifreq *)data; 3894 #if defined(INET) || defined(INET6) 3895 struct ifaddr *ifa = (struct ifaddr *)data; 3896 #endif 3897 bool avoid_reset = FALSE; 3898 int err = 0, reinit = 0, bits; 3899 3900 switch (command) { 3901 case SIOCSIFADDR: 3902 #ifdef INET 3903 if (ifa->ifa_addr->sa_family == AF_INET) 3904 avoid_reset = TRUE; 3905 #endif 3906 #ifdef INET6 3907 if (ifa->ifa_addr->sa_family == AF_INET6) 3908 avoid_reset = TRUE; 3909 #endif 3910 /* 3911 ** Calling init results in link renegotiation, 3912 ** so we avoid doing it when possible. 3913 */ 3914 if (avoid_reset) { 3915 if_setflagbits(ifp, IFF_UP,0); 3916 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3917 reinit = 1; 3918 #ifdef INET 3919 if (!(if_getflags(ifp) & IFF_NOARP)) 3920 arp_ifinit(ifp, ifa); 3921 #endif 3922 } else 3923 err = ether_ioctl(ifp, command, data); 3924 break; 3925 case SIOCSIFMTU: 3926 CTX_LOCK(ctx); 3927 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3928 CTX_UNLOCK(ctx); 3929 break; 3930 } 3931 bits = if_getdrvflags(ifp); 3932 /* stop the driver and free any clusters before proceeding */ 3933 iflib_stop(ctx); 3934 3935 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3936 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3937 ctx->ifc_flags |= IFC_MULTISEG; 3938 else 3939 ctx->ifc_flags &= ~IFC_MULTISEG; 3940 err = if_setmtu(ifp, ifr->ifr_mtu); 3941 } 3942 iflib_init_locked(ctx); 3943 if_setdrvflags(ifp, bits); 3944 CTX_UNLOCK(ctx); 3945 break; 3946 case SIOCSIFFLAGS: 3947 CTX_LOCK(ctx); 3948 if (if_getflags(ifp) & IFF_UP) { 3949 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3950 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3951 (IFF_PROMISC | IFF_ALLMULTI)) { 3952 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3953 } 3954 } else 3955 reinit = 1; 3956 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3957 iflib_stop(ctx); 3958 } 3959 ctx->ifc_if_flags = if_getflags(ifp); 3960 CTX_UNLOCK(ctx); 3961 break; 3962 case SIOCADDMULTI: 3963 case SIOCDELMULTI: 3964 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3965 CTX_LOCK(ctx); 3966 IFDI_INTR_DISABLE(ctx); 3967 IFDI_MULTI_SET(ctx); 3968 IFDI_INTR_ENABLE(ctx); 3969 CTX_UNLOCK(ctx); 3970 } 3971 break; 3972 case SIOCSIFMEDIA: 3973 CTX_LOCK(ctx); 3974 IFDI_MEDIA_SET(ctx); 3975 CTX_UNLOCK(ctx); 3976 /* falls thru */ 3977 case SIOCGIFMEDIA: 3978 case SIOCGIFXMEDIA: 3979 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3980 break; 3981 case SIOCGI2C: 3982 { 3983 struct ifi2creq i2c; 3984 3985 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3986 if (err != 0) 3987 break; 3988 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3989 err = EINVAL; 3990 break; 3991 } 3992 if (i2c.len > sizeof(i2c.data)) { 3993 err = EINVAL; 3994 break; 3995 } 3996 3997 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3998 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3999 break; 4000 } 4001 case SIOCSIFCAP: 4002 { 4003 int mask, setmask; 4004 4005 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4006 setmask = 0; 4007 #ifdef TCP_OFFLOAD 4008 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4009 #endif 4010 setmask |= (mask & IFCAP_FLAGS); 4011 4012 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4013 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4014 if ((mask & IFCAP_WOL) && 4015 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4016 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4017 if_vlancap(ifp); 4018 /* 4019 * want to ensure that traffic has stopped before we change any of the flags 4020 */ 4021 if (setmask) { 4022 CTX_LOCK(ctx); 4023 bits = if_getdrvflags(ifp); 4024 if (bits & IFF_DRV_RUNNING) 4025 iflib_stop(ctx); 4026 if_togglecapenable(ifp, setmask); 4027 if (bits & IFF_DRV_RUNNING) 4028 iflib_init_locked(ctx); 4029 if_setdrvflags(ifp, bits); 4030 CTX_UNLOCK(ctx); 4031 } 4032 break; 4033 } 4034 case SIOCGPRIVATE_0: 4035 case SIOCSDRVSPEC: 4036 case SIOCGDRVSPEC: 4037 CTX_LOCK(ctx); 4038 err = IFDI_PRIV_IOCTL(ctx, command, data); 4039 CTX_UNLOCK(ctx); 4040 break; 4041 default: 4042 err = ether_ioctl(ifp, command, data); 4043 break; 4044 } 4045 if (reinit) 4046 iflib_if_init(ctx); 4047 return (err); 4048 } 4049 4050 static uint64_t 4051 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4052 { 4053 if_ctx_t ctx = if_getsoftc(ifp); 4054 4055 return (IFDI_GET_COUNTER(ctx, cnt)); 4056 } 4057 4058 /********************************************************************* 4059 * 4060 * OTHER FUNCTIONS EXPORTED TO THE STACK 4061 * 4062 **********************************************************************/ 4063 4064 static void 4065 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4066 { 4067 if_ctx_t ctx = if_getsoftc(ifp); 4068 4069 if ((void *)ctx != arg) 4070 return; 4071 4072 if ((vtag == 0) || (vtag > 4095)) 4073 return; 4074 4075 CTX_LOCK(ctx); 4076 IFDI_VLAN_REGISTER(ctx, vtag); 4077 /* Re-init to load the changes */ 4078 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4079 iflib_if_init_locked(ctx); 4080 CTX_UNLOCK(ctx); 4081 } 4082 4083 static void 4084 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4085 { 4086 if_ctx_t ctx = if_getsoftc(ifp); 4087 4088 if ((void *)ctx != arg) 4089 return; 4090 4091 if ((vtag == 0) || (vtag > 4095)) 4092 return; 4093 4094 CTX_LOCK(ctx); 4095 IFDI_VLAN_UNREGISTER(ctx, vtag); 4096 /* Re-init to load the changes */ 4097 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4098 iflib_if_init_locked(ctx); 4099 CTX_UNLOCK(ctx); 4100 } 4101 4102 static void 4103 iflib_led_func(void *arg, int onoff) 4104 { 4105 if_ctx_t ctx = arg; 4106 4107 CTX_LOCK(ctx); 4108 IFDI_LED_FUNC(ctx, onoff); 4109 CTX_UNLOCK(ctx); 4110 } 4111 4112 /********************************************************************* 4113 * 4114 * BUS FUNCTION DEFINITIONS 4115 * 4116 **********************************************************************/ 4117 4118 int 4119 iflib_device_probe(device_t dev) 4120 { 4121 pci_vendor_info_t *ent; 4122 4123 uint16_t pci_vendor_id, pci_device_id; 4124 uint16_t pci_subvendor_id, pci_subdevice_id; 4125 uint16_t pci_rev_id; 4126 if_shared_ctx_t sctx; 4127 4128 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4129 return (ENOTSUP); 4130 4131 pci_vendor_id = pci_get_vendor(dev); 4132 pci_device_id = pci_get_device(dev); 4133 pci_subvendor_id = pci_get_subvendor(dev); 4134 pci_subdevice_id = pci_get_subdevice(dev); 4135 pci_rev_id = pci_get_revid(dev); 4136 if (sctx->isc_parse_devinfo != NULL) 4137 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4138 4139 ent = sctx->isc_vendor_info; 4140 while (ent->pvi_vendor_id != 0) { 4141 if (pci_vendor_id != ent->pvi_vendor_id) { 4142 ent++; 4143 continue; 4144 } 4145 if ((pci_device_id == ent->pvi_device_id) && 4146 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4147 (ent->pvi_subvendor_id == 0)) && 4148 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4149 (ent->pvi_subdevice_id == 0)) && 4150 ((pci_rev_id == ent->pvi_rev_id) || 4151 (ent->pvi_rev_id == 0))) { 4152 4153 device_set_desc_copy(dev, ent->pvi_name); 4154 /* this needs to be changed to zero if the bus probing code 4155 * ever stops re-probing on best match because the sctx 4156 * may have its values over written by register calls 4157 * in subsequent probes 4158 */ 4159 return (BUS_PROBE_DEFAULT); 4160 } 4161 ent++; 4162 } 4163 return (ENXIO); 4164 } 4165 4166 int 4167 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4168 { 4169 int err, rid, msix, msix_bar; 4170 if_ctx_t ctx; 4171 if_t ifp; 4172 if_softc_ctx_t scctx; 4173 int i; 4174 uint16_t main_txq; 4175 uint16_t main_rxq; 4176 4177 4178 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4179 4180 if (sc == NULL) { 4181 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4182 device_set_softc(dev, ctx); 4183 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4184 } 4185 4186 ctx->ifc_sctx = sctx; 4187 ctx->ifc_dev = dev; 4188 ctx->ifc_softc = sc; 4189 4190 if ((err = iflib_register(ctx)) != 0) { 4191 device_printf(dev, "iflib_register failed %d\n", err); 4192 return (err); 4193 } 4194 iflib_add_device_sysctl_pre(ctx); 4195 4196 scctx = &ctx->ifc_softc_ctx; 4197 ifp = ctx->ifc_ifp; 4198 4199 /* 4200 * XXX sanity check that ntxd & nrxd are a power of 2 4201 */ 4202 if (ctx->ifc_sysctl_ntxqs != 0) 4203 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4204 if (ctx->ifc_sysctl_nrxqs != 0) 4205 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4206 4207 for (i = 0; i < sctx->isc_ntxqs; i++) { 4208 if (ctx->ifc_sysctl_ntxds[i] != 0) 4209 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4210 else 4211 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4212 } 4213 4214 for (i = 0; i < sctx->isc_nrxqs; i++) { 4215 if (ctx->ifc_sysctl_nrxds[i] != 0) 4216 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4217 else 4218 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4219 } 4220 4221 for (i = 0; i < sctx->isc_nrxqs; i++) { 4222 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4223 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4224 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4225 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4226 } 4227 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4228 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4229 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4230 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4231 } 4232 } 4233 4234 for (i = 0; i < sctx->isc_ntxqs; i++) { 4235 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4236 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4237 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4238 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4239 } 4240 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4241 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4242 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4243 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4244 } 4245 } 4246 4247 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4248 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4249 return (err); 4250 } 4251 _iflib_pre_assert(scctx); 4252 ctx->ifc_txrx = *scctx->isc_txrx; 4253 4254 #ifdef INVARIANTS 4255 MPASS(scctx->isc_capenable); 4256 if (scctx->isc_capenable & IFCAP_TXCSUM) 4257 MPASS(scctx->isc_tx_csum_flags); 4258 #endif 4259 4260 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4261 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4262 4263 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4264 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4265 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4266 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4267 4268 #ifdef ACPI_DMAR 4269 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4270 ctx->ifc_flags |= IFC_DMAR; 4271 #elif !(defined(__i386__) || defined(__amd64__)) 4272 /* set unconditionally for !x86 */ 4273 ctx->ifc_flags |= IFC_DMAR; 4274 #endif 4275 4276 msix_bar = scctx->isc_msix_bar; 4277 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4278 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4279 4280 /* XXX change for per-queue sizes */ 4281 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4282 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4283 for (i = 0; i < sctx->isc_nrxqs; i++) { 4284 if (!powerof2(scctx->isc_nrxd[i])) { 4285 /* round down instead? */ 4286 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4287 err = EINVAL; 4288 goto fail; 4289 } 4290 } 4291 for (i = 0; i < sctx->isc_ntxqs; i++) { 4292 if (!powerof2(scctx->isc_ntxd[i])) { 4293 device_printf(dev, 4294 "# tx descriptors must be a power of 2"); 4295 err = EINVAL; 4296 goto fail; 4297 } 4298 } 4299 4300 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4301 MAX_SINGLE_PACKET_FRACTION) 4302 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4303 MAX_SINGLE_PACKET_FRACTION); 4304 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4305 MAX_SINGLE_PACKET_FRACTION) 4306 scctx->isc_tx_tso_segments_max = max(1, 4307 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4308 4309 /* 4310 * Protect the stack against modern hardware 4311 */ 4312 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4313 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4314 4315 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4316 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4317 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4318 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4319 if (scctx->isc_rss_table_size == 0) 4320 scctx->isc_rss_table_size = 64; 4321 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4322 4323 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4324 /* XXX format name */ 4325 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4326 4327 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4328 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4329 device_printf(dev, "Unable to fetch CPU list\n"); 4330 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4331 } 4332 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4333 4334 /* 4335 ** Now setup MSI or MSI/X, should 4336 ** return us the number of supported 4337 ** vectors. (Will be 1 for MSI) 4338 */ 4339 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4340 msix = scctx->isc_vectors; 4341 } else if (scctx->isc_msix_bar != 0) 4342 /* 4343 * The simple fact that isc_msix_bar is not 0 does not mean we 4344 * we have a good value there that is known to work. 4345 */ 4346 msix = iflib_msix_init(ctx); 4347 else { 4348 scctx->isc_vectors = 1; 4349 scctx->isc_ntxqsets = 1; 4350 scctx->isc_nrxqsets = 1; 4351 scctx->isc_intr = IFLIB_INTR_LEGACY; 4352 msix = 0; 4353 } 4354 /* Get memory for the station queues */ 4355 if ((err = iflib_queues_alloc(ctx))) { 4356 device_printf(dev, "Unable to allocate queue memory\n"); 4357 goto fail; 4358 } 4359 4360 if ((err = iflib_qset_structures_setup(ctx))) { 4361 device_printf(dev, "qset structure setup failed %d\n", err); 4362 goto fail_queues; 4363 } 4364 4365 /* 4366 * Group taskqueues aren't properly set up until SMP is started, 4367 * so we disable interrupts until we can handle them post 4368 * SI_SUB_SMP. 4369 * 4370 * XXX: disabling interrupts doesn't actually work, at least for 4371 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4372 * we do null handling and depend on this not causing too large an 4373 * interrupt storm. 4374 */ 4375 IFDI_INTR_DISABLE(ctx); 4376 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4377 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4378 goto fail_intr_free; 4379 } 4380 if (msix <= 1) { 4381 rid = 0; 4382 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4383 MPASS(msix == 1); 4384 rid = 1; 4385 } 4386 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4387 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4388 goto fail_intr_free; 4389 } 4390 } 4391 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4392 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4393 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4394 goto fail_detach; 4395 } 4396 if ((err = iflib_netmap_attach(ctx))) { 4397 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4398 goto fail_detach; 4399 } 4400 *ctxp = ctx; 4401 4402 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4403 iflib_add_device_sysctl_post(ctx); 4404 ctx->ifc_flags |= IFC_INIT_DONE; 4405 return (0); 4406 fail_detach: 4407 ether_ifdetach(ctx->ifc_ifp); 4408 fail_intr_free: 4409 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4410 pci_release_msi(ctx->ifc_dev); 4411 fail_queues: 4412 /* XXX free queues */ 4413 fail: 4414 IFDI_DETACH(ctx); 4415 return (err); 4416 } 4417 4418 int 4419 iflib_device_attach(device_t dev) 4420 { 4421 if_ctx_t ctx; 4422 if_shared_ctx_t sctx; 4423 4424 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4425 return (ENOTSUP); 4426 4427 pci_enable_busmaster(dev); 4428 4429 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4430 } 4431 4432 int 4433 iflib_device_deregister(if_ctx_t ctx) 4434 { 4435 if_t ifp = ctx->ifc_ifp; 4436 iflib_txq_t txq; 4437 iflib_rxq_t rxq; 4438 device_t dev = ctx->ifc_dev; 4439 int i, j; 4440 struct taskqgroup *tqg; 4441 iflib_fl_t fl; 4442 4443 /* Make sure VLANS are not using driver */ 4444 if (if_vlantrunkinuse(ifp)) { 4445 device_printf(dev,"Vlan in use, detach first\n"); 4446 return (EBUSY); 4447 } 4448 4449 CTX_LOCK(ctx); 4450 ctx->ifc_in_detach = 1; 4451 iflib_stop(ctx); 4452 CTX_UNLOCK(ctx); 4453 4454 /* Unregister VLAN events */ 4455 if (ctx->ifc_vlan_attach_event != NULL) 4456 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4457 if (ctx->ifc_vlan_detach_event != NULL) 4458 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4459 4460 iflib_netmap_detach(ifp); 4461 ether_ifdetach(ifp); 4462 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4463 CTX_LOCK_DESTROY(ctx); 4464 if (ctx->ifc_led_dev != NULL) 4465 led_destroy(ctx->ifc_led_dev); 4466 /* XXX drain any dependent tasks */ 4467 tqg = qgroup_if_io_tqg; 4468 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4469 callout_drain(&txq->ift_timer); 4470 if (txq->ift_task.gt_uniq != NULL) 4471 taskqgroup_detach(tqg, &txq->ift_task); 4472 } 4473 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4474 if (rxq->ifr_task.gt_uniq != NULL) 4475 taskqgroup_detach(tqg, &rxq->ifr_task); 4476 4477 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4478 free(fl->ifl_rx_bitmap, M_IFLIB); 4479 4480 } 4481 tqg = qgroup_if_config_tqg; 4482 if (ctx->ifc_admin_task.gt_uniq != NULL) 4483 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4484 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4485 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4486 4487 IFDI_DETACH(ctx); 4488 device_set_softc(ctx->ifc_dev, NULL); 4489 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4490 pci_release_msi(dev); 4491 } 4492 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4493 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4494 } 4495 if (ctx->ifc_msix_mem != NULL) { 4496 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4497 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4498 ctx->ifc_msix_mem = NULL; 4499 } 4500 4501 bus_generic_detach(dev); 4502 if_free(ifp); 4503 4504 iflib_tx_structures_free(ctx); 4505 iflib_rx_structures_free(ctx); 4506 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4507 free(ctx->ifc_softc, M_IFLIB); 4508 free(ctx, M_IFLIB); 4509 return (0); 4510 } 4511 4512 4513 int 4514 iflib_device_detach(device_t dev) 4515 { 4516 if_ctx_t ctx = device_get_softc(dev); 4517 4518 return (iflib_device_deregister(ctx)); 4519 } 4520 4521 int 4522 iflib_device_suspend(device_t dev) 4523 { 4524 if_ctx_t ctx = device_get_softc(dev); 4525 4526 CTX_LOCK(ctx); 4527 IFDI_SUSPEND(ctx); 4528 CTX_UNLOCK(ctx); 4529 4530 return bus_generic_suspend(dev); 4531 } 4532 int 4533 iflib_device_shutdown(device_t dev) 4534 { 4535 if_ctx_t ctx = device_get_softc(dev); 4536 4537 CTX_LOCK(ctx); 4538 IFDI_SHUTDOWN(ctx); 4539 CTX_UNLOCK(ctx); 4540 4541 return bus_generic_suspend(dev); 4542 } 4543 4544 4545 int 4546 iflib_device_resume(device_t dev) 4547 { 4548 if_ctx_t ctx = device_get_softc(dev); 4549 iflib_txq_t txq = ctx->ifc_txqs; 4550 4551 CTX_LOCK(ctx); 4552 IFDI_RESUME(ctx); 4553 iflib_init_locked(ctx); 4554 CTX_UNLOCK(ctx); 4555 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4556 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4557 4558 return (bus_generic_resume(dev)); 4559 } 4560 4561 int 4562 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4563 { 4564 int error; 4565 if_ctx_t ctx = device_get_softc(dev); 4566 4567 CTX_LOCK(ctx); 4568 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4569 CTX_UNLOCK(ctx); 4570 4571 return (error); 4572 } 4573 4574 void 4575 iflib_device_iov_uninit(device_t dev) 4576 { 4577 if_ctx_t ctx = device_get_softc(dev); 4578 4579 CTX_LOCK(ctx); 4580 IFDI_IOV_UNINIT(ctx); 4581 CTX_UNLOCK(ctx); 4582 } 4583 4584 int 4585 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4586 { 4587 int error; 4588 if_ctx_t ctx = device_get_softc(dev); 4589 4590 CTX_LOCK(ctx); 4591 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4592 CTX_UNLOCK(ctx); 4593 4594 return (error); 4595 } 4596 4597 /********************************************************************* 4598 * 4599 * MODULE FUNCTION DEFINITIONS 4600 * 4601 **********************************************************************/ 4602 4603 /* 4604 * - Start a fast taskqueue thread for each core 4605 * - Start a taskqueue for control operations 4606 */ 4607 static int 4608 iflib_module_init(void) 4609 { 4610 return (0); 4611 } 4612 4613 static int 4614 iflib_module_event_handler(module_t mod, int what, void *arg) 4615 { 4616 int err; 4617 4618 switch (what) { 4619 case MOD_LOAD: 4620 if ((err = iflib_module_init()) != 0) 4621 return (err); 4622 break; 4623 case MOD_UNLOAD: 4624 return (EBUSY); 4625 default: 4626 return (EOPNOTSUPP); 4627 } 4628 4629 return (0); 4630 } 4631 4632 /********************************************************************* 4633 * 4634 * PUBLIC FUNCTION DEFINITIONS 4635 * ordered as in iflib.h 4636 * 4637 **********************************************************************/ 4638 4639 4640 static void 4641 _iflib_assert(if_shared_ctx_t sctx) 4642 { 4643 MPASS(sctx->isc_tx_maxsize); 4644 MPASS(sctx->isc_tx_maxsegsize); 4645 4646 MPASS(sctx->isc_rx_maxsize); 4647 MPASS(sctx->isc_rx_nsegments); 4648 MPASS(sctx->isc_rx_maxsegsize); 4649 4650 MPASS(sctx->isc_nrxd_min[0]); 4651 MPASS(sctx->isc_nrxd_max[0]); 4652 MPASS(sctx->isc_nrxd_default[0]); 4653 MPASS(sctx->isc_ntxd_min[0]); 4654 MPASS(sctx->isc_ntxd_max[0]); 4655 MPASS(sctx->isc_ntxd_default[0]); 4656 } 4657 4658 static void 4659 _iflib_pre_assert(if_softc_ctx_t scctx) 4660 { 4661 4662 MPASS(scctx->isc_txrx->ift_txd_encap); 4663 MPASS(scctx->isc_txrx->ift_txd_flush); 4664 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4665 MPASS(scctx->isc_txrx->ift_rxd_available); 4666 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4667 MPASS(scctx->isc_txrx->ift_rxd_refill); 4668 MPASS(scctx->isc_txrx->ift_rxd_flush); 4669 } 4670 4671 static int 4672 iflib_register(if_ctx_t ctx) 4673 { 4674 if_shared_ctx_t sctx = ctx->ifc_sctx; 4675 driver_t *driver = sctx->isc_driver; 4676 device_t dev = ctx->ifc_dev; 4677 if_t ifp; 4678 4679 _iflib_assert(sctx); 4680 4681 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4682 4683 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4684 if (ifp == NULL) { 4685 device_printf(dev, "can not allocate ifnet structure\n"); 4686 return (ENOMEM); 4687 } 4688 4689 /* 4690 * Initialize our context's device specific methods 4691 */ 4692 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4693 kobj_class_compile((kobj_class_t) driver); 4694 driver->refs++; 4695 4696 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4697 if_setsoftc(ifp, ctx); 4698 if_setdev(ifp, dev); 4699 if_setinitfn(ifp, iflib_if_init); 4700 if_setioctlfn(ifp, iflib_if_ioctl); 4701 if_settransmitfn(ifp, iflib_if_transmit); 4702 if_setqflushfn(ifp, iflib_if_qflush); 4703 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4704 4705 ctx->ifc_vlan_attach_event = 4706 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4707 EVENTHANDLER_PRI_FIRST); 4708 ctx->ifc_vlan_detach_event = 4709 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4710 EVENTHANDLER_PRI_FIRST); 4711 4712 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4713 iflib_media_change, iflib_media_status); 4714 4715 return (0); 4716 } 4717 4718 4719 static int 4720 iflib_queues_alloc(if_ctx_t ctx) 4721 { 4722 if_shared_ctx_t sctx = ctx->ifc_sctx; 4723 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4724 device_t dev = ctx->ifc_dev; 4725 int nrxqsets = scctx->isc_nrxqsets; 4726 int ntxqsets = scctx->isc_ntxqsets; 4727 iflib_txq_t txq; 4728 iflib_rxq_t rxq; 4729 iflib_fl_t fl = NULL; 4730 int i, j, cpu, err, txconf, rxconf; 4731 iflib_dma_info_t ifdip; 4732 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4733 uint32_t *txqsizes = scctx->isc_txqsizes; 4734 uint8_t nrxqs = sctx->isc_nrxqs; 4735 uint8_t ntxqs = sctx->isc_ntxqs; 4736 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4737 caddr_t *vaddrs; 4738 uint64_t *paddrs; 4739 struct ifmp_ring **brscp; 4740 4741 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4742 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4743 4744 brscp = NULL; 4745 txq = NULL; 4746 rxq = NULL; 4747 4748 /* Allocate the TX ring struct memory */ 4749 if (!(txq = 4750 (iflib_txq_t) mallocarray(ntxqsets, sizeof(struct iflib_txq), 4751 M_IFLIB, M_NOWAIT | M_ZERO))) { 4752 device_printf(dev, "Unable to allocate TX ring memory\n"); 4753 err = ENOMEM; 4754 goto fail; 4755 } 4756 4757 /* Now allocate the RX */ 4758 if (!(rxq = 4759 (iflib_rxq_t) mallocarray(nrxqsets, sizeof(struct iflib_rxq), 4760 M_IFLIB, M_NOWAIT | M_ZERO))) { 4761 device_printf(dev, "Unable to allocate RX ring memory\n"); 4762 err = ENOMEM; 4763 goto rx_fail; 4764 } 4765 4766 ctx->ifc_txqs = txq; 4767 ctx->ifc_rxqs = rxq; 4768 4769 /* 4770 * XXX handle allocation failure 4771 */ 4772 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4773 /* Set up some basics */ 4774 4775 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4776 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4777 err = ENOMEM; 4778 goto err_tx_desc; 4779 } 4780 txq->ift_ifdi = ifdip; 4781 for (j = 0; j < ntxqs; j++, ifdip++) { 4782 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4783 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4784 err = ENOMEM; 4785 goto err_tx_desc; 4786 } 4787 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4788 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4789 } 4790 txq->ift_ctx = ctx; 4791 txq->ift_id = i; 4792 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4793 txq->ift_br_offset = 1; 4794 } else { 4795 txq->ift_br_offset = 0; 4796 } 4797 /* XXX fix this */ 4798 txq->ift_timer.c_cpu = cpu; 4799 4800 if (iflib_txsd_alloc(txq)) { 4801 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4802 err = ENOMEM; 4803 goto err_tx_desc; 4804 } 4805 4806 /* Initialize the TX lock */ 4807 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4808 device_get_nameunit(dev), txq->ift_id); 4809 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4810 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4811 4812 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4813 device_get_nameunit(dev), txq->ift_id); 4814 4815 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4816 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4817 if (err) { 4818 /* XXX free any allocated rings */ 4819 device_printf(dev, "Unable to allocate buf_ring\n"); 4820 goto err_tx_desc; 4821 } 4822 } 4823 4824 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4825 /* Set up some basics */ 4826 4827 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4828 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4829 err = ENOMEM; 4830 goto err_tx_desc; 4831 } 4832 4833 rxq->ifr_ifdi = ifdip; 4834 /* XXX this needs to be changed if #rx queues != #tx queues */ 4835 rxq->ifr_ntxqirq = 1; 4836 rxq->ifr_txqid[0] = i; 4837 for (j = 0; j < nrxqs; j++, ifdip++) { 4838 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4839 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4840 err = ENOMEM; 4841 goto err_tx_desc; 4842 } 4843 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4844 } 4845 rxq->ifr_ctx = ctx; 4846 rxq->ifr_id = i; 4847 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4848 rxq->ifr_fl_offset = 1; 4849 } else { 4850 rxq->ifr_fl_offset = 0; 4851 } 4852 rxq->ifr_nfl = nfree_lists; 4853 if (!(fl = 4854 (iflib_fl_t) mallocarray(nfree_lists, sizeof(struct iflib_fl), 4855 M_IFLIB, M_NOWAIT | M_ZERO))) { 4856 device_printf(dev, "Unable to allocate free list memory\n"); 4857 err = ENOMEM; 4858 goto err_tx_desc; 4859 } 4860 rxq->ifr_fl = fl; 4861 for (j = 0; j < nfree_lists; j++) { 4862 fl[j].ifl_rxq = rxq; 4863 fl[j].ifl_id = j; 4864 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4865 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4866 } 4867 /* Allocate receive buffers for the ring*/ 4868 if (iflib_rxsd_alloc(rxq)) { 4869 device_printf(dev, 4870 "Critical Failure setting up receive buffers\n"); 4871 err = ENOMEM; 4872 goto err_rx_desc; 4873 } 4874 4875 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4876 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4877 } 4878 4879 /* TXQs */ 4880 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4881 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4882 for (i = 0; i < ntxqsets; i++) { 4883 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4884 4885 for (j = 0; j < ntxqs; j++, di++) { 4886 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4887 paddrs[i*ntxqs + j] = di->idi_paddr; 4888 } 4889 } 4890 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4891 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4892 iflib_tx_structures_free(ctx); 4893 free(vaddrs, M_IFLIB); 4894 free(paddrs, M_IFLIB); 4895 goto err_rx_desc; 4896 } 4897 free(vaddrs, M_IFLIB); 4898 free(paddrs, M_IFLIB); 4899 4900 /* RXQs */ 4901 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4902 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4903 for (i = 0; i < nrxqsets; i++) { 4904 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4905 4906 for (j = 0; j < nrxqs; j++, di++) { 4907 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4908 paddrs[i*nrxqs + j] = di->idi_paddr; 4909 } 4910 } 4911 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4912 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4913 iflib_tx_structures_free(ctx); 4914 free(vaddrs, M_IFLIB); 4915 free(paddrs, M_IFLIB); 4916 goto err_rx_desc; 4917 } 4918 free(vaddrs, M_IFLIB); 4919 free(paddrs, M_IFLIB); 4920 4921 return (0); 4922 4923 /* XXX handle allocation failure changes */ 4924 err_rx_desc: 4925 err_tx_desc: 4926 if (ctx->ifc_rxqs != NULL) 4927 free(ctx->ifc_rxqs, M_IFLIB); 4928 ctx->ifc_rxqs = NULL; 4929 if (ctx->ifc_txqs != NULL) 4930 free(ctx->ifc_txqs, M_IFLIB); 4931 ctx->ifc_txqs = NULL; 4932 rx_fail: 4933 if (brscp != NULL) 4934 free(brscp, M_IFLIB); 4935 if (rxq != NULL) 4936 free(rxq, M_IFLIB); 4937 if (txq != NULL) 4938 free(txq, M_IFLIB); 4939 fail: 4940 return (err); 4941 } 4942 4943 static int 4944 iflib_tx_structures_setup(if_ctx_t ctx) 4945 { 4946 iflib_txq_t txq = ctx->ifc_txqs; 4947 int i; 4948 4949 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4950 iflib_txq_setup(txq); 4951 4952 return (0); 4953 } 4954 4955 static void 4956 iflib_tx_structures_free(if_ctx_t ctx) 4957 { 4958 iflib_txq_t txq = ctx->ifc_txqs; 4959 int i, j; 4960 4961 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4962 iflib_txq_destroy(txq); 4963 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4964 iflib_dma_free(&txq->ift_ifdi[j]); 4965 } 4966 free(ctx->ifc_txqs, M_IFLIB); 4967 ctx->ifc_txqs = NULL; 4968 IFDI_QUEUES_FREE(ctx); 4969 } 4970 4971 /********************************************************************* 4972 * 4973 * Initialize all receive rings. 4974 * 4975 **********************************************************************/ 4976 static int 4977 iflib_rx_structures_setup(if_ctx_t ctx) 4978 { 4979 iflib_rxq_t rxq = ctx->ifc_rxqs; 4980 int q; 4981 #if defined(INET6) || defined(INET) 4982 int i, err; 4983 #endif 4984 4985 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4986 #if defined(INET6) || defined(INET) 4987 tcp_lro_free(&rxq->ifr_lc); 4988 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4989 TCP_LRO_ENTRIES, min(1024, 4990 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4991 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4992 goto fail; 4993 } 4994 rxq->ifr_lro_enabled = TRUE; 4995 #endif 4996 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4997 } 4998 return (0); 4999 #if defined(INET6) || defined(INET) 5000 fail: 5001 /* 5002 * Free RX software descriptors allocated so far, we will only handle 5003 * the rings that completed, the failing case will have 5004 * cleaned up for itself. 'q' failed, so its the terminus. 5005 */ 5006 rxq = ctx->ifc_rxqs; 5007 for (i = 0; i < q; ++i, rxq++) { 5008 iflib_rx_sds_free(rxq); 5009 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5010 } 5011 return (err); 5012 #endif 5013 } 5014 5015 /********************************************************************* 5016 * 5017 * Free all receive rings. 5018 * 5019 **********************************************************************/ 5020 static void 5021 iflib_rx_structures_free(if_ctx_t ctx) 5022 { 5023 iflib_rxq_t rxq = ctx->ifc_rxqs; 5024 5025 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5026 iflib_rx_sds_free(rxq); 5027 } 5028 } 5029 5030 static int 5031 iflib_qset_structures_setup(if_ctx_t ctx) 5032 { 5033 int err; 5034 5035 if ((err = iflib_tx_structures_setup(ctx)) != 0) 5036 return (err); 5037 5038 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 5039 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5040 iflib_tx_structures_free(ctx); 5041 iflib_rx_structures_free(ctx); 5042 } 5043 return (err); 5044 } 5045 5046 int 5047 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5048 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5049 { 5050 5051 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5052 } 5053 5054 #ifdef SMP 5055 static int 5056 find_nth(if_ctx_t ctx, int qid) 5057 { 5058 cpuset_t cpus; 5059 int i, cpuid, eqid, count; 5060 5061 CPU_COPY(&ctx->ifc_cpus, &cpus); 5062 count = CPU_COUNT(&cpus); 5063 eqid = qid % count; 5064 /* clear up to the qid'th bit */ 5065 for (i = 0; i < eqid; i++) { 5066 cpuid = CPU_FFS(&cpus); 5067 MPASS(cpuid != 0); 5068 CPU_CLR(cpuid-1, &cpus); 5069 } 5070 cpuid = CPU_FFS(&cpus); 5071 MPASS(cpuid != 0); 5072 return (cpuid-1); 5073 } 5074 5075 #ifdef SCHED_ULE 5076 extern struct cpu_group *cpu_top; /* CPU topology */ 5077 5078 static int 5079 find_child_with_core(int cpu, struct cpu_group *grp) 5080 { 5081 int i; 5082 5083 if (grp->cg_children == 0) 5084 return -1; 5085 5086 MPASS(grp->cg_child); 5087 for (i = 0; i < grp->cg_children; i++) { 5088 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5089 return i; 5090 } 5091 5092 return -1; 5093 } 5094 5095 /* 5096 * Find the nth thread on the specified core 5097 */ 5098 static int 5099 find_thread(int cpu, int thread_num) 5100 { 5101 struct cpu_group *grp; 5102 int i; 5103 cpuset_t cs; 5104 5105 grp = cpu_top; 5106 if (grp == NULL) 5107 return cpu; 5108 i = 0; 5109 while ((i = find_child_with_core(cpu, grp)) != -1) { 5110 /* If the child only has one cpu, don't descend */ 5111 if (grp->cg_child[i].cg_count <= 1) 5112 break; 5113 grp = &grp->cg_child[i]; 5114 } 5115 5116 /* If they don't share at least an L2 cache, use the same CPU */ 5117 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5118 return cpu; 5119 5120 /* Now pick one */ 5121 CPU_COPY(&grp->cg_mask, &cs); 5122 for (i = thread_num % grp->cg_count; i > 0; i--) { 5123 MPASS(CPU_FFS(&cs)); 5124 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5125 } 5126 MPASS(CPU_FFS(&cs)); 5127 return CPU_FFS(&cs) - 1; 5128 } 5129 #else 5130 static int 5131 find_thread(int cpu, int thread_num __unused) 5132 { 5133 return cpu; 5134 } 5135 #endif 5136 5137 static int 5138 get_thread_num(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5139 { 5140 switch (type) { 5141 case IFLIB_INTR_TX: 5142 /* TX queues get threads on the same core as the corresponding RX queue */ 5143 /* XXX handle multiple RX threads per core and more than two threads per core */ 5144 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5145 case IFLIB_INTR_RX: 5146 case IFLIB_INTR_RXTX: 5147 /* RX queues get the first thread on their core */ 5148 return qid / CPU_COUNT(&ctx->ifc_cpus); 5149 default: 5150 return -1; 5151 } 5152 } 5153 #else 5154 #define get_thread_num(ctx, type, qid) CPU_FIRST() 5155 #define find_thread(cpuid, tid) CPU_FIRST() 5156 #define find_nth(ctx, gid) CPU_FIRST() 5157 #endif 5158 5159 /* Just to avoid copy/paste */ 5160 static inline int 5161 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5162 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5163 { 5164 int cpuid; 5165 int err, tid; 5166 5167 cpuid = find_nth(ctx, qid); 5168 tid = get_thread_num(ctx, type, qid); 5169 MPASS(tid >= 0); 5170 cpuid = find_thread(cpuid, tid); 5171 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5172 if (err) { 5173 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5174 return (err); 5175 } 5176 #ifdef notyet 5177 if (cpuid > ctx->ifc_cpuid_highest) 5178 ctx->ifc_cpuid_highest = cpuid; 5179 #endif 5180 return 0; 5181 } 5182 5183 int 5184 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5185 iflib_intr_type_t type, driver_filter_t *filter, 5186 void *filter_arg, int qid, char *name) 5187 { 5188 struct grouptask *gtask; 5189 struct taskqgroup *tqg; 5190 iflib_filter_info_t info; 5191 gtask_fn_t *fn; 5192 int tqrid, err; 5193 driver_filter_t *intr_fast; 5194 void *q; 5195 5196 info = &ctx->ifc_filter_info; 5197 tqrid = rid; 5198 5199 switch (type) { 5200 /* XXX merge tx/rx for netmap? */ 5201 case IFLIB_INTR_TX: 5202 q = &ctx->ifc_txqs[qid]; 5203 info = &ctx->ifc_txqs[qid].ift_filter_info; 5204 gtask = &ctx->ifc_txqs[qid].ift_task; 5205 tqg = qgroup_if_io_tqg; 5206 fn = _task_fn_tx; 5207 intr_fast = iflib_fast_intr; 5208 GROUPTASK_INIT(gtask, 0, fn, q); 5209 break; 5210 case IFLIB_INTR_RX: 5211 q = &ctx->ifc_rxqs[qid]; 5212 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5213 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5214 tqg = qgroup_if_io_tqg; 5215 fn = _task_fn_rx; 5216 intr_fast = iflib_fast_intr; 5217 GROUPTASK_INIT(gtask, 0, fn, q); 5218 break; 5219 case IFLIB_INTR_RXTX: 5220 q = &ctx->ifc_rxqs[qid]; 5221 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5222 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5223 tqg = qgroup_if_io_tqg; 5224 fn = _task_fn_rx; 5225 intr_fast = iflib_fast_intr_rxtx; 5226 GROUPTASK_INIT(gtask, 0, fn, q); 5227 break; 5228 case IFLIB_INTR_ADMIN: 5229 q = ctx; 5230 tqrid = -1; 5231 info = &ctx->ifc_filter_info; 5232 gtask = &ctx->ifc_admin_task; 5233 tqg = qgroup_if_config_tqg; 5234 fn = _task_fn_admin; 5235 intr_fast = iflib_fast_intr_ctx; 5236 break; 5237 default: 5238 panic("unknown net intr type"); 5239 } 5240 5241 info->ifi_filter = filter; 5242 info->ifi_filter_arg = filter_arg; 5243 info->ifi_task = gtask; 5244 info->ifi_ctx = q; 5245 5246 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5247 if (err != 0) { 5248 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5249 return (err); 5250 } 5251 if (type == IFLIB_INTR_ADMIN) 5252 return (0); 5253 5254 if (tqrid != -1) { 5255 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5256 if (err) 5257 return (err); 5258 } else { 5259 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5260 } 5261 5262 return (0); 5263 } 5264 5265 void 5266 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5267 { 5268 struct grouptask *gtask; 5269 struct taskqgroup *tqg; 5270 gtask_fn_t *fn; 5271 void *q; 5272 int irq_num = -1; 5273 int err; 5274 5275 switch (type) { 5276 case IFLIB_INTR_TX: 5277 q = &ctx->ifc_txqs[qid]; 5278 gtask = &ctx->ifc_txqs[qid].ift_task; 5279 tqg = qgroup_if_io_tqg; 5280 fn = _task_fn_tx; 5281 if (irq != NULL) 5282 irq_num = rman_get_start(irq->ii_res); 5283 break; 5284 case IFLIB_INTR_RX: 5285 q = &ctx->ifc_rxqs[qid]; 5286 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5287 tqg = qgroup_if_io_tqg; 5288 fn = _task_fn_rx; 5289 if (irq != NULL) 5290 irq_num = rman_get_start(irq->ii_res); 5291 break; 5292 case IFLIB_INTR_IOV: 5293 q = ctx; 5294 gtask = &ctx->ifc_vflr_task; 5295 tqg = qgroup_if_config_tqg; 5296 fn = _task_fn_iov; 5297 break; 5298 default: 5299 panic("unknown net intr type"); 5300 } 5301 GROUPTASK_INIT(gtask, 0, fn, q); 5302 if (irq_num != -1) { 5303 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5304 if (err) 5305 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5306 } 5307 else { 5308 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5309 } 5310 } 5311 5312 void 5313 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5314 { 5315 if (irq->ii_tag) 5316 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5317 5318 if (irq->ii_res) 5319 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5320 } 5321 5322 static int 5323 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5324 { 5325 iflib_txq_t txq = ctx->ifc_txqs; 5326 iflib_rxq_t rxq = ctx->ifc_rxqs; 5327 if_irq_t irq = &ctx->ifc_legacy_irq; 5328 iflib_filter_info_t info; 5329 struct grouptask *gtask; 5330 struct taskqgroup *tqg; 5331 gtask_fn_t *fn; 5332 int tqrid; 5333 void *q; 5334 int err; 5335 5336 q = &ctx->ifc_rxqs[0]; 5337 info = &rxq[0].ifr_filter_info; 5338 gtask = &rxq[0].ifr_task; 5339 tqg = qgroup_if_io_tqg; 5340 tqrid = irq->ii_rid = *rid; 5341 fn = _task_fn_rx; 5342 5343 ctx->ifc_flags |= IFC_LEGACY; 5344 info->ifi_filter = filter; 5345 info->ifi_filter_arg = filter_arg; 5346 info->ifi_task = gtask; 5347 info->ifi_ctx = ctx; 5348 5349 /* We allocate a single interrupt resource */ 5350 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5351 return (err); 5352 GROUPTASK_INIT(gtask, 0, fn, q); 5353 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5354 5355 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5356 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5357 return (0); 5358 } 5359 5360 void 5361 iflib_led_create(if_ctx_t ctx) 5362 { 5363 5364 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5365 device_get_nameunit(ctx->ifc_dev)); 5366 } 5367 5368 void 5369 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5370 { 5371 5372 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5373 } 5374 5375 void 5376 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5377 { 5378 5379 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5380 } 5381 5382 void 5383 iflib_admin_intr_deferred(if_ctx_t ctx) 5384 { 5385 #ifdef INVARIANTS 5386 struct grouptask *gtask; 5387 5388 gtask = &ctx->ifc_admin_task; 5389 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5390 #endif 5391 5392 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5393 } 5394 5395 void 5396 iflib_iov_intr_deferred(if_ctx_t ctx) 5397 { 5398 5399 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5400 } 5401 5402 void 5403 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5404 { 5405 5406 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5407 } 5408 5409 void 5410 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5411 char *name) 5412 { 5413 5414 GROUPTASK_INIT(gtask, 0, fn, ctx); 5415 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5416 } 5417 5418 void 5419 iflib_config_gtask_deinit(struct grouptask *gtask) 5420 { 5421 5422 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5423 } 5424 5425 void 5426 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5427 { 5428 if_t ifp = ctx->ifc_ifp; 5429 iflib_txq_t txq = ctx->ifc_txqs; 5430 5431 if_setbaudrate(ifp, baudrate); 5432 if (baudrate >= IF_Gbps(10)) 5433 ctx->ifc_flags |= IFC_PREFETCH; 5434 5435 /* If link down, disable watchdog */ 5436 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5437 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5438 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5439 } 5440 ctx->ifc_link_state = link_state; 5441 if_link_state_change(ifp, link_state); 5442 } 5443 5444 static int 5445 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5446 { 5447 int credits; 5448 #ifdef INVARIANTS 5449 int credits_pre = txq->ift_cidx_processed; 5450 #endif 5451 5452 if (ctx->isc_txd_credits_update == NULL) 5453 return (0); 5454 5455 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5456 return (0); 5457 5458 txq->ift_processed += credits; 5459 txq->ift_cidx_processed += credits; 5460 5461 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5462 if (txq->ift_cidx_processed >= txq->ift_size) 5463 txq->ift_cidx_processed -= txq->ift_size; 5464 return (credits); 5465 } 5466 5467 static int 5468 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5469 { 5470 5471 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5472 budget)); 5473 } 5474 5475 void 5476 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5477 const char *description, if_int_delay_info_t info, 5478 int offset, int value) 5479 { 5480 info->iidi_ctx = ctx; 5481 info->iidi_offset = offset; 5482 info->iidi_value = value; 5483 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5484 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5485 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5486 info, 0, iflib_sysctl_int_delay, "I", description); 5487 } 5488 5489 struct mtx * 5490 iflib_ctx_lock_get(if_ctx_t ctx) 5491 { 5492 5493 return (&ctx->ifc_mtx); 5494 } 5495 5496 static int 5497 iflib_msix_init(if_ctx_t ctx) 5498 { 5499 device_t dev = ctx->ifc_dev; 5500 if_shared_ctx_t sctx = ctx->ifc_sctx; 5501 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5502 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5503 int iflib_num_tx_queues, iflib_num_rx_queues; 5504 int err, admincnt, bar; 5505 5506 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5507 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5508 5509 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5510 5511 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5512 admincnt = sctx->isc_admin_intrcnt; 5513 /* Override by global tuneable */ 5514 { 5515 int i; 5516 size_t len = sizeof(i); 5517 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5518 if (err == 0) { 5519 if (i == 0) 5520 goto msi; 5521 } 5522 else { 5523 device_printf(dev, "unable to read hw.pci.enable_msix."); 5524 } 5525 } 5526 /* Override by tuneable */ 5527 if (scctx->isc_disable_msix) 5528 goto msi; 5529 5530 /* 5531 ** When used in a virtualized environment 5532 ** PCI BUSMASTER capability may not be set 5533 ** so explicity set it here and rewrite 5534 ** the ENABLE in the MSIX control register 5535 ** at this point to cause the host to 5536 ** successfully initialize us. 5537 */ 5538 { 5539 int msix_ctrl, rid; 5540 5541 pci_enable_busmaster(dev); 5542 rid = 0; 5543 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5544 rid += PCIR_MSIX_CTRL; 5545 msix_ctrl = pci_read_config(dev, rid, 2); 5546 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5547 pci_write_config(dev, rid, msix_ctrl, 2); 5548 } else { 5549 device_printf(dev, "PCIY_MSIX capability not found; " 5550 "or rid %d == 0.\n", rid); 5551 goto msi; 5552 } 5553 } 5554 5555 /* 5556 * bar == -1 => "trust me I know what I'm doing" 5557 * Some drivers are for hardware that is so shoddily 5558 * documented that no one knows which bars are which 5559 * so the developer has to map all bars. This hack 5560 * allows shoddy garbage to use msix in this framework. 5561 */ 5562 if (bar != -1) { 5563 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5564 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5565 if (ctx->ifc_msix_mem == NULL) { 5566 /* May not be enabled */ 5567 device_printf(dev, "Unable to map MSIX table \n"); 5568 goto msi; 5569 } 5570 } 5571 /* First try MSI/X */ 5572 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5573 device_printf(dev, "System has MSIX disabled \n"); 5574 bus_release_resource(dev, SYS_RES_MEMORY, 5575 bar, ctx->ifc_msix_mem); 5576 ctx->ifc_msix_mem = NULL; 5577 goto msi; 5578 } 5579 #if IFLIB_DEBUG 5580 /* use only 1 qset in debug mode */ 5581 queuemsgs = min(msgs - admincnt, 1); 5582 #else 5583 queuemsgs = msgs - admincnt; 5584 #endif 5585 #ifdef RSS 5586 queues = imin(queuemsgs, rss_getnumbuckets()); 5587 #else 5588 queues = queuemsgs; 5589 #endif 5590 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5591 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5592 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5593 #ifdef RSS 5594 /* If we're doing RSS, clamp at the number of RSS buckets */ 5595 if (queues > rss_getnumbuckets()) 5596 queues = rss_getnumbuckets(); 5597 #endif 5598 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5599 rx_queues = iflib_num_rx_queues; 5600 else 5601 rx_queues = queues; 5602 5603 if (rx_queues > scctx->isc_nrxqsets) 5604 rx_queues = scctx->isc_nrxqsets; 5605 5606 /* 5607 * We want this to be all logical CPUs by default 5608 */ 5609 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5610 tx_queues = iflib_num_tx_queues; 5611 else 5612 tx_queues = mp_ncpus; 5613 5614 if (tx_queues > scctx->isc_ntxqsets) 5615 tx_queues = scctx->isc_ntxqsets; 5616 5617 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5618 #ifdef INVARIANTS 5619 if (tx_queues != rx_queues) 5620 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5621 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5622 #endif 5623 tx_queues = min(rx_queues, tx_queues); 5624 rx_queues = min(rx_queues, tx_queues); 5625 } 5626 5627 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5628 5629 vectors = rx_queues + admincnt; 5630 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5631 device_printf(dev, 5632 "Using MSIX interrupts with %d vectors\n", vectors); 5633 scctx->isc_vectors = vectors; 5634 scctx->isc_nrxqsets = rx_queues; 5635 scctx->isc_ntxqsets = tx_queues; 5636 scctx->isc_intr = IFLIB_INTR_MSIX; 5637 5638 return (vectors); 5639 } else { 5640 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5641 } 5642 msi: 5643 vectors = pci_msi_count(dev); 5644 scctx->isc_nrxqsets = 1; 5645 scctx->isc_ntxqsets = 1; 5646 scctx->isc_vectors = vectors; 5647 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5648 device_printf(dev,"Using an MSI interrupt\n"); 5649 scctx->isc_intr = IFLIB_INTR_MSI; 5650 } else { 5651 device_printf(dev,"Using a Legacy interrupt\n"); 5652 scctx->isc_intr = IFLIB_INTR_LEGACY; 5653 } 5654 5655 return (vectors); 5656 } 5657 5658 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5659 5660 static int 5661 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5662 { 5663 int rc; 5664 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5665 struct sbuf *sb; 5666 char *ring_state = "UNKNOWN"; 5667 5668 /* XXX needed ? */ 5669 rc = sysctl_wire_old_buffer(req, 0); 5670 MPASS(rc == 0); 5671 if (rc != 0) 5672 return (rc); 5673 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5674 MPASS(sb != NULL); 5675 if (sb == NULL) 5676 return (ENOMEM); 5677 if (state[3] <= 3) 5678 ring_state = ring_states[state[3]]; 5679 5680 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5681 state[0], state[1], state[2], ring_state); 5682 rc = sbuf_finish(sb); 5683 sbuf_delete(sb); 5684 return(rc); 5685 } 5686 5687 enum iflib_ndesc_handler { 5688 IFLIB_NTXD_HANDLER, 5689 IFLIB_NRXD_HANDLER, 5690 }; 5691 5692 static int 5693 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5694 { 5695 if_ctx_t ctx = (void *)arg1; 5696 enum iflib_ndesc_handler type = arg2; 5697 char buf[256] = {0}; 5698 qidx_t *ndesc; 5699 char *p, *next; 5700 int nqs, rc, i; 5701 5702 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5703 5704 nqs = 8; 5705 switch(type) { 5706 case IFLIB_NTXD_HANDLER: 5707 ndesc = ctx->ifc_sysctl_ntxds; 5708 if (ctx->ifc_sctx) 5709 nqs = ctx->ifc_sctx->isc_ntxqs; 5710 break; 5711 case IFLIB_NRXD_HANDLER: 5712 ndesc = ctx->ifc_sysctl_nrxds; 5713 if (ctx->ifc_sctx) 5714 nqs = ctx->ifc_sctx->isc_nrxqs; 5715 break; 5716 } 5717 if (nqs == 0) 5718 nqs = 8; 5719 5720 for (i=0; i<8; i++) { 5721 if (i >= nqs) 5722 break; 5723 if (i) 5724 strcat(buf, ","); 5725 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5726 } 5727 5728 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5729 if (rc || req->newptr == NULL) 5730 return rc; 5731 5732 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5733 i++, p = strsep(&next, " ,")) { 5734 ndesc[i] = strtoul(p, NULL, 10); 5735 } 5736 5737 return(rc); 5738 } 5739 5740 #define NAME_BUFLEN 32 5741 static void 5742 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5743 { 5744 device_t dev = iflib_get_dev(ctx); 5745 struct sysctl_oid_list *child, *oid_list; 5746 struct sysctl_ctx_list *ctx_list; 5747 struct sysctl_oid *node; 5748 5749 ctx_list = device_get_sysctl_ctx(dev); 5750 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5751 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5752 CTLFLAG_RD, NULL, "IFLIB fields"); 5753 oid_list = SYSCTL_CHILDREN(node); 5754 5755 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5756 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5757 "driver version"); 5758 5759 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5760 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5761 "# of txqs to use, 0 => use default #"); 5762 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5763 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5764 "# of rxqs to use, 0 => use default #"); 5765 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5766 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5767 "permit #txq != #rxq"); 5768 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5769 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5770 "disable MSIX (default 0)"); 5771 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5772 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5773 "set the rx budget"); 5774 5775 /* XXX change for per-queue sizes */ 5776 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5777 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5778 mp_ndesc_handler, "A", 5779 "list of # of tx descriptors to use, 0 = use default #"); 5780 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5781 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5782 mp_ndesc_handler, "A", 5783 "list of # of rx descriptors to use, 0 = use default #"); 5784 } 5785 5786 static void 5787 iflib_add_device_sysctl_post(if_ctx_t ctx) 5788 { 5789 if_shared_ctx_t sctx = ctx->ifc_sctx; 5790 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5791 device_t dev = iflib_get_dev(ctx); 5792 struct sysctl_oid_list *child; 5793 struct sysctl_ctx_list *ctx_list; 5794 iflib_fl_t fl; 5795 iflib_txq_t txq; 5796 iflib_rxq_t rxq; 5797 int i, j; 5798 char namebuf[NAME_BUFLEN]; 5799 char *qfmt; 5800 struct sysctl_oid *queue_node, *fl_node, *node; 5801 struct sysctl_oid_list *queue_list, *fl_list; 5802 ctx_list = device_get_sysctl_ctx(dev); 5803 5804 node = ctx->ifc_sysctl_node; 5805 child = SYSCTL_CHILDREN(node); 5806 5807 if (scctx->isc_ntxqsets > 100) 5808 qfmt = "txq%03d"; 5809 else if (scctx->isc_ntxqsets > 10) 5810 qfmt = "txq%02d"; 5811 else 5812 qfmt = "txq%d"; 5813 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5814 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5815 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5816 CTLFLAG_RD, NULL, "Queue Name"); 5817 queue_list = SYSCTL_CHILDREN(queue_node); 5818 #if MEMORY_LOGGING 5819 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5820 CTLFLAG_RD, 5821 &txq->ift_dequeued, "total mbufs freed"); 5822 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5823 CTLFLAG_RD, 5824 &txq->ift_enqueued, "total mbufs enqueued"); 5825 #endif 5826 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5827 CTLFLAG_RD, 5828 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5829 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5830 CTLFLAG_RD, 5831 &txq->ift_pullups, "# of times m_pullup was called"); 5832 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5833 CTLFLAG_RD, 5834 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5835 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5836 CTLFLAG_RD, 5837 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5838 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5839 CTLFLAG_RD, 5840 &txq->ift_map_failed, "# of times dma map failed"); 5841 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5842 CTLFLAG_RD, 5843 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5844 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5845 CTLFLAG_RD, 5846 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5847 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5848 CTLFLAG_RD, 5849 &txq->ift_pidx, 1, "Producer Index"); 5850 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5851 CTLFLAG_RD, 5852 &txq->ift_cidx, 1, "Consumer Index"); 5853 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5854 CTLFLAG_RD, 5855 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5856 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5857 CTLFLAG_RD, 5858 &txq->ift_in_use, 1, "descriptors in use"); 5859 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5860 CTLFLAG_RD, 5861 &txq->ift_processed, "descriptors procesed for clean"); 5862 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5863 CTLFLAG_RD, 5864 &txq->ift_cleaned, "total cleaned"); 5865 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5866 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5867 0, mp_ring_state_handler, "A", "soft ring state"); 5868 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5869 CTLFLAG_RD, &txq->ift_br->enqueues, 5870 "# of enqueues to the mp_ring for this queue"); 5871 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5872 CTLFLAG_RD, &txq->ift_br->drops, 5873 "# of drops in the mp_ring for this queue"); 5874 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5875 CTLFLAG_RD, &txq->ift_br->starts, 5876 "# of normal consumer starts in the mp_ring for this queue"); 5877 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5878 CTLFLAG_RD, &txq->ift_br->stalls, 5879 "# of consumer stalls in the mp_ring for this queue"); 5880 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5881 CTLFLAG_RD, &txq->ift_br->restarts, 5882 "# of consumer restarts in the mp_ring for this queue"); 5883 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5884 CTLFLAG_RD, &txq->ift_br->abdications, 5885 "# of consumer abdications in the mp_ring for this queue"); 5886 } 5887 5888 if (scctx->isc_nrxqsets > 100) 5889 qfmt = "rxq%03d"; 5890 else if (scctx->isc_nrxqsets > 10) 5891 qfmt = "rxq%02d"; 5892 else 5893 qfmt = "rxq%d"; 5894 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5895 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5896 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5897 CTLFLAG_RD, NULL, "Queue Name"); 5898 queue_list = SYSCTL_CHILDREN(queue_node); 5899 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5900 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5901 CTLFLAG_RD, 5902 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5903 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5904 CTLFLAG_RD, 5905 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5906 } 5907 5908 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5909 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5910 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5911 CTLFLAG_RD, NULL, "freelist Name"); 5912 fl_list = SYSCTL_CHILDREN(fl_node); 5913 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5914 CTLFLAG_RD, 5915 &fl->ifl_pidx, 1, "Producer Index"); 5916 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5917 CTLFLAG_RD, 5918 &fl->ifl_cidx, 1, "Consumer Index"); 5919 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5920 CTLFLAG_RD, 5921 &fl->ifl_credits, 1, "credits available"); 5922 #if MEMORY_LOGGING 5923 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5924 CTLFLAG_RD, 5925 &fl->ifl_m_enqueued, "mbufs allocated"); 5926 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5927 CTLFLAG_RD, 5928 &fl->ifl_m_dequeued, "mbufs freed"); 5929 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5930 CTLFLAG_RD, 5931 &fl->ifl_cl_enqueued, "clusters allocated"); 5932 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5933 CTLFLAG_RD, 5934 &fl->ifl_cl_dequeued, "clusters freed"); 5935 #endif 5936 5937 } 5938 } 5939 5940 } 5941 5942 #ifndef __NO_STRICT_ALIGNMENT 5943 static struct mbuf * 5944 iflib_fixup_rx(struct mbuf *m) 5945 { 5946 struct mbuf *n; 5947 5948 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5949 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5950 m->m_data += ETHER_HDR_LEN; 5951 n = m; 5952 } else { 5953 MGETHDR(n, M_NOWAIT, MT_DATA); 5954 if (n == NULL) { 5955 m_freem(m); 5956 return (NULL); 5957 } 5958 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5959 m->m_data += ETHER_HDR_LEN; 5960 m->m_len -= ETHER_HDR_LEN; 5961 n->m_len = ETHER_HDR_LEN; 5962 M_MOVE_PKTHDR(n, m); 5963 n->m_next = m; 5964 } 5965 return (n); 5966 } 5967 #endif 5968