1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <[email protected]> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #ifdef PCI_IOV 96 #include <dev/pci/pci_iov.h> 97 #endif 98 99 #include <sys/bitstring.h> 100 /* 101 * enable accounting of every mbuf as it comes in to and goes out of 102 * iflib's software descriptor references 103 */ 104 #define MEMORY_LOGGING 0 105 /* 106 * Enable mbuf vectors for compressing long mbuf chains 107 */ 108 109 /* 110 * NB: 111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 112 * we prefetch needs to be determined by the time spent in m_free vis a vis 113 * the cost of a prefetch. This will of course vary based on the workload: 114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 115 * is quite expensive, thus suggesting very little prefetch. 116 * - small packet forwarding which is just returning a single mbuf to 117 * UMA will typically be very fast vis a vis the cost of a memory 118 * access. 119 */ 120 121 122 /* 123 * File organization: 124 * - private structures 125 * - iflib private utility functions 126 * - ifnet functions 127 * - vlan registry and other exported functions 128 * - iflib public core functions 129 * 130 * 131 */ 132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 uint32_t ifc_rx_mbuf_sz; 175 176 int ifc_link_state; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 uint16_t ifc_sysctl_core_offset; 194 #define CORE_OFFSET_UNSPECIFIED 0xffff 195 uint8_t ifc_sysctl_separate_txrx; 196 197 qidx_t ifc_sysctl_ntxds[8]; 198 qidx_t ifc_sysctl_nrxds[8]; 199 struct if_txrx ifc_txrx; 200 #define isc_txd_encap ifc_txrx.ift_txd_encap 201 #define isc_txd_flush ifc_txrx.ift_txd_flush 202 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 203 #define isc_rxd_available ifc_txrx.ift_rxd_available 204 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 eventhandler_tag ifc_vlan_attach_event; 211 eventhandler_tag ifc_vlan_detach_event; 212 uint8_t ifc_mac[ETHER_ADDR_LEN]; 213 }; 214 215 void * 216 iflib_get_softc(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_softc); 220 } 221 222 device_t 223 iflib_get_dev(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_dev); 227 } 228 229 if_t 230 iflib_get_ifp(if_ctx_t ctx) 231 { 232 233 return (ctx->ifc_ifp); 234 } 235 236 struct ifmedia * 237 iflib_get_media(if_ctx_t ctx) 238 { 239 240 return (&ctx->ifc_media); 241 } 242 243 uint32_t 244 iflib_get_flags(if_ctx_t ctx) 245 { 246 return (ctx->ifc_flags); 247 } 248 249 void 250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 251 { 252 253 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 254 } 255 256 if_softc_ctx_t 257 iflib_get_softc_ctx(if_ctx_t ctx) 258 { 259 260 return (&ctx->ifc_softc_ctx); 261 } 262 263 if_shared_ctx_t 264 iflib_get_sctx(if_ctx_t ctx) 265 { 266 267 return (ctx->ifc_sctx); 268 } 269 270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 273 274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 276 277 typedef struct iflib_sw_rx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 282 } iflib_rxsd_array_t; 283 284 typedef struct iflib_sw_tx_desc_array { 285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 287 struct mbuf **ifsd_m; /* pkthdr mbufs */ 288 } if_txsd_vec_t; 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 311 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 351 if_txsd_vec_t ift_sds; 352 uint8_t ift_qstatus; 353 uint8_t ift_closed; 354 uint8_t ift_update_freq; 355 struct iflib_filter_info ift_filter_info; 356 bus_dma_tag_t ift_buf_tag; 357 bus_dma_tag_t ift_tso_buf_tag; 358 iflib_dma_info_t ift_ifdi; 359 #define MTX_NAME_LEN 16 360 char ift_mtx_name[MTX_NAME_LEN]; 361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 362 #ifdef IFLIB_DIAGNOSTICS 363 uint64_t ift_cpu_exec_count[256]; 364 #endif 365 } __aligned(CACHE_LINE_SIZE); 366 367 struct iflib_fl { 368 qidx_t ifl_cidx; 369 qidx_t ifl_pidx; 370 qidx_t ifl_credits; 371 uint8_t ifl_gen; 372 uint8_t ifl_rxd_size; 373 #if MEMORY_LOGGING 374 uint64_t ifl_m_enqueued; 375 uint64_t ifl_m_dequeued; 376 uint64_t ifl_cl_enqueued; 377 uint64_t ifl_cl_dequeued; 378 #endif 379 /* implicit pad */ 380 381 bitstr_t *ifl_rx_bitmap; 382 qidx_t ifl_fragidx; 383 /* constant */ 384 qidx_t ifl_size; 385 uint16_t ifl_buf_size; 386 uint16_t ifl_cltype; 387 uma_zone_t ifl_zone; 388 iflib_rxsd_array_t ifl_sds; 389 iflib_rxq_t ifl_rxq; 390 uint8_t ifl_id; 391 bus_dma_tag_t ifl_buf_tag; 392 iflib_dma_info_t ifl_ifdi; 393 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 394 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 395 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 396 } __aligned(CACHE_LINE_SIZE); 397 398 static inline qidx_t 399 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 400 { 401 qidx_t used; 402 403 if (pidx > cidx) 404 used = pidx - cidx; 405 else if (pidx < cidx) 406 used = size - cidx + pidx; 407 else if (gen == 0 && pidx == cidx) 408 used = 0; 409 else if (gen == 1 && pidx == cidx) 410 used = size; 411 else 412 panic("bad state"); 413 414 return (used); 415 } 416 417 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 418 419 #define IDXDIFF(head, tail, wrap) \ 420 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 421 422 struct iflib_rxq { 423 if_ctx_t ifr_ctx; 424 iflib_fl_t ifr_fl; 425 uint64_t ifr_rx_irq; 426 /* 427 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 428 * the command queue consumer index. Otherwise it's unused. 429 */ 430 qidx_t ifr_cq_cidx; 431 uint16_t ifr_id; 432 uint8_t ifr_nfl; 433 uint8_t ifr_ntxqirq; 434 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 435 uint8_t ifr_fl_offset; 436 struct lro_ctrl ifr_lc; 437 struct grouptask ifr_task; 438 struct iflib_filter_info ifr_filter_info; 439 iflib_dma_info_t ifr_ifdi; 440 441 /* dynamically allocate if any drivers need a value substantially larger than this */ 442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 443 #ifdef IFLIB_DIAGNOSTICS 444 uint64_t ifr_cpu_exec_count[256]; 445 #endif 446 } __aligned(CACHE_LINE_SIZE); 447 448 typedef struct if_rxsd { 449 caddr_t *ifsd_cl; 450 struct mbuf **ifsd_m; 451 iflib_fl_t ifsd_fl; 452 qidx_t ifsd_cidx; 453 } *if_rxsd_t; 454 455 /* multiple of word size */ 456 #ifdef __LP64__ 457 #define PKT_INFO_SIZE 6 458 #define RXD_INFO_SIZE 5 459 #define PKT_TYPE uint64_t 460 #else 461 #define PKT_INFO_SIZE 11 462 #define RXD_INFO_SIZE 8 463 #define PKT_TYPE uint32_t 464 #endif 465 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 466 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 467 468 typedef struct if_pkt_info_pad { 469 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 470 } *if_pkt_info_pad_t; 471 typedef struct if_rxd_info_pad { 472 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 473 } *if_rxd_info_pad_t; 474 475 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 476 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 477 478 479 static inline void 480 pkt_info_zero(if_pkt_info_t pi) 481 { 482 if_pkt_info_pad_t pi_pad; 483 484 pi_pad = (if_pkt_info_pad_t)pi; 485 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 486 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 487 #ifndef __LP64__ 488 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 489 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 490 #endif 491 } 492 493 static device_method_t iflib_pseudo_methods[] = { 494 DEVMETHOD(device_attach, noop_attach), 495 DEVMETHOD(device_detach, iflib_pseudo_detach), 496 DEVMETHOD_END 497 }; 498 499 driver_t iflib_pseudodriver = { 500 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 501 }; 502 503 static inline void 504 rxd_info_zero(if_rxd_info_t ri) 505 { 506 if_rxd_info_pad_t ri_pad; 507 int i; 508 509 ri_pad = (if_rxd_info_pad_t)ri; 510 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 511 ri_pad->rxd_val[i] = 0; 512 ri_pad->rxd_val[i+1] = 0; 513 ri_pad->rxd_val[i+2] = 0; 514 ri_pad->rxd_val[i+3] = 0; 515 } 516 #ifdef __LP64__ 517 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 518 #endif 519 } 520 521 /* 522 * Only allow a single packet to take up most 1/nth of the tx ring 523 */ 524 #define MAX_SINGLE_PACKET_FRACTION 12 525 #define IF_BAD_DMA (bus_addr_t)-1 526 527 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 528 529 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 530 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 531 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 532 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 533 534 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 535 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 536 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 537 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 538 539 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 540 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 541 542 void 543 iflib_set_detach(if_ctx_t ctx) 544 { 545 STATE_LOCK(ctx); 546 ctx->ifc_flags |= IFC_IN_DETACH; 547 STATE_UNLOCK(ctx); 548 } 549 550 /* Our boot-time initialization hook */ 551 static int iflib_module_event_handler(module_t, int, void *); 552 553 static moduledata_t iflib_moduledata = { 554 "iflib", 555 iflib_module_event_handler, 556 NULL 557 }; 558 559 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 560 MODULE_VERSION(iflib, 1); 561 562 MODULE_DEPEND(iflib, pci, 1, 1, 1); 563 MODULE_DEPEND(iflib, ether, 1, 1, 1); 564 565 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 566 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 567 568 #ifndef IFLIB_DEBUG_COUNTERS 569 #ifdef INVARIANTS 570 #define IFLIB_DEBUG_COUNTERS 1 571 #else 572 #define IFLIB_DEBUG_COUNTERS 0 573 #endif /* !INVARIANTS */ 574 #endif 575 576 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 577 "iflib driver parameters"); 578 579 /* 580 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 581 */ 582 static int iflib_min_tx_latency = 0; 583 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 584 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 585 static int iflib_no_tx_batch = 0; 586 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 587 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 588 589 590 #if IFLIB_DEBUG_COUNTERS 591 592 static int iflib_tx_seen; 593 static int iflib_tx_sent; 594 static int iflib_tx_encap; 595 static int iflib_rx_allocs; 596 static int iflib_fl_refills; 597 static int iflib_fl_refills_large; 598 static int iflib_tx_frees; 599 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 601 &iflib_tx_seen, 0, "# TX mbufs seen"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 603 &iflib_tx_sent, 0, "# TX mbufs sent"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 605 &iflib_tx_encap, 0, "# TX mbufs encapped"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 607 &iflib_tx_frees, 0, "# TX frees"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 609 &iflib_rx_allocs, 0, "# RX allocations"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 611 &iflib_fl_refills, 0, "# refills"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 613 &iflib_fl_refills_large, 0, "# large refills"); 614 615 616 static int iflib_txq_drain_flushing; 617 static int iflib_txq_drain_oactive; 618 static int iflib_txq_drain_notready; 619 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 621 &iflib_txq_drain_flushing, 0, "# drain flushes"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 623 &iflib_txq_drain_oactive, 0, "# drain oactives"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 625 &iflib_txq_drain_notready, 0, "# drain notready"); 626 627 628 static int iflib_encap_load_mbuf_fail; 629 static int iflib_encap_pad_mbuf_fail; 630 static int iflib_encap_txq_avail_fail; 631 static int iflib_encap_txd_encap_fail; 632 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 636 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 638 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 640 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 641 642 static int iflib_task_fn_rxs; 643 static int iflib_rx_intr_enables; 644 static int iflib_fast_intrs; 645 static int iflib_rx_unavail; 646 static int iflib_rx_ctx_inactive; 647 static int iflib_rx_if_input; 648 static int iflib_rx_mbuf_null; 649 static int iflib_rxd_flush; 650 651 static int iflib_verbose_debug; 652 653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 656 &iflib_rx_intr_enables, 0, "# RX intr enables"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 658 &iflib_fast_intrs, 0, "# fast_intr calls"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 660 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 664 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 666 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 668 &iflib_rxd_flush, 0, "# times rxd_flush called"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 670 &iflib_verbose_debug, 0, "enable verbose debugging"); 671 672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 673 static void 674 iflib_debug_reset(void) 675 { 676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 678 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 679 iflib_txq_drain_notready = 680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 683 iflib_rx_unavail = 684 iflib_rx_ctx_inactive = iflib_rx_if_input = 685 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 686 } 687 688 #else 689 #define DBG_COUNTER_INC(name) 690 static void iflib_debug_reset(void) {} 691 #endif 692 693 #define IFLIB_DEBUG 0 694 695 static void iflib_tx_structures_free(if_ctx_t ctx); 696 static void iflib_rx_structures_free(if_ctx_t ctx); 697 static int iflib_queues_alloc(if_ctx_t ctx); 698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 700 static int iflib_qset_structures_setup(if_ctx_t ctx); 701 static int iflib_msix_init(if_ctx_t ctx); 702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 705 #ifdef ALTQ 706 static void iflib_altq_if_start(if_t ifp); 707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 708 #endif 709 static int iflib_register(if_ctx_t); 710 static void iflib_deregister(if_ctx_t); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 static void iflib_free_intr_mem(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 723 SLIST_HEAD_INITIALIZER(cpu_offsets); 724 struct cpu_offset { 725 SLIST_ENTRY(cpu_offset) entries; 726 cpuset_t set; 727 unsigned int refcount; 728 uint16_t offset; 729 }; 730 static struct mtx cpu_offset_mtx; 731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 732 MTX_DEF); 733 734 NETDUMP_DEFINE(iflib); 735 736 #ifdef DEV_NETMAP 737 #include <sys/selinfo.h> 738 #include <net/netmap.h> 739 #include <dev/netmap/netmap_kern.h> 740 741 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 742 743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 744 745 /* 746 * device-specific sysctl variables: 747 * 748 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 749 * During regular operations the CRC is stripped, but on some 750 * hardware reception of frames not multiple of 64 is slower, 751 * so using crcstrip=0 helps in benchmarks. 752 * 753 * iflib_rx_miss, iflib_rx_miss_bufs: 754 * count packets that might be missed due to lost interrupts. 755 */ 756 SYSCTL_DECL(_dev_netmap); 757 /* 758 * The xl driver by default strips CRCs and we do not override it. 759 */ 760 761 int iflib_crcstrip = 1; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 763 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 764 765 int iflib_rx_miss, iflib_rx_miss_bufs; 766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 767 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 769 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 770 771 /* 772 * Register/unregister. We are already under netmap lock. 773 * Only called on the first register or the last unregister. 774 */ 775 static int 776 iflib_netmap_register(struct netmap_adapter *na, int onoff) 777 { 778 if_t ifp = na->ifp; 779 if_ctx_t ctx = ifp->if_softc; 780 int status; 781 782 CTX_LOCK(ctx); 783 IFDI_INTR_DISABLE(ctx); 784 785 /* Tell the stack that the interface is no longer active */ 786 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 787 788 if (!CTX_IS_VF(ctx)) 789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 790 791 /* enable or disable flags and callbacks in na and ifp */ 792 if (onoff) { 793 nm_set_native_flags(na); 794 } else { 795 nm_clear_native_flags(na); 796 } 797 iflib_stop(ctx); 798 iflib_init_locked(ctx); 799 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 800 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 801 if (status) 802 nm_clear_native_flags(na); 803 CTX_UNLOCK(ctx); 804 return (status); 805 } 806 807 static int 808 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 809 { 810 struct netmap_adapter *na = kring->na; 811 u_int const lim = kring->nkr_num_slots - 1; 812 u_int head = kring->rhead; 813 struct netmap_ring *ring = kring->ring; 814 bus_dmamap_t *map; 815 struct if_rxd_update iru; 816 if_ctx_t ctx = rxq->ifr_ctx; 817 iflib_fl_t fl = &rxq->ifr_fl[0]; 818 uint32_t refill_pidx, nic_i; 819 #if IFLIB_DEBUG_COUNTERS 820 int rf_count = 0; 821 #endif 822 823 if (nm_i == head && __predict_true(!init)) 824 return 0; 825 iru_init(&iru, rxq, 0 /* flid */); 826 map = fl->ifl_sds.ifsd_map; 827 refill_pidx = netmap_idx_k2n(kring, nm_i); 828 /* 829 * IMPORTANT: we must leave one free slot in the ring, 830 * so move head back by one unit 831 */ 832 head = nm_prev(head, lim); 833 nic_i = UINT_MAX; 834 DBG_COUNTER_INC(fl_refills); 835 while (nm_i != head) { 836 #if IFLIB_DEBUG_COUNTERS 837 if (++rf_count == 9) 838 DBG_COUNTER_INC(fl_refills_large); 839 #endif 840 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 841 struct netmap_slot *slot = &ring->slot[nm_i]; 842 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 843 uint32_t nic_i_dma = refill_pidx; 844 nic_i = netmap_idx_k2n(kring, nm_i); 845 846 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 847 848 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 849 return netmap_ring_reinit(kring); 850 851 fl->ifl_vm_addrs[tmp_pidx] = addr; 852 if (__predict_false(init)) { 853 netmap_load_map(na, fl->ifl_buf_tag, 854 map[nic_i], addr); 855 } else if (slot->flags & NS_BUF_CHANGED) { 856 /* buffer has changed, reload map */ 857 netmap_reload_map(na, fl->ifl_buf_tag, 858 map[nic_i], addr); 859 } 860 slot->flags &= ~NS_BUF_CHANGED; 861 862 nm_i = nm_next(nm_i, lim); 863 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 864 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 865 continue; 866 867 iru.iru_pidx = refill_pidx; 868 iru.iru_count = tmp_pidx+1; 869 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 870 refill_pidx = nic_i; 871 for (int n = 0; n < iru.iru_count; n++) { 872 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 873 BUS_DMASYNC_PREREAD); 874 /* XXX - change this to not use the netmap func*/ 875 nic_i_dma = nm_next(nic_i_dma, lim); 876 } 877 } 878 } 879 kring->nr_hwcur = head; 880 881 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 883 if (__predict_true(nic_i != UINT_MAX)) { 884 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 885 DBG_COUNTER_INC(rxd_flush); 886 } 887 return (0); 888 } 889 890 /* 891 * Reconcile kernel and user view of the transmit ring. 892 * 893 * All information is in the kring. 894 * Userspace wants to send packets up to the one before kring->rhead, 895 * kernel knows kring->nr_hwcur is the first unsent packet. 896 * 897 * Here we push packets out (as many as possible), and possibly 898 * reclaim buffers from previously completed transmission. 899 * 900 * The caller (netmap) guarantees that there is only one instance 901 * running at any time. Any interference with other driver 902 * methods should be handled by the individual drivers. 903 */ 904 static int 905 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 906 { 907 struct netmap_adapter *na = kring->na; 908 if_t ifp = na->ifp; 909 struct netmap_ring *ring = kring->ring; 910 u_int nm_i; /* index into the netmap kring */ 911 u_int nic_i; /* index into the NIC ring */ 912 u_int n; 913 u_int const lim = kring->nkr_num_slots - 1; 914 u_int const head = kring->rhead; 915 struct if_pkt_info pi; 916 917 /* 918 * interrupts on every tx packet are expensive so request 919 * them every half ring, or where NS_REPORT is set 920 */ 921 u_int report_frequency = kring->nkr_num_slots >> 1; 922 /* device-specific */ 923 if_ctx_t ctx = ifp->if_softc; 924 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 925 926 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 927 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 928 929 /* 930 * First part: process new packets to send. 931 * nm_i is the current index in the netmap kring, 932 * nic_i is the corresponding index in the NIC ring. 933 * 934 * If we have packets to send (nm_i != head) 935 * iterate over the netmap ring, fetch length and update 936 * the corresponding slot in the NIC ring. Some drivers also 937 * need to update the buffer's physical address in the NIC slot 938 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 939 * 940 * The netmap_reload_map() calls is especially expensive, 941 * even when (as in this case) the tag is 0, so do only 942 * when the buffer has actually changed. 943 * 944 * If possible do not set the report/intr bit on all slots, 945 * but only a few times per ring or when NS_REPORT is set. 946 * 947 * Finally, on 10G and faster drivers, it might be useful 948 * to prefetch the next slot and txr entry. 949 */ 950 951 nm_i = kring->nr_hwcur; 952 if (nm_i != head) { /* we have new packets to send */ 953 pkt_info_zero(&pi); 954 pi.ipi_segs = txq->ift_segs; 955 pi.ipi_qsidx = kring->ring_id; 956 nic_i = netmap_idx_k2n(kring, nm_i); 957 958 __builtin_prefetch(&ring->slot[nm_i]); 959 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 960 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 961 962 for (n = 0; nm_i != head; n++) { 963 struct netmap_slot *slot = &ring->slot[nm_i]; 964 u_int len = slot->len; 965 uint64_t paddr; 966 void *addr = PNMB(na, slot, &paddr); 967 int flags = (slot->flags & NS_REPORT || 968 nic_i == 0 || nic_i == report_frequency) ? 969 IPI_TX_INTR : 0; 970 971 /* device-specific */ 972 pi.ipi_len = len; 973 pi.ipi_segs[0].ds_addr = paddr; 974 pi.ipi_segs[0].ds_len = len; 975 pi.ipi_nsegs = 1; 976 pi.ipi_ndescs = 0; 977 pi.ipi_pidx = nic_i; 978 pi.ipi_flags = flags; 979 980 /* Fill the slot in the NIC ring. */ 981 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 982 DBG_COUNTER_INC(tx_encap); 983 984 /* prefetch for next round */ 985 __builtin_prefetch(&ring->slot[nm_i + 1]); 986 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 987 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 988 989 NM_CHECK_ADDR_LEN(na, addr, len); 990 991 if (slot->flags & NS_BUF_CHANGED) { 992 /* buffer has changed, reload map */ 993 netmap_reload_map(na, txq->ift_buf_tag, 994 txq->ift_sds.ifsd_map[nic_i], addr); 995 } 996 /* make sure changes to the buffer are synced */ 997 bus_dmamap_sync(txq->ift_buf_tag, 998 txq->ift_sds.ifsd_map[nic_i], 999 BUS_DMASYNC_PREWRITE); 1000 1001 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1002 nm_i = nm_next(nm_i, lim); 1003 nic_i = nm_next(nic_i, lim); 1004 } 1005 kring->nr_hwcur = nm_i; 1006 1007 /* synchronize the NIC ring */ 1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1010 1011 /* (re)start the tx unit up to slot nic_i (excluded) */ 1012 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1013 } 1014 1015 /* 1016 * Second part: reclaim buffers for completed transmissions. 1017 * 1018 * If there are unclaimed buffers, attempt to reclaim them. 1019 * If none are reclaimed, and TX IRQs are not in use, do an initial 1020 * minimal delay, then trigger the tx handler which will spin in the 1021 * group task queue. 1022 */ 1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1024 if (iflib_tx_credits_update(ctx, txq)) { 1025 /* some tx completed, increment avail */ 1026 nic_i = txq->ift_cidx_processed; 1027 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1028 } 1029 } 1030 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1032 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1033 iflib_timer, txq, txq->ift_timer.c_cpu); 1034 } 1035 return (0); 1036 } 1037 1038 /* 1039 * Reconcile kernel and user view of the receive ring. 1040 * Same as for the txsync, this routine must be efficient. 1041 * The caller guarantees a single invocations, but races against 1042 * the rest of the driver should be handled here. 1043 * 1044 * On call, kring->rhead is the first packet that userspace wants 1045 * to keep, and kring->rcur is the wakeup point. 1046 * The kernel has previously reported packets up to kring->rtail. 1047 * 1048 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1049 * of whether or not we received an interrupt. 1050 */ 1051 static int 1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1053 { 1054 struct netmap_adapter *na = kring->na; 1055 struct netmap_ring *ring = kring->ring; 1056 if_t ifp = na->ifp; 1057 iflib_fl_t fl; 1058 uint32_t nm_i; /* index into the netmap ring */ 1059 uint32_t nic_i; /* index into the NIC ring */ 1060 u_int i, n; 1061 u_int const lim = kring->nkr_num_slots - 1; 1062 u_int const head = kring->rhead; 1063 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1064 struct if_rxd_info ri; 1065 1066 if_ctx_t ctx = ifp->if_softc; 1067 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1068 if (head > lim) 1069 return netmap_ring_reinit(kring); 1070 1071 /* 1072 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1073 */ 1074 1075 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1076 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1078 } 1079 1080 /* 1081 * First part: import newly received packets. 1082 * 1083 * nm_i is the index of the next free slot in the netmap ring, 1084 * nic_i is the index of the next received packet in the NIC ring, 1085 * and they may differ in case if_init() has been called while 1086 * in netmap mode. For the receive ring we have 1087 * 1088 * nic_i = rxr->next_check; 1089 * nm_i = kring->nr_hwtail (previous) 1090 * and 1091 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1092 * 1093 * rxr->next_check is set to 0 on a ring reinit 1094 */ 1095 if (netmap_no_pendintr || force_update) { 1096 int crclen = iflib_crcstrip ? 0 : 4; 1097 int error, avail; 1098 1099 for (i = 0; i < rxq->ifr_nfl; i++) { 1100 fl = &rxq->ifr_fl[i]; 1101 nic_i = fl->ifl_cidx; 1102 nm_i = netmap_idx_n2k(kring, nic_i); 1103 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1104 rxq->ifr_id, nic_i, USHRT_MAX); 1105 for (n = 0; avail > 0; n++, avail--) { 1106 rxd_info_zero(&ri); 1107 ri.iri_frags = rxq->ifr_frags; 1108 ri.iri_qsidx = kring->ring_id; 1109 ri.iri_ifp = ctx->ifc_ifp; 1110 ri.iri_cidx = nic_i; 1111 1112 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1113 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1114 ring->slot[nm_i].flags = 0; 1115 bus_dmamap_sync(fl->ifl_buf_tag, 1116 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1117 nm_i = nm_next(nm_i, lim); 1118 nic_i = nm_next(nic_i, lim); 1119 } 1120 if (n) { /* update the state variables */ 1121 if (netmap_no_pendintr && !force_update) { 1122 /* diagnostics */ 1123 iflib_rx_miss ++; 1124 iflib_rx_miss_bufs += n; 1125 } 1126 fl->ifl_cidx = nic_i; 1127 kring->nr_hwtail = nm_i; 1128 } 1129 kring->nr_kflags &= ~NKR_PENDINTR; 1130 } 1131 } 1132 /* 1133 * Second part: skip past packets that userspace has released. 1134 * (kring->nr_hwcur to head excluded), 1135 * and make the buffers available for reception. 1136 * As usual nm_i is the index in the netmap ring, 1137 * nic_i is the index in the NIC ring, and 1138 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1139 */ 1140 /* XXX not sure how this will work with multiple free lists */ 1141 nm_i = kring->nr_hwcur; 1142 1143 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1144 } 1145 1146 static void 1147 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1148 { 1149 if_ctx_t ctx = na->ifp->if_softc; 1150 1151 CTX_LOCK(ctx); 1152 if (onoff) { 1153 IFDI_INTR_ENABLE(ctx); 1154 } else { 1155 IFDI_INTR_DISABLE(ctx); 1156 } 1157 CTX_UNLOCK(ctx); 1158 } 1159 1160 1161 static int 1162 iflib_netmap_attach(if_ctx_t ctx) 1163 { 1164 struct netmap_adapter na; 1165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1166 1167 bzero(&na, sizeof(na)); 1168 1169 na.ifp = ctx->ifc_ifp; 1170 na.na_flags = NAF_BDG_MAYSLEEP; 1171 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1172 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1173 1174 na.num_tx_desc = scctx->isc_ntxd[0]; 1175 na.num_rx_desc = scctx->isc_nrxd[0]; 1176 na.nm_txsync = iflib_netmap_txsync; 1177 na.nm_rxsync = iflib_netmap_rxsync; 1178 na.nm_register = iflib_netmap_register; 1179 na.nm_intr = iflib_netmap_intr; 1180 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1181 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1182 return (netmap_attach(&na)); 1183 } 1184 1185 static void 1186 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1187 { 1188 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1189 struct netmap_slot *slot; 1190 1191 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1192 if (slot == NULL) 1193 return; 1194 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1195 1196 /* 1197 * In netmap mode, set the map for the packet buffer. 1198 * NOTE: Some drivers (not this one) also need to set 1199 * the physical buffer address in the NIC ring. 1200 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1201 * netmap slot index, si 1202 */ 1203 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1204 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1205 NMB(na, slot + si)); 1206 } 1207 } 1208 1209 static void 1210 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1211 { 1212 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1213 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1214 struct netmap_slot *slot; 1215 uint32_t nm_i; 1216 1217 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1218 if (slot == NULL) 1219 return; 1220 nm_i = netmap_idx_n2k(kring, 0); 1221 netmap_fl_refill(rxq, kring, nm_i, true); 1222 } 1223 1224 static void 1225 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1226 { 1227 struct netmap_kring *kring; 1228 uint16_t txqid; 1229 1230 txqid = txq->ift_id; 1231 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1232 1233 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1234 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1235 BUS_DMASYNC_POSTREAD); 1236 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1237 netmap_tx_irq(ctx->ifc_ifp, txqid); 1238 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1239 if (hz < 2000) 1240 *reset_on = 1; 1241 else 1242 *reset_on = hz / 1000; 1243 } 1244 } 1245 } 1246 1247 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1248 1249 #else 1250 #define iflib_netmap_txq_init(ctx, txq) 1251 #define iflib_netmap_rxq_init(ctx, rxq) 1252 #define iflib_netmap_detach(ifp) 1253 1254 #define iflib_netmap_attach(ctx) (0) 1255 #define netmap_rx_irq(ifp, qid, budget) (0) 1256 #define netmap_tx_irq(ifp, qid) do {} while (0) 1257 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1258 1259 #endif 1260 1261 #if defined(__i386__) || defined(__amd64__) 1262 static __inline void 1263 prefetch(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 } 1267 static __inline void 1268 prefetch2cachelines(void *x) 1269 { 1270 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1271 #if (CACHE_LINE_SIZE < 128) 1272 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1273 #endif 1274 } 1275 #else 1276 #define prefetch(x) 1277 #define prefetch2cachelines(x) 1278 #endif 1279 1280 static void 1281 iflib_gen_mac(if_ctx_t ctx) 1282 { 1283 struct thread *td; 1284 MD5_CTX mdctx; 1285 char uuid[HOSTUUIDLEN+1]; 1286 char buf[HOSTUUIDLEN+16]; 1287 uint8_t *mac; 1288 unsigned char digest[16]; 1289 1290 td = curthread; 1291 mac = ctx->ifc_mac; 1292 uuid[HOSTUUIDLEN] = 0; 1293 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1294 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1295 /* 1296 * Generate a pseudo-random, deterministic MAC 1297 * address based on the UUID and unit number. 1298 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1299 */ 1300 MD5Init(&mdctx); 1301 MD5Update(&mdctx, buf, strlen(buf)); 1302 MD5Final(digest, &mdctx); 1303 1304 mac[0] = 0x58; 1305 mac[1] = 0x9C; 1306 mac[2] = 0xFC; 1307 mac[3] = digest[0]; 1308 mac[4] = digest[1]; 1309 mac[5] = digest[2]; 1310 } 1311 1312 static void 1313 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1314 { 1315 iflib_fl_t fl; 1316 1317 fl = &rxq->ifr_fl[flid]; 1318 iru->iru_paddrs = fl->ifl_bus_addrs; 1319 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1320 iru->iru_idxs = fl->ifl_rxd_idxs; 1321 iru->iru_qsidx = rxq->ifr_id; 1322 iru->iru_buf_size = fl->ifl_buf_size; 1323 iru->iru_flidx = fl->ifl_id; 1324 } 1325 1326 static void 1327 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1328 { 1329 if (err) 1330 return; 1331 *(bus_addr_t *) arg = segs[0].ds_addr; 1332 } 1333 1334 int 1335 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1336 { 1337 int err; 1338 device_t dev = ctx->ifc_dev; 1339 1340 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1341 align, 0, /* alignment, bounds */ 1342 BUS_SPACE_MAXADDR, /* lowaddr */ 1343 BUS_SPACE_MAXADDR, /* highaddr */ 1344 NULL, NULL, /* filter, filterarg */ 1345 size, /* maxsize */ 1346 1, /* nsegments */ 1347 size, /* maxsegsize */ 1348 BUS_DMA_ALLOCNOW, /* flags */ 1349 NULL, /* lockfunc */ 1350 NULL, /* lockarg */ 1351 &dma->idi_tag); 1352 if (err) { 1353 device_printf(dev, 1354 "%s: bus_dma_tag_create failed: %d\n", 1355 __func__, err); 1356 goto fail_0; 1357 } 1358 1359 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1360 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1361 if (err) { 1362 device_printf(dev, 1363 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1364 __func__, (uintmax_t)size, err); 1365 goto fail_1; 1366 } 1367 1368 dma->idi_paddr = IF_BAD_DMA; 1369 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1370 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1371 if (err || dma->idi_paddr == IF_BAD_DMA) { 1372 device_printf(dev, 1373 "%s: bus_dmamap_load failed: %d\n", 1374 __func__, err); 1375 goto fail_2; 1376 } 1377 1378 dma->idi_size = size; 1379 return (0); 1380 1381 fail_2: 1382 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1383 fail_1: 1384 bus_dma_tag_destroy(dma->idi_tag); 1385 fail_0: 1386 dma->idi_tag = NULL; 1387 1388 return (err); 1389 } 1390 1391 int 1392 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1393 { 1394 if_shared_ctx_t sctx = ctx->ifc_sctx; 1395 1396 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1397 1398 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1399 } 1400 1401 int 1402 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1403 { 1404 int i, err; 1405 iflib_dma_info_t *dmaiter; 1406 1407 dmaiter = dmalist; 1408 for (i = 0; i < count; i++, dmaiter++) { 1409 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1410 break; 1411 } 1412 if (err) 1413 iflib_dma_free_multi(dmalist, i); 1414 return (err); 1415 } 1416 1417 void 1418 iflib_dma_free(iflib_dma_info_t dma) 1419 { 1420 if (dma->idi_tag == NULL) 1421 return; 1422 if (dma->idi_paddr != IF_BAD_DMA) { 1423 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1424 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1425 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1426 dma->idi_paddr = IF_BAD_DMA; 1427 } 1428 if (dma->idi_vaddr != NULL) { 1429 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1430 dma->idi_vaddr = NULL; 1431 } 1432 bus_dma_tag_destroy(dma->idi_tag); 1433 dma->idi_tag = NULL; 1434 } 1435 1436 void 1437 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1438 { 1439 int i; 1440 iflib_dma_info_t *dmaiter = dmalist; 1441 1442 for (i = 0; i < count; i++, dmaiter++) 1443 iflib_dma_free(*dmaiter); 1444 } 1445 1446 #ifdef EARLY_AP_STARTUP 1447 static const int iflib_started = 1; 1448 #else 1449 /* 1450 * We used to abuse the smp_started flag to decide if the queues have been 1451 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1452 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1453 * is set. Run a SYSINIT() strictly after that to just set a usable 1454 * completion flag. 1455 */ 1456 1457 static int iflib_started; 1458 1459 static void 1460 iflib_record_started(void *arg) 1461 { 1462 iflib_started = 1; 1463 } 1464 1465 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1466 iflib_record_started, NULL); 1467 #endif 1468 1469 static int 1470 iflib_fast_intr(void *arg) 1471 { 1472 iflib_filter_info_t info = arg; 1473 struct grouptask *gtask = info->ifi_task; 1474 int result; 1475 1476 if (!iflib_started) 1477 return (FILTER_STRAY); 1478 1479 DBG_COUNTER_INC(fast_intrs); 1480 if (info->ifi_filter != NULL) { 1481 result = info->ifi_filter(info->ifi_filter_arg); 1482 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1483 return (result); 1484 } 1485 1486 GROUPTASK_ENQUEUE(gtask); 1487 return (FILTER_HANDLED); 1488 } 1489 1490 static int 1491 iflib_fast_intr_rxtx(void *arg) 1492 { 1493 iflib_filter_info_t info = arg; 1494 struct grouptask *gtask = info->ifi_task; 1495 if_ctx_t ctx; 1496 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1497 iflib_txq_t txq; 1498 void *sc; 1499 int i, cidx, result; 1500 qidx_t txqid; 1501 bool intr_enable, intr_legacy; 1502 1503 if (!iflib_started) 1504 return (FILTER_STRAY); 1505 1506 DBG_COUNTER_INC(fast_intrs); 1507 if (info->ifi_filter != NULL) { 1508 result = info->ifi_filter(info->ifi_filter_arg); 1509 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1510 return (result); 1511 } 1512 1513 ctx = rxq->ifr_ctx; 1514 sc = ctx->ifc_softc; 1515 intr_enable = false; 1516 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1517 MPASS(rxq->ifr_ntxqirq); 1518 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1519 txqid = rxq->ifr_txqid[i]; 1520 txq = &ctx->ifc_txqs[txqid]; 1521 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1522 BUS_DMASYNC_POSTREAD); 1523 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1524 if (intr_legacy) 1525 intr_enable = true; 1526 else 1527 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1528 continue; 1529 } 1530 GROUPTASK_ENQUEUE(&txq->ift_task); 1531 } 1532 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1533 cidx = rxq->ifr_cq_cidx; 1534 else 1535 cidx = rxq->ifr_fl[0].ifl_cidx; 1536 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1537 GROUPTASK_ENQUEUE(gtask); 1538 else { 1539 if (intr_legacy) 1540 intr_enable = true; 1541 else 1542 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1543 DBG_COUNTER_INC(rx_intr_enables); 1544 } 1545 if (intr_enable) 1546 IFDI_INTR_ENABLE(ctx); 1547 return (FILTER_HANDLED); 1548 } 1549 1550 1551 static int 1552 iflib_fast_intr_ctx(void *arg) 1553 { 1554 iflib_filter_info_t info = arg; 1555 struct grouptask *gtask = info->ifi_task; 1556 int result; 1557 1558 if (!iflib_started) 1559 return (FILTER_STRAY); 1560 1561 DBG_COUNTER_INC(fast_intrs); 1562 if (info->ifi_filter != NULL) { 1563 result = info->ifi_filter(info->ifi_filter_arg); 1564 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1565 return (result); 1566 } 1567 1568 GROUPTASK_ENQUEUE(gtask); 1569 return (FILTER_HANDLED); 1570 } 1571 1572 static int 1573 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1574 driver_filter_t filter, driver_intr_t handler, void *arg, 1575 const char *name) 1576 { 1577 int rc, flags; 1578 struct resource *res; 1579 void *tag = NULL; 1580 device_t dev = ctx->ifc_dev; 1581 1582 flags = RF_ACTIVE; 1583 if (ctx->ifc_flags & IFC_LEGACY) 1584 flags |= RF_SHAREABLE; 1585 MPASS(rid < 512); 1586 irq->ii_rid = rid; 1587 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1588 if (res == NULL) { 1589 device_printf(dev, 1590 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1591 return (ENOMEM); 1592 } 1593 irq->ii_res = res; 1594 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1595 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1596 filter, handler, arg, &tag); 1597 if (rc != 0) { 1598 device_printf(dev, 1599 "failed to setup interrupt for rid %d, name %s: %d\n", 1600 rid, name ? name : "unknown", rc); 1601 return (rc); 1602 } else if (name) 1603 bus_describe_intr(dev, res, tag, "%s", name); 1604 1605 irq->ii_tag = tag; 1606 return (0); 1607 } 1608 1609 1610 /********************************************************************* 1611 * 1612 * Allocate DMA resources for TX buffers as well as memory for the TX 1613 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1614 * iflib_sw_tx_desc_array structure, storing all the information that 1615 * is needed to transmit a packet on the wire. This is called only 1616 * once at attach, setup is done every reset. 1617 * 1618 **********************************************************************/ 1619 static int 1620 iflib_txsd_alloc(iflib_txq_t txq) 1621 { 1622 if_ctx_t ctx = txq->ift_ctx; 1623 if_shared_ctx_t sctx = ctx->ifc_sctx; 1624 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1625 device_t dev = ctx->ifc_dev; 1626 bus_size_t tsomaxsize; 1627 int err, nsegments, ntsosegments; 1628 bool tso; 1629 1630 nsegments = scctx->isc_tx_nsegments; 1631 ntsosegments = scctx->isc_tx_tso_segments_max; 1632 tsomaxsize = scctx->isc_tx_tso_size_max; 1633 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1634 tsomaxsize += sizeof(struct ether_vlan_header); 1635 MPASS(scctx->isc_ntxd[0] > 0); 1636 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1637 MPASS(nsegments > 0); 1638 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1639 MPASS(ntsosegments > 0); 1640 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1641 } 1642 1643 /* 1644 * Set up DMA tags for TX buffers. 1645 */ 1646 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1647 1, 0, /* alignment, bounds */ 1648 BUS_SPACE_MAXADDR, /* lowaddr */ 1649 BUS_SPACE_MAXADDR, /* highaddr */ 1650 NULL, NULL, /* filter, filterarg */ 1651 sctx->isc_tx_maxsize, /* maxsize */ 1652 nsegments, /* nsegments */ 1653 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1654 0, /* flags */ 1655 NULL, /* lockfunc */ 1656 NULL, /* lockfuncarg */ 1657 &txq->ift_buf_tag))) { 1658 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1659 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1660 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1661 goto fail; 1662 } 1663 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1664 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1665 1, 0, /* alignment, bounds */ 1666 BUS_SPACE_MAXADDR, /* lowaddr */ 1667 BUS_SPACE_MAXADDR, /* highaddr */ 1668 NULL, NULL, /* filter, filterarg */ 1669 tsomaxsize, /* maxsize */ 1670 ntsosegments, /* nsegments */ 1671 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1672 0, /* flags */ 1673 NULL, /* lockfunc */ 1674 NULL, /* lockfuncarg */ 1675 &txq->ift_tso_buf_tag))) { 1676 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1677 err); 1678 goto fail; 1679 } 1680 1681 /* Allocate memory for the TX mbuf map. */ 1682 if (!(txq->ift_sds.ifsd_m = 1683 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1684 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1685 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1686 err = ENOMEM; 1687 goto fail; 1688 } 1689 1690 /* 1691 * Create the DMA maps for TX buffers. 1692 */ 1693 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1694 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1695 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1696 device_printf(dev, 1697 "Unable to allocate TX buffer DMA map memory\n"); 1698 err = ENOMEM; 1699 goto fail; 1700 } 1701 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1702 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1703 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1704 device_printf(dev, 1705 "Unable to allocate TSO TX buffer map memory\n"); 1706 err = ENOMEM; 1707 goto fail; 1708 } 1709 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1710 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1711 &txq->ift_sds.ifsd_map[i]); 1712 if (err != 0) { 1713 device_printf(dev, "Unable to create TX DMA map\n"); 1714 goto fail; 1715 } 1716 if (!tso) 1717 continue; 1718 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1719 &txq->ift_sds.ifsd_tso_map[i]); 1720 if (err != 0) { 1721 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1722 goto fail; 1723 } 1724 } 1725 return (0); 1726 fail: 1727 /* We free all, it handles case where we are in the middle */ 1728 iflib_tx_structures_free(ctx); 1729 return (err); 1730 } 1731 1732 static void 1733 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1734 { 1735 bus_dmamap_t map; 1736 1737 map = NULL; 1738 if (txq->ift_sds.ifsd_map != NULL) 1739 map = txq->ift_sds.ifsd_map[i]; 1740 if (map != NULL) { 1741 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1742 bus_dmamap_unload(txq->ift_buf_tag, map); 1743 bus_dmamap_destroy(txq->ift_buf_tag, map); 1744 txq->ift_sds.ifsd_map[i] = NULL; 1745 } 1746 1747 map = NULL; 1748 if (txq->ift_sds.ifsd_tso_map != NULL) 1749 map = txq->ift_sds.ifsd_tso_map[i]; 1750 if (map != NULL) { 1751 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1752 BUS_DMASYNC_POSTWRITE); 1753 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1754 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1755 txq->ift_sds.ifsd_tso_map[i] = NULL; 1756 } 1757 } 1758 1759 static void 1760 iflib_txq_destroy(iflib_txq_t txq) 1761 { 1762 if_ctx_t ctx = txq->ift_ctx; 1763 1764 for (int i = 0; i < txq->ift_size; i++) 1765 iflib_txsd_destroy(ctx, txq, i); 1766 if (txq->ift_sds.ifsd_map != NULL) { 1767 free(txq->ift_sds.ifsd_map, M_IFLIB); 1768 txq->ift_sds.ifsd_map = NULL; 1769 } 1770 if (txq->ift_sds.ifsd_tso_map != NULL) { 1771 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1772 txq->ift_sds.ifsd_tso_map = NULL; 1773 } 1774 if (txq->ift_sds.ifsd_m != NULL) { 1775 free(txq->ift_sds.ifsd_m, M_IFLIB); 1776 txq->ift_sds.ifsd_m = NULL; 1777 } 1778 if (txq->ift_buf_tag != NULL) { 1779 bus_dma_tag_destroy(txq->ift_buf_tag); 1780 txq->ift_buf_tag = NULL; 1781 } 1782 if (txq->ift_tso_buf_tag != NULL) { 1783 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1784 txq->ift_tso_buf_tag = NULL; 1785 } 1786 } 1787 1788 static void 1789 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1790 { 1791 struct mbuf **mp; 1792 1793 mp = &txq->ift_sds.ifsd_m[i]; 1794 if (*mp == NULL) 1795 return; 1796 1797 if (txq->ift_sds.ifsd_map != NULL) { 1798 bus_dmamap_sync(txq->ift_buf_tag, 1799 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1800 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1801 } 1802 if (txq->ift_sds.ifsd_tso_map != NULL) { 1803 bus_dmamap_sync(txq->ift_tso_buf_tag, 1804 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1805 bus_dmamap_unload(txq->ift_tso_buf_tag, 1806 txq->ift_sds.ifsd_tso_map[i]); 1807 } 1808 m_free(*mp); 1809 DBG_COUNTER_INC(tx_frees); 1810 *mp = NULL; 1811 } 1812 1813 static int 1814 iflib_txq_setup(iflib_txq_t txq) 1815 { 1816 if_ctx_t ctx = txq->ift_ctx; 1817 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1818 if_shared_ctx_t sctx = ctx->ifc_sctx; 1819 iflib_dma_info_t di; 1820 int i; 1821 1822 /* Set number of descriptors available */ 1823 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1824 /* XXX make configurable */ 1825 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1826 1827 /* Reset indices */ 1828 txq->ift_cidx_processed = 0; 1829 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1830 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1831 1832 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1833 bzero((void *)di->idi_vaddr, di->idi_size); 1834 1835 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1836 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1837 bus_dmamap_sync(di->idi_tag, di->idi_map, 1838 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1839 return (0); 1840 } 1841 1842 /********************************************************************* 1843 * 1844 * Allocate DMA resources for RX buffers as well as memory for the RX 1845 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1846 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1847 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1848 * Since we use use one entry in iflib_sw_rx_desc_array per received 1849 * packet, the maximum number of entries we'll need is equal to the 1850 * number of hardware receive descriptors that we've allocated. 1851 * 1852 **********************************************************************/ 1853 static int 1854 iflib_rxsd_alloc(iflib_rxq_t rxq) 1855 { 1856 if_ctx_t ctx = rxq->ifr_ctx; 1857 if_shared_ctx_t sctx = ctx->ifc_sctx; 1858 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1859 device_t dev = ctx->ifc_dev; 1860 iflib_fl_t fl; 1861 int err; 1862 1863 MPASS(scctx->isc_nrxd[0] > 0); 1864 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1865 1866 fl = rxq->ifr_fl; 1867 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1868 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1869 /* Set up DMA tag for RX buffers. */ 1870 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1871 1, 0, /* alignment, bounds */ 1872 BUS_SPACE_MAXADDR, /* lowaddr */ 1873 BUS_SPACE_MAXADDR, /* highaddr */ 1874 NULL, NULL, /* filter, filterarg */ 1875 sctx->isc_rx_maxsize, /* maxsize */ 1876 sctx->isc_rx_nsegments, /* nsegments */ 1877 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1878 0, /* flags */ 1879 NULL, /* lockfunc */ 1880 NULL, /* lockarg */ 1881 &fl->ifl_buf_tag); 1882 if (err) { 1883 device_printf(dev, 1884 "Unable to allocate RX DMA tag: %d\n", err); 1885 goto fail; 1886 } 1887 1888 /* Allocate memory for the RX mbuf map. */ 1889 if (!(fl->ifl_sds.ifsd_m = 1890 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1891 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1892 device_printf(dev, 1893 "Unable to allocate RX mbuf map memory\n"); 1894 err = ENOMEM; 1895 goto fail; 1896 } 1897 1898 /* Allocate memory for the direct RX cluster pointer map. */ 1899 if (!(fl->ifl_sds.ifsd_cl = 1900 (caddr_t *) malloc(sizeof(caddr_t) * 1901 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1902 device_printf(dev, 1903 "Unable to allocate RX cluster map memory\n"); 1904 err = ENOMEM; 1905 goto fail; 1906 } 1907 1908 /* Allocate memory for the RX cluster bus address map. */ 1909 if (!(fl->ifl_sds.ifsd_ba = 1910 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1911 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1912 device_printf(dev, 1913 "Unable to allocate RX bus address map memory\n"); 1914 err = ENOMEM; 1915 goto fail; 1916 } 1917 1918 /* 1919 * Create the DMA maps for RX buffers. 1920 */ 1921 if (!(fl->ifl_sds.ifsd_map = 1922 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1923 device_printf(dev, 1924 "Unable to allocate RX buffer DMA map memory\n"); 1925 err = ENOMEM; 1926 goto fail; 1927 } 1928 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1929 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1930 &fl->ifl_sds.ifsd_map[i]); 1931 if (err != 0) { 1932 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1933 goto fail; 1934 } 1935 } 1936 } 1937 return (0); 1938 1939 fail: 1940 iflib_rx_structures_free(ctx); 1941 return (err); 1942 } 1943 1944 1945 /* 1946 * Internal service routines 1947 */ 1948 1949 struct rxq_refill_cb_arg { 1950 int error; 1951 bus_dma_segment_t seg; 1952 int nseg; 1953 }; 1954 1955 static void 1956 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1957 { 1958 struct rxq_refill_cb_arg *cb_arg = arg; 1959 1960 cb_arg->error = error; 1961 cb_arg->seg = segs[0]; 1962 cb_arg->nseg = nseg; 1963 } 1964 1965 /** 1966 * _iflib_fl_refill - refill an rxq free-buffer list 1967 * @ctx: the iflib context 1968 * @fl: the free list to refill 1969 * @count: the number of new buffers to allocate 1970 * 1971 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1972 * The caller must assure that @count does not exceed the queue's capacity. 1973 */ 1974 static void 1975 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1976 { 1977 struct if_rxd_update iru; 1978 struct rxq_refill_cb_arg cb_arg; 1979 struct mbuf *m; 1980 caddr_t cl, *sd_cl; 1981 struct mbuf **sd_m; 1982 bus_dmamap_t *sd_map; 1983 bus_addr_t bus_addr, *sd_ba; 1984 int err, frag_idx, i, idx, n, pidx; 1985 qidx_t credits; 1986 1987 sd_m = fl->ifl_sds.ifsd_m; 1988 sd_map = fl->ifl_sds.ifsd_map; 1989 sd_cl = fl->ifl_sds.ifsd_cl; 1990 sd_ba = fl->ifl_sds.ifsd_ba; 1991 pidx = fl->ifl_pidx; 1992 idx = pidx; 1993 frag_idx = fl->ifl_fragidx; 1994 credits = fl->ifl_credits; 1995 1996 i = 0; 1997 n = count; 1998 MPASS(n > 0); 1999 MPASS(credits + n <= fl->ifl_size); 2000 2001 if (pidx < fl->ifl_cidx) 2002 MPASS(pidx + n <= fl->ifl_cidx); 2003 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2004 MPASS(fl->ifl_gen == 0); 2005 if (pidx > fl->ifl_cidx) 2006 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2007 2008 DBG_COUNTER_INC(fl_refills); 2009 if (n > 8) 2010 DBG_COUNTER_INC(fl_refills_large); 2011 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2012 while (n--) { 2013 /* 2014 * We allocate an uninitialized mbuf + cluster, mbuf is 2015 * initialized after rx. 2016 * 2017 * If the cluster is still set then we know a minimum sized packet was received 2018 */ 2019 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2020 &frag_idx); 2021 if (frag_idx < 0) 2022 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2023 MPASS(frag_idx >= 0); 2024 if ((cl = sd_cl[frag_idx]) == NULL) { 2025 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 2026 break; 2027 2028 cb_arg.error = 0; 2029 MPASS(sd_map != NULL); 2030 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2031 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2032 BUS_DMA_NOWAIT); 2033 if (err != 0 || cb_arg.error) { 2034 /* 2035 * !zone_pack ? 2036 */ 2037 if (fl->ifl_zone == zone_pack) 2038 uma_zfree(fl->ifl_zone, cl); 2039 break; 2040 } 2041 2042 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2043 sd_cl[frag_idx] = cl; 2044 #if MEMORY_LOGGING 2045 fl->ifl_cl_enqueued++; 2046 #endif 2047 } else { 2048 bus_addr = sd_ba[frag_idx]; 2049 } 2050 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2051 BUS_DMASYNC_PREREAD); 2052 2053 MPASS(sd_m[frag_idx] == NULL); 2054 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2055 break; 2056 } 2057 sd_m[frag_idx] = m; 2058 bit_set(fl->ifl_rx_bitmap, frag_idx); 2059 #if MEMORY_LOGGING 2060 fl->ifl_m_enqueued++; 2061 #endif 2062 2063 DBG_COUNTER_INC(rx_allocs); 2064 fl->ifl_rxd_idxs[i] = frag_idx; 2065 fl->ifl_bus_addrs[i] = bus_addr; 2066 fl->ifl_vm_addrs[i] = cl; 2067 credits++; 2068 i++; 2069 MPASS(credits <= fl->ifl_size); 2070 if (++idx == fl->ifl_size) { 2071 fl->ifl_gen = 1; 2072 idx = 0; 2073 } 2074 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2075 iru.iru_pidx = pidx; 2076 iru.iru_count = i; 2077 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2078 i = 0; 2079 pidx = idx; 2080 fl->ifl_pidx = idx; 2081 fl->ifl_credits = credits; 2082 } 2083 } 2084 2085 if (i) { 2086 iru.iru_pidx = pidx; 2087 iru.iru_count = i; 2088 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2089 fl->ifl_pidx = idx; 2090 fl->ifl_credits = credits; 2091 } 2092 DBG_COUNTER_INC(rxd_flush); 2093 if (fl->ifl_pidx == 0) 2094 pidx = fl->ifl_size - 1; 2095 else 2096 pidx = fl->ifl_pidx - 1; 2097 2098 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2099 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2100 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2101 fl->ifl_fragidx = frag_idx; 2102 } 2103 2104 static __inline void 2105 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2106 { 2107 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2108 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2109 #ifdef INVARIANTS 2110 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2111 #endif 2112 2113 MPASS(fl->ifl_credits <= fl->ifl_size); 2114 MPASS(reclaimable == delta); 2115 2116 if (reclaimable > 0) 2117 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2118 } 2119 2120 uint8_t 2121 iflib_in_detach(if_ctx_t ctx) 2122 { 2123 bool in_detach; 2124 2125 STATE_LOCK(ctx); 2126 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2127 STATE_UNLOCK(ctx); 2128 return (in_detach); 2129 } 2130 2131 static void 2132 iflib_fl_bufs_free(iflib_fl_t fl) 2133 { 2134 iflib_dma_info_t idi = fl->ifl_ifdi; 2135 bus_dmamap_t sd_map; 2136 uint32_t i; 2137 2138 for (i = 0; i < fl->ifl_size; i++) { 2139 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2140 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2141 2142 if (*sd_cl != NULL) { 2143 sd_map = fl->ifl_sds.ifsd_map[i]; 2144 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2145 BUS_DMASYNC_POSTREAD); 2146 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2147 if (*sd_cl != NULL) 2148 uma_zfree(fl->ifl_zone, *sd_cl); 2149 // XXX: Should this get moved out? 2150 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2151 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2152 if (*sd_m != NULL) { 2153 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2154 uma_zfree(zone_mbuf, *sd_m); 2155 } 2156 } else { 2157 MPASS(*sd_cl == NULL); 2158 MPASS(*sd_m == NULL); 2159 } 2160 #if MEMORY_LOGGING 2161 fl->ifl_m_dequeued++; 2162 fl->ifl_cl_dequeued++; 2163 #endif 2164 *sd_cl = NULL; 2165 *sd_m = NULL; 2166 } 2167 #ifdef INVARIANTS 2168 for (i = 0; i < fl->ifl_size; i++) { 2169 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2170 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2171 } 2172 #endif 2173 /* 2174 * Reset free list values 2175 */ 2176 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2177 bzero(idi->idi_vaddr, idi->idi_size); 2178 } 2179 2180 /********************************************************************* 2181 * 2182 * Initialize a free list and its buffers. 2183 * 2184 **********************************************************************/ 2185 static int 2186 iflib_fl_setup(iflib_fl_t fl) 2187 { 2188 iflib_rxq_t rxq = fl->ifl_rxq; 2189 if_ctx_t ctx = rxq->ifr_ctx; 2190 2191 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2192 /* 2193 ** Free current RX buffer structs and their mbufs 2194 */ 2195 iflib_fl_bufs_free(fl); 2196 /* Now replenish the mbufs */ 2197 MPASS(fl->ifl_credits == 0); 2198 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2199 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2200 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2201 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2202 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2203 2204 2205 /* avoid pre-allocating zillions of clusters to an idle card 2206 * potentially speeding up attach 2207 */ 2208 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2209 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2210 if (min(128, fl->ifl_size) != fl->ifl_credits) 2211 return (ENOBUFS); 2212 /* 2213 * handle failure 2214 */ 2215 MPASS(rxq != NULL); 2216 MPASS(fl->ifl_ifdi != NULL); 2217 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2218 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2219 return (0); 2220 } 2221 2222 /********************************************************************* 2223 * 2224 * Free receive ring data structures 2225 * 2226 **********************************************************************/ 2227 static void 2228 iflib_rx_sds_free(iflib_rxq_t rxq) 2229 { 2230 iflib_fl_t fl; 2231 int i, j; 2232 2233 if (rxq->ifr_fl != NULL) { 2234 for (i = 0; i < rxq->ifr_nfl; i++) { 2235 fl = &rxq->ifr_fl[i]; 2236 if (fl->ifl_buf_tag != NULL) { 2237 if (fl->ifl_sds.ifsd_map != NULL) { 2238 for (j = 0; j < fl->ifl_size; j++) { 2239 if (fl->ifl_sds.ifsd_map[j] == 2240 NULL) 2241 continue; 2242 bus_dmamap_sync( 2243 fl->ifl_buf_tag, 2244 fl->ifl_sds.ifsd_map[j], 2245 BUS_DMASYNC_POSTREAD); 2246 bus_dmamap_unload( 2247 fl->ifl_buf_tag, 2248 fl->ifl_sds.ifsd_map[j]); 2249 } 2250 } 2251 bus_dma_tag_destroy(fl->ifl_buf_tag); 2252 fl->ifl_buf_tag = NULL; 2253 } 2254 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2255 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2256 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2257 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2258 fl->ifl_sds.ifsd_m = NULL; 2259 fl->ifl_sds.ifsd_cl = NULL; 2260 fl->ifl_sds.ifsd_ba = NULL; 2261 fl->ifl_sds.ifsd_map = NULL; 2262 } 2263 free(rxq->ifr_fl, M_IFLIB); 2264 rxq->ifr_fl = NULL; 2265 rxq->ifr_cq_cidx = 0; 2266 } 2267 } 2268 2269 /* 2270 * Timer routine 2271 */ 2272 static void 2273 iflib_timer(void *arg) 2274 { 2275 iflib_txq_t txq = arg; 2276 if_ctx_t ctx = txq->ift_ctx; 2277 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2278 uint64_t this_tick = ticks; 2279 uint32_t reset_on = hz / 2; 2280 2281 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2282 return; 2283 2284 /* 2285 ** Check on the state of the TX queue(s), this 2286 ** can be done without the lock because its RO 2287 ** and the HUNG state will be static if set. 2288 */ 2289 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2290 txq->ift_last_timer_tick = this_tick; 2291 IFDI_TIMER(ctx, txq->ift_id); 2292 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2293 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2294 (sctx->isc_pause_frames == 0))) 2295 goto hung; 2296 2297 if (ifmp_ring_is_stalled(txq->ift_br)) 2298 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2299 txq->ift_cleaned_prev = txq->ift_cleaned; 2300 } 2301 #ifdef DEV_NETMAP 2302 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2303 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2304 #endif 2305 /* handle any laggards */ 2306 if (txq->ift_db_pending) 2307 GROUPTASK_ENQUEUE(&txq->ift_task); 2308 2309 sctx->isc_pause_frames = 0; 2310 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2311 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2312 return; 2313 2314 hung: 2315 device_printf(ctx->ifc_dev, 2316 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2317 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2318 STATE_LOCK(ctx); 2319 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2320 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2321 iflib_admin_intr_deferred(ctx); 2322 STATE_UNLOCK(ctx); 2323 } 2324 2325 static void 2326 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2327 { 2328 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2329 2330 /* 2331 * XXX don't set the max_frame_size to larger 2332 * than the hardware can handle 2333 */ 2334 if (sctx->isc_max_frame_size <= MCLBYTES) 2335 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2336 else 2337 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2338 } 2339 2340 uint32_t 2341 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2342 { 2343 2344 return (ctx->ifc_rx_mbuf_sz); 2345 } 2346 2347 static void 2348 iflib_init_locked(if_ctx_t ctx) 2349 { 2350 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2351 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2352 if_t ifp = ctx->ifc_ifp; 2353 iflib_fl_t fl; 2354 iflib_txq_t txq; 2355 iflib_rxq_t rxq; 2356 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2357 2358 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2359 IFDI_INTR_DISABLE(ctx); 2360 2361 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2362 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2363 /* Set hardware offload abilities */ 2364 if_clearhwassist(ifp); 2365 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2366 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2367 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2368 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2369 if (if_getcapenable(ifp) & IFCAP_TSO4) 2370 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2371 if (if_getcapenable(ifp) & IFCAP_TSO6) 2372 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2373 2374 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2375 CALLOUT_LOCK(txq); 2376 callout_stop(&txq->ift_timer); 2377 CALLOUT_UNLOCK(txq); 2378 iflib_netmap_txq_init(ctx, txq); 2379 } 2380 2381 /* 2382 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2383 * that drivers can use the value when setting up the hardware receive 2384 * buffers. 2385 */ 2386 iflib_calc_rx_mbuf_sz(ctx); 2387 2388 #ifdef INVARIANTS 2389 i = if_getdrvflags(ifp); 2390 #endif 2391 IFDI_INIT(ctx); 2392 MPASS(if_getdrvflags(ifp) == i); 2393 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2394 /* XXX this should really be done on a per-queue basis */ 2395 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2396 MPASS(rxq->ifr_id == i); 2397 iflib_netmap_rxq_init(ctx, rxq); 2398 continue; 2399 } 2400 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2401 if (iflib_fl_setup(fl)) { 2402 device_printf(ctx->ifc_dev, 2403 "setting up free list %d failed - " 2404 "check cluster settings\n", j); 2405 goto done; 2406 } 2407 } 2408 } 2409 done: 2410 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2411 IFDI_INTR_ENABLE(ctx); 2412 txq = ctx->ifc_txqs; 2413 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2414 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2415 txq->ift_timer.c_cpu); 2416 } 2417 2418 static int 2419 iflib_media_change(if_t ifp) 2420 { 2421 if_ctx_t ctx = if_getsoftc(ifp); 2422 int err; 2423 2424 CTX_LOCK(ctx); 2425 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2426 iflib_init_locked(ctx); 2427 CTX_UNLOCK(ctx); 2428 return (err); 2429 } 2430 2431 static void 2432 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2433 { 2434 if_ctx_t ctx = if_getsoftc(ifp); 2435 2436 CTX_LOCK(ctx); 2437 IFDI_UPDATE_ADMIN_STATUS(ctx); 2438 IFDI_MEDIA_STATUS(ctx, ifmr); 2439 CTX_UNLOCK(ctx); 2440 } 2441 2442 void 2443 iflib_stop(if_ctx_t ctx) 2444 { 2445 iflib_txq_t txq = ctx->ifc_txqs; 2446 iflib_rxq_t rxq = ctx->ifc_rxqs; 2447 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2448 if_shared_ctx_t sctx = ctx->ifc_sctx; 2449 iflib_dma_info_t di; 2450 iflib_fl_t fl; 2451 int i, j; 2452 2453 /* Tell the stack that the interface is no longer active */ 2454 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2455 2456 IFDI_INTR_DISABLE(ctx); 2457 DELAY(1000); 2458 IFDI_STOP(ctx); 2459 DELAY(1000); 2460 2461 iflib_debug_reset(); 2462 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2463 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2464 /* make sure all transmitters have completed before proceeding XXX */ 2465 2466 CALLOUT_LOCK(txq); 2467 callout_stop(&txq->ift_timer); 2468 CALLOUT_UNLOCK(txq); 2469 2470 /* clean any enqueued buffers */ 2471 iflib_ifmp_purge(txq); 2472 /* Free any existing tx buffers. */ 2473 for (j = 0; j < txq->ift_size; j++) { 2474 iflib_txsd_free(ctx, txq, j); 2475 } 2476 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2477 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2478 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2479 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2480 txq->ift_pullups = 0; 2481 ifmp_ring_reset_stats(txq->ift_br); 2482 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2483 bzero((void *)di->idi_vaddr, di->idi_size); 2484 } 2485 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2486 /* make sure all transmitters have completed before proceeding XXX */ 2487 2488 rxq->ifr_cq_cidx = 0; 2489 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2490 bzero((void *)di->idi_vaddr, di->idi_size); 2491 /* also resets the free lists pidx/cidx */ 2492 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2493 iflib_fl_bufs_free(fl); 2494 } 2495 } 2496 2497 static inline caddr_t 2498 calc_next_rxd(iflib_fl_t fl, int cidx) 2499 { 2500 qidx_t size; 2501 int nrxd; 2502 caddr_t start, end, cur, next; 2503 2504 nrxd = fl->ifl_size; 2505 size = fl->ifl_rxd_size; 2506 start = fl->ifl_ifdi->idi_vaddr; 2507 2508 if (__predict_false(size == 0)) 2509 return (start); 2510 cur = start + size*cidx; 2511 end = start + size*nrxd; 2512 next = CACHE_PTR_NEXT(cur); 2513 return (next < end ? next : start); 2514 } 2515 2516 static inline void 2517 prefetch_pkts(iflib_fl_t fl, int cidx) 2518 { 2519 int nextptr; 2520 int nrxd = fl->ifl_size; 2521 caddr_t next_rxd; 2522 2523 2524 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2525 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2526 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2527 next_rxd = calc_next_rxd(fl, cidx); 2528 prefetch(next_rxd); 2529 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2530 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2531 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2532 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2533 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2534 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2535 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2536 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2537 } 2538 2539 static void 2540 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2541 { 2542 int flid, cidx; 2543 bus_dmamap_t map; 2544 iflib_fl_t fl; 2545 int next; 2546 2547 map = NULL; 2548 flid = irf->irf_flid; 2549 cidx = irf->irf_idx; 2550 fl = &rxq->ifr_fl[flid]; 2551 sd->ifsd_fl = fl; 2552 sd->ifsd_cidx = cidx; 2553 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2554 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2555 fl->ifl_credits--; 2556 #if MEMORY_LOGGING 2557 fl->ifl_m_dequeued++; 2558 #endif 2559 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2560 prefetch_pkts(fl, cidx); 2561 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2562 prefetch(&fl->ifl_sds.ifsd_map[next]); 2563 map = fl->ifl_sds.ifsd_map[cidx]; 2564 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2565 2566 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2567 MPASS(fl->ifl_cidx == cidx); 2568 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2569 if (unload) 2570 bus_dmamap_unload(fl->ifl_buf_tag, map); 2571 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2572 if (__predict_false(fl->ifl_cidx == 0)) 2573 fl->ifl_gen = 0; 2574 bit_clear(fl->ifl_rx_bitmap, cidx); 2575 } 2576 2577 static struct mbuf * 2578 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2579 { 2580 int i, padlen , flags; 2581 struct mbuf *m, *mh, *mt; 2582 caddr_t cl; 2583 2584 i = 0; 2585 mh = NULL; 2586 do { 2587 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2588 2589 MPASS(*sd->ifsd_cl != NULL); 2590 MPASS(*sd->ifsd_m != NULL); 2591 2592 /* Don't include zero-length frags */ 2593 if (ri->iri_frags[i].irf_len == 0) { 2594 /* XXX we can save the cluster here, but not the mbuf */ 2595 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2596 m_free(*sd->ifsd_m); 2597 *sd->ifsd_m = NULL; 2598 continue; 2599 } 2600 m = *sd->ifsd_m; 2601 *sd->ifsd_m = NULL; 2602 if (mh == NULL) { 2603 flags = M_PKTHDR|M_EXT; 2604 mh = mt = m; 2605 padlen = ri->iri_pad; 2606 } else { 2607 flags = M_EXT; 2608 mt->m_next = m; 2609 mt = m; 2610 /* assuming padding is only on the first fragment */ 2611 padlen = 0; 2612 } 2613 cl = *sd->ifsd_cl; 2614 *sd->ifsd_cl = NULL; 2615 2616 /* Can these two be made one ? */ 2617 m_init(m, M_NOWAIT, MT_DATA, flags); 2618 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2619 /* 2620 * These must follow m_init and m_cljset 2621 */ 2622 m->m_data += padlen; 2623 ri->iri_len -= padlen; 2624 m->m_len = ri->iri_frags[i].irf_len; 2625 } while (++i < ri->iri_nfrags); 2626 2627 return (mh); 2628 } 2629 2630 /* 2631 * Process one software descriptor 2632 */ 2633 static struct mbuf * 2634 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2635 { 2636 struct if_rxsd sd; 2637 struct mbuf *m; 2638 2639 /* should I merge this back in now that the two paths are basically duplicated? */ 2640 if (ri->iri_nfrags == 1 && 2641 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2642 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2643 m = *sd.ifsd_m; 2644 *sd.ifsd_m = NULL; 2645 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2646 #ifndef __NO_STRICT_ALIGNMENT 2647 if (!IP_ALIGNED(m)) 2648 m->m_data += 2; 2649 #endif 2650 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2651 m->m_len = ri->iri_frags[0].irf_len; 2652 } else { 2653 m = assemble_segments(rxq, ri, &sd); 2654 } 2655 m->m_pkthdr.len = ri->iri_len; 2656 m->m_pkthdr.rcvif = ri->iri_ifp; 2657 m->m_flags |= ri->iri_flags; 2658 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2659 m->m_pkthdr.flowid = ri->iri_flowid; 2660 M_HASHTYPE_SET(m, ri->iri_rsstype); 2661 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2662 m->m_pkthdr.csum_data = ri->iri_csum_data; 2663 return (m); 2664 } 2665 2666 #if defined(INET6) || defined(INET) 2667 static void 2668 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2669 { 2670 CURVNET_SET(lc->ifp->if_vnet); 2671 #if defined(INET6) 2672 *v6 = VNET(ip6_forwarding); 2673 #endif 2674 #if defined(INET) 2675 *v4 = VNET(ipforwarding); 2676 #endif 2677 CURVNET_RESTORE(); 2678 } 2679 2680 /* 2681 * Returns true if it's possible this packet could be LROed. 2682 * if it returns false, it is guaranteed that tcp_lro_rx() 2683 * would not return zero. 2684 */ 2685 static bool 2686 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2687 { 2688 struct ether_header *eh; 2689 uint16_t eh_type; 2690 2691 eh = mtod(m, struct ether_header *); 2692 eh_type = ntohs(eh->ether_type); 2693 switch (eh_type) { 2694 #if defined(INET6) 2695 case ETHERTYPE_IPV6: 2696 return !v6_forwarding; 2697 #endif 2698 #if defined (INET) 2699 case ETHERTYPE_IP: 2700 return !v4_forwarding; 2701 #endif 2702 } 2703 2704 return false; 2705 } 2706 #else 2707 static void 2708 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2709 { 2710 } 2711 #endif 2712 2713 static bool 2714 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2715 { 2716 if_t ifp; 2717 if_ctx_t ctx = rxq->ifr_ctx; 2718 if_shared_ctx_t sctx = ctx->ifc_sctx; 2719 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2720 int avail, i; 2721 qidx_t *cidxp; 2722 struct if_rxd_info ri; 2723 int err, budget_left, rx_bytes, rx_pkts; 2724 iflib_fl_t fl; 2725 int lro_enabled; 2726 bool v4_forwarding, v6_forwarding, lro_possible; 2727 2728 /* 2729 * XXX early demux data packets so that if_input processing only handles 2730 * acks in interrupt context 2731 */ 2732 struct mbuf *m, *mh, *mt, *mf; 2733 2734 lro_possible = v4_forwarding = v6_forwarding = false; 2735 ifp = ctx->ifc_ifp; 2736 mh = mt = NULL; 2737 MPASS(budget > 0); 2738 rx_pkts = rx_bytes = 0; 2739 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2740 cidxp = &rxq->ifr_cq_cidx; 2741 else 2742 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2743 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2744 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2745 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2746 DBG_COUNTER_INC(rx_unavail); 2747 return (false); 2748 } 2749 2750 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2751 if (__predict_false(!CTX_ACTIVE(ctx))) { 2752 DBG_COUNTER_INC(rx_ctx_inactive); 2753 break; 2754 } 2755 /* 2756 * Reset client set fields to their default values 2757 */ 2758 rxd_info_zero(&ri); 2759 ri.iri_qsidx = rxq->ifr_id; 2760 ri.iri_cidx = *cidxp; 2761 ri.iri_ifp = ifp; 2762 ri.iri_frags = rxq->ifr_frags; 2763 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2764 2765 if (err) 2766 goto err; 2767 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2768 *cidxp = ri.iri_cidx; 2769 /* Update our consumer index */ 2770 /* XXX NB: shurd - check if this is still safe */ 2771 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2772 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2773 /* was this only a completion queue message? */ 2774 if (__predict_false(ri.iri_nfrags == 0)) 2775 continue; 2776 } 2777 MPASS(ri.iri_nfrags != 0); 2778 MPASS(ri.iri_len != 0); 2779 2780 /* will advance the cidx on the corresponding free lists */ 2781 m = iflib_rxd_pkt_get(rxq, &ri); 2782 avail--; 2783 budget_left--; 2784 if (avail == 0 && budget_left) 2785 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2786 2787 if (__predict_false(m == NULL)) { 2788 DBG_COUNTER_INC(rx_mbuf_null); 2789 continue; 2790 } 2791 /* imm_pkt: -- cxgb */ 2792 if (mh == NULL) 2793 mh = mt = m; 2794 else { 2795 mt->m_nextpkt = m; 2796 mt = m; 2797 } 2798 } 2799 /* make sure that we can refill faster than drain */ 2800 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2801 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2802 2803 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2804 if (lro_enabled) 2805 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2806 mt = mf = NULL; 2807 while (mh != NULL) { 2808 m = mh; 2809 mh = mh->m_nextpkt; 2810 m->m_nextpkt = NULL; 2811 #ifndef __NO_STRICT_ALIGNMENT 2812 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2813 continue; 2814 #endif 2815 rx_bytes += m->m_pkthdr.len; 2816 rx_pkts++; 2817 #if defined(INET6) || defined(INET) 2818 if (lro_enabled) { 2819 if (!lro_possible) { 2820 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2821 if (lro_possible && mf != NULL) { 2822 ifp->if_input(ifp, mf); 2823 DBG_COUNTER_INC(rx_if_input); 2824 mt = mf = NULL; 2825 } 2826 } 2827 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2828 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2829 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2830 continue; 2831 } 2832 } 2833 #endif 2834 if (lro_possible) { 2835 ifp->if_input(ifp, m); 2836 DBG_COUNTER_INC(rx_if_input); 2837 continue; 2838 } 2839 2840 if (mf == NULL) 2841 mf = m; 2842 if (mt != NULL) 2843 mt->m_nextpkt = m; 2844 mt = m; 2845 } 2846 if (mf != NULL) { 2847 ifp->if_input(ifp, mf); 2848 DBG_COUNTER_INC(rx_if_input); 2849 } 2850 2851 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2852 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2853 2854 /* 2855 * Flush any outstanding LRO work 2856 */ 2857 #if defined(INET6) || defined(INET) 2858 tcp_lro_flush_all(&rxq->ifr_lc); 2859 #endif 2860 if (avail) 2861 return true; 2862 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2863 err: 2864 STATE_LOCK(ctx); 2865 ctx->ifc_flags |= IFC_DO_RESET; 2866 iflib_admin_intr_deferred(ctx); 2867 STATE_UNLOCK(ctx); 2868 return (false); 2869 } 2870 2871 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2872 static inline qidx_t 2873 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2874 { 2875 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2876 qidx_t minthresh = txq->ift_size / 8; 2877 if (in_use > 4*minthresh) 2878 return (notify_count); 2879 if (in_use > 2*minthresh) 2880 return (notify_count >> 1); 2881 if (in_use > minthresh) 2882 return (notify_count >> 3); 2883 return (0); 2884 } 2885 2886 static inline qidx_t 2887 txq_max_rs_deferred(iflib_txq_t txq) 2888 { 2889 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2890 qidx_t minthresh = txq->ift_size / 8; 2891 if (txq->ift_in_use > 4*minthresh) 2892 return (notify_count); 2893 if (txq->ift_in_use > 2*minthresh) 2894 return (notify_count >> 1); 2895 if (txq->ift_in_use > minthresh) 2896 return (notify_count >> 2); 2897 return (2); 2898 } 2899 2900 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2901 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2902 2903 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2904 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2905 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2906 2907 /* forward compatibility for cxgb */ 2908 #define FIRST_QSET(ctx) 0 2909 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2910 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2911 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2912 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2913 2914 /* XXX we should be setting this to something other than zero */ 2915 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2916 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2917 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2918 2919 static inline bool 2920 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2921 { 2922 qidx_t dbval, max; 2923 bool rang; 2924 2925 rang = false; 2926 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2927 if (ring || txq->ift_db_pending >= max) { 2928 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2929 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2931 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2932 txq->ift_db_pending = txq->ift_npending = 0; 2933 rang = true; 2934 } 2935 return (rang); 2936 } 2937 2938 #ifdef PKT_DEBUG 2939 static void 2940 print_pkt(if_pkt_info_t pi) 2941 { 2942 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2943 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2944 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2945 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2946 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2947 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2948 } 2949 #endif 2950 2951 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2952 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2953 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2954 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2955 2956 static int 2957 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2958 { 2959 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2960 struct ether_vlan_header *eh; 2961 struct mbuf *m; 2962 2963 m = *mp; 2964 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2965 M_WRITABLE(m) == 0) { 2966 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2967 return (ENOMEM); 2968 } else { 2969 m_freem(*mp); 2970 DBG_COUNTER_INC(tx_frees); 2971 *mp = m; 2972 } 2973 } 2974 2975 /* 2976 * Determine where frame payload starts. 2977 * Jump over vlan headers if already present, 2978 * helpful for QinQ too. 2979 */ 2980 if (__predict_false(m->m_len < sizeof(*eh))) { 2981 txq->ift_pullups++; 2982 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2983 return (ENOMEM); 2984 } 2985 eh = mtod(m, struct ether_vlan_header *); 2986 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2987 pi->ipi_etype = ntohs(eh->evl_proto); 2988 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2989 } else { 2990 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2991 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2992 } 2993 2994 switch (pi->ipi_etype) { 2995 #ifdef INET 2996 case ETHERTYPE_IP: 2997 { 2998 struct mbuf *n; 2999 struct ip *ip = NULL; 3000 struct tcphdr *th = NULL; 3001 int minthlen; 3002 3003 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3004 if (__predict_false(m->m_len < minthlen)) { 3005 /* 3006 * if this code bloat is causing too much of a hit 3007 * move it to a separate function and mark it noinline 3008 */ 3009 if (m->m_len == pi->ipi_ehdrlen) { 3010 n = m->m_next; 3011 MPASS(n); 3012 if (n->m_len >= sizeof(*ip)) { 3013 ip = (struct ip *)n->m_data; 3014 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3015 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3016 } else { 3017 txq->ift_pullups++; 3018 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3019 return (ENOMEM); 3020 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3021 } 3022 } else { 3023 txq->ift_pullups++; 3024 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3025 return (ENOMEM); 3026 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3027 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3028 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3029 } 3030 } else { 3031 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3032 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3033 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3034 } 3035 pi->ipi_ip_hlen = ip->ip_hl << 2; 3036 pi->ipi_ipproto = ip->ip_p; 3037 pi->ipi_flags |= IPI_TX_IPV4; 3038 3039 /* TCP checksum offload may require TCP header length */ 3040 if (IS_TX_OFFLOAD4(pi)) { 3041 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3042 if (__predict_false(th == NULL)) { 3043 txq->ift_pullups++; 3044 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3045 return (ENOMEM); 3046 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3047 } 3048 pi->ipi_tcp_hflags = th->th_flags; 3049 pi->ipi_tcp_hlen = th->th_off << 2; 3050 pi->ipi_tcp_seq = th->th_seq; 3051 } 3052 if (IS_TSO4(pi)) { 3053 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3054 return (ENXIO); 3055 /* 3056 * TSO always requires hardware checksum offload. 3057 */ 3058 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3059 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3060 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3061 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3062 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3063 ip->ip_sum = 0; 3064 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3065 } 3066 } 3067 } 3068 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3069 ip->ip_sum = 0; 3070 3071 break; 3072 } 3073 #endif 3074 #ifdef INET6 3075 case ETHERTYPE_IPV6: 3076 { 3077 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3078 struct tcphdr *th; 3079 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3080 3081 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3082 txq->ift_pullups++; 3083 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3084 return (ENOMEM); 3085 } 3086 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3087 3088 /* XXX-BZ this will go badly in case of ext hdrs. */ 3089 pi->ipi_ipproto = ip6->ip6_nxt; 3090 pi->ipi_flags |= IPI_TX_IPV6; 3091 3092 /* TCP checksum offload may require TCP header length */ 3093 if (IS_TX_OFFLOAD6(pi)) { 3094 if (pi->ipi_ipproto == IPPROTO_TCP) { 3095 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3096 txq->ift_pullups++; 3097 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3098 return (ENOMEM); 3099 } 3100 pi->ipi_tcp_hflags = th->th_flags; 3101 pi->ipi_tcp_hlen = th->th_off << 2; 3102 pi->ipi_tcp_seq = th->th_seq; 3103 } 3104 if (IS_TSO6(pi)) { 3105 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3106 return (ENXIO); 3107 /* 3108 * TSO always requires hardware checksum offload. 3109 */ 3110 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3111 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3112 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3113 } 3114 } 3115 break; 3116 } 3117 #endif 3118 default: 3119 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3120 pi->ipi_ip_hlen = 0; 3121 break; 3122 } 3123 *mp = m; 3124 3125 return (0); 3126 } 3127 3128 /* 3129 * If dodgy hardware rejects the scatter gather chain we've handed it 3130 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3131 * m_defrag'd mbufs 3132 */ 3133 static __noinline struct mbuf * 3134 iflib_remove_mbuf(iflib_txq_t txq) 3135 { 3136 int ntxd, pidx; 3137 struct mbuf *m, **ifsd_m; 3138 3139 ifsd_m = txq->ift_sds.ifsd_m; 3140 ntxd = txq->ift_size; 3141 pidx = txq->ift_pidx & (ntxd - 1); 3142 ifsd_m = txq->ift_sds.ifsd_m; 3143 m = ifsd_m[pidx]; 3144 ifsd_m[pidx] = NULL; 3145 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3146 if (txq->ift_sds.ifsd_tso_map != NULL) 3147 bus_dmamap_unload(txq->ift_tso_buf_tag, 3148 txq->ift_sds.ifsd_tso_map[pidx]); 3149 #if MEMORY_LOGGING 3150 txq->ift_dequeued++; 3151 #endif 3152 return (m); 3153 } 3154 3155 static inline caddr_t 3156 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3157 { 3158 qidx_t size; 3159 int ntxd; 3160 caddr_t start, end, cur, next; 3161 3162 ntxd = txq->ift_size; 3163 size = txq->ift_txd_size[qid]; 3164 start = txq->ift_ifdi[qid].idi_vaddr; 3165 3166 if (__predict_false(size == 0)) 3167 return (start); 3168 cur = start + size*cidx; 3169 end = start + size*ntxd; 3170 next = CACHE_PTR_NEXT(cur); 3171 return (next < end ? next : start); 3172 } 3173 3174 /* 3175 * Pad an mbuf to ensure a minimum ethernet frame size. 3176 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3177 */ 3178 static __noinline int 3179 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3180 { 3181 /* 3182 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3183 * and ARP message is the smallest common payload I can think of 3184 */ 3185 static char pad[18]; /* just zeros */ 3186 int n; 3187 struct mbuf *new_head; 3188 3189 if (!M_WRITABLE(*m_head)) { 3190 new_head = m_dup(*m_head, M_NOWAIT); 3191 if (new_head == NULL) { 3192 m_freem(*m_head); 3193 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3194 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3195 DBG_COUNTER_INC(tx_frees); 3196 return ENOMEM; 3197 } 3198 m_freem(*m_head); 3199 *m_head = new_head; 3200 } 3201 3202 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3203 n > 0; n -= sizeof(pad)) 3204 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3205 break; 3206 3207 if (n > 0) { 3208 m_freem(*m_head); 3209 device_printf(dev, "cannot pad short frame\n"); 3210 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3211 DBG_COUNTER_INC(tx_frees); 3212 return (ENOBUFS); 3213 } 3214 3215 return 0; 3216 } 3217 3218 static int 3219 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3220 { 3221 if_ctx_t ctx; 3222 if_shared_ctx_t sctx; 3223 if_softc_ctx_t scctx; 3224 bus_dma_tag_t buf_tag; 3225 bus_dma_segment_t *segs; 3226 struct mbuf *m_head, **ifsd_m; 3227 void *next_txd; 3228 bus_dmamap_t map; 3229 struct if_pkt_info pi; 3230 int remap = 0; 3231 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3232 3233 ctx = txq->ift_ctx; 3234 sctx = ctx->ifc_sctx; 3235 scctx = &ctx->ifc_softc_ctx; 3236 segs = txq->ift_segs; 3237 ntxd = txq->ift_size; 3238 m_head = *m_headp; 3239 map = NULL; 3240 3241 /* 3242 * If we're doing TSO the next descriptor to clean may be quite far ahead 3243 */ 3244 cidx = txq->ift_cidx; 3245 pidx = txq->ift_pidx; 3246 if (ctx->ifc_flags & IFC_PREFETCH) { 3247 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3248 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3249 next_txd = calc_next_txd(txq, cidx, 0); 3250 prefetch(next_txd); 3251 } 3252 3253 /* prefetch the next cache line of mbuf pointers and flags */ 3254 prefetch(&txq->ift_sds.ifsd_m[next]); 3255 prefetch(&txq->ift_sds.ifsd_map[next]); 3256 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3257 } 3258 map = txq->ift_sds.ifsd_map[pidx]; 3259 ifsd_m = txq->ift_sds.ifsd_m; 3260 3261 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3262 buf_tag = txq->ift_tso_buf_tag; 3263 max_segs = scctx->isc_tx_tso_segments_max; 3264 map = txq->ift_sds.ifsd_tso_map[pidx]; 3265 MPASS(buf_tag != NULL); 3266 MPASS(max_segs > 0); 3267 } else { 3268 buf_tag = txq->ift_buf_tag; 3269 max_segs = scctx->isc_tx_nsegments; 3270 map = txq->ift_sds.ifsd_map[pidx]; 3271 } 3272 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3273 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3274 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3275 if (err) { 3276 DBG_COUNTER_INC(encap_txd_encap_fail); 3277 return err; 3278 } 3279 } 3280 m_head = *m_headp; 3281 3282 pkt_info_zero(&pi); 3283 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3284 pi.ipi_pidx = pidx; 3285 pi.ipi_qsidx = txq->ift_id; 3286 pi.ipi_len = m_head->m_pkthdr.len; 3287 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3288 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3289 3290 /* deliberate bitwise OR to make one condition */ 3291 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3292 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3293 DBG_COUNTER_INC(encap_txd_encap_fail); 3294 return (err); 3295 } 3296 m_head = *m_headp; 3297 } 3298 3299 retry: 3300 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3301 BUS_DMA_NOWAIT); 3302 defrag: 3303 if (__predict_false(err)) { 3304 switch (err) { 3305 case EFBIG: 3306 /* try collapse once and defrag once */ 3307 if (remap == 0) { 3308 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3309 /* try defrag if collapsing fails */ 3310 if (m_head == NULL) 3311 remap++; 3312 } 3313 if (remap == 1) { 3314 txq->ift_mbuf_defrag++; 3315 m_head = m_defrag(*m_headp, M_NOWAIT); 3316 } 3317 /* 3318 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3319 * failed to map an mbuf that was run through m_defrag 3320 */ 3321 MPASS(remap <= 1); 3322 if (__predict_false(m_head == NULL || remap > 1)) 3323 goto defrag_failed; 3324 remap++; 3325 *m_headp = m_head; 3326 goto retry; 3327 break; 3328 case ENOMEM: 3329 txq->ift_no_tx_dma_setup++; 3330 break; 3331 default: 3332 txq->ift_no_tx_dma_setup++; 3333 m_freem(*m_headp); 3334 DBG_COUNTER_INC(tx_frees); 3335 *m_headp = NULL; 3336 break; 3337 } 3338 txq->ift_map_failed++; 3339 DBG_COUNTER_INC(encap_load_mbuf_fail); 3340 DBG_COUNTER_INC(encap_txd_encap_fail); 3341 return (err); 3342 } 3343 ifsd_m[pidx] = m_head; 3344 /* 3345 * XXX assumes a 1 to 1 relationship between segments and 3346 * descriptors - this does not hold true on all drivers, e.g. 3347 * cxgb 3348 */ 3349 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3350 txq->ift_no_desc_avail++; 3351 bus_dmamap_unload(buf_tag, map); 3352 DBG_COUNTER_INC(encap_txq_avail_fail); 3353 DBG_COUNTER_INC(encap_txd_encap_fail); 3354 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3355 GROUPTASK_ENQUEUE(&txq->ift_task); 3356 return (ENOBUFS); 3357 } 3358 /* 3359 * On Intel cards we can greatly reduce the number of TX interrupts 3360 * we see by only setting report status on every Nth descriptor. 3361 * However, this also means that the driver will need to keep track 3362 * of the descriptors that RS was set on to check them for the DD bit. 3363 */ 3364 txq->ift_rs_pending += nsegs + 1; 3365 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3366 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3367 pi.ipi_flags |= IPI_TX_INTR; 3368 txq->ift_rs_pending = 0; 3369 } 3370 3371 pi.ipi_segs = segs; 3372 pi.ipi_nsegs = nsegs; 3373 3374 MPASS(pidx >= 0 && pidx < txq->ift_size); 3375 #ifdef PKT_DEBUG 3376 print_pkt(&pi); 3377 #endif 3378 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3379 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3380 DBG_COUNTER_INC(tx_encap); 3381 MPASS(pi.ipi_new_pidx < txq->ift_size); 3382 3383 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3384 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3385 ndesc += txq->ift_size; 3386 txq->ift_gen = 1; 3387 } 3388 /* 3389 * drivers can need as many as 3390 * two sentinels 3391 */ 3392 MPASS(ndesc <= pi.ipi_nsegs + 2); 3393 MPASS(pi.ipi_new_pidx != pidx); 3394 MPASS(ndesc > 0); 3395 txq->ift_in_use += ndesc; 3396 3397 /* 3398 * We update the last software descriptor again here because there may 3399 * be a sentinel and/or there may be more mbufs than segments 3400 */ 3401 txq->ift_pidx = pi.ipi_new_pidx; 3402 txq->ift_npending += pi.ipi_ndescs; 3403 } else { 3404 *m_headp = m_head = iflib_remove_mbuf(txq); 3405 if (err == EFBIG) { 3406 txq->ift_txd_encap_efbig++; 3407 if (remap < 2) { 3408 remap = 1; 3409 goto defrag; 3410 } 3411 } 3412 goto defrag_failed; 3413 } 3414 /* 3415 * err can't possibly be non-zero here, so we don't neet to test it 3416 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3417 */ 3418 return (err); 3419 3420 defrag_failed: 3421 txq->ift_mbuf_defrag_failed++; 3422 txq->ift_map_failed++; 3423 m_freem(*m_headp); 3424 DBG_COUNTER_INC(tx_frees); 3425 *m_headp = NULL; 3426 DBG_COUNTER_INC(encap_txd_encap_fail); 3427 return (ENOMEM); 3428 } 3429 3430 static void 3431 iflib_tx_desc_free(iflib_txq_t txq, int n) 3432 { 3433 uint32_t qsize, cidx, mask, gen; 3434 struct mbuf *m, **ifsd_m; 3435 bool do_prefetch; 3436 3437 cidx = txq->ift_cidx; 3438 gen = txq->ift_gen; 3439 qsize = txq->ift_size; 3440 mask = qsize-1; 3441 ifsd_m = txq->ift_sds.ifsd_m; 3442 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3443 3444 while (n-- > 0) { 3445 if (do_prefetch) { 3446 prefetch(ifsd_m[(cidx + 3) & mask]); 3447 prefetch(ifsd_m[(cidx + 4) & mask]); 3448 } 3449 if ((m = ifsd_m[cidx]) != NULL) { 3450 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3451 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3452 bus_dmamap_sync(txq->ift_tso_buf_tag, 3453 txq->ift_sds.ifsd_tso_map[cidx], 3454 BUS_DMASYNC_POSTWRITE); 3455 bus_dmamap_unload(txq->ift_tso_buf_tag, 3456 txq->ift_sds.ifsd_tso_map[cidx]); 3457 } else { 3458 bus_dmamap_sync(txq->ift_buf_tag, 3459 txq->ift_sds.ifsd_map[cidx], 3460 BUS_DMASYNC_POSTWRITE); 3461 bus_dmamap_unload(txq->ift_buf_tag, 3462 txq->ift_sds.ifsd_map[cidx]); 3463 } 3464 /* XXX we don't support any drivers that batch packets yet */ 3465 MPASS(m->m_nextpkt == NULL); 3466 m_freem(m); 3467 ifsd_m[cidx] = NULL; 3468 #if MEMORY_LOGGING 3469 txq->ift_dequeued++; 3470 #endif 3471 DBG_COUNTER_INC(tx_frees); 3472 } 3473 if (__predict_false(++cidx == qsize)) { 3474 cidx = 0; 3475 gen = 0; 3476 } 3477 } 3478 txq->ift_cidx = cidx; 3479 txq->ift_gen = gen; 3480 } 3481 3482 static __inline int 3483 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3484 { 3485 int reclaim; 3486 if_ctx_t ctx = txq->ift_ctx; 3487 3488 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3489 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3490 3491 /* 3492 * Need a rate-limiting check so that this isn't called every time 3493 */ 3494 iflib_tx_credits_update(ctx, txq); 3495 reclaim = DESC_RECLAIMABLE(txq); 3496 3497 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3498 #ifdef INVARIANTS 3499 if (iflib_verbose_debug) { 3500 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3501 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3502 reclaim, thresh); 3503 3504 } 3505 #endif 3506 return (0); 3507 } 3508 iflib_tx_desc_free(txq, reclaim); 3509 txq->ift_cleaned += reclaim; 3510 txq->ift_in_use -= reclaim; 3511 3512 return (reclaim); 3513 } 3514 3515 static struct mbuf ** 3516 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3517 { 3518 int next, size; 3519 struct mbuf **items; 3520 3521 size = r->size; 3522 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3523 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3524 3525 prefetch(items[(cidx + offset) & (size-1)]); 3526 if (remaining > 1) { 3527 prefetch2cachelines(&items[next]); 3528 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3529 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3530 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3531 } 3532 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3533 } 3534 3535 static void 3536 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3537 { 3538 3539 ifmp_ring_check_drainage(txq->ift_br, budget); 3540 } 3541 3542 static uint32_t 3543 iflib_txq_can_drain(struct ifmp_ring *r) 3544 { 3545 iflib_txq_t txq = r->cookie; 3546 if_ctx_t ctx = txq->ift_ctx; 3547 3548 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3549 return (1); 3550 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3551 BUS_DMASYNC_POSTREAD); 3552 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3553 false)); 3554 } 3555 3556 static uint32_t 3557 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3558 { 3559 iflib_txq_t txq = r->cookie; 3560 if_ctx_t ctx = txq->ift_ctx; 3561 if_t ifp = ctx->ifc_ifp; 3562 struct mbuf **mp, *m; 3563 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3564 int reclaimed, err, in_use_prev, desc_used; 3565 bool do_prefetch, ring, rang; 3566 3567 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3568 !LINK_ACTIVE(ctx))) { 3569 DBG_COUNTER_INC(txq_drain_notready); 3570 return (0); 3571 } 3572 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3573 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3574 avail = IDXDIFF(pidx, cidx, r->size); 3575 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3576 DBG_COUNTER_INC(txq_drain_flushing); 3577 for (i = 0; i < avail; i++) { 3578 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3579 m_free(r->items[(cidx + i) & (r->size-1)]); 3580 r->items[(cidx + i) & (r->size-1)] = NULL; 3581 } 3582 return (avail); 3583 } 3584 3585 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3586 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3587 CALLOUT_LOCK(txq); 3588 callout_stop(&txq->ift_timer); 3589 CALLOUT_UNLOCK(txq); 3590 DBG_COUNTER_INC(txq_drain_oactive); 3591 return (0); 3592 } 3593 if (reclaimed) 3594 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3595 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3596 count = MIN(avail, TX_BATCH_SIZE); 3597 #ifdef INVARIANTS 3598 if (iflib_verbose_debug) 3599 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3600 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3601 #endif 3602 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3603 avail = TXQ_AVAIL(txq); 3604 err = 0; 3605 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3606 int rem = do_prefetch ? count - i : 0; 3607 3608 mp = _ring_peek_one(r, cidx, i, rem); 3609 MPASS(mp != NULL && *mp != NULL); 3610 if (__predict_false(*mp == (struct mbuf *)txq)) { 3611 consumed++; 3612 reclaimed++; 3613 continue; 3614 } 3615 in_use_prev = txq->ift_in_use; 3616 err = iflib_encap(txq, mp); 3617 if (__predict_false(err)) { 3618 /* no room - bail out */ 3619 if (err == ENOBUFS) 3620 break; 3621 consumed++; 3622 /* we can't send this packet - skip it */ 3623 continue; 3624 } 3625 consumed++; 3626 pkt_sent++; 3627 m = *mp; 3628 DBG_COUNTER_INC(tx_sent); 3629 bytes_sent += m->m_pkthdr.len; 3630 mcast_sent += !!(m->m_flags & M_MCAST); 3631 avail = TXQ_AVAIL(txq); 3632 3633 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3634 desc_used += (txq->ift_in_use - in_use_prev); 3635 ETHER_BPF_MTAP(ifp, m); 3636 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3637 break; 3638 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3639 } 3640 3641 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3642 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3643 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3644 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3645 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3646 if (mcast_sent) 3647 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3648 #ifdef INVARIANTS 3649 if (iflib_verbose_debug) 3650 printf("consumed=%d\n", consumed); 3651 #endif 3652 return (consumed); 3653 } 3654 3655 static uint32_t 3656 iflib_txq_drain_always(struct ifmp_ring *r) 3657 { 3658 return (1); 3659 } 3660 3661 static uint32_t 3662 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3663 { 3664 int i, avail; 3665 struct mbuf **mp; 3666 iflib_txq_t txq; 3667 3668 txq = r->cookie; 3669 3670 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3671 CALLOUT_LOCK(txq); 3672 callout_stop(&txq->ift_timer); 3673 CALLOUT_UNLOCK(txq); 3674 3675 avail = IDXDIFF(pidx, cidx, r->size); 3676 for (i = 0; i < avail; i++) { 3677 mp = _ring_peek_one(r, cidx, i, avail - i); 3678 if (__predict_false(*mp == (struct mbuf *)txq)) 3679 continue; 3680 m_freem(*mp); 3681 DBG_COUNTER_INC(tx_frees); 3682 } 3683 MPASS(ifmp_ring_is_stalled(r) == 0); 3684 return (avail); 3685 } 3686 3687 static void 3688 iflib_ifmp_purge(iflib_txq_t txq) 3689 { 3690 struct ifmp_ring *r; 3691 3692 r = txq->ift_br; 3693 r->drain = iflib_txq_drain_free; 3694 r->can_drain = iflib_txq_drain_always; 3695 3696 ifmp_ring_check_drainage(r, r->size); 3697 3698 r->drain = iflib_txq_drain; 3699 r->can_drain = iflib_txq_can_drain; 3700 } 3701 3702 static void 3703 _task_fn_tx(void *context) 3704 { 3705 iflib_txq_t txq = context; 3706 if_ctx_t ctx = txq->ift_ctx; 3707 #if defined(ALTQ) || defined(DEV_NETMAP) 3708 if_t ifp = ctx->ifc_ifp; 3709 #endif 3710 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3711 3712 #ifdef IFLIB_DIAGNOSTICS 3713 txq->ift_cpu_exec_count[curcpu]++; 3714 #endif 3715 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3716 return; 3717 #ifdef DEV_NETMAP 3718 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3719 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3720 BUS_DMASYNC_POSTREAD); 3721 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3722 netmap_tx_irq(ifp, txq->ift_id); 3723 if (ctx->ifc_flags & IFC_LEGACY) 3724 IFDI_INTR_ENABLE(ctx); 3725 else 3726 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3727 return; 3728 } 3729 #endif 3730 #ifdef ALTQ 3731 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3732 iflib_altq_if_start(ifp); 3733 #endif 3734 if (txq->ift_db_pending) 3735 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3736 else if (!abdicate) 3737 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3738 /* 3739 * When abdicating, we always need to check drainage, not just when we don't enqueue 3740 */ 3741 if (abdicate) 3742 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3743 if (ctx->ifc_flags & IFC_LEGACY) 3744 IFDI_INTR_ENABLE(ctx); 3745 else 3746 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3747 } 3748 3749 static void 3750 _task_fn_rx(void *context) 3751 { 3752 iflib_rxq_t rxq = context; 3753 if_ctx_t ctx = rxq->ifr_ctx; 3754 bool more; 3755 uint16_t budget; 3756 3757 #ifdef IFLIB_DIAGNOSTICS 3758 rxq->ifr_cpu_exec_count[curcpu]++; 3759 #endif 3760 DBG_COUNTER_INC(task_fn_rxs); 3761 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3762 return; 3763 more = true; 3764 #ifdef DEV_NETMAP 3765 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3766 u_int work = 0; 3767 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3768 more = false; 3769 } 3770 } 3771 #endif 3772 budget = ctx->ifc_sysctl_rx_budget; 3773 if (budget == 0) 3774 budget = 16; /* XXX */ 3775 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3776 if (ctx->ifc_flags & IFC_LEGACY) 3777 IFDI_INTR_ENABLE(ctx); 3778 else 3779 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3780 DBG_COUNTER_INC(rx_intr_enables); 3781 } 3782 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3783 return; 3784 if (more) 3785 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3786 } 3787 3788 static void 3789 _task_fn_admin(void *context) 3790 { 3791 if_ctx_t ctx = context; 3792 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3793 iflib_txq_t txq; 3794 int i; 3795 bool oactive, running, do_reset, do_watchdog, in_detach; 3796 uint32_t reset_on = hz / 2; 3797 3798 STATE_LOCK(ctx); 3799 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3800 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3801 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3802 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3803 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3804 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3805 STATE_UNLOCK(ctx); 3806 3807 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3808 return; 3809 if (in_detach) 3810 return; 3811 3812 CTX_LOCK(ctx); 3813 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3814 CALLOUT_LOCK(txq); 3815 callout_stop(&txq->ift_timer); 3816 CALLOUT_UNLOCK(txq); 3817 } 3818 if (do_watchdog) { 3819 ctx->ifc_watchdog_events++; 3820 IFDI_WATCHDOG_RESET(ctx); 3821 } 3822 IFDI_UPDATE_ADMIN_STATUS(ctx); 3823 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3824 #ifdef DEV_NETMAP 3825 reset_on = hz / 2; 3826 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3827 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3828 #endif 3829 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3830 } 3831 IFDI_LINK_INTR_ENABLE(ctx); 3832 if (do_reset) 3833 iflib_if_init_locked(ctx); 3834 CTX_UNLOCK(ctx); 3835 3836 if (LINK_ACTIVE(ctx) == 0) 3837 return; 3838 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3839 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3840 } 3841 3842 3843 static void 3844 _task_fn_iov(void *context) 3845 { 3846 if_ctx_t ctx = context; 3847 3848 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3849 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3850 return; 3851 3852 CTX_LOCK(ctx); 3853 IFDI_VFLR_HANDLE(ctx); 3854 CTX_UNLOCK(ctx); 3855 } 3856 3857 static int 3858 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3859 { 3860 int err; 3861 if_int_delay_info_t info; 3862 if_ctx_t ctx; 3863 3864 info = (if_int_delay_info_t)arg1; 3865 ctx = info->iidi_ctx; 3866 info->iidi_req = req; 3867 info->iidi_oidp = oidp; 3868 CTX_LOCK(ctx); 3869 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3870 CTX_UNLOCK(ctx); 3871 return (err); 3872 } 3873 3874 /********************************************************************* 3875 * 3876 * IFNET FUNCTIONS 3877 * 3878 **********************************************************************/ 3879 3880 static void 3881 iflib_if_init_locked(if_ctx_t ctx) 3882 { 3883 iflib_stop(ctx); 3884 iflib_init_locked(ctx); 3885 } 3886 3887 3888 static void 3889 iflib_if_init(void *arg) 3890 { 3891 if_ctx_t ctx = arg; 3892 3893 CTX_LOCK(ctx); 3894 iflib_if_init_locked(ctx); 3895 CTX_UNLOCK(ctx); 3896 } 3897 3898 static int 3899 iflib_if_transmit(if_t ifp, struct mbuf *m) 3900 { 3901 if_ctx_t ctx = if_getsoftc(ifp); 3902 3903 iflib_txq_t txq; 3904 int err, qidx; 3905 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3906 3907 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3908 DBG_COUNTER_INC(tx_frees); 3909 m_freem(m); 3910 return (ENETDOWN); 3911 } 3912 3913 MPASS(m->m_nextpkt == NULL); 3914 /* ALTQ-enabled interfaces always use queue 0. */ 3915 qidx = 0; 3916 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3917 qidx = QIDX(ctx, m); 3918 /* 3919 * XXX calculate buf_ring based on flowid (divvy up bits?) 3920 */ 3921 txq = &ctx->ifc_txqs[qidx]; 3922 3923 #ifdef DRIVER_BACKPRESSURE 3924 if (txq->ift_closed) { 3925 while (m != NULL) { 3926 next = m->m_nextpkt; 3927 m->m_nextpkt = NULL; 3928 m_freem(m); 3929 DBG_COUNTER_INC(tx_frees); 3930 m = next; 3931 } 3932 return (ENOBUFS); 3933 } 3934 #endif 3935 #ifdef notyet 3936 qidx = count = 0; 3937 mp = marr; 3938 next = m; 3939 do { 3940 count++; 3941 next = next->m_nextpkt; 3942 } while (next != NULL); 3943 3944 if (count > nitems(marr)) 3945 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3946 /* XXX check nextpkt */ 3947 m_freem(m); 3948 /* XXX simplify for now */ 3949 DBG_COUNTER_INC(tx_frees); 3950 return (ENOBUFS); 3951 } 3952 for (next = m, i = 0; next != NULL; i++) { 3953 mp[i] = next; 3954 next = next->m_nextpkt; 3955 mp[i]->m_nextpkt = NULL; 3956 } 3957 #endif 3958 DBG_COUNTER_INC(tx_seen); 3959 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3960 3961 if (abdicate) 3962 GROUPTASK_ENQUEUE(&txq->ift_task); 3963 if (err) { 3964 if (!abdicate) 3965 GROUPTASK_ENQUEUE(&txq->ift_task); 3966 /* support forthcoming later */ 3967 #ifdef DRIVER_BACKPRESSURE 3968 txq->ift_closed = TRUE; 3969 #endif 3970 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3971 m_freem(m); 3972 DBG_COUNTER_INC(tx_frees); 3973 } 3974 3975 return (err); 3976 } 3977 3978 #ifdef ALTQ 3979 /* 3980 * The overall approach to integrating iflib with ALTQ is to continue to use 3981 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 3982 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 3983 * is redundant/unnecessary, but doing so minimizes the amount of 3984 * ALTQ-specific code required in iflib. It is assumed that the overhead of 3985 * redundantly queueing to an intermediate mp_ring is swamped by the 3986 * performance limitations inherent in using ALTQ. 3987 * 3988 * When ALTQ support is compiled in, all iflib drivers will use a transmit 3989 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 3990 * given interface. If ALTQ is enabled for an interface, then all 3991 * transmitted packets for that interface will be submitted to the ALTQ 3992 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 3993 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 3994 * update stats that the iflib machinery handles, and which is sensitve to 3995 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 3996 * will be installed as the start routine for use by ALTQ facilities that 3997 * need to trigger queue drains on a scheduled basis. 3998 * 3999 */ 4000 static void 4001 iflib_altq_if_start(if_t ifp) 4002 { 4003 struct ifaltq *ifq = &ifp->if_snd; 4004 struct mbuf *m; 4005 4006 IFQ_LOCK(ifq); 4007 IFQ_DEQUEUE_NOLOCK(ifq, m); 4008 while (m != NULL) { 4009 iflib_if_transmit(ifp, m); 4010 IFQ_DEQUEUE_NOLOCK(ifq, m); 4011 } 4012 IFQ_UNLOCK(ifq); 4013 } 4014 4015 static int 4016 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4017 { 4018 int err; 4019 4020 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4021 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4022 if (err == 0) 4023 iflib_altq_if_start(ifp); 4024 } else 4025 err = iflib_if_transmit(ifp, m); 4026 4027 return (err); 4028 } 4029 #endif /* ALTQ */ 4030 4031 static void 4032 iflib_if_qflush(if_t ifp) 4033 { 4034 if_ctx_t ctx = if_getsoftc(ifp); 4035 iflib_txq_t txq = ctx->ifc_txqs; 4036 int i; 4037 4038 STATE_LOCK(ctx); 4039 ctx->ifc_flags |= IFC_QFLUSH; 4040 STATE_UNLOCK(ctx); 4041 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4042 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4043 iflib_txq_check_drain(txq, 0); 4044 STATE_LOCK(ctx); 4045 ctx->ifc_flags &= ~IFC_QFLUSH; 4046 STATE_UNLOCK(ctx); 4047 4048 /* 4049 * When ALTQ is enabled, this will also take care of purging the 4050 * ALTQ queue(s). 4051 */ 4052 if_qflush(ifp); 4053 } 4054 4055 4056 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4057 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4058 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4059 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4060 4061 static int 4062 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4063 { 4064 if_ctx_t ctx = if_getsoftc(ifp); 4065 struct ifreq *ifr = (struct ifreq *)data; 4066 #if defined(INET) || defined(INET6) 4067 struct ifaddr *ifa = (struct ifaddr *)data; 4068 #endif 4069 bool avoid_reset = false; 4070 int err = 0, reinit = 0, bits; 4071 4072 switch (command) { 4073 case SIOCSIFADDR: 4074 #ifdef INET 4075 if (ifa->ifa_addr->sa_family == AF_INET) 4076 avoid_reset = true; 4077 #endif 4078 #ifdef INET6 4079 if (ifa->ifa_addr->sa_family == AF_INET6) 4080 avoid_reset = true; 4081 #endif 4082 /* 4083 ** Calling init results in link renegotiation, 4084 ** so we avoid doing it when possible. 4085 */ 4086 if (avoid_reset) { 4087 if_setflagbits(ifp, IFF_UP,0); 4088 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4089 reinit = 1; 4090 #ifdef INET 4091 if (!(if_getflags(ifp) & IFF_NOARP)) 4092 arp_ifinit(ifp, ifa); 4093 #endif 4094 } else 4095 err = ether_ioctl(ifp, command, data); 4096 break; 4097 case SIOCSIFMTU: 4098 CTX_LOCK(ctx); 4099 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4100 CTX_UNLOCK(ctx); 4101 break; 4102 } 4103 bits = if_getdrvflags(ifp); 4104 /* stop the driver and free any clusters before proceeding */ 4105 iflib_stop(ctx); 4106 4107 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4108 STATE_LOCK(ctx); 4109 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4110 ctx->ifc_flags |= IFC_MULTISEG; 4111 else 4112 ctx->ifc_flags &= ~IFC_MULTISEG; 4113 STATE_UNLOCK(ctx); 4114 err = if_setmtu(ifp, ifr->ifr_mtu); 4115 } 4116 iflib_init_locked(ctx); 4117 STATE_LOCK(ctx); 4118 if_setdrvflags(ifp, bits); 4119 STATE_UNLOCK(ctx); 4120 CTX_UNLOCK(ctx); 4121 break; 4122 case SIOCSIFFLAGS: 4123 CTX_LOCK(ctx); 4124 if (if_getflags(ifp) & IFF_UP) { 4125 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4126 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4127 (IFF_PROMISC | IFF_ALLMULTI)) { 4128 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4129 } 4130 } else 4131 reinit = 1; 4132 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4133 iflib_stop(ctx); 4134 } 4135 ctx->ifc_if_flags = if_getflags(ifp); 4136 CTX_UNLOCK(ctx); 4137 break; 4138 case SIOCADDMULTI: 4139 case SIOCDELMULTI: 4140 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4141 CTX_LOCK(ctx); 4142 IFDI_INTR_DISABLE(ctx); 4143 IFDI_MULTI_SET(ctx); 4144 IFDI_INTR_ENABLE(ctx); 4145 CTX_UNLOCK(ctx); 4146 } 4147 break; 4148 case SIOCSIFMEDIA: 4149 CTX_LOCK(ctx); 4150 IFDI_MEDIA_SET(ctx); 4151 CTX_UNLOCK(ctx); 4152 /* FALLTHROUGH */ 4153 case SIOCGIFMEDIA: 4154 case SIOCGIFXMEDIA: 4155 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4156 break; 4157 case SIOCGI2C: 4158 { 4159 struct ifi2creq i2c; 4160 4161 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4162 if (err != 0) 4163 break; 4164 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4165 err = EINVAL; 4166 break; 4167 } 4168 if (i2c.len > sizeof(i2c.data)) { 4169 err = EINVAL; 4170 break; 4171 } 4172 4173 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4174 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4175 sizeof(i2c)); 4176 break; 4177 } 4178 case SIOCSIFCAP: 4179 { 4180 int mask, setmask, oldmask; 4181 4182 oldmask = if_getcapenable(ifp); 4183 mask = ifr->ifr_reqcap ^ oldmask; 4184 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4185 setmask = 0; 4186 #ifdef TCP_OFFLOAD 4187 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4188 #endif 4189 setmask |= (mask & IFCAP_FLAGS); 4190 setmask |= (mask & IFCAP_WOL); 4191 4192 /* 4193 * If any RX csum has changed, change all the ones that 4194 * are supported by the driver. 4195 */ 4196 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4197 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4198 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4199 } 4200 4201 /* 4202 * want to ensure that traffic has stopped before we change any of the flags 4203 */ 4204 if (setmask) { 4205 CTX_LOCK(ctx); 4206 bits = if_getdrvflags(ifp); 4207 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4208 iflib_stop(ctx); 4209 STATE_LOCK(ctx); 4210 if_togglecapenable(ifp, setmask); 4211 STATE_UNLOCK(ctx); 4212 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4213 iflib_init_locked(ctx); 4214 STATE_LOCK(ctx); 4215 if_setdrvflags(ifp, bits); 4216 STATE_UNLOCK(ctx); 4217 CTX_UNLOCK(ctx); 4218 } 4219 if_vlancap(ifp); 4220 break; 4221 } 4222 case SIOCGPRIVATE_0: 4223 case SIOCSDRVSPEC: 4224 case SIOCGDRVSPEC: 4225 CTX_LOCK(ctx); 4226 err = IFDI_PRIV_IOCTL(ctx, command, data); 4227 CTX_UNLOCK(ctx); 4228 break; 4229 default: 4230 err = ether_ioctl(ifp, command, data); 4231 break; 4232 } 4233 if (reinit) 4234 iflib_if_init(ctx); 4235 return (err); 4236 } 4237 4238 static uint64_t 4239 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4240 { 4241 if_ctx_t ctx = if_getsoftc(ifp); 4242 4243 return (IFDI_GET_COUNTER(ctx, cnt)); 4244 } 4245 4246 /********************************************************************* 4247 * 4248 * OTHER FUNCTIONS EXPORTED TO THE STACK 4249 * 4250 **********************************************************************/ 4251 4252 static void 4253 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4254 { 4255 if_ctx_t ctx = if_getsoftc(ifp); 4256 4257 if ((void *)ctx != arg) 4258 return; 4259 4260 if ((vtag == 0) || (vtag > 4095)) 4261 return; 4262 4263 CTX_LOCK(ctx); 4264 IFDI_VLAN_REGISTER(ctx, vtag); 4265 /* Re-init to load the changes */ 4266 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4267 iflib_if_init_locked(ctx); 4268 CTX_UNLOCK(ctx); 4269 } 4270 4271 static void 4272 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4273 { 4274 if_ctx_t ctx = if_getsoftc(ifp); 4275 4276 if ((void *)ctx != arg) 4277 return; 4278 4279 if ((vtag == 0) || (vtag > 4095)) 4280 return; 4281 4282 CTX_LOCK(ctx); 4283 IFDI_VLAN_UNREGISTER(ctx, vtag); 4284 /* Re-init to load the changes */ 4285 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4286 iflib_if_init_locked(ctx); 4287 CTX_UNLOCK(ctx); 4288 } 4289 4290 static void 4291 iflib_led_func(void *arg, int onoff) 4292 { 4293 if_ctx_t ctx = arg; 4294 4295 CTX_LOCK(ctx); 4296 IFDI_LED_FUNC(ctx, onoff); 4297 CTX_UNLOCK(ctx); 4298 } 4299 4300 /********************************************************************* 4301 * 4302 * BUS FUNCTION DEFINITIONS 4303 * 4304 **********************************************************************/ 4305 4306 int 4307 iflib_device_probe(device_t dev) 4308 { 4309 pci_vendor_info_t *ent; 4310 4311 uint16_t pci_vendor_id, pci_device_id; 4312 uint16_t pci_subvendor_id, pci_subdevice_id; 4313 uint16_t pci_rev_id; 4314 if_shared_ctx_t sctx; 4315 4316 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4317 return (ENOTSUP); 4318 4319 pci_vendor_id = pci_get_vendor(dev); 4320 pci_device_id = pci_get_device(dev); 4321 pci_subvendor_id = pci_get_subvendor(dev); 4322 pci_subdevice_id = pci_get_subdevice(dev); 4323 pci_rev_id = pci_get_revid(dev); 4324 if (sctx->isc_parse_devinfo != NULL) 4325 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4326 4327 ent = sctx->isc_vendor_info; 4328 while (ent->pvi_vendor_id != 0) { 4329 if (pci_vendor_id != ent->pvi_vendor_id) { 4330 ent++; 4331 continue; 4332 } 4333 if ((pci_device_id == ent->pvi_device_id) && 4334 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4335 (ent->pvi_subvendor_id == 0)) && 4336 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4337 (ent->pvi_subdevice_id == 0)) && 4338 ((pci_rev_id == ent->pvi_rev_id) || 4339 (ent->pvi_rev_id == 0))) { 4340 4341 device_set_desc_copy(dev, ent->pvi_name); 4342 /* this needs to be changed to zero if the bus probing code 4343 * ever stops re-probing on best match because the sctx 4344 * may have its values over written by register calls 4345 * in subsequent probes 4346 */ 4347 return (BUS_PROBE_DEFAULT); 4348 } 4349 ent++; 4350 } 4351 return (ENXIO); 4352 } 4353 4354 int 4355 iflib_device_probe_vendor(device_t dev) 4356 { 4357 int probe; 4358 4359 probe = iflib_device_probe(dev); 4360 if (probe == BUS_PROBE_DEFAULT) 4361 return (BUS_PROBE_VENDOR); 4362 else 4363 return (probe); 4364 } 4365 4366 static void 4367 iflib_reset_qvalues(if_ctx_t ctx) 4368 { 4369 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4370 if_shared_ctx_t sctx = ctx->ifc_sctx; 4371 device_t dev = ctx->ifc_dev; 4372 int i; 4373 4374 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4375 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4376 if (ctx->ifc_sysctl_ntxqs != 0) 4377 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4378 if (ctx->ifc_sysctl_nrxqs != 0) 4379 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4380 4381 for (i = 0; i < sctx->isc_ntxqs; i++) { 4382 if (ctx->ifc_sysctl_ntxds[i] != 0) 4383 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4384 else 4385 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4386 } 4387 4388 for (i = 0; i < sctx->isc_nrxqs; i++) { 4389 if (ctx->ifc_sysctl_nrxds[i] != 0) 4390 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4391 else 4392 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4393 } 4394 4395 for (i = 0; i < sctx->isc_nrxqs; i++) { 4396 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4397 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4398 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4399 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4400 } 4401 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4402 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4403 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4404 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4405 } 4406 if (!powerof2(scctx->isc_nrxd[i])) { 4407 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4408 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4409 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4410 } 4411 } 4412 4413 for (i = 0; i < sctx->isc_ntxqs; i++) { 4414 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4415 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4416 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4417 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4418 } 4419 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4420 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4421 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4422 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4423 } 4424 if (!powerof2(scctx->isc_ntxd[i])) { 4425 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4426 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4427 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4428 } 4429 } 4430 } 4431 4432 static uint16_t 4433 get_ctx_core_offset(if_ctx_t ctx) 4434 { 4435 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4436 struct cpu_offset *op; 4437 uint16_t qc; 4438 uint16_t ret = ctx->ifc_sysctl_core_offset; 4439 4440 if (ret != CORE_OFFSET_UNSPECIFIED) 4441 return (ret); 4442 4443 if (ctx->ifc_sysctl_separate_txrx) 4444 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4445 else 4446 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4447 4448 mtx_lock(&cpu_offset_mtx); 4449 SLIST_FOREACH(op, &cpu_offsets, entries) { 4450 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4451 ret = op->offset; 4452 op->offset += qc; 4453 MPASS(op->refcount < UINT_MAX); 4454 op->refcount++; 4455 break; 4456 } 4457 } 4458 if (ret == CORE_OFFSET_UNSPECIFIED) { 4459 ret = 0; 4460 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4461 M_NOWAIT | M_ZERO); 4462 if (op == NULL) { 4463 device_printf(ctx->ifc_dev, 4464 "allocation for cpu offset failed.\n"); 4465 } else { 4466 op->offset = qc; 4467 op->refcount = 1; 4468 CPU_COPY(&ctx->ifc_cpus, &op->set); 4469 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4470 } 4471 } 4472 mtx_unlock(&cpu_offset_mtx); 4473 4474 return (ret); 4475 } 4476 4477 static void 4478 unref_ctx_core_offset(if_ctx_t ctx) 4479 { 4480 struct cpu_offset *op, *top; 4481 4482 mtx_lock(&cpu_offset_mtx); 4483 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4484 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4485 MPASS(op->refcount > 0); 4486 op->refcount--; 4487 if (op->refcount == 0) { 4488 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4489 free(op, M_IFLIB); 4490 } 4491 break; 4492 } 4493 } 4494 mtx_unlock(&cpu_offset_mtx); 4495 } 4496 4497 int 4498 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4499 { 4500 if_ctx_t ctx; 4501 if_t ifp; 4502 if_softc_ctx_t scctx; 4503 kobjop_desc_t kobj_desc; 4504 kobj_method_t *kobj_method; 4505 int err, msix, rid; 4506 uint16_t main_rxq, main_txq; 4507 4508 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4509 4510 if (sc == NULL) { 4511 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4512 device_set_softc(dev, ctx); 4513 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4514 } 4515 4516 ctx->ifc_sctx = sctx; 4517 ctx->ifc_dev = dev; 4518 ctx->ifc_softc = sc; 4519 4520 if ((err = iflib_register(ctx)) != 0) { 4521 device_printf(dev, "iflib_register failed %d\n", err); 4522 goto fail_ctx_free; 4523 } 4524 iflib_add_device_sysctl_pre(ctx); 4525 4526 scctx = &ctx->ifc_softc_ctx; 4527 ifp = ctx->ifc_ifp; 4528 4529 iflib_reset_qvalues(ctx); 4530 CTX_LOCK(ctx); 4531 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4532 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4533 goto fail_unlock; 4534 } 4535 _iflib_pre_assert(scctx); 4536 ctx->ifc_txrx = *scctx->isc_txrx; 4537 4538 #ifdef INVARIANTS 4539 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4540 MPASS(scctx->isc_tx_csum_flags); 4541 #endif 4542 4543 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4544 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4545 4546 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4547 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4548 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4549 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4550 4551 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4552 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4553 4554 /* XXX change for per-queue sizes */ 4555 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4556 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4557 4558 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4559 MAX_SINGLE_PACKET_FRACTION) 4560 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4561 MAX_SINGLE_PACKET_FRACTION); 4562 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4563 MAX_SINGLE_PACKET_FRACTION) 4564 scctx->isc_tx_tso_segments_max = max(1, 4565 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4566 4567 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4568 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4569 /* 4570 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4571 * but some MACs do. 4572 */ 4573 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4574 IP_MAXPACKET)); 4575 /* 4576 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4577 * into account. In the worst case, each of these calls will 4578 * add another mbuf and, thus, the requirement for another DMA 4579 * segment. So for best performance, it doesn't make sense to 4580 * advertize a maximum of TSO segments that typically will 4581 * require defragmentation in iflib_encap(). 4582 */ 4583 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4584 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4585 } 4586 if (scctx->isc_rss_table_size == 0) 4587 scctx->isc_rss_table_size = 64; 4588 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4589 4590 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4591 /* XXX format name */ 4592 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4593 -1, "admin"); 4594 4595 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4596 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4597 device_printf(dev, "Unable to fetch CPU list\n"); 4598 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4599 } 4600 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4601 4602 /* 4603 ** Now set up MSI or MSI-X, should return us the number of supported 4604 ** vectors (will be 1 for a legacy interrupt and MSI). 4605 */ 4606 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4607 msix = scctx->isc_vectors; 4608 } else if (scctx->isc_msix_bar != 0) 4609 /* 4610 * The simple fact that isc_msix_bar is not 0 does not mean we 4611 * we have a good value there that is known to work. 4612 */ 4613 msix = iflib_msix_init(ctx); 4614 else { 4615 scctx->isc_vectors = 1; 4616 scctx->isc_ntxqsets = 1; 4617 scctx->isc_nrxqsets = 1; 4618 scctx->isc_intr = IFLIB_INTR_LEGACY; 4619 msix = 0; 4620 } 4621 /* Get memory for the station queues */ 4622 if ((err = iflib_queues_alloc(ctx))) { 4623 device_printf(dev, "Unable to allocate queue memory\n"); 4624 goto fail_intr_free; 4625 } 4626 4627 if ((err = iflib_qset_structures_setup(ctx))) 4628 goto fail_queues; 4629 4630 /* 4631 * Now that we know how many queues there are, get the core offset. 4632 */ 4633 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4634 4635 /* 4636 * Group taskqueues aren't properly set up until SMP is started, 4637 * so we disable interrupts until we can handle them post 4638 * SI_SUB_SMP. 4639 * 4640 * XXX: disabling interrupts doesn't actually work, at least for 4641 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4642 * we do null handling and depend on this not causing too large an 4643 * interrupt storm. 4644 */ 4645 IFDI_INTR_DISABLE(ctx); 4646 4647 if (msix > 1) { 4648 /* 4649 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4650 * aren't the default NULL implementation. 4651 */ 4652 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4653 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4654 kobj_desc); 4655 if (kobj_method == &kobj_desc->deflt) { 4656 device_printf(dev, 4657 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4658 err = EOPNOTSUPP; 4659 goto fail_queues; 4660 } 4661 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4662 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4663 kobj_desc); 4664 if (kobj_method == &kobj_desc->deflt) { 4665 device_printf(dev, 4666 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4667 err = EOPNOTSUPP; 4668 goto fail_queues; 4669 } 4670 4671 /* 4672 * Assign the MSI-X vectors. 4673 * Note that the default NULL ifdi_msix_intr_assign method will 4674 * fail here, too. 4675 */ 4676 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4677 if (err != 0) { 4678 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4679 err); 4680 goto fail_queues; 4681 } 4682 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4683 rid = 0; 4684 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4685 MPASS(msix == 1); 4686 rid = 1; 4687 } 4688 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4689 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4690 goto fail_queues; 4691 } 4692 } else { 4693 device_printf(dev, 4694 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4695 err = ENODEV; 4696 goto fail_intr_free; 4697 } 4698 4699 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4700 4701 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4702 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4703 goto fail_detach; 4704 } 4705 4706 /* 4707 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4708 * This must appear after the call to ether_ifattach() because 4709 * ether_ifattach() sets if_hdrlen to the default value. 4710 */ 4711 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4712 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4713 4714 if ((err = iflib_netmap_attach(ctx))) { 4715 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4716 goto fail_detach; 4717 } 4718 *ctxp = ctx; 4719 4720 NETDUMP_SET(ctx->ifc_ifp, iflib); 4721 4722 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4723 iflib_add_device_sysctl_post(ctx); 4724 ctx->ifc_flags |= IFC_INIT_DONE; 4725 CTX_UNLOCK(ctx); 4726 4727 return (0); 4728 4729 fail_detach: 4730 ether_ifdetach(ctx->ifc_ifp); 4731 fail_intr_free: 4732 iflib_free_intr_mem(ctx); 4733 fail_queues: 4734 iflib_tx_structures_free(ctx); 4735 iflib_rx_structures_free(ctx); 4736 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4737 IFDI_DETACH(ctx); 4738 fail_unlock: 4739 CTX_UNLOCK(ctx); 4740 iflib_deregister(ctx); 4741 fail_ctx_free: 4742 device_set_softc(ctx->ifc_dev, NULL); 4743 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4744 free(ctx->ifc_softc, M_IFLIB); 4745 free(ctx, M_IFLIB); 4746 return (err); 4747 } 4748 4749 int 4750 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4751 struct iflib_cloneattach_ctx *clctx) 4752 { 4753 int err; 4754 if_ctx_t ctx; 4755 if_t ifp; 4756 if_softc_ctx_t scctx; 4757 int i; 4758 void *sc; 4759 uint16_t main_txq; 4760 uint16_t main_rxq; 4761 4762 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4763 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4764 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4765 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4766 ctx->ifc_flags |= IFC_PSEUDO; 4767 4768 ctx->ifc_sctx = sctx; 4769 ctx->ifc_softc = sc; 4770 ctx->ifc_dev = dev; 4771 4772 if ((err = iflib_register(ctx)) != 0) { 4773 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4774 goto fail_ctx_free; 4775 } 4776 iflib_add_device_sysctl_pre(ctx); 4777 4778 scctx = &ctx->ifc_softc_ctx; 4779 ifp = ctx->ifc_ifp; 4780 4781 iflib_reset_qvalues(ctx); 4782 CTX_LOCK(ctx); 4783 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4784 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4785 goto fail_unlock; 4786 } 4787 if (sctx->isc_flags & IFLIB_GEN_MAC) 4788 iflib_gen_mac(ctx); 4789 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4790 clctx->cc_params)) != 0) { 4791 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4792 goto fail_ctx_free; 4793 } 4794 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4795 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4796 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4797 4798 #ifdef INVARIANTS 4799 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4800 MPASS(scctx->isc_tx_csum_flags); 4801 #endif 4802 4803 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4804 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4805 4806 ifp->if_flags |= IFF_NOGROUP; 4807 if (sctx->isc_flags & IFLIB_PSEUDO) { 4808 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4809 4810 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4811 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4812 goto fail_detach; 4813 } 4814 *ctxp = ctx; 4815 4816 /* 4817 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4818 * This must appear after the call to ether_ifattach() because 4819 * ether_ifattach() sets if_hdrlen to the default value. 4820 */ 4821 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4822 if_setifheaderlen(ifp, 4823 sizeof(struct ether_vlan_header)); 4824 4825 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4826 iflib_add_device_sysctl_post(ctx); 4827 ctx->ifc_flags |= IFC_INIT_DONE; 4828 return (0); 4829 } 4830 _iflib_pre_assert(scctx); 4831 ctx->ifc_txrx = *scctx->isc_txrx; 4832 4833 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4834 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4835 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4836 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4837 4838 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4839 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4840 4841 /* XXX change for per-queue sizes */ 4842 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4843 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4844 4845 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4846 MAX_SINGLE_PACKET_FRACTION) 4847 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4848 MAX_SINGLE_PACKET_FRACTION); 4849 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4850 MAX_SINGLE_PACKET_FRACTION) 4851 scctx->isc_tx_tso_segments_max = max(1, 4852 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4853 4854 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4855 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4856 /* 4857 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4858 * but some MACs do. 4859 */ 4860 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4861 IP_MAXPACKET)); 4862 /* 4863 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4864 * into account. In the worst case, each of these calls will 4865 * add another mbuf and, thus, the requirement for another DMA 4866 * segment. So for best performance, it doesn't make sense to 4867 * advertize a maximum of TSO segments that typically will 4868 * require defragmentation in iflib_encap(). 4869 */ 4870 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4871 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4872 } 4873 if (scctx->isc_rss_table_size == 0) 4874 scctx->isc_rss_table_size = 64; 4875 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4876 4877 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4878 /* XXX format name */ 4879 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4880 -1, "admin"); 4881 4882 /* XXX --- can support > 1 -- but keep it simple for now */ 4883 scctx->isc_intr = IFLIB_INTR_LEGACY; 4884 4885 /* Get memory for the station queues */ 4886 if ((err = iflib_queues_alloc(ctx))) { 4887 device_printf(dev, "Unable to allocate queue memory\n"); 4888 goto fail_iflib_detach; 4889 } 4890 4891 if ((err = iflib_qset_structures_setup(ctx))) { 4892 device_printf(dev, "qset structure setup failed %d\n", err); 4893 goto fail_queues; 4894 } 4895 4896 /* 4897 * XXX What if anything do we want to do about interrupts? 4898 */ 4899 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4900 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4901 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4902 goto fail_detach; 4903 } 4904 4905 /* 4906 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4907 * This must appear after the call to ether_ifattach() because 4908 * ether_ifattach() sets if_hdrlen to the default value. 4909 */ 4910 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4911 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4912 4913 /* XXX handle more than one queue */ 4914 for (i = 0; i < scctx->isc_nrxqsets; i++) 4915 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4916 4917 *ctxp = ctx; 4918 4919 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4920 iflib_add_device_sysctl_post(ctx); 4921 ctx->ifc_flags |= IFC_INIT_DONE; 4922 CTX_UNLOCK(ctx); 4923 4924 return (0); 4925 fail_detach: 4926 ether_ifdetach(ctx->ifc_ifp); 4927 fail_queues: 4928 iflib_tx_structures_free(ctx); 4929 iflib_rx_structures_free(ctx); 4930 fail_iflib_detach: 4931 IFDI_DETACH(ctx); 4932 fail_unlock: 4933 CTX_UNLOCK(ctx); 4934 iflib_deregister(ctx); 4935 fail_ctx_free: 4936 free(ctx->ifc_softc, M_IFLIB); 4937 free(ctx, M_IFLIB); 4938 return (err); 4939 } 4940 4941 int 4942 iflib_pseudo_deregister(if_ctx_t ctx) 4943 { 4944 if_t ifp = ctx->ifc_ifp; 4945 iflib_txq_t txq; 4946 iflib_rxq_t rxq; 4947 int i, j; 4948 struct taskqgroup *tqg; 4949 iflib_fl_t fl; 4950 4951 ether_ifdetach(ifp); 4952 /* XXX drain any dependent tasks */ 4953 tqg = qgroup_if_io_tqg; 4954 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4955 callout_drain(&txq->ift_timer); 4956 if (txq->ift_task.gt_uniq != NULL) 4957 taskqgroup_detach(tqg, &txq->ift_task); 4958 } 4959 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4960 if (rxq->ifr_task.gt_uniq != NULL) 4961 taskqgroup_detach(tqg, &rxq->ifr_task); 4962 4963 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4964 free(fl->ifl_rx_bitmap, M_IFLIB); 4965 } 4966 tqg = qgroup_if_config_tqg; 4967 if (ctx->ifc_admin_task.gt_uniq != NULL) 4968 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4969 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4970 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4971 4972 iflib_tx_structures_free(ctx); 4973 iflib_rx_structures_free(ctx); 4974 4975 iflib_deregister(ctx); 4976 4977 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4978 free(ctx->ifc_softc, M_IFLIB); 4979 free(ctx, M_IFLIB); 4980 return (0); 4981 } 4982 4983 int 4984 iflib_device_attach(device_t dev) 4985 { 4986 if_ctx_t ctx; 4987 if_shared_ctx_t sctx; 4988 4989 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4990 return (ENOTSUP); 4991 4992 pci_enable_busmaster(dev); 4993 4994 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4995 } 4996 4997 int 4998 iflib_device_deregister(if_ctx_t ctx) 4999 { 5000 if_t ifp = ctx->ifc_ifp; 5001 iflib_txq_t txq; 5002 iflib_rxq_t rxq; 5003 device_t dev = ctx->ifc_dev; 5004 int i, j; 5005 struct taskqgroup *tqg; 5006 iflib_fl_t fl; 5007 5008 /* Make sure VLANS are not using driver */ 5009 if (if_vlantrunkinuse(ifp)) { 5010 device_printf(dev, "Vlan in use, detach first\n"); 5011 return (EBUSY); 5012 } 5013 #ifdef PCI_IOV 5014 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5015 device_printf(dev, "SR-IOV in use; detach first.\n"); 5016 return (EBUSY); 5017 } 5018 #endif 5019 5020 STATE_LOCK(ctx); 5021 ctx->ifc_flags |= IFC_IN_DETACH; 5022 STATE_UNLOCK(ctx); 5023 5024 CTX_LOCK(ctx); 5025 iflib_stop(ctx); 5026 CTX_UNLOCK(ctx); 5027 5028 /* Unregister VLAN events */ 5029 if (ctx->ifc_vlan_attach_event != NULL) 5030 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5031 if (ctx->ifc_vlan_detach_event != NULL) 5032 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5033 5034 iflib_netmap_detach(ifp); 5035 ether_ifdetach(ifp); 5036 if (ctx->ifc_led_dev != NULL) 5037 led_destroy(ctx->ifc_led_dev); 5038 /* XXX drain any dependent tasks */ 5039 tqg = qgroup_if_io_tqg; 5040 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5041 callout_drain(&txq->ift_timer); 5042 if (txq->ift_task.gt_uniq != NULL) 5043 taskqgroup_detach(tqg, &txq->ift_task); 5044 } 5045 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5046 if (rxq->ifr_task.gt_uniq != NULL) 5047 taskqgroup_detach(tqg, &rxq->ifr_task); 5048 5049 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5050 free(fl->ifl_rx_bitmap, M_IFLIB); 5051 } 5052 tqg = qgroup_if_config_tqg; 5053 if (ctx->ifc_admin_task.gt_uniq != NULL) 5054 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5055 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5056 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5057 CTX_LOCK(ctx); 5058 IFDI_DETACH(ctx); 5059 CTX_UNLOCK(ctx); 5060 5061 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5062 iflib_free_intr_mem(ctx); 5063 5064 bus_generic_detach(dev); 5065 5066 iflib_tx_structures_free(ctx); 5067 iflib_rx_structures_free(ctx); 5068 5069 iflib_deregister(ctx); 5070 5071 device_set_softc(ctx->ifc_dev, NULL); 5072 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5073 free(ctx->ifc_softc, M_IFLIB); 5074 unref_ctx_core_offset(ctx); 5075 free(ctx, M_IFLIB); 5076 return (0); 5077 } 5078 5079 static void 5080 iflib_free_intr_mem(if_ctx_t ctx) 5081 { 5082 5083 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5084 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5085 } 5086 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5087 pci_release_msi(ctx->ifc_dev); 5088 } 5089 if (ctx->ifc_msix_mem != NULL) { 5090 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5091 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5092 ctx->ifc_msix_mem = NULL; 5093 } 5094 } 5095 5096 int 5097 iflib_device_detach(device_t dev) 5098 { 5099 if_ctx_t ctx = device_get_softc(dev); 5100 5101 return (iflib_device_deregister(ctx)); 5102 } 5103 5104 int 5105 iflib_device_suspend(device_t dev) 5106 { 5107 if_ctx_t ctx = device_get_softc(dev); 5108 5109 CTX_LOCK(ctx); 5110 IFDI_SUSPEND(ctx); 5111 CTX_UNLOCK(ctx); 5112 5113 return bus_generic_suspend(dev); 5114 } 5115 int 5116 iflib_device_shutdown(device_t dev) 5117 { 5118 if_ctx_t ctx = device_get_softc(dev); 5119 5120 CTX_LOCK(ctx); 5121 IFDI_SHUTDOWN(ctx); 5122 CTX_UNLOCK(ctx); 5123 5124 return bus_generic_suspend(dev); 5125 } 5126 5127 5128 int 5129 iflib_device_resume(device_t dev) 5130 { 5131 if_ctx_t ctx = device_get_softc(dev); 5132 iflib_txq_t txq = ctx->ifc_txqs; 5133 5134 CTX_LOCK(ctx); 5135 IFDI_RESUME(ctx); 5136 iflib_if_init_locked(ctx); 5137 CTX_UNLOCK(ctx); 5138 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5139 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5140 5141 return (bus_generic_resume(dev)); 5142 } 5143 5144 int 5145 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5146 { 5147 int error; 5148 if_ctx_t ctx = device_get_softc(dev); 5149 5150 CTX_LOCK(ctx); 5151 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5152 CTX_UNLOCK(ctx); 5153 5154 return (error); 5155 } 5156 5157 void 5158 iflib_device_iov_uninit(device_t dev) 5159 { 5160 if_ctx_t ctx = device_get_softc(dev); 5161 5162 CTX_LOCK(ctx); 5163 IFDI_IOV_UNINIT(ctx); 5164 CTX_UNLOCK(ctx); 5165 } 5166 5167 int 5168 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5169 { 5170 int error; 5171 if_ctx_t ctx = device_get_softc(dev); 5172 5173 CTX_LOCK(ctx); 5174 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5175 CTX_UNLOCK(ctx); 5176 5177 return (error); 5178 } 5179 5180 /********************************************************************* 5181 * 5182 * MODULE FUNCTION DEFINITIONS 5183 * 5184 **********************************************************************/ 5185 5186 /* 5187 * - Start a fast taskqueue thread for each core 5188 * - Start a taskqueue for control operations 5189 */ 5190 static int 5191 iflib_module_init(void) 5192 { 5193 return (0); 5194 } 5195 5196 static int 5197 iflib_module_event_handler(module_t mod, int what, void *arg) 5198 { 5199 int err; 5200 5201 switch (what) { 5202 case MOD_LOAD: 5203 if ((err = iflib_module_init()) != 0) 5204 return (err); 5205 break; 5206 case MOD_UNLOAD: 5207 return (EBUSY); 5208 default: 5209 return (EOPNOTSUPP); 5210 } 5211 5212 return (0); 5213 } 5214 5215 /********************************************************************* 5216 * 5217 * PUBLIC FUNCTION DEFINITIONS 5218 * ordered as in iflib.h 5219 * 5220 **********************************************************************/ 5221 5222 5223 static void 5224 _iflib_assert(if_shared_ctx_t sctx) 5225 { 5226 int i; 5227 5228 MPASS(sctx->isc_tx_maxsize); 5229 MPASS(sctx->isc_tx_maxsegsize); 5230 5231 MPASS(sctx->isc_rx_maxsize); 5232 MPASS(sctx->isc_rx_nsegments); 5233 MPASS(sctx->isc_rx_maxsegsize); 5234 5235 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5236 for (i = 0; i < sctx->isc_nrxqs; i++) { 5237 MPASS(sctx->isc_nrxd_min[i]); 5238 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5239 MPASS(sctx->isc_nrxd_max[i]); 5240 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5241 MPASS(sctx->isc_nrxd_default[i]); 5242 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5243 } 5244 5245 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5246 for (i = 0; i < sctx->isc_ntxqs; i++) { 5247 MPASS(sctx->isc_ntxd_min[i]); 5248 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5249 MPASS(sctx->isc_ntxd_max[i]); 5250 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5251 MPASS(sctx->isc_ntxd_default[i]); 5252 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5253 } 5254 } 5255 5256 static void 5257 _iflib_pre_assert(if_softc_ctx_t scctx) 5258 { 5259 5260 MPASS(scctx->isc_txrx->ift_txd_encap); 5261 MPASS(scctx->isc_txrx->ift_txd_flush); 5262 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5263 MPASS(scctx->isc_txrx->ift_rxd_available); 5264 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5265 MPASS(scctx->isc_txrx->ift_rxd_refill); 5266 MPASS(scctx->isc_txrx->ift_rxd_flush); 5267 } 5268 5269 static int 5270 iflib_register(if_ctx_t ctx) 5271 { 5272 if_shared_ctx_t sctx = ctx->ifc_sctx; 5273 driver_t *driver = sctx->isc_driver; 5274 device_t dev = ctx->ifc_dev; 5275 if_t ifp; 5276 5277 _iflib_assert(sctx); 5278 5279 CTX_LOCK_INIT(ctx); 5280 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5281 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5282 if (ifp == NULL) { 5283 device_printf(dev, "can not allocate ifnet structure\n"); 5284 return (ENOMEM); 5285 } 5286 5287 /* 5288 * Initialize our context's device specific methods 5289 */ 5290 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5291 kobj_class_compile((kobj_class_t) driver); 5292 5293 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5294 if_setsoftc(ifp, ctx); 5295 if_setdev(ifp, dev); 5296 if_setinitfn(ifp, iflib_if_init); 5297 if_setioctlfn(ifp, iflib_if_ioctl); 5298 #ifdef ALTQ 5299 if_setstartfn(ifp, iflib_altq_if_start); 5300 if_settransmitfn(ifp, iflib_altq_if_transmit); 5301 if_setsendqready(ifp); 5302 #else 5303 if_settransmitfn(ifp, iflib_if_transmit); 5304 #endif 5305 if_setqflushfn(ifp, iflib_if_qflush); 5306 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5307 5308 ctx->ifc_vlan_attach_event = 5309 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5310 EVENTHANDLER_PRI_FIRST); 5311 ctx->ifc_vlan_detach_event = 5312 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5313 EVENTHANDLER_PRI_FIRST); 5314 5315 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5316 iflib_media_change, iflib_media_status); 5317 5318 return (0); 5319 } 5320 5321 static void 5322 iflib_deregister(if_ctx_t ctx) 5323 { 5324 if_t ifp = ctx->ifc_ifp; 5325 5326 /* Remove all media */ 5327 ifmedia_removeall(&ctx->ifc_media); 5328 5329 /* Unregister VLAN events */ 5330 if (ctx->ifc_vlan_attach_event != NULL) { 5331 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5332 ctx->ifc_vlan_attach_event = NULL; 5333 } 5334 if (ctx->ifc_vlan_detach_event != NULL) { 5335 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5336 ctx->ifc_vlan_detach_event = NULL; 5337 } 5338 5339 /* Release kobject reference */ 5340 kobj_delete((kobj_t) ctx, NULL); 5341 5342 /* Free the ifnet structure */ 5343 if_free(ifp); 5344 5345 STATE_LOCK_DESTROY(ctx); 5346 5347 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5348 CTX_LOCK_DESTROY(ctx); 5349 } 5350 5351 static int 5352 iflib_queues_alloc(if_ctx_t ctx) 5353 { 5354 if_shared_ctx_t sctx = ctx->ifc_sctx; 5355 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5356 device_t dev = ctx->ifc_dev; 5357 int nrxqsets = scctx->isc_nrxqsets; 5358 int ntxqsets = scctx->isc_ntxqsets; 5359 iflib_txq_t txq; 5360 iflib_rxq_t rxq; 5361 iflib_fl_t fl = NULL; 5362 int i, j, cpu, err, txconf, rxconf; 5363 iflib_dma_info_t ifdip; 5364 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5365 uint32_t *txqsizes = scctx->isc_txqsizes; 5366 uint8_t nrxqs = sctx->isc_nrxqs; 5367 uint8_t ntxqs = sctx->isc_ntxqs; 5368 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5369 caddr_t *vaddrs; 5370 uint64_t *paddrs; 5371 5372 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5373 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5374 5375 /* Allocate the TX ring struct memory */ 5376 if (!(ctx->ifc_txqs = 5377 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5378 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5379 device_printf(dev, "Unable to allocate TX ring memory\n"); 5380 err = ENOMEM; 5381 goto fail; 5382 } 5383 5384 /* Now allocate the RX */ 5385 if (!(ctx->ifc_rxqs = 5386 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5387 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5388 device_printf(dev, "Unable to allocate RX ring memory\n"); 5389 err = ENOMEM; 5390 goto rx_fail; 5391 } 5392 5393 txq = ctx->ifc_txqs; 5394 rxq = ctx->ifc_rxqs; 5395 5396 /* 5397 * XXX handle allocation failure 5398 */ 5399 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5400 /* Set up some basics */ 5401 5402 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5403 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5404 device_printf(dev, 5405 "Unable to allocate TX DMA info memory\n"); 5406 err = ENOMEM; 5407 goto err_tx_desc; 5408 } 5409 txq->ift_ifdi = ifdip; 5410 for (j = 0; j < ntxqs; j++, ifdip++) { 5411 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5412 device_printf(dev, 5413 "Unable to allocate TX descriptors\n"); 5414 err = ENOMEM; 5415 goto err_tx_desc; 5416 } 5417 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5418 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5419 } 5420 txq->ift_ctx = ctx; 5421 txq->ift_id = i; 5422 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5423 txq->ift_br_offset = 1; 5424 } else { 5425 txq->ift_br_offset = 0; 5426 } 5427 /* XXX fix this */ 5428 txq->ift_timer.c_cpu = cpu; 5429 5430 if (iflib_txsd_alloc(txq)) { 5431 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5432 err = ENOMEM; 5433 goto err_tx_desc; 5434 } 5435 5436 /* Initialize the TX lock */ 5437 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5438 device_get_nameunit(dev), txq->ift_id); 5439 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5440 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5441 5442 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5443 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5444 if (err) { 5445 /* XXX free any allocated rings */ 5446 device_printf(dev, "Unable to allocate buf_ring\n"); 5447 goto err_tx_desc; 5448 } 5449 } 5450 5451 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5452 /* Set up some basics */ 5453 5454 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5455 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5456 device_printf(dev, 5457 "Unable to allocate RX DMA info memory\n"); 5458 err = ENOMEM; 5459 goto err_tx_desc; 5460 } 5461 5462 rxq->ifr_ifdi = ifdip; 5463 /* XXX this needs to be changed if #rx queues != #tx queues */ 5464 rxq->ifr_ntxqirq = 1; 5465 rxq->ifr_txqid[0] = i; 5466 for (j = 0; j < nrxqs; j++, ifdip++) { 5467 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5468 device_printf(dev, 5469 "Unable to allocate RX descriptors\n"); 5470 err = ENOMEM; 5471 goto err_tx_desc; 5472 } 5473 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5474 } 5475 rxq->ifr_ctx = ctx; 5476 rxq->ifr_id = i; 5477 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5478 rxq->ifr_fl_offset = 1; 5479 } else { 5480 rxq->ifr_fl_offset = 0; 5481 } 5482 rxq->ifr_nfl = nfree_lists; 5483 if (!(fl = 5484 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5485 device_printf(dev, "Unable to allocate free list memory\n"); 5486 err = ENOMEM; 5487 goto err_tx_desc; 5488 } 5489 rxq->ifr_fl = fl; 5490 for (j = 0; j < nfree_lists; j++) { 5491 fl[j].ifl_rxq = rxq; 5492 fl[j].ifl_id = j; 5493 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5494 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5495 } 5496 /* Allocate receive buffers for the ring */ 5497 if (iflib_rxsd_alloc(rxq)) { 5498 device_printf(dev, 5499 "Critical Failure setting up receive buffers\n"); 5500 err = ENOMEM; 5501 goto err_rx_desc; 5502 } 5503 5504 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5505 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5506 M_WAITOK); 5507 } 5508 5509 /* TXQs */ 5510 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5511 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5512 for (i = 0; i < ntxqsets; i++) { 5513 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5514 5515 for (j = 0; j < ntxqs; j++, di++) { 5516 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5517 paddrs[i*ntxqs + j] = di->idi_paddr; 5518 } 5519 } 5520 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5521 device_printf(ctx->ifc_dev, 5522 "Unable to allocate device TX queue\n"); 5523 iflib_tx_structures_free(ctx); 5524 free(vaddrs, M_IFLIB); 5525 free(paddrs, M_IFLIB); 5526 goto err_rx_desc; 5527 } 5528 free(vaddrs, M_IFLIB); 5529 free(paddrs, M_IFLIB); 5530 5531 /* RXQs */ 5532 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5533 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5534 for (i = 0; i < nrxqsets; i++) { 5535 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5536 5537 for (j = 0; j < nrxqs; j++, di++) { 5538 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5539 paddrs[i*nrxqs + j] = di->idi_paddr; 5540 } 5541 } 5542 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5543 device_printf(ctx->ifc_dev, 5544 "Unable to allocate device RX queue\n"); 5545 iflib_tx_structures_free(ctx); 5546 free(vaddrs, M_IFLIB); 5547 free(paddrs, M_IFLIB); 5548 goto err_rx_desc; 5549 } 5550 free(vaddrs, M_IFLIB); 5551 free(paddrs, M_IFLIB); 5552 5553 return (0); 5554 5555 /* XXX handle allocation failure changes */ 5556 err_rx_desc: 5557 err_tx_desc: 5558 rx_fail: 5559 if (ctx->ifc_rxqs != NULL) 5560 free(ctx->ifc_rxqs, M_IFLIB); 5561 ctx->ifc_rxqs = NULL; 5562 if (ctx->ifc_txqs != NULL) 5563 free(ctx->ifc_txqs, M_IFLIB); 5564 ctx->ifc_txqs = NULL; 5565 fail: 5566 return (err); 5567 } 5568 5569 static int 5570 iflib_tx_structures_setup(if_ctx_t ctx) 5571 { 5572 iflib_txq_t txq = ctx->ifc_txqs; 5573 int i; 5574 5575 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5576 iflib_txq_setup(txq); 5577 5578 return (0); 5579 } 5580 5581 static void 5582 iflib_tx_structures_free(if_ctx_t ctx) 5583 { 5584 iflib_txq_t txq = ctx->ifc_txqs; 5585 if_shared_ctx_t sctx = ctx->ifc_sctx; 5586 int i, j; 5587 5588 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5589 iflib_txq_destroy(txq); 5590 for (j = 0; j < sctx->isc_ntxqs; j++) 5591 iflib_dma_free(&txq->ift_ifdi[j]); 5592 } 5593 free(ctx->ifc_txqs, M_IFLIB); 5594 ctx->ifc_txqs = NULL; 5595 IFDI_QUEUES_FREE(ctx); 5596 } 5597 5598 /********************************************************************* 5599 * 5600 * Initialize all receive rings. 5601 * 5602 **********************************************************************/ 5603 static int 5604 iflib_rx_structures_setup(if_ctx_t ctx) 5605 { 5606 iflib_rxq_t rxq = ctx->ifc_rxqs; 5607 int q; 5608 #if defined(INET6) || defined(INET) 5609 int err, i; 5610 #endif 5611 5612 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5613 #if defined(INET6) || defined(INET) 5614 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5615 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5616 TCP_LRO_ENTRIES, min(1024, 5617 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5618 if (err != 0) { 5619 device_printf(ctx->ifc_dev, 5620 "LRO Initialization failed!\n"); 5621 goto fail; 5622 } 5623 } 5624 #endif 5625 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5626 } 5627 return (0); 5628 #if defined(INET6) || defined(INET) 5629 fail: 5630 /* 5631 * Free LRO resources allocated so far, we will only handle 5632 * the rings that completed, the failing case will have 5633 * cleaned up for itself. 'q' failed, so its the terminus. 5634 */ 5635 rxq = ctx->ifc_rxqs; 5636 for (i = 0; i < q; ++i, rxq++) { 5637 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5638 tcp_lro_free(&rxq->ifr_lc); 5639 } 5640 return (err); 5641 #endif 5642 } 5643 5644 /********************************************************************* 5645 * 5646 * Free all receive rings. 5647 * 5648 **********************************************************************/ 5649 static void 5650 iflib_rx_structures_free(if_ctx_t ctx) 5651 { 5652 iflib_rxq_t rxq = ctx->ifc_rxqs; 5653 int i; 5654 5655 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5656 iflib_rx_sds_free(rxq); 5657 #if defined(INET6) || defined(INET) 5658 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5659 tcp_lro_free(&rxq->ifr_lc); 5660 #endif 5661 } 5662 free(ctx->ifc_rxqs, M_IFLIB); 5663 ctx->ifc_rxqs = NULL; 5664 } 5665 5666 static int 5667 iflib_qset_structures_setup(if_ctx_t ctx) 5668 { 5669 int err; 5670 5671 /* 5672 * It is expected that the caller takes care of freeing queues if this 5673 * fails. 5674 */ 5675 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5676 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5677 return (err); 5678 } 5679 5680 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5681 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5682 5683 return (err); 5684 } 5685 5686 int 5687 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5688 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5689 { 5690 5691 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5692 } 5693 5694 #ifdef SMP 5695 static int 5696 find_nth(if_ctx_t ctx, int qid) 5697 { 5698 cpuset_t cpus; 5699 int i, cpuid, eqid, count; 5700 5701 CPU_COPY(&ctx->ifc_cpus, &cpus); 5702 count = CPU_COUNT(&cpus); 5703 eqid = qid % count; 5704 /* clear up to the qid'th bit */ 5705 for (i = 0; i < eqid; i++) { 5706 cpuid = CPU_FFS(&cpus); 5707 MPASS(cpuid != 0); 5708 CPU_CLR(cpuid-1, &cpus); 5709 } 5710 cpuid = CPU_FFS(&cpus); 5711 MPASS(cpuid != 0); 5712 return (cpuid-1); 5713 } 5714 5715 #ifdef SCHED_ULE 5716 extern struct cpu_group *cpu_top; /* CPU topology */ 5717 5718 static int 5719 find_child_with_core(int cpu, struct cpu_group *grp) 5720 { 5721 int i; 5722 5723 if (grp->cg_children == 0) 5724 return -1; 5725 5726 MPASS(grp->cg_child); 5727 for (i = 0; i < grp->cg_children; i++) { 5728 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5729 return i; 5730 } 5731 5732 return -1; 5733 } 5734 5735 /* 5736 * Find the nth "close" core to the specified core 5737 * "close" is defined as the deepest level that shares 5738 * at least an L2 cache. With threads, this will be 5739 * threads on the same core. If the shared cache is L3 5740 * or higher, simply returns the same core. 5741 */ 5742 static int 5743 find_close_core(int cpu, int core_offset) 5744 { 5745 struct cpu_group *grp; 5746 int i; 5747 int fcpu; 5748 cpuset_t cs; 5749 5750 grp = cpu_top; 5751 if (grp == NULL) 5752 return cpu; 5753 i = 0; 5754 while ((i = find_child_with_core(cpu, grp)) != -1) { 5755 /* If the child only has one cpu, don't descend */ 5756 if (grp->cg_child[i].cg_count <= 1) 5757 break; 5758 grp = &grp->cg_child[i]; 5759 } 5760 5761 /* If they don't share at least an L2 cache, use the same CPU */ 5762 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5763 return cpu; 5764 5765 /* Now pick one */ 5766 CPU_COPY(&grp->cg_mask, &cs); 5767 5768 /* Add the selected CPU offset to core offset. */ 5769 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5770 if (fcpu - 1 == cpu) 5771 break; 5772 CPU_CLR(fcpu - 1, &cs); 5773 } 5774 MPASS(fcpu); 5775 5776 core_offset += i; 5777 5778 CPU_COPY(&grp->cg_mask, &cs); 5779 for (i = core_offset % grp->cg_count; i > 0; i--) { 5780 MPASS(CPU_FFS(&cs)); 5781 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5782 } 5783 MPASS(CPU_FFS(&cs)); 5784 return CPU_FFS(&cs) - 1; 5785 } 5786 #else 5787 static int 5788 find_close_core(int cpu, int core_offset __unused) 5789 { 5790 return cpu; 5791 } 5792 #endif 5793 5794 static int 5795 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5796 { 5797 switch (type) { 5798 case IFLIB_INTR_TX: 5799 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5800 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5801 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5802 case IFLIB_INTR_RX: 5803 case IFLIB_INTR_RXTX: 5804 /* RX queues get the specified core */ 5805 return qid / CPU_COUNT(&ctx->ifc_cpus); 5806 default: 5807 return -1; 5808 } 5809 } 5810 #else 5811 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5812 #define find_close_core(cpuid, tid) CPU_FIRST() 5813 #define find_nth(ctx, gid) CPU_FIRST() 5814 #endif 5815 5816 /* Just to avoid copy/paste */ 5817 static inline int 5818 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5819 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5820 const char *name) 5821 { 5822 device_t dev; 5823 int co, cpuid, err, tid; 5824 5825 dev = ctx->ifc_dev; 5826 co = ctx->ifc_sysctl_core_offset; 5827 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5828 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5829 cpuid = find_nth(ctx, qid + co); 5830 tid = get_core_offset(ctx, type, qid); 5831 if (tid < 0) { 5832 device_printf(dev, "get_core_offset failed\n"); 5833 return (EOPNOTSUPP); 5834 } 5835 cpuid = find_close_core(cpuid, tid); 5836 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, 5837 rman_get_start(irq->ii_res), name); 5838 if (err) { 5839 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5840 return (err); 5841 } 5842 #ifdef notyet 5843 if (cpuid > ctx->ifc_cpuid_highest) 5844 ctx->ifc_cpuid_highest = cpuid; 5845 #endif 5846 return (0); 5847 } 5848 5849 int 5850 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5851 iflib_intr_type_t type, driver_filter_t *filter, 5852 void *filter_arg, int qid, const char *name) 5853 { 5854 device_t dev; 5855 struct grouptask *gtask; 5856 struct taskqgroup *tqg; 5857 iflib_filter_info_t info; 5858 gtask_fn_t *fn; 5859 int tqrid, err; 5860 driver_filter_t *intr_fast; 5861 void *q; 5862 5863 info = &ctx->ifc_filter_info; 5864 tqrid = rid; 5865 5866 switch (type) { 5867 /* XXX merge tx/rx for netmap? */ 5868 case IFLIB_INTR_TX: 5869 q = &ctx->ifc_txqs[qid]; 5870 info = &ctx->ifc_txqs[qid].ift_filter_info; 5871 gtask = &ctx->ifc_txqs[qid].ift_task; 5872 tqg = qgroup_if_io_tqg; 5873 fn = _task_fn_tx; 5874 intr_fast = iflib_fast_intr; 5875 GROUPTASK_INIT(gtask, 0, fn, q); 5876 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5877 break; 5878 case IFLIB_INTR_RX: 5879 q = &ctx->ifc_rxqs[qid]; 5880 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5881 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5882 tqg = qgroup_if_io_tqg; 5883 fn = _task_fn_rx; 5884 intr_fast = iflib_fast_intr; 5885 GROUPTASK_INIT(gtask, 0, fn, q); 5886 break; 5887 case IFLIB_INTR_RXTX: 5888 q = &ctx->ifc_rxqs[qid]; 5889 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5890 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5891 tqg = qgroup_if_io_tqg; 5892 fn = _task_fn_rx; 5893 intr_fast = iflib_fast_intr_rxtx; 5894 GROUPTASK_INIT(gtask, 0, fn, q); 5895 break; 5896 case IFLIB_INTR_ADMIN: 5897 q = ctx; 5898 tqrid = -1; 5899 info = &ctx->ifc_filter_info; 5900 gtask = &ctx->ifc_admin_task; 5901 tqg = qgroup_if_config_tqg; 5902 fn = _task_fn_admin; 5903 intr_fast = iflib_fast_intr_ctx; 5904 break; 5905 default: 5906 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 5907 __func__); 5908 return (EINVAL); 5909 } 5910 5911 info->ifi_filter = filter; 5912 info->ifi_filter_arg = filter_arg; 5913 info->ifi_task = gtask; 5914 info->ifi_ctx = q; 5915 5916 dev = ctx->ifc_dev; 5917 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5918 if (err != 0) { 5919 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5920 return (err); 5921 } 5922 if (type == IFLIB_INTR_ADMIN) 5923 return (0); 5924 5925 if (tqrid != -1) { 5926 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5927 q, name); 5928 if (err) 5929 return (err); 5930 } else { 5931 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), 5932 name); 5933 } 5934 5935 return (0); 5936 } 5937 5938 void 5939 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5940 { 5941 struct grouptask *gtask; 5942 struct taskqgroup *tqg; 5943 gtask_fn_t *fn; 5944 void *q; 5945 int err; 5946 5947 switch (type) { 5948 case IFLIB_INTR_TX: 5949 q = &ctx->ifc_txqs[qid]; 5950 gtask = &ctx->ifc_txqs[qid].ift_task; 5951 tqg = qgroup_if_io_tqg; 5952 fn = _task_fn_tx; 5953 break; 5954 case IFLIB_INTR_RX: 5955 q = &ctx->ifc_rxqs[qid]; 5956 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5957 tqg = qgroup_if_io_tqg; 5958 fn = _task_fn_rx; 5959 break; 5960 case IFLIB_INTR_IOV: 5961 q = ctx; 5962 gtask = &ctx->ifc_vflr_task; 5963 tqg = qgroup_if_config_tqg; 5964 fn = _task_fn_iov; 5965 break; 5966 default: 5967 panic("unknown net intr type"); 5968 } 5969 GROUPTASK_INIT(gtask, 0, fn, q); 5970 if (irq != NULL) { 5971 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5972 q, name); 5973 if (err) 5974 taskqgroup_attach(tqg, gtask, q, 5975 rman_get_start(irq->ii_res), name); 5976 } else { 5977 taskqgroup_attach(tqg, gtask, q, -1, name); 5978 } 5979 } 5980 5981 void 5982 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5983 { 5984 5985 if (irq->ii_tag) 5986 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5987 5988 if (irq->ii_res) 5989 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 5990 rman_get_rid(irq->ii_res), irq->ii_res); 5991 } 5992 5993 static int 5994 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5995 { 5996 iflib_txq_t txq = ctx->ifc_txqs; 5997 iflib_rxq_t rxq = ctx->ifc_rxqs; 5998 if_irq_t irq = &ctx->ifc_legacy_irq; 5999 iflib_filter_info_t info; 6000 struct grouptask *gtask; 6001 struct taskqgroup *tqg; 6002 gtask_fn_t *fn; 6003 int tqrid; 6004 void *q; 6005 int err; 6006 6007 q = &ctx->ifc_rxqs[0]; 6008 info = &rxq[0].ifr_filter_info; 6009 gtask = &rxq[0].ifr_task; 6010 tqg = qgroup_if_io_tqg; 6011 tqrid = irq->ii_rid = *rid; 6012 fn = _task_fn_rx; 6013 6014 ctx->ifc_flags |= IFC_LEGACY; 6015 info->ifi_filter = filter; 6016 info->ifi_filter_arg = filter_arg; 6017 info->ifi_task = gtask; 6018 info->ifi_ctx = q; 6019 6020 /* We allocate a single interrupt resource */ 6021 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_rxtx, 6022 NULL, info, name)) != 0) 6023 return (err); 6024 GROUPTASK_INIT(gtask, 0, fn, q); 6025 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 6026 6027 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6028 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, 6029 rman_get_start(irq->ii_res), "tx"); 6030 return (0); 6031 } 6032 6033 void 6034 iflib_led_create(if_ctx_t ctx) 6035 { 6036 6037 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6038 device_get_nameunit(ctx->ifc_dev)); 6039 } 6040 6041 void 6042 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6043 { 6044 6045 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6046 } 6047 6048 void 6049 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6050 { 6051 6052 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6053 } 6054 6055 void 6056 iflib_admin_intr_deferred(if_ctx_t ctx) 6057 { 6058 #ifdef INVARIANTS 6059 struct grouptask *gtask; 6060 6061 gtask = &ctx->ifc_admin_task; 6062 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6063 #endif 6064 6065 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6066 } 6067 6068 void 6069 iflib_iov_intr_deferred(if_ctx_t ctx) 6070 { 6071 6072 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6073 } 6074 6075 void 6076 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 6077 { 6078 6079 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 6080 } 6081 6082 void 6083 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6084 const char *name) 6085 { 6086 6087 GROUPTASK_INIT(gtask, 0, fn, ctx); 6088 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 6089 } 6090 6091 void 6092 iflib_config_gtask_deinit(struct grouptask *gtask) 6093 { 6094 6095 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6096 } 6097 6098 void 6099 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6100 { 6101 if_t ifp = ctx->ifc_ifp; 6102 iflib_txq_t txq = ctx->ifc_txqs; 6103 6104 if_setbaudrate(ifp, baudrate); 6105 if (baudrate >= IF_Gbps(10)) { 6106 STATE_LOCK(ctx); 6107 ctx->ifc_flags |= IFC_PREFETCH; 6108 STATE_UNLOCK(ctx); 6109 } 6110 /* If link down, disable watchdog */ 6111 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6112 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6113 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6114 } 6115 ctx->ifc_link_state = link_state; 6116 if_link_state_change(ifp, link_state); 6117 } 6118 6119 static int 6120 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6121 { 6122 int credits; 6123 #ifdef INVARIANTS 6124 int credits_pre = txq->ift_cidx_processed; 6125 #endif 6126 6127 if (ctx->isc_txd_credits_update == NULL) 6128 return (0); 6129 6130 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6131 BUS_DMASYNC_POSTREAD); 6132 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6133 return (0); 6134 6135 txq->ift_processed += credits; 6136 txq->ift_cidx_processed += credits; 6137 6138 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6139 if (txq->ift_cidx_processed >= txq->ift_size) 6140 txq->ift_cidx_processed -= txq->ift_size; 6141 return (credits); 6142 } 6143 6144 static int 6145 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6146 { 6147 iflib_fl_t fl; 6148 u_int i; 6149 6150 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6151 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6152 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6153 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6154 budget)); 6155 } 6156 6157 void 6158 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6159 const char *description, if_int_delay_info_t info, 6160 int offset, int value) 6161 { 6162 info->iidi_ctx = ctx; 6163 info->iidi_offset = offset; 6164 info->iidi_value = value; 6165 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6166 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6167 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6168 info, 0, iflib_sysctl_int_delay, "I", description); 6169 } 6170 6171 struct sx * 6172 iflib_ctx_lock_get(if_ctx_t ctx) 6173 { 6174 6175 return (&ctx->ifc_ctx_sx); 6176 } 6177 6178 static int 6179 iflib_msix_init(if_ctx_t ctx) 6180 { 6181 device_t dev = ctx->ifc_dev; 6182 if_shared_ctx_t sctx = ctx->ifc_sctx; 6183 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6184 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6185 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6186 6187 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6188 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6189 6190 if (bootverbose) 6191 device_printf(dev, "msix_init qsets capped at %d\n", 6192 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6193 6194 /* Override by tuneable */ 6195 if (scctx->isc_disable_msix) 6196 goto msi; 6197 6198 /* First try MSI-X */ 6199 if ((msgs = pci_msix_count(dev)) == 0) { 6200 if (bootverbose) 6201 device_printf(dev, "MSI-X not supported or disabled\n"); 6202 goto msi; 6203 } 6204 6205 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6206 /* 6207 * bar == -1 => "trust me I know what I'm doing" 6208 * Some drivers are for hardware that is so shoddily 6209 * documented that no one knows which bars are which 6210 * so the developer has to map all bars. This hack 6211 * allows shoddy garbage to use MSI-X in this framework. 6212 */ 6213 if (bar != -1) { 6214 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6215 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6216 if (ctx->ifc_msix_mem == NULL) { 6217 device_printf(dev, "Unable to map MSI-X table\n"); 6218 goto msi; 6219 } 6220 } 6221 6222 admincnt = sctx->isc_admin_intrcnt; 6223 #if IFLIB_DEBUG 6224 /* use only 1 qset in debug mode */ 6225 queuemsgs = min(msgs - admincnt, 1); 6226 #else 6227 queuemsgs = msgs - admincnt; 6228 #endif 6229 #ifdef RSS 6230 queues = imin(queuemsgs, rss_getnumbuckets()); 6231 #else 6232 queues = queuemsgs; 6233 #endif 6234 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6235 if (bootverbose) 6236 device_printf(dev, 6237 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6238 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6239 #ifdef RSS 6240 /* If we're doing RSS, clamp at the number of RSS buckets */ 6241 if (queues > rss_getnumbuckets()) 6242 queues = rss_getnumbuckets(); 6243 #endif 6244 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6245 rx_queues = iflib_num_rx_queues; 6246 else 6247 rx_queues = queues; 6248 6249 if (rx_queues > scctx->isc_nrxqsets) 6250 rx_queues = scctx->isc_nrxqsets; 6251 6252 /* 6253 * We want this to be all logical CPUs by default 6254 */ 6255 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6256 tx_queues = iflib_num_tx_queues; 6257 else 6258 tx_queues = mp_ncpus; 6259 6260 if (tx_queues > scctx->isc_ntxqsets) 6261 tx_queues = scctx->isc_ntxqsets; 6262 6263 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6264 #ifdef INVARIANTS 6265 if (tx_queues != rx_queues) 6266 device_printf(dev, 6267 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6268 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6269 #endif 6270 tx_queues = min(rx_queues, tx_queues); 6271 rx_queues = min(rx_queues, tx_queues); 6272 } 6273 6274 vectors = rx_queues + admincnt; 6275 if (msgs < vectors) { 6276 device_printf(dev, 6277 "insufficient number of MSI-X vectors " 6278 "(supported %d, need %d)\n", msgs, vectors); 6279 goto msi; 6280 } 6281 6282 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6283 tx_queues); 6284 msgs = vectors; 6285 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6286 if (vectors != msgs) { 6287 device_printf(dev, 6288 "Unable to allocate sufficient MSI-X vectors " 6289 "(got %d, need %d)\n", vectors, msgs); 6290 pci_release_msi(dev); 6291 if (bar != -1) { 6292 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6293 ctx->ifc_msix_mem); 6294 ctx->ifc_msix_mem = NULL; 6295 } 6296 goto msi; 6297 } 6298 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6299 vectors); 6300 scctx->isc_vectors = vectors; 6301 scctx->isc_nrxqsets = rx_queues; 6302 scctx->isc_ntxqsets = tx_queues; 6303 scctx->isc_intr = IFLIB_INTR_MSIX; 6304 6305 return (vectors); 6306 } else { 6307 device_printf(dev, 6308 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6309 err); 6310 if (bar != -1) { 6311 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6312 ctx->ifc_msix_mem); 6313 ctx->ifc_msix_mem = NULL; 6314 } 6315 } 6316 6317 msi: 6318 vectors = pci_msi_count(dev); 6319 scctx->isc_nrxqsets = 1; 6320 scctx->isc_ntxqsets = 1; 6321 scctx->isc_vectors = vectors; 6322 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6323 device_printf(dev,"Using an MSI interrupt\n"); 6324 scctx->isc_intr = IFLIB_INTR_MSI; 6325 } else { 6326 scctx->isc_vectors = 1; 6327 device_printf(dev,"Using a Legacy interrupt\n"); 6328 scctx->isc_intr = IFLIB_INTR_LEGACY; 6329 } 6330 6331 return (vectors); 6332 } 6333 6334 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6335 6336 static int 6337 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6338 { 6339 int rc; 6340 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6341 struct sbuf *sb; 6342 const char *ring_state = "UNKNOWN"; 6343 6344 /* XXX needed ? */ 6345 rc = sysctl_wire_old_buffer(req, 0); 6346 MPASS(rc == 0); 6347 if (rc != 0) 6348 return (rc); 6349 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6350 MPASS(sb != NULL); 6351 if (sb == NULL) 6352 return (ENOMEM); 6353 if (state[3] <= 3) 6354 ring_state = ring_states[state[3]]; 6355 6356 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6357 state[0], state[1], state[2], ring_state); 6358 rc = sbuf_finish(sb); 6359 sbuf_delete(sb); 6360 return(rc); 6361 } 6362 6363 enum iflib_ndesc_handler { 6364 IFLIB_NTXD_HANDLER, 6365 IFLIB_NRXD_HANDLER, 6366 }; 6367 6368 static int 6369 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6370 { 6371 if_ctx_t ctx = (void *)arg1; 6372 enum iflib_ndesc_handler type = arg2; 6373 char buf[256] = {0}; 6374 qidx_t *ndesc; 6375 char *p, *next; 6376 int nqs, rc, i; 6377 6378 nqs = 8; 6379 switch(type) { 6380 case IFLIB_NTXD_HANDLER: 6381 ndesc = ctx->ifc_sysctl_ntxds; 6382 if (ctx->ifc_sctx) 6383 nqs = ctx->ifc_sctx->isc_ntxqs; 6384 break; 6385 case IFLIB_NRXD_HANDLER: 6386 ndesc = ctx->ifc_sysctl_nrxds; 6387 if (ctx->ifc_sctx) 6388 nqs = ctx->ifc_sctx->isc_nrxqs; 6389 break; 6390 default: 6391 printf("%s: unhandled type\n", __func__); 6392 return (EINVAL); 6393 } 6394 if (nqs == 0) 6395 nqs = 8; 6396 6397 for (i=0; i<8; i++) { 6398 if (i >= nqs) 6399 break; 6400 if (i) 6401 strcat(buf, ","); 6402 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6403 } 6404 6405 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6406 if (rc || req->newptr == NULL) 6407 return rc; 6408 6409 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6410 i++, p = strsep(&next, " ,")) { 6411 ndesc[i] = strtoul(p, NULL, 10); 6412 } 6413 6414 return(rc); 6415 } 6416 6417 #define NAME_BUFLEN 32 6418 static void 6419 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6420 { 6421 device_t dev = iflib_get_dev(ctx); 6422 struct sysctl_oid_list *child, *oid_list; 6423 struct sysctl_ctx_list *ctx_list; 6424 struct sysctl_oid *node; 6425 6426 ctx_list = device_get_sysctl_ctx(dev); 6427 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6428 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6429 CTLFLAG_RD, NULL, "IFLIB fields"); 6430 oid_list = SYSCTL_CHILDREN(node); 6431 6432 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6433 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6434 "driver version"); 6435 6436 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6437 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6438 "# of txqs to use, 0 => use default #"); 6439 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6440 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6441 "# of rxqs to use, 0 => use default #"); 6442 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6443 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6444 "permit #txq != #rxq"); 6445 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6446 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6447 "disable MSI-X (default 0)"); 6448 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6449 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6450 "set the RX budget"); 6451 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6452 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6453 "cause TX to abdicate instead of running to completion"); 6454 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6455 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6456 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6457 "offset to start using cores at"); 6458 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6459 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6460 "use separate cores for TX and RX"); 6461 6462 /* XXX change for per-queue sizes */ 6463 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6464 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6465 mp_ndesc_handler, "A", 6466 "list of # of TX descriptors to use, 0 = use default #"); 6467 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6468 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6469 mp_ndesc_handler, "A", 6470 "list of # of RX descriptors to use, 0 = use default #"); 6471 } 6472 6473 static void 6474 iflib_add_device_sysctl_post(if_ctx_t ctx) 6475 { 6476 if_shared_ctx_t sctx = ctx->ifc_sctx; 6477 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6478 device_t dev = iflib_get_dev(ctx); 6479 struct sysctl_oid_list *child; 6480 struct sysctl_ctx_list *ctx_list; 6481 iflib_fl_t fl; 6482 iflib_txq_t txq; 6483 iflib_rxq_t rxq; 6484 int i, j; 6485 char namebuf[NAME_BUFLEN]; 6486 char *qfmt; 6487 struct sysctl_oid *queue_node, *fl_node, *node; 6488 struct sysctl_oid_list *queue_list, *fl_list; 6489 ctx_list = device_get_sysctl_ctx(dev); 6490 6491 node = ctx->ifc_sysctl_node; 6492 child = SYSCTL_CHILDREN(node); 6493 6494 if (scctx->isc_ntxqsets > 100) 6495 qfmt = "txq%03d"; 6496 else if (scctx->isc_ntxqsets > 10) 6497 qfmt = "txq%02d"; 6498 else 6499 qfmt = "txq%d"; 6500 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6501 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6502 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6503 CTLFLAG_RD, NULL, "Queue Name"); 6504 queue_list = SYSCTL_CHILDREN(queue_node); 6505 #if MEMORY_LOGGING 6506 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6507 CTLFLAG_RD, 6508 &txq->ift_dequeued, "total mbufs freed"); 6509 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6510 CTLFLAG_RD, 6511 &txq->ift_enqueued, "total mbufs enqueued"); 6512 #endif 6513 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6514 CTLFLAG_RD, 6515 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6516 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6517 CTLFLAG_RD, 6518 &txq->ift_pullups, "# of times m_pullup was called"); 6519 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6520 CTLFLAG_RD, 6521 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6522 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6523 CTLFLAG_RD, 6524 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6525 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6526 CTLFLAG_RD, 6527 &txq->ift_map_failed, "# of times DMA map failed"); 6528 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6529 CTLFLAG_RD, 6530 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6531 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6532 CTLFLAG_RD, 6533 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6534 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6535 CTLFLAG_RD, 6536 &txq->ift_pidx, 1, "Producer Index"); 6537 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6538 CTLFLAG_RD, 6539 &txq->ift_cidx, 1, "Consumer Index"); 6540 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6541 CTLFLAG_RD, 6542 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6543 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6544 CTLFLAG_RD, 6545 &txq->ift_in_use, 1, "descriptors in use"); 6546 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6547 CTLFLAG_RD, 6548 &txq->ift_processed, "descriptors procesed for clean"); 6549 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6550 CTLFLAG_RD, 6551 &txq->ift_cleaned, "total cleaned"); 6552 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6553 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6554 0, mp_ring_state_handler, "A", "soft ring state"); 6555 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6556 CTLFLAG_RD, &txq->ift_br->enqueues, 6557 "# of enqueues to the mp_ring for this queue"); 6558 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6559 CTLFLAG_RD, &txq->ift_br->drops, 6560 "# of drops in the mp_ring for this queue"); 6561 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6562 CTLFLAG_RD, &txq->ift_br->starts, 6563 "# of normal consumer starts in the mp_ring for this queue"); 6564 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6565 CTLFLAG_RD, &txq->ift_br->stalls, 6566 "# of consumer stalls in the mp_ring for this queue"); 6567 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6568 CTLFLAG_RD, &txq->ift_br->restarts, 6569 "# of consumer restarts in the mp_ring for this queue"); 6570 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6571 CTLFLAG_RD, &txq->ift_br->abdications, 6572 "# of consumer abdications in the mp_ring for this queue"); 6573 } 6574 6575 if (scctx->isc_nrxqsets > 100) 6576 qfmt = "rxq%03d"; 6577 else if (scctx->isc_nrxqsets > 10) 6578 qfmt = "rxq%02d"; 6579 else 6580 qfmt = "rxq%d"; 6581 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6582 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6583 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6584 CTLFLAG_RD, NULL, "Queue Name"); 6585 queue_list = SYSCTL_CHILDREN(queue_node); 6586 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6587 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6588 CTLFLAG_RD, 6589 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6590 } 6591 6592 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6593 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6594 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6595 CTLFLAG_RD, NULL, "freelist Name"); 6596 fl_list = SYSCTL_CHILDREN(fl_node); 6597 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6598 CTLFLAG_RD, 6599 &fl->ifl_pidx, 1, "Producer Index"); 6600 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6601 CTLFLAG_RD, 6602 &fl->ifl_cidx, 1, "Consumer Index"); 6603 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6604 CTLFLAG_RD, 6605 &fl->ifl_credits, 1, "credits available"); 6606 #if MEMORY_LOGGING 6607 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6608 CTLFLAG_RD, 6609 &fl->ifl_m_enqueued, "mbufs allocated"); 6610 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6611 CTLFLAG_RD, 6612 &fl->ifl_m_dequeued, "mbufs freed"); 6613 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6614 CTLFLAG_RD, 6615 &fl->ifl_cl_enqueued, "clusters allocated"); 6616 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6617 CTLFLAG_RD, 6618 &fl->ifl_cl_dequeued, "clusters freed"); 6619 #endif 6620 6621 } 6622 } 6623 6624 } 6625 6626 void 6627 iflib_request_reset(if_ctx_t ctx) 6628 { 6629 6630 STATE_LOCK(ctx); 6631 ctx->ifc_flags |= IFC_DO_RESET; 6632 STATE_UNLOCK(ctx); 6633 } 6634 6635 #ifndef __NO_STRICT_ALIGNMENT 6636 static struct mbuf * 6637 iflib_fixup_rx(struct mbuf *m) 6638 { 6639 struct mbuf *n; 6640 6641 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6642 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6643 m->m_data += ETHER_HDR_LEN; 6644 n = m; 6645 } else { 6646 MGETHDR(n, M_NOWAIT, MT_DATA); 6647 if (n == NULL) { 6648 m_freem(m); 6649 return (NULL); 6650 } 6651 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6652 m->m_data += ETHER_HDR_LEN; 6653 m->m_len -= ETHER_HDR_LEN; 6654 n->m_len = ETHER_HDR_LEN; 6655 M_MOVE_PKTHDR(n, m); 6656 n->m_next = m; 6657 } 6658 return (n); 6659 } 6660 #endif 6661 6662 #ifdef NETDUMP 6663 static void 6664 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6665 { 6666 if_ctx_t ctx; 6667 6668 ctx = if_getsoftc(ifp); 6669 CTX_LOCK(ctx); 6670 *nrxr = NRXQSETS(ctx); 6671 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6672 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6673 CTX_UNLOCK(ctx); 6674 } 6675 6676 static void 6677 iflib_netdump_event(if_t ifp, enum netdump_ev event) 6678 { 6679 if_ctx_t ctx; 6680 if_softc_ctx_t scctx; 6681 iflib_fl_t fl; 6682 iflib_rxq_t rxq; 6683 int i, j; 6684 6685 ctx = if_getsoftc(ifp); 6686 scctx = &ctx->ifc_softc_ctx; 6687 6688 switch (event) { 6689 case NETDUMP_START: 6690 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6691 rxq = &ctx->ifc_rxqs[i]; 6692 for (j = 0; j < rxq->ifr_nfl; j++) { 6693 fl = rxq->ifr_fl; 6694 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6695 } 6696 } 6697 iflib_no_tx_batch = 1; 6698 break; 6699 default: 6700 break; 6701 } 6702 } 6703 6704 static int 6705 iflib_netdump_transmit(if_t ifp, struct mbuf *m) 6706 { 6707 if_ctx_t ctx; 6708 iflib_txq_t txq; 6709 int error; 6710 6711 ctx = if_getsoftc(ifp); 6712 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6713 IFF_DRV_RUNNING) 6714 return (EBUSY); 6715 6716 txq = &ctx->ifc_txqs[0]; 6717 error = iflib_encap(txq, &m); 6718 if (error == 0) 6719 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6720 return (error); 6721 } 6722 6723 static int 6724 iflib_netdump_poll(if_t ifp, int count) 6725 { 6726 if_ctx_t ctx; 6727 if_softc_ctx_t scctx; 6728 iflib_txq_t txq; 6729 int i; 6730 6731 ctx = if_getsoftc(ifp); 6732 scctx = &ctx->ifc_softc_ctx; 6733 6734 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6735 IFF_DRV_RUNNING) 6736 return (EBUSY); 6737 6738 txq = &ctx->ifc_txqs[0]; 6739 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6740 6741 for (i = 0; i < scctx->isc_nrxqsets; i++) 6742 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6743 return (0); 6744 } 6745 #endif /* NETDUMP */ 6746