1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 4 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the DesignWare series USB 2.0 OTG 31 * Controller. 32 */ 33 34 /* 35 * LIMITATION: Drivers must be bound to all OUT endpoints in the 36 * active configuration for this driver to work properly. Blocking any 37 * OUT endpoint will block all OUT endpoints including the control 38 * endpoint. Usually this is not a problem. 39 */ 40 41 /* 42 * NOTE: Writing to non-existing registers appears to cause an 43 * internal reset. 44 */ 45 46 #ifdef USB_GLOBAL_INCLUDE_FILE 47 #include USB_GLOBAL_INCLUDE_FILE 48 #else 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR dwc_otg_debug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #endif /* USB_GLOBAL_INCLUDE_FILE */ 85 86 #include <dev/usb/controller/dwc_otg.h> 87 #include <dev/usb/controller/dwc_otgreg.h> 88 89 #define DWC_OTG_BUS2SC(bus) \ 90 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 91 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 92 93 #define DWC_OTG_PC2UDEV(pc) \ 94 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 95 96 #define DWC_OTG_MSK_GINT_ENABLED \ 97 (GINTMSK_ENUMDONEMSK | \ 98 GINTMSK_USBRSTMSK | \ 99 GINTMSK_USBSUSPMSK | \ 100 GINTMSK_IEPINTMSK | \ 101 GINTMSK_SESSREQINTMSK | \ 102 GINTMSK_RXFLVLMSK | \ 103 GINTMSK_HCHINTMSK | \ 104 GINTMSK_OTGINTMSK | \ 105 GINTMSK_PRTINTMSK) 106 107 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 108 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 109 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 110 GINTSTS_SESSREQINT) 111 112 #define DWC_OTG_PHY_ULPI 0 113 #define DWC_OTG_PHY_HSIC 1 114 #define DWC_OTG_PHY_INTERNAL 2 115 116 #ifndef DWC_OTG_PHY_DEFAULT 117 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 118 #endif 119 120 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 121 122 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 123 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 124 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 125 126 #ifdef USB_DEBUG 127 static int dwc_otg_debug; 128 129 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 130 &dwc_otg_debug, 0, "DWC OTG debug level"); 131 #endif 132 133 #define DWC_OTG_INTR_ENDPT 1 134 135 /* prototypes */ 136 137 static const struct usb_bus_methods dwc_otg_bus_methods; 138 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 139 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 140 141 static dwc_otg_cmd_t dwc_otg_setup_rx; 142 static dwc_otg_cmd_t dwc_otg_data_rx; 143 static dwc_otg_cmd_t dwc_otg_data_tx; 144 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 145 146 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 147 static dwc_otg_cmd_t dwc_otg_host_data_tx; 148 static dwc_otg_cmd_t dwc_otg_host_data_rx; 149 150 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 151 static void dwc_otg_do_poll(struct usb_bus *); 152 static void dwc_otg_standard_done(struct usb_xfer *); 153 static void dwc_otg_root_intr(struct dwc_otg_softc *); 154 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 155 156 /* 157 * Here is a configuration that the chip supports. 158 */ 159 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 160 161 [0] = { 162 .max_in_frame_size = 64,/* fixed */ 163 .max_out_frame_size = 64, /* fixed */ 164 .is_simplex = 1, 165 .support_control = 1, 166 } 167 }; 168 169 static void 170 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 171 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 172 { 173 struct dwc_otg_softc *sc; 174 175 sc = DWC_OTG_BUS2SC(udev->bus); 176 177 if (ep_addr < sc->sc_dev_ep_max) 178 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 179 else 180 *ppf = NULL; 181 } 182 183 static void 184 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 185 { 186 uint32_t temp; 187 188 /* reset FIFO */ 189 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 190 191 /* wait for reset to complete */ 192 for (temp = 0; temp != 16; temp++) { 193 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 194 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 195 break; 196 } 197 } 198 199 static int 200 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 201 { 202 struct dwc_otg_profile *pf; 203 uint32_t fifo_size; 204 uint32_t fifo_regs; 205 uint32_t tx_start; 206 uint8_t x; 207 208 fifo_size = sc->sc_fifo_size; 209 210 /* 211 * NOTE: Reserved fixed size area at end of RAM, which must 212 * not be allocated to the FIFOs: 213 */ 214 fifo_regs = 4 * 16; 215 216 if (fifo_size < fifo_regs) { 217 DPRINTF("Too little FIFO\n"); 218 return (EINVAL); 219 } 220 221 /* subtract FIFO regs from total once */ 222 fifo_size -= fifo_regs; 223 224 /* split equally for IN and OUT */ 225 fifo_size /= 2; 226 227 /* Align to 4 bytes boundary (refer to PGM) */ 228 fifo_size &= ~3; 229 230 /* set global receive FIFO size */ 231 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 232 233 tx_start = fifo_size; 234 235 if (fifo_size < 64) { 236 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 237 return (EINVAL); 238 } 239 240 if (mode == DWC_MODE_HOST) { 241 242 /* reset active endpoints */ 243 sc->sc_active_rx_ep = 0; 244 245 /* split equally for periodic and non-periodic */ 246 fifo_size /= 2; 247 248 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 249 250 /* align to 4 bytes boundary */ 251 fifo_size &= ~3; 252 253 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 254 ((fifo_size / 4) << 16) | 255 (tx_start / 4)); 256 257 tx_start += fifo_size; 258 259 for (x = 0; x != sc->sc_host_ch_max; x++) { 260 /* enable all host interrupts */ 261 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 262 HCINT_DEFAULT_MASK); 263 } 264 265 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 266 ((fifo_size / 4) << 16) | 267 (tx_start / 4)); 268 269 /* reset host channel state */ 270 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 271 272 /* enable all host channel interrupts */ 273 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 274 (1U << sc->sc_host_ch_max) - 1U); 275 } 276 277 if (mode == DWC_MODE_DEVICE) { 278 279 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 280 (0x10 << 16) | (tx_start / 4)); 281 fifo_size -= 0x40; 282 tx_start += 0x40; 283 284 /* setup control endpoint profile */ 285 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 286 287 /* reset active endpoints */ 288 sc->sc_active_rx_ep = 1; 289 290 for (x = 1; x != sc->sc_dev_ep_max; x++) { 291 292 pf = sc->sc_hw_ep_profile + x; 293 294 pf->usb.max_out_frame_size = 1024 * 3; 295 pf->usb.is_simplex = 0; /* assume duplex */ 296 pf->usb.support_bulk = 1; 297 pf->usb.support_interrupt = 1; 298 pf->usb.support_isochronous = 1; 299 pf->usb.support_out = 1; 300 301 if (x < sc->sc_dev_in_ep_max) { 302 uint32_t limit; 303 304 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 305 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 306 DWC_OTG_TX_MAX_FIFO_SIZE); 307 308 /* see if there is enough FIFO space */ 309 if (limit <= fifo_size) { 310 pf->max_buffer = limit; 311 pf->usb.support_in = 1; 312 } else { 313 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 314 if (limit <= fifo_size) { 315 pf->usb.support_in = 1; 316 } else { 317 pf->usb.is_simplex = 1; 318 limit = 0; 319 } 320 } 321 /* set FIFO size */ 322 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 323 ((limit / 4) << 16) | (tx_start / 4)); 324 tx_start += limit; 325 fifo_size -= limit; 326 pf->usb.max_in_frame_size = limit; 327 } else { 328 pf->usb.is_simplex = 1; 329 } 330 331 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 332 pf->usb.max_in_frame_size, 333 pf->usb.max_out_frame_size); 334 } 335 } 336 337 /* reset RX FIFO */ 338 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 339 340 if (mode != DWC_MODE_OTG) { 341 /* reset all TX FIFOs */ 342 dwc_otg_tx_fifo_reset(sc, 343 GRSTCTL_TXFIFO(0x10) | 344 GRSTCTL_TXFFLSH); 345 } else { 346 /* reset active endpoints */ 347 sc->sc_active_rx_ep = 0; 348 349 /* reset host channel state */ 350 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 351 } 352 return (0); 353 } 354 355 static void 356 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 357 { 358 359 /* 360 * Disabled until further. Assuming that the register is already 361 * programmed correctly by the boot loader. 362 */ 363 #if 0 364 uint32_t temp; 365 366 /* setup HOST frame interval register, based on existing value */ 367 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 368 if (temp >= 10000) 369 temp /= 1000; 370 else 371 temp /= 125; 372 373 /* figure out nearest X-tal value */ 374 if (temp >= 54) 375 temp = 60; /* MHz */ 376 else if (temp >= 39) 377 temp = 48; /* MHz */ 378 else 379 temp = 30; /* MHz */ 380 381 if (sc->sc_flags.status_high_speed) 382 temp *= 125; 383 else 384 temp *= 1000; 385 386 DPRINTF("HFIR=0x%08x\n", temp); 387 388 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 389 #endif 390 } 391 392 static void 393 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 394 { 395 if (sc->sc_flags.clocks_off && 396 sc->sc_flags.port_powered) { 397 398 DPRINTFN(5, "\n"); 399 400 /* TODO - platform specific */ 401 402 sc->sc_flags.clocks_off = 0; 403 } 404 } 405 406 static void 407 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 408 { 409 if (!sc->sc_flags.clocks_off) { 410 411 DPRINTFN(5, "\n"); 412 413 /* TODO - platform specific */ 414 415 sc->sc_flags.clocks_off = 1; 416 } 417 } 418 419 static void 420 dwc_otg_pull_up(struct dwc_otg_softc *sc) 421 { 422 uint32_t temp; 423 424 /* pullup D+, if possible */ 425 426 if (!sc->sc_flags.d_pulled_up && 427 sc->sc_flags.port_powered) { 428 sc->sc_flags.d_pulled_up = 1; 429 430 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 431 temp &= ~DCTL_SFTDISCON; 432 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 433 } 434 } 435 436 static void 437 dwc_otg_pull_down(struct dwc_otg_softc *sc) 438 { 439 uint32_t temp; 440 441 /* pulldown D+, if possible */ 442 443 if (sc->sc_flags.d_pulled_up) { 444 sc->sc_flags.d_pulled_up = 0; 445 446 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 447 temp |= DCTL_SFTDISCON; 448 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 449 } 450 } 451 452 static void 453 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 454 { 455 /* In device mode we don't use the SOF interrupt */ 456 if (sc->sc_flags.status_device_mode != 0 || 457 (sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 458 return; 459 sc->sc_irq_mask |= GINTMSK_SOFMSK; 460 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 461 } 462 463 static void 464 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 465 { 466 if (sc->sc_flags.status_suspend) { 467 /* update status bits */ 468 sc->sc_flags.status_suspend = 0; 469 sc->sc_flags.change_suspend = 1; 470 471 if (sc->sc_flags.status_device_mode) { 472 /* 473 * Disable resume interrupt and enable suspend 474 * interrupt: 475 */ 476 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 477 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 478 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 479 } 480 481 /* complete root HUB interrupt endpoint */ 482 dwc_otg_root_intr(sc); 483 } 484 } 485 486 static void 487 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 488 { 489 if (!sc->sc_flags.status_suspend) { 490 /* update status bits */ 491 sc->sc_flags.status_suspend = 1; 492 sc->sc_flags.change_suspend = 1; 493 494 if (sc->sc_flags.status_device_mode) { 495 /* 496 * Disable suspend interrupt and enable resume 497 * interrupt: 498 */ 499 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 500 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 501 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 502 } 503 504 /* complete root HUB interrupt endpoint */ 505 dwc_otg_root_intr(sc); 506 } 507 } 508 509 static void 510 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 511 { 512 if (!sc->sc_flags.status_suspend) 513 return; 514 515 DPRINTFN(5, "Remote wakeup\n"); 516 517 if (sc->sc_flags.status_device_mode) { 518 uint32_t temp; 519 520 /* enable remote wakeup signalling */ 521 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 522 temp |= DCTL_RMTWKUPSIG; 523 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 524 525 /* Wait 8ms for remote wakeup to complete. */ 526 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 527 528 temp &= ~DCTL_RMTWKUPSIG; 529 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 530 } else { 531 /* enable USB port */ 532 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 533 534 /* wait 10ms */ 535 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 536 537 /* resume port */ 538 sc->sc_hprt_val |= HPRT_PRTRES; 539 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 540 541 /* Wait 100ms for resume signalling to complete. */ 542 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 543 544 /* clear suspend and resume */ 545 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 546 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 547 548 /* Wait 4ms */ 549 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 550 } 551 552 /* need to fake resume IRQ */ 553 dwc_otg_resume_irq(sc); 554 } 555 556 static void 557 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 558 { 559 uint32_t temp; 560 561 DPRINTFN(5, "addr=%d\n", addr); 562 563 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 564 temp &= ~DCFG_DEVADDR_SET(0x7F); 565 temp |= DCFG_DEVADDR_SET(addr); 566 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 567 } 568 569 static void 570 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 571 { 572 DPRINTFN(5, "RX status clear\n"); 573 574 /* enable RX FIFO level interrupt */ 575 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 576 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 577 578 /* clear cached status */ 579 sc->sc_last_rx_status = 0; 580 } 581 582 static void 583 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 584 { 585 uint32_t hcint; 586 587 /* clear all pending interrupts */ 588 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 589 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 590 591 /* clear buffered interrupts */ 592 sc->sc_chan_state[x].hcint = 0; 593 } 594 595 static uint8_t 596 dwc_otg_host_check_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 597 { 598 uint32_t temp; 599 600 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 601 602 if (td->ep_type == UE_INTERRUPT || 603 td->ep_type == UE_ISOCHRONOUS) { 604 if (!(temp & GINTSTS_PTXFEMP)) { 605 DPRINTF("Periodic TX FIFO is not empty\n"); 606 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 607 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 608 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 609 } 610 return (1); /* busy */ 611 } 612 } else { 613 if (!(temp & GINTSTS_NPTXFEMP)) { 614 DPRINTF("Non-periodic TX FIFO is not empty\n"); 615 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 616 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 617 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 618 } 619 return (1); /* busy */ 620 } 621 } 622 return (0); /* ready for transmit */ 623 } 624 625 static uint8_t 626 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 627 struct dwc_otg_td *td, uint8_t is_out) 628 { 629 uint8_t x; 630 631 if (td->channel < DWC_OTG_MAX_CHANNELS) 632 return (0); /* already allocated */ 633 634 /* check if device is suspended */ 635 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 636 return (1); /* busy - cannot transfer data */ 637 638 /* compute needed TX FIFO size */ 639 if (is_out != 0) { 640 if (dwc_otg_host_check_fifo_empty(sc, td) != 0) 641 return (1); /* busy - cannot transfer data */ 642 } 643 644 for (x = 0; x != sc->sc_host_ch_max; x++) { 645 /* check if channel is allocated */ 646 if (sc->sc_chan_state[x].allocated != 0) 647 continue; 648 /* check if channel is still enabled */ 649 if (sc->sc_chan_state[x].wait_halted != 0) 650 continue; 651 652 sc->sc_chan_state[x].allocated = 1; 653 654 /* clear interrupts */ 655 dwc_otg_clear_hcint(sc, x); 656 657 DPRINTF("CH=%d HCCHAR=0x%08x " 658 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 659 660 /* set active channel */ 661 sc->sc_active_rx_ep |= (1 << x); 662 663 /* set channel */ 664 td->channel = x; 665 666 return (0); /* allocated */ 667 } 668 /* wait a bit */ 669 dwc_otg_enable_sof_irq(sc); 670 return (1); /* busy */ 671 } 672 673 static void 674 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 675 { 676 uint32_t hcchar; 677 uint8_t x; 678 679 if (td->channel >= DWC_OTG_MAX_CHANNELS) 680 return; /* already freed */ 681 682 /* free channel */ 683 x = td->channel; 684 td->channel = DWC_OTG_MAX_CHANNELS; 685 686 DPRINTF("CH=%d\n", x); 687 688 /* 689 * We need to let programmed host channels run till complete 690 * else the host channel will stop functioning. 691 */ 692 sc->sc_chan_state[x].allocated = 0; 693 694 /* ack any pending messages */ 695 if (sc->sc_last_rx_status != 0 && 696 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 697 dwc_otg_common_rx_ack(sc); 698 } 699 700 /* clear active channel */ 701 sc->sc_active_rx_ep &= ~(1 << x); 702 703 /* disable host channel */ 704 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 705 if (hcchar & HCCHAR_CHENA) { 706 DPRINTF("Halting channel %d\n", x); 707 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 708 hcchar | HCCHAR_CHDIS); 709 sc->sc_chan_state[x].wait_halted = 1; 710 /* don't write HCCHAR until the channel is halted */ 711 } 712 } 713 714 static void 715 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 716 { 717 /* dump any pending messages */ 718 if (sc->sc_last_rx_status != 0) { 719 if (td->channel < DWC_OTG_MAX_CHANNELS && 720 td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) { 721 dwc_otg_common_rx_ack(sc); 722 } 723 } 724 } 725 726 static uint8_t 727 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 728 { 729 struct usb_device_request req __aligned(4); 730 uint32_t hcint; 731 uint32_t hcchar; 732 uint8_t delta; 733 734 dwc_otg_host_dump_rx(sc, td); 735 736 if (td->channel < DWC_OTG_MAX_CHANNELS) { 737 hcint = sc->sc_chan_state[td->channel].hcint; 738 739 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 740 td->channel, td->state, hcint, 741 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 742 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 743 } else { 744 hcint = 0; 745 goto check_state; 746 } 747 748 if (hcint & (HCINT_RETRY | 749 HCINT_ACK | HCINT_NYET)) { 750 /* give success bits priority over failure bits */ 751 } else if (hcint & HCINT_STALL) { 752 DPRINTF("CH=%d STALL\n", td->channel); 753 td->error_stall = 1; 754 td->error_any = 1; 755 goto complete; 756 } else if (hcint & HCINT_ERRORS) { 757 DPRINTF("CH=%d ERROR\n", td->channel); 758 td->errcnt++; 759 if (td->hcsplt != 0 || td->errcnt >= 3) { 760 td->error_any = 1; 761 goto complete; 762 } 763 } 764 765 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 766 HCINT_ACK | HCINT_NYET)) { 767 if (!(hcint & HCINT_ERRORS)) 768 td->errcnt = 0; 769 } 770 771 check_state: 772 switch (td->state) { 773 case DWC_CHAN_ST_START: 774 goto send_pkt; 775 776 case DWC_CHAN_ST_WAIT_ANE: 777 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 778 td->did_nak++; 779 td->tt_scheduled = 0; 780 goto send_pkt; 781 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 782 td->offset += td->tx_bytes; 783 td->remainder -= td->tx_bytes; 784 td->toggle = 1; 785 td->tt_scheduled = 0; 786 goto complete; 787 } 788 break; 789 790 case DWC_CHAN_ST_WAIT_S_ANE: 791 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 792 td->did_nak++; 793 td->tt_scheduled = 0; 794 goto send_pkt; 795 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 796 goto send_cpkt; 797 } 798 break; 799 800 case DWC_CHAN_ST_WAIT_C_ANE: 801 if (hcint & HCINT_NYET) { 802 goto send_cpkt; 803 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 804 td->did_nak++; 805 td->tt_scheduled = 0; 806 goto send_pkt; 807 } else if (hcint & HCINT_ACK) { 808 td->offset += td->tx_bytes; 809 td->remainder -= td->tx_bytes; 810 td->toggle = 1; 811 goto complete; 812 } 813 break; 814 815 case DWC_CHAN_ST_WAIT_C_PKT: 816 goto send_cpkt; 817 818 default: 819 break; 820 } 821 goto busy; 822 823 send_pkt: 824 /* free existing channel, if any */ 825 dwc_otg_host_channel_free(sc, td); 826 827 if (sizeof(req) != td->remainder) { 828 td->error_any = 1; 829 goto complete; 830 } 831 832 if (td->hcsplt != 0) { 833 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 834 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 835 td->state = DWC_CHAN_ST_START; 836 goto busy; 837 } 838 delta = sc->sc_last_frame_num - td->tt_start_slot; 839 if (delta > 5) { 840 /* missed it */ 841 td->tt_scheduled = 0; 842 td->state = DWC_CHAN_ST_START; 843 goto busy; 844 } 845 } 846 847 /* allocate a new channel */ 848 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 849 td->state = DWC_CHAN_ST_START; 850 goto busy; 851 } 852 853 if (td->hcsplt != 0) { 854 td->hcsplt &= ~HCSPLT_COMPSPLT; 855 td->state = DWC_CHAN_ST_WAIT_S_ANE; 856 } else { 857 td->state = DWC_CHAN_ST_WAIT_ANE; 858 } 859 860 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 861 862 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 863 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 864 (1 << HCTSIZ_PKTCNT_SHIFT) | 865 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 866 867 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 868 869 hcchar = td->hcchar; 870 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 871 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 872 873 /* must enable channel before writing data to FIFO */ 874 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 875 876 /* transfer data into FIFO */ 877 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 878 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 879 880 /* wait until next slot before trying complete split */ 881 td->tt_complete_slot = sc->sc_last_frame_num + 1; 882 883 /* store number of bytes transmitted */ 884 td->tx_bytes = sizeof(req); 885 goto busy; 886 887 send_cpkt: 888 /* free existing channel, if any */ 889 dwc_otg_host_channel_free(sc, td); 890 891 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 892 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 893 td->state = DWC_CHAN_ST_WAIT_C_PKT; 894 goto busy; 895 } 896 delta = sc->sc_last_frame_num - td->tt_start_slot; 897 if (delta > DWC_OTG_TT_SLOT_MAX) { 898 /* we missed the service interval */ 899 if (td->ep_type != UE_ISOCHRONOUS) 900 td->error_any = 1; 901 goto complete; 902 } 903 /* allocate a new channel */ 904 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 905 td->state = DWC_CHAN_ST_WAIT_C_PKT; 906 goto busy; 907 } 908 909 /* wait until next slot before trying complete split */ 910 td->tt_complete_slot = sc->sc_last_frame_num + 1; 911 912 td->hcsplt |= HCSPLT_COMPSPLT; 913 td->state = DWC_CHAN_ST_WAIT_C_ANE; 914 915 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 916 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 917 918 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 919 920 hcchar = td->hcchar; 921 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 922 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 923 924 /* must enable channel before writing data to FIFO */ 925 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 926 927 busy: 928 return (1); /* busy */ 929 930 complete: 931 dwc_otg_host_channel_free(sc, td); 932 return (0); /* complete */ 933 } 934 935 static uint8_t 936 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 937 { 938 struct usb_device_request req __aligned(4); 939 uint32_t temp; 940 uint16_t count; 941 942 /* check endpoint status */ 943 944 if (sc->sc_last_rx_status == 0) 945 goto not_complete; 946 947 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 948 goto not_complete; 949 950 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 951 GRXSTSRD_STP_DATA) { 952 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 953 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 954 /* release FIFO */ 955 dwc_otg_common_rx_ack(sc); 956 goto not_complete; 957 } 958 /* release FIFO */ 959 dwc_otg_common_rx_ack(sc); 960 return (0); /* complete */ 961 } 962 963 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 964 GRXSTSRD_DPID_DATA0) { 965 /* release FIFO */ 966 dwc_otg_common_rx_ack(sc); 967 goto not_complete; 968 } 969 970 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 971 972 /* clear did stall */ 973 td->did_stall = 0; 974 975 /* get the packet byte count */ 976 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 977 978 if (count != sizeof(req)) { 979 DPRINTFN(0, "Unsupported SETUP packet " 980 "length, %d bytes\n", count); 981 /* release FIFO */ 982 dwc_otg_common_rx_ack(sc); 983 goto not_complete; 984 } 985 986 /* copy in control request */ 987 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 988 989 /* copy data into real buffer */ 990 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 991 992 td->offset = sizeof(req); 993 td->remainder = 0; 994 995 /* sneak peek the set address */ 996 if ((req.bmRequestType == UT_WRITE_DEVICE) && 997 (req.bRequest == UR_SET_ADDRESS)) { 998 /* must write address before ZLP */ 999 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1000 } 1001 1002 /* don't send any data by default */ 1003 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1004 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1005 1006 /* reset IN endpoint buffer */ 1007 dwc_otg_tx_fifo_reset(sc, 1008 GRSTCTL_TXFIFO(0) | 1009 GRSTCTL_TXFFLSH); 1010 1011 /* acknowledge RX status */ 1012 dwc_otg_common_rx_ack(sc); 1013 td->did_stall = 1; 1014 1015 not_complete: 1016 /* abort any ongoing transfer, before enabling again */ 1017 if (!td->did_stall) { 1018 td->did_stall = 1; 1019 1020 DPRINTFN(5, "stalling IN and OUT direction\n"); 1021 1022 temp = sc->sc_out_ctl[0]; 1023 1024 /* set stall after enabling endpoint */ 1025 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1026 temp | DOEPCTL_STALL); 1027 1028 temp = sc->sc_in_ctl[0]; 1029 1030 /* set stall assuming endpoint is enabled */ 1031 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1032 temp | DIEPCTL_STALL); 1033 } 1034 return (1); /* not complete */ 1035 } 1036 1037 static uint8_t 1038 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1039 { 1040 uint8_t delta; 1041 1042 delta = sc->sc_tmr_val - td->tmr_val; 1043 if (delta >= 128) 1044 return (1); /* busy */ 1045 1046 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1047 1048 /* set toggle, if any */ 1049 if (td->set_toggle) { 1050 td->set_toggle = 0; 1051 td->toggle = 1; 1052 } 1053 return (0); 1054 } 1055 1056 static uint8_t 1057 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1058 { 1059 if (td->ep_type == UE_ISOCHRONOUS) { 1060 /* non TT isochronous traffic */ 1061 if ((td->tmr_val != 0) || 1062 (sc->sc_last_frame_num & (td->tmr_res - 1))) { 1063 goto busy; 1064 } 1065 td->tmr_val = 1; /* executed */ 1066 td->toggle = 0; 1067 1068 } else if (td->ep_type == UE_INTERRUPT) { 1069 if (!td->tt_scheduled) 1070 goto busy; 1071 td->tt_scheduled = 0; 1072 } else if (td->did_nak >= DWC_OTG_NAK_MAX) { 1073 goto busy; 1074 } else if (td->set_toggle) { 1075 td->set_toggle = 0; 1076 td->toggle = 1; 1077 } 1078 return (0); 1079 busy: 1080 return (1); 1081 } 1082 1083 static uint8_t 1084 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1085 { 1086 uint32_t count; 1087 uint8_t channel; 1088 1089 /* check endpoint status */ 1090 if (sc->sc_last_rx_status == 0) 1091 goto busy; 1092 1093 channel = td->channel; 1094 if (channel >= DWC_OTG_MAX_CHANNELS) 1095 goto busy; 1096 1097 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1098 goto busy; 1099 1100 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1101 case GRXSTSRH_IN_DATA: 1102 1103 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1104 (int)td->state, (int)sc->sc_last_rx_status); 1105 1106 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1107 /* 1108 * When using SPLIT transactions on interrupt 1109 * endpoints, sometimes data occurs twice. 1110 */ 1111 DPRINTF("Data already received\n"); 1112 break; 1113 } 1114 1115 /* get the packet byte count */ 1116 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1117 1118 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1119 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1120 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1121 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1122 } else { 1123 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1124 1125 /* verify the packet byte count */ 1126 if (count < td->max_packet_size) { 1127 /* we have a short packet */ 1128 td->short_pkt = 1; 1129 td->got_short = 1; 1130 } 1131 } 1132 td->toggle = 0; 1133 } else { 1134 /* verify the packet byte count */ 1135 if (count != td->max_packet_size) { 1136 if (count < td->max_packet_size) { 1137 /* we have a short packet */ 1138 td->short_pkt = 1; 1139 td->got_short = 1; 1140 } else { 1141 /* invalid USB packet */ 1142 td->error_any = 1; 1143 1144 /* release FIFO */ 1145 dwc_otg_common_rx_ack(sc); 1146 goto complete; 1147 } 1148 } 1149 td->toggle ^= 1; 1150 td->tt_scheduled = 0; 1151 } 1152 1153 /* verify the packet byte count */ 1154 if (count > td->remainder) { 1155 /* invalid USB packet */ 1156 td->error_any = 1; 1157 1158 /* release FIFO */ 1159 dwc_otg_common_rx_ack(sc); 1160 goto complete; 1161 } 1162 1163 usbd_copy_in(td->pc, td->offset, 1164 sc->sc_rx_bounce_buffer, count); 1165 1166 td->remainder -= count; 1167 td->offset += count; 1168 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1169 break; 1170 default: 1171 break; 1172 } 1173 /* release FIFO */ 1174 dwc_otg_common_rx_ack(sc); 1175 busy: 1176 return (0); 1177 complete: 1178 return (1); 1179 } 1180 1181 static uint8_t 1182 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1183 { 1184 uint32_t hcint; 1185 uint32_t hcchar; 1186 uint8_t delta; 1187 uint8_t channel; 1188 1189 channel = td->channel; 1190 1191 if (channel < DWC_OTG_MAX_CHANNELS) { 1192 hcint = sc->sc_chan_state[channel].hcint; 1193 1194 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1195 channel, td->state, hcint, 1196 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1197 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1198 1199 /* check interrupt bits */ 1200 if (hcint & (HCINT_RETRY | 1201 HCINT_ACK | HCINT_NYET)) { 1202 /* give success bits priority over failure bits */ 1203 } else if (hcint & HCINT_STALL) { 1204 DPRINTF("CH=%d STALL\n", channel); 1205 td->error_stall = 1; 1206 td->error_any = 1; 1207 goto complete; 1208 } else if (hcint & HCINT_ERRORS) { 1209 DPRINTF("CH=%d ERROR\n", channel); 1210 td->errcnt++; 1211 if (td->hcsplt != 0 || td->errcnt >= 3) { 1212 if (td->ep_type != UE_ISOCHRONOUS) { 1213 td->error_any = 1; 1214 goto complete; 1215 } 1216 } 1217 } 1218 1219 /* check channels for data, if any */ 1220 if (dwc_otg_host_data_rx_sub(sc, td)) 1221 goto complete; 1222 1223 /* refresh interrupt status */ 1224 hcint = sc->sc_chan_state[channel].hcint; 1225 1226 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1227 HCINT_ACK | HCINT_NYET)) { 1228 if (!(hcint & HCINT_ERRORS)) 1229 td->errcnt = 0; 1230 } 1231 } else { 1232 hcint = 0; 1233 } 1234 1235 switch (td->state) { 1236 case DWC_CHAN_ST_START: 1237 if (td->hcsplt != 0) 1238 goto receive_spkt; 1239 else 1240 goto receive_pkt; 1241 1242 case DWC_CHAN_ST_WAIT_ANE: 1243 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1244 if (td->ep_type == UE_INTERRUPT) { 1245 /* 1246 * The USB specification does not 1247 * mandate a particular data toggle 1248 * value for USB INTERRUPT 1249 * transfers. Switch the data toggle 1250 * value to receive the packet 1251 * correctly: 1252 */ 1253 if (hcint & HCINT_DATATGLERR) { 1254 DPRINTF("Retrying packet due to " 1255 "data toggle error\n"); 1256 td->toggle ^= 1; 1257 goto receive_pkt; 1258 } 1259 } 1260 td->did_nak++; 1261 td->tt_scheduled = 0; 1262 if (td->hcsplt != 0) 1263 goto receive_spkt; 1264 else 1265 goto receive_pkt; 1266 } else if (hcint & HCINT_NYET) { 1267 if (td->hcsplt != 0) { 1268 /* try again */ 1269 goto receive_pkt; 1270 } else { 1271 /* not a valid token for IN endpoints */ 1272 td->error_any = 1; 1273 goto complete; 1274 } 1275 } else if (hcint & HCINT_ACK) { 1276 /* wait for data - ACK arrived first */ 1277 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1278 goto busy; 1279 1280 if (td->ep_type == UE_ISOCHRONOUS) { 1281 /* check if we are complete */ 1282 if ((td->remainder == 0) || 1283 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { 1284 goto complete; 1285 } 1286 /* get another packet */ 1287 goto receive_pkt; 1288 } else { 1289 /* check if we are complete */ 1290 if ((td->remainder == 0) || (td->got_short != 0)) { 1291 if (td->short_pkt) 1292 goto complete; 1293 1294 /* 1295 * Else need to receive a zero length 1296 * packet. 1297 */ 1298 } 1299 td->tt_scheduled = 0; 1300 td->did_nak = 0; 1301 if (td->hcsplt != 0) 1302 goto receive_spkt; 1303 else 1304 goto receive_pkt; 1305 } 1306 } 1307 break; 1308 1309 case DWC_CHAN_ST_WAIT_S_ANE: 1310 /* 1311 * NOTE: The DWC OTG hardware provides a fake ACK in 1312 * case of interrupt and isochronous transfers: 1313 */ 1314 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1315 td->did_nak++; 1316 td->tt_scheduled = 0; 1317 goto receive_spkt; 1318 } else if (hcint & HCINT_NYET) { 1319 td->tt_scheduled = 0; 1320 goto receive_spkt; 1321 } else if (hcint & HCINT_ACK) { 1322 td->did_nak = 0; 1323 goto receive_pkt; 1324 } 1325 break; 1326 1327 case DWC_CHAN_ST_WAIT_C_PKT: 1328 goto receive_pkt; 1329 1330 default: 1331 break; 1332 } 1333 goto busy; 1334 1335 receive_pkt: 1336 /* free existing channel, if any */ 1337 dwc_otg_host_channel_free(sc, td); 1338 1339 if (td->hcsplt != 0) { 1340 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1341 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1342 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1343 goto busy; 1344 } 1345 delta = sc->sc_last_frame_num - td->tt_start_slot; 1346 if (delta > DWC_OTG_TT_SLOT_MAX) { 1347 if (td->ep_type != UE_ISOCHRONOUS) { 1348 /* we missed the service interval */ 1349 td->error_any = 1; 1350 } 1351 goto complete; 1352 } 1353 /* complete split */ 1354 td->hcsplt |= HCSPLT_COMPSPLT; 1355 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1356 dwc_otg_host_rate_check(sc, td)) { 1357 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1358 goto busy; 1359 } 1360 1361 /* allocate a new channel */ 1362 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1363 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1364 goto busy; 1365 } 1366 1367 channel = td->channel; 1368 1369 /* set toggle, if any */ 1370 if (td->set_toggle) { 1371 td->set_toggle = 0; 1372 td->toggle = 1; 1373 } 1374 1375 td->state = DWC_CHAN_ST_WAIT_ANE; 1376 1377 /* receive one packet */ 1378 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1379 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1380 (1 << HCTSIZ_PKTCNT_SHIFT) | 1381 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1382 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1383 1384 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1385 1386 hcchar = td->hcchar; 1387 hcchar |= HCCHAR_EPDIR_IN; 1388 1389 /* receive complete split ASAP */ 1390 if ((sc->sc_last_frame_num & 1) != 0 && 1391 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1392 hcchar |= HCCHAR_ODDFRM; 1393 else 1394 hcchar &= ~HCCHAR_ODDFRM; 1395 1396 /* must enable channel before data can be received */ 1397 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1398 1399 /* wait until next slot before trying complete split */ 1400 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1401 1402 goto busy; 1403 1404 receive_spkt: 1405 /* free existing channel(s), if any */ 1406 dwc_otg_host_channel_free(sc, td); 1407 1408 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1409 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1410 td->state = DWC_CHAN_ST_START; 1411 goto busy; 1412 } 1413 delta = sc->sc_last_frame_num - td->tt_start_slot; 1414 if (delta > 5) { 1415 /* missed it */ 1416 td->tt_scheduled = 0; 1417 td->state = DWC_CHAN_ST_START; 1418 goto busy; 1419 } 1420 1421 /* allocate a new channel */ 1422 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1423 td->state = DWC_CHAN_ST_START; 1424 goto busy; 1425 } 1426 1427 channel = td->channel; 1428 1429 td->hcsplt &= ~HCSPLT_COMPSPLT; 1430 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1431 1432 /* receive one packet */ 1433 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1434 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1435 1436 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1437 1438 /* send after next SOF event */ 1439 if ((sc->sc_last_frame_num & 1) == 0 && 1440 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1441 td->hcchar |= HCCHAR_ODDFRM; 1442 else 1443 td->hcchar &= ~HCCHAR_ODDFRM; 1444 1445 hcchar = td->hcchar; 1446 hcchar |= HCCHAR_EPDIR_IN; 1447 1448 /* wait until next slot before trying complete split */ 1449 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1450 1451 /* must enable channel before data can be received */ 1452 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1453 busy: 1454 return (1); /* busy */ 1455 1456 complete: 1457 dwc_otg_host_channel_free(sc, td); 1458 return (0); /* complete */ 1459 } 1460 1461 static uint8_t 1462 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1463 { 1464 uint32_t temp; 1465 uint16_t count; 1466 uint8_t got_short; 1467 1468 got_short = 0; 1469 1470 /* check endpoint status */ 1471 if (sc->sc_last_rx_status == 0) 1472 goto not_complete; 1473 1474 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1475 goto not_complete; 1476 1477 /* check for SETUP packet */ 1478 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1479 GRXSTSRD_STP_DATA || 1480 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1481 GRXSTSRD_STP_COMPLETE) { 1482 if (td->remainder == 0) { 1483 /* 1484 * We are actually complete and have 1485 * received the next SETUP 1486 */ 1487 DPRINTFN(5, "faking complete\n"); 1488 return (0); /* complete */ 1489 } 1490 /* 1491 * USB Host Aborted the transfer. 1492 */ 1493 td->error_any = 1; 1494 return (0); /* complete */ 1495 } 1496 1497 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1498 GRXSTSRD_OUT_DATA) { 1499 /* release FIFO */ 1500 dwc_otg_common_rx_ack(sc); 1501 goto not_complete; 1502 } 1503 1504 /* get the packet byte count */ 1505 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1506 1507 /* verify the packet byte count */ 1508 if (count != td->max_packet_size) { 1509 if (count < td->max_packet_size) { 1510 /* we have a short packet */ 1511 td->short_pkt = 1; 1512 got_short = 1; 1513 } else { 1514 /* invalid USB packet */ 1515 td->error_any = 1; 1516 1517 /* release FIFO */ 1518 dwc_otg_common_rx_ack(sc); 1519 return (0); /* we are complete */ 1520 } 1521 } 1522 /* verify the packet byte count */ 1523 if (count > td->remainder) { 1524 /* invalid USB packet */ 1525 td->error_any = 1; 1526 1527 /* release FIFO */ 1528 dwc_otg_common_rx_ack(sc); 1529 return (0); /* we are complete */ 1530 } 1531 1532 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1533 td->remainder -= count; 1534 td->offset += count; 1535 1536 /* release FIFO */ 1537 dwc_otg_common_rx_ack(sc); 1538 1539 temp = sc->sc_out_ctl[td->ep_no]; 1540 1541 /* check for isochronous mode */ 1542 if ((temp & DIEPCTL_EPTYPE_MASK) == 1543 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1544 /* toggle odd or even frame bit */ 1545 if (temp & DIEPCTL_SETD1PID) { 1546 temp &= ~DIEPCTL_SETD1PID; 1547 temp |= DIEPCTL_SETD0PID; 1548 } else { 1549 temp &= ~DIEPCTL_SETD0PID; 1550 temp |= DIEPCTL_SETD1PID; 1551 } 1552 sc->sc_out_ctl[td->ep_no] = temp; 1553 } 1554 1555 /* check if we are complete */ 1556 if ((td->remainder == 0) || got_short) { 1557 if (td->short_pkt) { 1558 /* we are complete */ 1559 return (0); 1560 } 1561 /* else need to receive a zero length packet */ 1562 } 1563 1564 not_complete: 1565 1566 /* enable SETUP and transfer complete interrupt */ 1567 if (td->ep_no == 0) { 1568 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1569 DXEPTSIZ_SET_MULTI(3) | 1570 DXEPTSIZ_SET_NPKT(1) | 1571 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1572 } else { 1573 /* allow reception of multiple packets */ 1574 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1575 DXEPTSIZ_SET_MULTI(1) | 1576 DXEPTSIZ_SET_NPKT(4) | 1577 DXEPTSIZ_SET_NBYTES(4 * 1578 ((td->max_packet_size + 3) & ~3))); 1579 } 1580 temp = sc->sc_out_ctl[td->ep_no]; 1581 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1582 DOEPCTL_EPENA | DOEPCTL_CNAK); 1583 1584 return (1); /* not complete */ 1585 } 1586 1587 static uint8_t 1588 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1589 { 1590 uint32_t count; 1591 uint32_t hcint; 1592 uint32_t hcchar; 1593 uint8_t delta; 1594 uint8_t channel; 1595 1596 dwc_otg_host_dump_rx(sc, td); 1597 1598 channel = td->channel; 1599 1600 if (channel < DWC_OTG_MAX_CHANNELS) { 1601 hcint = sc->sc_chan_state[channel].hcint; 1602 1603 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1604 channel, td->state, hcint, 1605 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1606 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1607 1608 if (hcint & (HCINT_RETRY | 1609 HCINT_ACK | HCINT_NYET)) { 1610 /* give success bits priority over failure bits */ 1611 } else if (hcint & HCINT_STALL) { 1612 DPRINTF("CH=%d STALL\n", channel); 1613 td->error_stall = 1; 1614 td->error_any = 1; 1615 goto complete; 1616 } else if (hcint & HCINT_ERRORS) { 1617 DPRINTF("CH=%d ERROR\n", channel); 1618 td->errcnt++; 1619 if (td->hcsplt != 0 || td->errcnt >= 3) { 1620 td->error_any = 1; 1621 goto complete; 1622 } 1623 } 1624 1625 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1626 HCINT_ACK | HCINT_NYET)) { 1627 1628 if (!(hcint & HCINT_ERRORS)) 1629 td->errcnt = 0; 1630 } 1631 } else { 1632 hcint = 0; 1633 } 1634 1635 switch (td->state) { 1636 case DWC_CHAN_ST_START: 1637 goto send_pkt; 1638 1639 case DWC_CHAN_ST_WAIT_ANE: 1640 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1641 td->did_nak++; 1642 td->tt_scheduled = 0; 1643 goto send_pkt; 1644 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1645 td->offset += td->tx_bytes; 1646 td->remainder -= td->tx_bytes; 1647 td->toggle ^= 1; 1648 td->did_nak = 0; 1649 td->tt_scheduled = 0; 1650 1651 /* check remainder */ 1652 if (td->remainder == 0) { 1653 if (td->short_pkt) 1654 goto complete; 1655 1656 /* 1657 * Else we need to transmit a short 1658 * packet: 1659 */ 1660 } 1661 goto send_pkt; 1662 } 1663 break; 1664 1665 case DWC_CHAN_ST_WAIT_S_ANE: 1666 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1667 td->did_nak++; 1668 td->tt_scheduled = 0; 1669 goto send_pkt; 1670 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1671 td->did_nak = 0; 1672 goto send_cpkt; 1673 } 1674 break; 1675 1676 case DWC_CHAN_ST_WAIT_C_ANE: 1677 if (hcint & HCINT_NYET) { 1678 goto send_cpkt; 1679 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1680 td->did_nak++; 1681 td->tt_scheduled = 0; 1682 goto send_pkt; 1683 } else if (hcint & HCINT_ACK) { 1684 td->offset += td->tx_bytes; 1685 td->remainder -= td->tx_bytes; 1686 td->toggle ^= 1; 1687 td->did_nak = 0; 1688 td->tt_scheduled = 0; 1689 1690 /* check remainder */ 1691 if (td->remainder == 0) { 1692 if (td->short_pkt) 1693 goto complete; 1694 1695 /* else we need to transmit a short packet */ 1696 } 1697 goto send_pkt; 1698 } 1699 break; 1700 1701 case DWC_CHAN_ST_WAIT_C_PKT: 1702 goto send_cpkt; 1703 1704 case DWC_CHAN_ST_TX_WAIT_ISOC: 1705 1706 /* Check if isochronous OUT traffic is complete */ 1707 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1708 break; 1709 1710 td->offset += td->tx_bytes; 1711 td->remainder -= td->tx_bytes; 1712 1713 if (td->hcsplt != 0 || td->remainder == 0) 1714 goto complete; 1715 1716 /* check for next packet */ 1717 if (td->max_packet_count > 1) 1718 td->tt_xactpos++; 1719 1720 /* free existing channel, if any */ 1721 dwc_otg_host_channel_free(sc, td); 1722 1723 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1724 1725 /* FALLTHROUGH */ 1726 1727 case DWC_CHAN_ST_TX_PKT_ISOC: 1728 if (dwc_otg_host_channel_alloc(sc, td, 1)) 1729 break; 1730 channel = td->channel; 1731 goto send_isoc_pkt; 1732 default: 1733 break; 1734 } 1735 goto busy; 1736 1737 send_pkt: 1738 /* free existing channel(s), if any */ 1739 dwc_otg_host_channel_free(sc, td); 1740 1741 if (td->hcsplt != 0) { 1742 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1743 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1744 td->state = DWC_CHAN_ST_START; 1745 goto busy; 1746 } 1747 delta = sc->sc_last_frame_num - td->tt_start_slot; 1748 if (delta > 5) { 1749 /* missed it */ 1750 td->tt_scheduled = 0; 1751 td->state = DWC_CHAN_ST_START; 1752 goto busy; 1753 } 1754 } else if (dwc_otg_host_rate_check(sc, td)) { 1755 td->state = DWC_CHAN_ST_START; 1756 goto busy; 1757 } 1758 1759 /* allocate a new channel */ 1760 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1761 td->state = DWC_CHAN_ST_START; 1762 goto busy; 1763 } 1764 1765 channel = td->channel; 1766 1767 /* set toggle, if any */ 1768 if (td->set_toggle) { 1769 td->set_toggle = 0; 1770 td->toggle = 1; 1771 } 1772 1773 if (td->ep_type == UE_ISOCHRONOUS) { 1774 send_isoc_pkt: 1775 /* Isochronous OUT transfers don't have any ACKs */ 1776 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1777 td->hcsplt &= ~HCSPLT_COMPSPLT; 1778 if (td->hcsplt != 0) { 1779 /* get maximum transfer length */ 1780 count = td->remainder; 1781 if (count > HCSPLT_XACTLEN_BURST) { 1782 DPRINTF("TT overflow\n"); 1783 td->error_any = 1; 1784 goto complete; 1785 } 1786 /* Update transaction position */ 1787 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1788 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1789 } else { 1790 /* send one packet at a time */ 1791 count = td->max_packet_size; 1792 if (td->remainder < count) { 1793 /* we have a short packet */ 1794 td->short_pkt = 1; 1795 count = td->remainder; 1796 } 1797 } 1798 } else if (td->hcsplt != 0) { 1799 1800 td->hcsplt &= ~HCSPLT_COMPSPLT; 1801 1802 /* Wait for ACK/NAK/ERR from TT */ 1803 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1804 1805 /* send one packet at a time */ 1806 count = td->max_packet_size; 1807 if (td->remainder < count) { 1808 /* we have a short packet */ 1809 td->short_pkt = 1; 1810 count = td->remainder; 1811 } 1812 } else { 1813 /* Wait for ACK/NAK/STALL from device */ 1814 td->state = DWC_CHAN_ST_WAIT_ANE; 1815 1816 /* send one packet at a time */ 1817 count = td->max_packet_size; 1818 if (td->remainder < count) { 1819 /* we have a short packet */ 1820 td->short_pkt = 1; 1821 count = td->remainder; 1822 } 1823 } 1824 1825 /* check for High-Speed multi-packets */ 1826 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1827 if (td->npkt == 0) { 1828 if (td->remainder >= (3 * td->max_packet_size)) 1829 td->npkt = 3; 1830 else if (td->remainder >= (2 * td->max_packet_size)) 1831 td->npkt = 2; 1832 else 1833 td->npkt = 1; 1834 1835 if (td->npkt > td->max_packet_count) 1836 td->npkt = td->max_packet_count; 1837 1838 td->tt_xactpos = 1; /* overload */ 1839 } 1840 if (td->tt_xactpos == td->npkt) { 1841 if (td->npkt == 1) { 1842 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1843 (count << HCTSIZ_XFERSIZE_SHIFT) | 1844 (1 << HCTSIZ_PKTCNT_SHIFT) | 1845 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1846 } else if (td->npkt == 2) { 1847 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1848 (count << HCTSIZ_XFERSIZE_SHIFT) | 1849 (1 << HCTSIZ_PKTCNT_SHIFT) | 1850 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1851 } else { 1852 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1853 (count << HCTSIZ_XFERSIZE_SHIFT) | 1854 (1 << HCTSIZ_PKTCNT_SHIFT) | 1855 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1856 } 1857 td->npkt = 0; 1858 } else { 1859 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1860 (count << HCTSIZ_XFERSIZE_SHIFT) | 1861 (1 << HCTSIZ_PKTCNT_SHIFT) | 1862 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1863 } 1864 } else { 1865 /* TODO: HCTSIZ_DOPNG */ 1866 1867 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1868 (count << HCTSIZ_XFERSIZE_SHIFT) | 1869 (1 << HCTSIZ_PKTCNT_SHIFT) | 1870 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1871 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1872 } 1873 1874 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1875 1876 hcchar = td->hcchar; 1877 hcchar &= ~HCCHAR_EPDIR_IN; 1878 1879 /* send after next SOF event */ 1880 if ((sc->sc_last_frame_num & 1) == 0 && 1881 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1882 hcchar |= HCCHAR_ODDFRM; 1883 else 1884 hcchar &= ~HCCHAR_ODDFRM; 1885 1886 /* must enable before writing data to FIFO */ 1887 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1888 1889 if (count != 0) { 1890 1891 /* clear topmost word before copy */ 1892 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1893 1894 /* copy out data */ 1895 usbd_copy_out(td->pc, td->offset, 1896 sc->sc_tx_bounce_buffer, count); 1897 1898 /* transfer data into FIFO */ 1899 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1900 DOTG_DFIFO(channel), 1901 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1902 } 1903 1904 /* store number of bytes transmitted */ 1905 td->tx_bytes = count; 1906 goto busy; 1907 1908 send_cpkt: 1909 /* free existing channel, if any */ 1910 dwc_otg_host_channel_free(sc, td); 1911 1912 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1913 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1914 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1915 goto busy; 1916 } 1917 delta = sc->sc_last_frame_num - td->tt_start_slot; 1918 if (delta > DWC_OTG_TT_SLOT_MAX) { 1919 /* we missed the service interval */ 1920 if (td->ep_type != UE_ISOCHRONOUS) 1921 td->error_any = 1; 1922 goto complete; 1923 } 1924 1925 /* allocate a new channel */ 1926 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1927 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1928 goto busy; 1929 } 1930 1931 channel = td->channel; 1932 1933 td->hcsplt |= HCSPLT_COMPSPLT; 1934 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1935 1936 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1937 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1938 1939 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1940 1941 hcchar = td->hcchar; 1942 hcchar &= ~HCCHAR_EPDIR_IN; 1943 1944 /* receive complete split ASAP */ 1945 if ((sc->sc_last_frame_num & 1) != 0 && 1946 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1947 hcchar |= HCCHAR_ODDFRM; 1948 else 1949 hcchar &= ~HCCHAR_ODDFRM; 1950 1951 /* must enable channel before data can be received */ 1952 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1953 1954 /* wait until next slot before trying complete split */ 1955 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1956 busy: 1957 return (1); /* busy */ 1958 1959 complete: 1960 dwc_otg_host_channel_free(sc, td); 1961 return (0); /* complete */ 1962 } 1963 1964 static uint8_t 1965 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1966 { 1967 uint32_t max_buffer; 1968 uint32_t count; 1969 uint32_t fifo_left; 1970 uint32_t mpkt; 1971 uint32_t temp; 1972 uint8_t to; 1973 1974 to = 3; /* don't loop forever! */ 1975 1976 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1977 1978 repeat: 1979 /* check for for endpoint 0 data */ 1980 1981 temp = sc->sc_last_rx_status; 1982 1983 if ((td->ep_no == 0) && (temp != 0) && 1984 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1985 1986 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1987 GRXSTSRD_STP_DATA && 1988 (temp & GRXSTSRD_PKTSTS_MASK) != 1989 GRXSTSRD_STP_COMPLETE) { 1990 1991 /* dump data - wrong direction */ 1992 dwc_otg_common_rx_ack(sc); 1993 } else { 1994 /* 1995 * The current transfer was cancelled 1996 * by the USB Host: 1997 */ 1998 td->error_any = 1; 1999 return (0); /* complete */ 2000 } 2001 } 2002 2003 /* fill in more TX data, if possible */ 2004 if (td->tx_bytes != 0) { 2005 2006 uint16_t cpkt; 2007 2008 /* check if packets have been transferred */ 2009 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2010 2011 /* get current packet number */ 2012 cpkt = DXEPTSIZ_GET_NPKT(temp); 2013 2014 if (cpkt >= td->npkt) { 2015 fifo_left = 0; 2016 } else { 2017 if (max_buffer != 0) { 2018 fifo_left = (td->npkt - cpkt) * 2019 td->max_packet_size; 2020 2021 if (fifo_left > max_buffer) 2022 fifo_left = max_buffer; 2023 } else { 2024 fifo_left = td->max_packet_size; 2025 } 2026 } 2027 2028 count = td->tx_bytes; 2029 if (count > fifo_left) 2030 count = fifo_left; 2031 2032 if (count != 0) { 2033 2034 /* clear topmost word before copy */ 2035 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2036 2037 /* copy out data */ 2038 usbd_copy_out(td->pc, td->offset, 2039 sc->sc_tx_bounce_buffer, count); 2040 2041 /* transfer data into FIFO */ 2042 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2043 DOTG_DFIFO(td->ep_no), 2044 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2045 2046 td->tx_bytes -= count; 2047 td->remainder -= count; 2048 td->offset += count; 2049 td->npkt = cpkt; 2050 } 2051 if (td->tx_bytes != 0) 2052 goto not_complete; 2053 2054 /* check remainder */ 2055 if (td->remainder == 0) { 2056 if (td->short_pkt) 2057 return (0); /* complete */ 2058 2059 /* else we need to transmit a short packet */ 2060 } 2061 } 2062 2063 if (!to--) 2064 goto not_complete; 2065 2066 /* check if not all packets have been transferred */ 2067 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2068 2069 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2070 2071 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2072 "DIEPCTL=0x%08x\n", td->ep_no, 2073 DXEPTSIZ_GET_NPKT(temp), 2074 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2075 2076 goto not_complete; 2077 } 2078 2079 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2080 2081 /* try to optimise by sending more data */ 2082 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2083 2084 /* send multiple packets at the same time */ 2085 mpkt = max_buffer / td->max_packet_size; 2086 2087 if (mpkt > 0x3FE) 2088 mpkt = 0x3FE; 2089 2090 count = td->remainder; 2091 if (count > 0x7FFFFF) 2092 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2093 2094 td->npkt = count / td->max_packet_size; 2095 2096 /* 2097 * NOTE: We could use 0x3FE instead of "mpkt" in the 2098 * check below to get more throughput, but then we 2099 * have a dependency towards non-generic chip features 2100 * to disable the TX-FIFO-EMPTY interrupts on a per 2101 * endpoint basis. Increase the maximum buffer size of 2102 * the IN endpoint to increase the performance. 2103 */ 2104 if (td->npkt > mpkt) { 2105 td->npkt = mpkt; 2106 count = td->max_packet_size * mpkt; 2107 } else if ((count == 0) || (count % td->max_packet_size)) { 2108 /* we are transmitting a short packet */ 2109 td->npkt++; 2110 td->short_pkt = 1; 2111 } 2112 } else { 2113 /* send one packet at a time */ 2114 mpkt = 1; 2115 count = td->max_packet_size; 2116 if (td->remainder < count) { 2117 /* we have a short packet */ 2118 td->short_pkt = 1; 2119 count = td->remainder; 2120 } 2121 td->npkt = 1; 2122 } 2123 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2124 DXEPTSIZ_SET_MULTI(1) | 2125 DXEPTSIZ_SET_NPKT(td->npkt) | 2126 DXEPTSIZ_SET_NBYTES(count)); 2127 2128 /* make room for buffering */ 2129 td->npkt += mpkt; 2130 2131 temp = sc->sc_in_ctl[td->ep_no]; 2132 2133 /* check for isochronous mode */ 2134 if ((temp & DIEPCTL_EPTYPE_MASK) == 2135 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2136 /* toggle odd or even frame bit */ 2137 if (temp & DIEPCTL_SETD1PID) { 2138 temp &= ~DIEPCTL_SETD1PID; 2139 temp |= DIEPCTL_SETD0PID; 2140 } else { 2141 temp &= ~DIEPCTL_SETD0PID; 2142 temp |= DIEPCTL_SETD1PID; 2143 } 2144 sc->sc_in_ctl[td->ep_no] = temp; 2145 } 2146 2147 /* must enable before writing data to FIFO */ 2148 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2149 DIEPCTL_EPENA | DIEPCTL_CNAK); 2150 2151 td->tx_bytes = count; 2152 2153 /* check remainder */ 2154 if (td->tx_bytes == 0 && 2155 td->remainder == 0) { 2156 if (td->short_pkt) 2157 return (0); /* complete */ 2158 2159 /* else we need to transmit a short packet */ 2160 } 2161 goto repeat; 2162 2163 not_complete: 2164 return (1); /* not complete */ 2165 } 2166 2167 static uint8_t 2168 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2169 { 2170 uint32_t temp; 2171 2172 /* 2173 * If all packets are transferred we are complete: 2174 */ 2175 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2176 2177 /* check that all packets have been transferred */ 2178 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2179 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2180 goto not_complete; 2181 } 2182 return (0); 2183 2184 not_complete: 2185 2186 /* we only want to know if there is a SETUP packet or free IN packet */ 2187 2188 temp = sc->sc_last_rx_status; 2189 2190 if ((td->ep_no == 0) && (temp != 0) && 2191 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2192 2193 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2194 GRXSTSRD_STP_DATA || 2195 (temp & GRXSTSRD_PKTSTS_MASK) == 2196 GRXSTSRD_STP_COMPLETE) { 2197 DPRINTFN(5, "faking complete\n"); 2198 /* 2199 * Race condition: We are complete! 2200 */ 2201 return (0); 2202 } else { 2203 /* dump data - wrong direction */ 2204 dwc_otg_common_rx_ack(sc); 2205 } 2206 } 2207 return (1); /* not complete */ 2208 } 2209 2210 static void 2211 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2212 { 2213 struct dwc_otg_td *td; 2214 uint8_t toggle; 2215 uint8_t tmr_val; 2216 uint8_t tmr_res; 2217 2218 DPRINTFN(9, "\n"); 2219 2220 td = xfer->td_transfer_cache; 2221 if (td == NULL) 2222 return; 2223 2224 while (1) { 2225 if ((td->func) (sc, td)) { 2226 /* operation in progress */ 2227 break; 2228 } 2229 if (((void *)td) == xfer->td_transfer_last) { 2230 goto done; 2231 } 2232 if (td->error_any) { 2233 goto done; 2234 } else if (td->remainder > 0) { 2235 /* 2236 * We had a short transfer. If there is no alternate 2237 * next, stop processing ! 2238 */ 2239 if (!td->alt_next) 2240 goto done; 2241 } 2242 2243 /* 2244 * Fetch the next transfer descriptor and transfer 2245 * some flags to the next transfer descriptor 2246 */ 2247 tmr_res = td->tmr_res; 2248 tmr_val = td->tmr_val; 2249 toggle = td->toggle; 2250 td = td->obj_next; 2251 xfer->td_transfer_cache = td; 2252 td->toggle = toggle; /* transfer toggle */ 2253 td->tmr_res = tmr_res; 2254 td->tmr_val = tmr_val; 2255 } 2256 return; 2257 2258 done: 2259 xfer->td_transfer_cache = NULL; 2260 sc->sc_xfer_complete = 1; 2261 } 2262 2263 static uint8_t 2264 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2265 { 2266 struct dwc_otg_td *td; 2267 2268 DPRINTFN(9, "\n"); 2269 2270 td = xfer->td_transfer_cache; 2271 if (td == NULL) { 2272 /* compute all actual lengths */ 2273 dwc_otg_standard_done(xfer); 2274 return (1); 2275 } 2276 return (0); 2277 } 2278 2279 static void 2280 dwc_otg_timer(void *_sc) 2281 { 2282 struct dwc_otg_softc *sc = _sc; 2283 struct usb_xfer *xfer; 2284 struct dwc_otg_td *td; 2285 2286 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2287 2288 DPRINTF("\n"); 2289 2290 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2291 2292 /* increment timer value */ 2293 sc->sc_tmr_val++; 2294 2295 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2296 td = xfer->td_transfer_cache; 2297 if (td != NULL) { 2298 /* reset NAK counter */ 2299 td->did_nak = 0; 2300 } 2301 } 2302 2303 /* enable SOF interrupt, which will poll jobs */ 2304 dwc_otg_enable_sof_irq(sc); 2305 2306 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2307 2308 if (sc->sc_timer_active) { 2309 /* restart timer */ 2310 usb_callout_reset(&sc->sc_timer, 2311 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2312 &dwc_otg_timer, sc); 2313 } 2314 } 2315 2316 static void 2317 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2318 { 2319 if (sc->sc_timer_active != 0) 2320 return; 2321 2322 sc->sc_timer_active = 1; 2323 2324 /* restart timer */ 2325 usb_callout_reset(&sc->sc_timer, 2326 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2327 &dwc_otg_timer, sc); 2328 } 2329 2330 static void 2331 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2332 { 2333 if (sc->sc_timer_active == 0) 2334 return; 2335 2336 sc->sc_timer_active = 0; 2337 2338 /* stop timer */ 2339 usb_callout_stop(&sc->sc_timer); 2340 } 2341 2342 static uint16_t 2343 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2344 { 2345 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2346 pinfo->slot_index++; 2347 return (pinfo->slot_index); 2348 } 2349 2350 static uint8_t 2351 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2352 { 2353 TAILQ_HEAD(, usb_xfer) head; 2354 struct usb_xfer *xfer; 2355 struct usb_xfer *xfer_next; 2356 struct dwc_otg_td *td; 2357 uint16_t temp; 2358 uint16_t slot; 2359 2360 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2361 2362 if (sc->sc_last_frame_num == temp) 2363 return (0); 2364 2365 sc->sc_last_frame_num = temp; 2366 2367 TAILQ_INIT(&head); 2368 2369 if ((temp & 7) == 0) { 2370 2371 /* reset the schedule */ 2372 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2373 2374 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2375 td = xfer->td_transfer_cache; 2376 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2377 continue; 2378 2379 /* check for IN direction */ 2380 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2381 continue; 2382 2383 /* execute more frames */ 2384 td->tmr_val = 0; 2385 2386 sc->sc_needsof = 1; 2387 2388 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2389 continue; 2390 2391 /* compute slot */ 2392 slot = dwc_otg_compute_isoc_rx_tt_slot( 2393 sc->sc_tt_info + td->tt_index); 2394 if (slot > 3) { 2395 /* 2396 * Not enough time to get complete 2397 * split executed. 2398 */ 2399 continue; 2400 } 2401 /* Delayed start */ 2402 td->tt_start_slot = temp + slot; 2403 td->tt_scheduled = 1; 2404 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2405 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2406 } 2407 2408 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2409 td = xfer->td_transfer_cache; 2410 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2411 continue; 2412 2413 /* check for OUT direction */ 2414 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2415 continue; 2416 2417 /* execute more frames */ 2418 td->tmr_val = 0; 2419 2420 sc->sc_needsof = 1; 2421 2422 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2423 continue; 2424 2425 /* Start ASAP */ 2426 td->tt_start_slot = temp; 2427 td->tt_scheduled = 1; 2428 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2429 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2430 } 2431 2432 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2433 td = xfer->td_transfer_cache; 2434 if (td == NULL || td->ep_type != UE_INTERRUPT) 2435 continue; 2436 2437 if (td->tt_scheduled != 0) { 2438 sc->sc_needsof = 1; 2439 continue; 2440 } 2441 2442 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2443 continue; 2444 2445 if (td->hcsplt == 0) { 2446 sc->sc_needsof = 1; 2447 td->tt_scheduled = 1; 2448 continue; 2449 } 2450 2451 /* start ASAP */ 2452 td->tt_start_slot = temp; 2453 sc->sc_needsof = 1; 2454 td->tt_scheduled = 1; 2455 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2456 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2457 } 2458 2459 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2460 td = xfer->td_transfer_cache; 2461 if (td == NULL || 2462 td->ep_type != UE_CONTROL || 2463 td->did_nak >= DWC_OTG_NAK_MAX) { 2464 continue; 2465 } 2466 2467 sc->sc_needsof = 1; 2468 2469 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2470 continue; 2471 2472 /* start ASAP */ 2473 td->tt_start_slot = temp; 2474 td->tt_scheduled = 1; 2475 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2476 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2477 } 2478 } 2479 if ((temp & 7) < 6) { 2480 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2481 td = xfer->td_transfer_cache; 2482 if (td == NULL || 2483 td->ep_type != UE_BULK || 2484 td->did_nak >= DWC_OTG_NAK_MAX) { 2485 continue; 2486 } 2487 2488 sc->sc_needsof = 1; 2489 2490 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2491 continue; 2492 2493 /* start ASAP */ 2494 td->tt_start_slot = temp; 2495 td->tt_scheduled = 1; 2496 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2497 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2498 } 2499 } 2500 2501 /* Put TT transfers in execution order at the end */ 2502 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2503 2504 /* move all TT transfers in front, keeping the current order */ 2505 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2506 td = xfer->td_transfer_cache; 2507 if (td == NULL || td->hcsplt == 0) 2508 continue; 2509 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2510 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2511 } 2512 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2513 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2514 2515 /* put non-TT BULK transfers last */ 2516 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2517 td = xfer->td_transfer_cache; 2518 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) 2519 continue; 2520 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2521 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2522 } 2523 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2524 2525 if ((temp & 7) == 0) { 2526 2527 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2528 (int)temp, (int)sc->sc_needsof); 2529 2530 /* update SOF IRQ mask */ 2531 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2532 if (sc->sc_needsof == 0) { 2533 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2534 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2535 } 2536 } else { 2537 if (sc->sc_needsof != 0) { 2538 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2539 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2540 } 2541 } 2542 2543 /* clear need SOF flag */ 2544 sc->sc_needsof = 0; 2545 } 2546 return (1); 2547 } 2548 2549 static void 2550 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2551 { 2552 struct usb_xfer *xfer; 2553 uint32_t temp; 2554 uint8_t got_rx_status; 2555 uint8_t x; 2556 2557 repeat: 2558 /* get all channel interrupts */ 2559 for (x = 0; x != sc->sc_host_ch_max; x++) { 2560 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2561 if (temp != 0) { 2562 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2563 temp &= ~HCINT_SOFTWARE_ONLY; 2564 sc->sc_chan_state[x].hcint |= temp; 2565 } 2566 } 2567 2568 if (sc->sc_last_rx_status == 0) { 2569 2570 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2571 if (temp & GINTSTS_RXFLVL) { 2572 /* pop current status */ 2573 sc->sc_last_rx_status = 2574 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2575 } 2576 2577 if (sc->sc_last_rx_status != 0) { 2578 2579 uint8_t ep_no; 2580 2581 temp = sc->sc_last_rx_status & 2582 GRXSTSRD_PKTSTS_MASK; 2583 2584 /* non-data messages we simply skip */ 2585 if (temp != GRXSTSRD_STP_DATA && 2586 temp != GRXSTSRD_STP_COMPLETE && 2587 temp != GRXSTSRD_OUT_DATA) { 2588 /* check for halted channel */ 2589 if (temp == GRXSTSRH_HALTED) { 2590 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2591 sc->sc_chan_state[ep_no].wait_halted = 0; 2592 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2593 } 2594 dwc_otg_common_rx_ack(sc); 2595 goto repeat; 2596 } 2597 2598 temp = GRXSTSRD_BCNT_GET( 2599 sc->sc_last_rx_status); 2600 ep_no = GRXSTSRD_CHNUM_GET( 2601 sc->sc_last_rx_status); 2602 2603 /* receive data, if any */ 2604 if (temp != 0) { 2605 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2606 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2607 DOTG_DFIFO(ep_no), 2608 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2609 } 2610 2611 /* check if we should dump the data */ 2612 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2613 dwc_otg_common_rx_ack(sc); 2614 goto repeat; 2615 } 2616 2617 got_rx_status = 1; 2618 2619 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2620 sc->sc_last_rx_status, ep_no, 2621 (sc->sc_last_rx_status >> 15) & 3, 2622 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2623 (sc->sc_last_rx_status >> 17) & 15); 2624 } else { 2625 got_rx_status = 0; 2626 } 2627 } else { 2628 uint8_t ep_no; 2629 2630 ep_no = GRXSTSRD_CHNUM_GET( 2631 sc->sc_last_rx_status); 2632 2633 /* check if we should dump the data */ 2634 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2635 dwc_otg_common_rx_ack(sc); 2636 goto repeat; 2637 } 2638 2639 got_rx_status = 1; 2640 } 2641 2642 /* execute FIFOs */ 2643 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2644 dwc_otg_xfer_do_fifo(sc, xfer); 2645 2646 if (got_rx_status) { 2647 /* check if data was consumed */ 2648 if (sc->sc_last_rx_status == 0) 2649 goto repeat; 2650 2651 /* disable RX FIFO level interrupt */ 2652 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2653 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2654 } 2655 2656 if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) { 2657 /* update host transfer schedule, so that new transfers can be issued */ 2658 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2659 goto repeat; 2660 } 2661 } 2662 2663 static void 2664 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2665 { 2666 struct usb_xfer *xfer; 2667 repeat: 2668 /* scan for completion events */ 2669 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2670 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2671 goto repeat; 2672 } 2673 } 2674 2675 static void 2676 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2677 { 2678 DPRINTFN(5, "vbus = %u\n", is_on); 2679 2680 /* 2681 * If the USB host mode is forced, then assume VBUS is always 2682 * present else rely on the input to this function: 2683 */ 2684 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2685 2686 if (!sc->sc_flags.status_vbus) { 2687 sc->sc_flags.status_vbus = 1; 2688 2689 /* complete root HUB interrupt endpoint */ 2690 2691 dwc_otg_root_intr(sc); 2692 } 2693 } else { 2694 if (sc->sc_flags.status_vbus) { 2695 sc->sc_flags.status_vbus = 0; 2696 sc->sc_flags.status_bus_reset = 0; 2697 sc->sc_flags.status_suspend = 0; 2698 sc->sc_flags.change_suspend = 0; 2699 sc->sc_flags.change_connect = 1; 2700 2701 /* complete root HUB interrupt endpoint */ 2702 2703 dwc_otg_root_intr(sc); 2704 } 2705 } 2706 } 2707 2708 int 2709 dwc_otg_filter_interrupt(void *arg) 2710 { 2711 struct dwc_otg_softc *sc = arg; 2712 int retval = FILTER_HANDLED; 2713 uint32_t status; 2714 2715 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2716 2717 /* read and clear interrupt status */ 2718 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2719 2720 /* clear interrupts we are handling here */ 2721 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2722 2723 /* check for USB state change interrupts */ 2724 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2725 retval = FILTER_SCHEDULE_THREAD; 2726 2727 /* clear FIFO empty interrupts */ 2728 if (status & sc->sc_irq_mask & 2729 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2730 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2731 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2732 } 2733 /* clear all IN endpoint interrupts */ 2734 if (status & GINTSTS_IEPINT) { 2735 uint32_t temp; 2736 uint8_t x; 2737 2738 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2739 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2740 if (temp & DIEPMSK_XFERCOMPLMSK) { 2741 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2742 DIEPMSK_XFERCOMPLMSK); 2743 } 2744 } 2745 } 2746 2747 /* poll FIFOs, if any */ 2748 dwc_otg_interrupt_poll_locked(sc); 2749 2750 if (sc->sc_xfer_complete != 0) 2751 retval = FILTER_SCHEDULE_THREAD; 2752 2753 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2754 2755 return (retval); 2756 } 2757 2758 void 2759 dwc_otg_interrupt(void *arg) 2760 { 2761 struct dwc_otg_softc *sc = arg; 2762 uint32_t status; 2763 2764 USB_BUS_LOCK(&sc->sc_bus); 2765 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2766 2767 /* read and clear interrupt status */ 2768 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2769 2770 /* clear interrupts we are handling here */ 2771 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2772 2773 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2774 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2775 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2776 2777 if (status & GINTSTS_USBRST) { 2778 2779 /* set correct state */ 2780 sc->sc_flags.status_device_mode = 1; 2781 sc->sc_flags.status_bus_reset = 0; 2782 sc->sc_flags.status_suspend = 0; 2783 sc->sc_flags.change_suspend = 0; 2784 sc->sc_flags.change_connect = 1; 2785 2786 /* Disable SOF interrupt */ 2787 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2788 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2789 2790 /* complete root HUB interrupt endpoint */ 2791 dwc_otg_root_intr(sc); 2792 } 2793 2794 /* check for any bus state change interrupts */ 2795 if (status & GINTSTS_ENUMDONE) { 2796 2797 uint32_t temp; 2798 2799 DPRINTFN(5, "end of reset\n"); 2800 2801 /* set correct state */ 2802 sc->sc_flags.status_device_mode = 1; 2803 sc->sc_flags.status_bus_reset = 1; 2804 sc->sc_flags.status_suspend = 0; 2805 sc->sc_flags.change_suspend = 0; 2806 sc->sc_flags.change_connect = 1; 2807 sc->sc_flags.status_low_speed = 0; 2808 sc->sc_flags.port_enabled = 1; 2809 2810 /* reset FIFOs */ 2811 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2812 2813 /* reset function address */ 2814 dwc_otg_set_address(sc, 0); 2815 2816 /* figure out enumeration speed */ 2817 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2818 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2819 sc->sc_flags.status_high_speed = 1; 2820 else 2821 sc->sc_flags.status_high_speed = 0; 2822 2823 /* 2824 * Disable resume and SOF interrupt, and enable 2825 * suspend and RX frame interrupt: 2826 */ 2827 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2828 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2829 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2830 2831 /* complete root HUB interrupt endpoint */ 2832 dwc_otg_root_intr(sc); 2833 } 2834 2835 if (status & GINTSTS_PRTINT) { 2836 uint32_t hprt; 2837 2838 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2839 2840 /* clear change bits */ 2841 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2842 HPRT_PRTPWR | HPRT_PRTENCHNG | 2843 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2844 sc->sc_hprt_val); 2845 2846 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2847 2848 sc->sc_flags.status_device_mode = 0; 2849 2850 if (hprt & HPRT_PRTCONNSTS) 2851 sc->sc_flags.status_bus_reset = 1; 2852 else 2853 sc->sc_flags.status_bus_reset = 0; 2854 2855 if (hprt & HPRT_PRTENCHNG) 2856 sc->sc_flags.change_enabled = 1; 2857 2858 if (hprt & HPRT_PRTENA) 2859 sc->sc_flags.port_enabled = 1; 2860 else 2861 sc->sc_flags.port_enabled = 0; 2862 2863 if (hprt & HPRT_PRTOVRCURRCHNG) 2864 sc->sc_flags.change_over_current = 1; 2865 2866 if (hprt & HPRT_PRTOVRCURRACT) 2867 sc->sc_flags.port_over_current = 1; 2868 else 2869 sc->sc_flags.port_over_current = 0; 2870 2871 if (hprt & HPRT_PRTPWR) 2872 sc->sc_flags.port_powered = 1; 2873 else 2874 sc->sc_flags.port_powered = 0; 2875 2876 if (((hprt & HPRT_PRTSPD_MASK) 2877 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2878 sc->sc_flags.status_low_speed = 1; 2879 else 2880 sc->sc_flags.status_low_speed = 0; 2881 2882 if (((hprt & HPRT_PRTSPD_MASK) 2883 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2884 sc->sc_flags.status_high_speed = 1; 2885 else 2886 sc->sc_flags.status_high_speed = 0; 2887 2888 if (hprt & HPRT_PRTCONNDET) 2889 sc->sc_flags.change_connect = 1; 2890 2891 if (hprt & HPRT_PRTSUSP) 2892 dwc_otg_suspend_irq(sc); 2893 else 2894 dwc_otg_resume_irq(sc); 2895 2896 /* complete root HUB interrupt endpoint */ 2897 dwc_otg_root_intr(sc); 2898 2899 /* update host frame interval */ 2900 dwc_otg_update_host_frame_interval(sc); 2901 } 2902 2903 /* 2904 * If resume and suspend is set at the same time we interpret 2905 * that like RESUME. Resume is set when there is at least 3 2906 * milliseconds of inactivity on the USB BUS. 2907 */ 2908 if (status & GINTSTS_WKUPINT) { 2909 2910 DPRINTFN(5, "resume interrupt\n"); 2911 2912 dwc_otg_resume_irq(sc); 2913 2914 } else if (status & GINTSTS_USBSUSP) { 2915 2916 DPRINTFN(5, "suspend interrupt\n"); 2917 2918 dwc_otg_suspend_irq(sc); 2919 } 2920 /* check VBUS */ 2921 if (status & (GINTSTS_USBSUSP | 2922 GINTSTS_USBRST | 2923 GINTMSK_OTGINTMSK | 2924 GINTSTS_SESSREQINT)) { 2925 uint32_t temp; 2926 2927 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2928 2929 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2930 2931 dwc_otg_vbus_interrupt(sc, 2932 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2933 } 2934 2935 if (sc->sc_xfer_complete != 0) { 2936 sc->sc_xfer_complete = 0; 2937 2938 /* complete FIFOs, if any */ 2939 dwc_otg_interrupt_complete_locked(sc); 2940 2941 if (sc->sc_flags.status_device_mode == 0) { 2942 /* update host transfer schedule, so that new transfers can be issued */ 2943 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2944 dwc_otg_interrupt_poll_locked(sc); 2945 } 2946 } 2947 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2948 USB_BUS_UNLOCK(&sc->sc_bus); 2949 } 2950 2951 static void 2952 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2953 { 2954 struct dwc_otg_td *td; 2955 2956 /* get current Transfer Descriptor */ 2957 td = temp->td_next; 2958 temp->td = td; 2959 2960 /* prepare for next TD */ 2961 temp->td_next = td->obj_next; 2962 2963 /* fill out the Transfer Descriptor */ 2964 td->func = temp->func; 2965 td->pc = temp->pc; 2966 td->offset = temp->offset; 2967 td->remainder = temp->len; 2968 td->tx_bytes = 0; 2969 td->error_any = 0; 2970 td->error_stall = 0; 2971 td->npkt = 0; 2972 td->did_stall = temp->did_stall; 2973 td->short_pkt = temp->short_pkt; 2974 td->alt_next = temp->setup_alt_next; 2975 td->set_toggle = 0; 2976 td->got_short = 0; 2977 td->did_nak = 0; 2978 td->channel = DWC_OTG_MAX_CHANNELS; 2979 td->state = 0; 2980 td->errcnt = 0; 2981 td->tt_scheduled = 0; 2982 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 2983 } 2984 2985 static void 2986 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2987 { 2988 struct dwc_otg_std_temp temp; 2989 struct dwc_otg_td *td; 2990 uint32_t x; 2991 uint8_t need_sync; 2992 uint8_t is_host; 2993 2994 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2995 xfer->address, UE_GET_ADDR(xfer->endpointno), 2996 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2997 2998 temp.max_frame_size = xfer->max_frame_size; 2999 3000 td = xfer->td_start[0]; 3001 xfer->td_transfer_first = td; 3002 xfer->td_transfer_cache = td; 3003 3004 /* setup temp */ 3005 3006 temp.pc = NULL; 3007 temp.td = NULL; 3008 temp.td_next = xfer->td_start[0]; 3009 temp.offset = 0; 3010 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3011 xfer->flags_int.isochronous_xfr; 3012 temp.did_stall = !xfer->flags_int.control_stall; 3013 3014 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3015 3016 /* check if we should prepend a setup message */ 3017 3018 if (xfer->flags_int.control_xfr) { 3019 if (xfer->flags_int.control_hdr) { 3020 3021 if (is_host) 3022 temp.func = &dwc_otg_host_setup_tx; 3023 else 3024 temp.func = &dwc_otg_setup_rx; 3025 3026 temp.len = xfer->frlengths[0]; 3027 temp.pc = xfer->frbuffers + 0; 3028 temp.short_pkt = temp.len ? 1 : 0; 3029 3030 /* check for last frame */ 3031 if (xfer->nframes == 1) { 3032 /* no STATUS stage yet, SETUP is last */ 3033 if (xfer->flags_int.control_act) 3034 temp.setup_alt_next = 0; 3035 } 3036 3037 dwc_otg_setup_standard_chain_sub(&temp); 3038 } 3039 x = 1; 3040 } else { 3041 x = 0; 3042 } 3043 3044 if (x != xfer->nframes) { 3045 if (xfer->endpointno & UE_DIR_IN) { 3046 if (is_host) { 3047 temp.func = &dwc_otg_host_data_rx; 3048 need_sync = 0; 3049 } else { 3050 temp.func = &dwc_otg_data_tx; 3051 need_sync = 1; 3052 } 3053 } else { 3054 if (is_host) { 3055 temp.func = &dwc_otg_host_data_tx; 3056 need_sync = 0; 3057 } else { 3058 temp.func = &dwc_otg_data_rx; 3059 need_sync = 0; 3060 } 3061 } 3062 3063 /* setup "pc" pointer */ 3064 temp.pc = xfer->frbuffers + x; 3065 } else { 3066 need_sync = 0; 3067 } 3068 while (x != xfer->nframes) { 3069 3070 /* DATA0 / DATA1 message */ 3071 3072 temp.len = xfer->frlengths[x]; 3073 3074 x++; 3075 3076 if (x == xfer->nframes) { 3077 if (xfer->flags_int.control_xfr) { 3078 if (xfer->flags_int.control_act) { 3079 temp.setup_alt_next = 0; 3080 } 3081 } else { 3082 temp.setup_alt_next = 0; 3083 } 3084 } 3085 if (temp.len == 0) { 3086 3087 /* make sure that we send an USB packet */ 3088 3089 temp.short_pkt = 0; 3090 3091 } else { 3092 3093 /* regular data transfer */ 3094 3095 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3096 } 3097 3098 dwc_otg_setup_standard_chain_sub(&temp); 3099 3100 if (xfer->flags_int.isochronous_xfr) { 3101 temp.offset += temp.len; 3102 } else { 3103 /* get next Page Cache pointer */ 3104 temp.pc = xfer->frbuffers + x; 3105 } 3106 } 3107 3108 if (xfer->flags_int.control_xfr) { 3109 3110 /* always setup a valid "pc" pointer for status and sync */ 3111 temp.pc = xfer->frbuffers + 0; 3112 temp.len = 0; 3113 temp.short_pkt = 0; 3114 temp.setup_alt_next = 0; 3115 3116 /* check if we need to sync */ 3117 if (need_sync) { 3118 /* we need a SYNC point after TX */ 3119 temp.func = &dwc_otg_data_tx_sync; 3120 dwc_otg_setup_standard_chain_sub(&temp); 3121 } 3122 3123 /* check if we should append a status stage */ 3124 if (!xfer->flags_int.control_act) { 3125 3126 /* 3127 * Send a DATA1 message and invert the current 3128 * endpoint direction. 3129 */ 3130 if (xfer->endpointno & UE_DIR_IN) { 3131 if (is_host) { 3132 temp.func = &dwc_otg_host_data_tx; 3133 need_sync = 0; 3134 } else { 3135 temp.func = &dwc_otg_data_rx; 3136 need_sync = 0; 3137 } 3138 } else { 3139 if (is_host) { 3140 temp.func = &dwc_otg_host_data_rx; 3141 need_sync = 0; 3142 } else { 3143 temp.func = &dwc_otg_data_tx; 3144 need_sync = 1; 3145 } 3146 } 3147 3148 dwc_otg_setup_standard_chain_sub(&temp); 3149 3150 /* data toggle should be DATA1 */ 3151 td = temp.td; 3152 td->set_toggle = 1; 3153 3154 if (need_sync) { 3155 /* we need a SYNC point after TX */ 3156 temp.func = &dwc_otg_data_tx_sync; 3157 dwc_otg_setup_standard_chain_sub(&temp); 3158 } 3159 } 3160 } else { 3161 /* check if we need to sync */ 3162 if (need_sync) { 3163 3164 temp.pc = xfer->frbuffers + 0; 3165 temp.len = 0; 3166 temp.short_pkt = 0; 3167 temp.setup_alt_next = 0; 3168 3169 /* we need a SYNC point after TX */ 3170 temp.func = &dwc_otg_data_tx_sync; 3171 dwc_otg_setup_standard_chain_sub(&temp); 3172 } 3173 } 3174 3175 /* must have at least one frame! */ 3176 td = temp.td; 3177 xfer->td_transfer_last = td; 3178 3179 if (is_host) { 3180 3181 struct dwc_otg_softc *sc; 3182 uint32_t hcchar; 3183 uint32_t hcsplt; 3184 3185 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3186 3187 /* get first again */ 3188 td = xfer->td_transfer_first; 3189 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3190 3191 hcchar = 3192 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3193 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3194 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3195 HCCHAR_CHENA; 3196 3197 /* 3198 * We are not always able to meet the timing 3199 * requirements of the USB interrupt endpoint's 3200 * complete split token, when doing transfers going 3201 * via a transaction translator. Use the CONTROL 3202 * transfer type instead of the INTERRUPT transfer 3203 * type in general, as a means to workaround 3204 * that. This trick should work for both FULL and LOW 3205 * speed USB traffic going through a TT. For non-TT 3206 * traffic it works aswell. The reason for using 3207 * CONTROL type instead of BULK is that some TTs might 3208 * reject LOW speed BULK traffic. 3209 */ 3210 if (td->ep_type == UE_INTERRUPT) 3211 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3212 else 3213 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3214 3215 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3216 hcchar |= HCCHAR_LSPDDEV; 3217 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3218 hcchar |= HCCHAR_EPDIR_IN; 3219 3220 switch (xfer->xroot->udev->speed) { 3221 case USB_SPEED_FULL: 3222 case USB_SPEED_LOW: 3223 /* check if root HUB port is running High Speed */ 3224 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3225 hcsplt = HCSPLT_SPLTENA | 3226 (xfer->xroot->udev->hs_port_no << 3227 HCSPLT_PRTADDR_SHIFT) | 3228 (xfer->xroot->udev->hs_hub_addr << 3229 HCSPLT_HUBADDR_SHIFT); 3230 } else { 3231 hcsplt = 0; 3232 } 3233 if (td->ep_type == UE_INTERRUPT) { 3234 uint32_t ival; 3235 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3236 if (ival == 0) 3237 ival = 1; 3238 else if (ival > 127) 3239 ival = 127; 3240 td->tmr_val = sc->sc_tmr_val + ival; 3241 td->tmr_res = ival; 3242 } else if (td->ep_type == UE_ISOCHRONOUS) { 3243 td->tmr_val = 0; 3244 td->tmr_res = 1; 3245 } else { 3246 td->tmr_val = 0; 3247 td->tmr_res = 0; 3248 } 3249 break; 3250 case USB_SPEED_HIGH: 3251 hcsplt = 0; 3252 if (td->ep_type == UE_INTERRUPT) { 3253 uint32_t ival; 3254 #if 0 3255 hcchar |= ((xfer->max_packet_count & 3) 3256 << HCCHAR_MC_SHIFT); 3257 #endif 3258 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3259 if (ival == 0) 3260 ival = 1; 3261 else if (ival > 127) 3262 ival = 127; 3263 td->tmr_val = sc->sc_tmr_val + ival; 3264 td->tmr_res = ival; 3265 } else if (td->ep_type == UE_ISOCHRONOUS) { 3266 hcchar |= ((xfer->max_packet_count & 3) 3267 << HCCHAR_MC_SHIFT); 3268 td->tmr_val = 0; 3269 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3270 } else { 3271 td->tmr_val = 0; 3272 td->tmr_res = 0; 3273 } 3274 break; 3275 default: 3276 hcsplt = 0; 3277 td->tmr_val = 0; 3278 td->tmr_res = 0; 3279 break; 3280 } 3281 3282 /* store configuration in all TD's */ 3283 while (1) { 3284 td->hcchar = hcchar; 3285 td->hcsplt = hcsplt; 3286 3287 if (((void *)td) == xfer->td_transfer_last) 3288 break; 3289 3290 td = td->obj_next; 3291 } 3292 } 3293 } 3294 3295 static void 3296 dwc_otg_timeout(void *arg) 3297 { 3298 struct usb_xfer *xfer = arg; 3299 3300 DPRINTF("xfer=%p\n", xfer); 3301 3302 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3303 3304 /* transfer is transferred */ 3305 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3306 } 3307 3308 static void 3309 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3310 { 3311 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3312 struct usb_xfer_root *xroot; 3313 struct dwc_otg_td *td; 3314 3315 DPRINTFN(9, "\n"); 3316 3317 /* 3318 * Poll one time in device mode, which will turn on the 3319 * endpoint interrupts. Else wait for SOF interrupt in host 3320 * mode. 3321 */ 3322 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3323 3324 if (sc->sc_flags.status_device_mode != 0) { 3325 dwc_otg_xfer_do_fifo(sc, xfer); 3326 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3327 goto done; 3328 } 3329 3330 /* put transfer on interrupt queue */ 3331 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3332 3333 /* start timeout, if any */ 3334 if (xfer->timeout != 0) { 3335 usbd_transfer_timeout_ms(xfer, 3336 &dwc_otg_timeout, xfer->timeout); 3337 } 3338 3339 if (sc->sc_flags.status_device_mode != 0) 3340 goto done; 3341 3342 /* enable SOF interrupt, if any */ 3343 dwc_otg_enable_sof_irq(sc); 3344 3345 td = xfer->td_transfer_cache; 3346 if (td->ep_type != UE_BULK) 3347 goto done; 3348 3349 xroot = xfer->xroot; 3350 3351 /* 3352 * Optimise the ping-pong effect by waking up other BULK 3353 * transfers belonging to the same device group: 3354 */ 3355 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3356 td = xfer->td_transfer_cache; 3357 if (td == NULL || td->ep_type != UE_BULK || xfer->xroot != xroot) 3358 continue; 3359 /* reset NAK counter */ 3360 td->did_nak = 0; 3361 } 3362 done: 3363 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3364 } 3365 3366 static void 3367 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3368 { 3369 DPRINTFN(9, "\n"); 3370 3371 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3372 3373 /* set port bit */ 3374 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3375 3376 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3377 sizeof(sc->sc_hub_idata)); 3378 } 3379 3380 static usb_error_t 3381 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3382 { 3383 struct dwc_otg_td *td; 3384 uint32_t len; 3385 usb_error_t error; 3386 3387 DPRINTFN(9, "\n"); 3388 3389 td = xfer->td_transfer_cache; 3390 3391 do { 3392 len = td->remainder; 3393 3394 /* store last data toggle */ 3395 xfer->endpoint->toggle_next = td->toggle; 3396 3397 if (xfer->aframes != xfer->nframes) { 3398 /* 3399 * Verify the length and subtract 3400 * the remainder from "frlengths[]": 3401 */ 3402 if (len > xfer->frlengths[xfer->aframes]) { 3403 td->error_any = 1; 3404 } else { 3405 xfer->frlengths[xfer->aframes] -= len; 3406 } 3407 } 3408 /* Check for transfer error */ 3409 if (td->error_any) { 3410 /* the transfer is finished */ 3411 error = (td->error_stall ? 3412 USB_ERR_STALLED : USB_ERR_IOERROR); 3413 td = NULL; 3414 break; 3415 } 3416 /* Check for short transfer */ 3417 if (len > 0) { 3418 if (xfer->flags_int.short_frames_ok || 3419 xfer->flags_int.isochronous_xfr) { 3420 /* follow alt next */ 3421 if (td->alt_next) { 3422 td = td->obj_next; 3423 } else { 3424 td = NULL; 3425 } 3426 } else { 3427 /* the transfer is finished */ 3428 td = NULL; 3429 } 3430 error = 0; 3431 break; 3432 } 3433 td = td->obj_next; 3434 3435 /* this USB frame is complete */ 3436 error = 0; 3437 break; 3438 3439 } while (0); 3440 3441 /* update transfer cache */ 3442 3443 xfer->td_transfer_cache = td; 3444 3445 return (error); 3446 } 3447 3448 static void 3449 dwc_otg_standard_done(struct usb_xfer *xfer) 3450 { 3451 usb_error_t err = 0; 3452 3453 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3454 xfer, xfer->endpoint); 3455 3456 /* reset scanner */ 3457 3458 xfer->td_transfer_cache = xfer->td_transfer_first; 3459 3460 if (xfer->flags_int.control_xfr) { 3461 3462 if (xfer->flags_int.control_hdr) { 3463 3464 err = dwc_otg_standard_done_sub(xfer); 3465 } 3466 xfer->aframes = 1; 3467 3468 if (xfer->td_transfer_cache == NULL) { 3469 goto done; 3470 } 3471 } 3472 while (xfer->aframes != xfer->nframes) { 3473 3474 err = dwc_otg_standard_done_sub(xfer); 3475 xfer->aframes++; 3476 3477 if (xfer->td_transfer_cache == NULL) { 3478 goto done; 3479 } 3480 } 3481 3482 if (xfer->flags_int.control_xfr && 3483 !xfer->flags_int.control_act) { 3484 3485 err = dwc_otg_standard_done_sub(xfer); 3486 } 3487 done: 3488 dwc_otg_device_done(xfer, err); 3489 } 3490 3491 /*------------------------------------------------------------------------* 3492 * dwc_otg_device_done 3493 * 3494 * NOTE: this function can be called more than one time on the 3495 * same USB transfer! 3496 *------------------------------------------------------------------------*/ 3497 static void 3498 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3499 { 3500 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3501 3502 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3503 xfer, xfer->endpoint, error); 3504 3505 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3506 3507 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3508 /* Interrupts are cleared by the interrupt handler */ 3509 } else { 3510 struct dwc_otg_td *td; 3511 3512 td = xfer->td_transfer_cache; 3513 if (td != NULL) 3514 dwc_otg_host_channel_free(sc, td); 3515 } 3516 /* dequeue transfer and start next transfer */ 3517 usbd_transfer_done(xfer, error); 3518 3519 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3520 } 3521 3522 static void 3523 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3524 { 3525 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3526 } 3527 3528 static void 3529 dwc_otg_set_stall(struct usb_device *udev, 3530 struct usb_endpoint *ep, uint8_t *did_stall) 3531 { 3532 struct dwc_otg_softc *sc; 3533 uint32_t temp; 3534 uint32_t reg; 3535 uint8_t ep_no; 3536 3537 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3538 3539 /* check mode */ 3540 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3541 /* not supported */ 3542 return; 3543 } 3544 3545 sc = DWC_OTG_BUS2SC(udev->bus); 3546 3547 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3548 3549 /* get endpoint address */ 3550 ep_no = ep->edesc->bEndpointAddress; 3551 3552 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3553 3554 if (ep_no & UE_DIR_IN) { 3555 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3556 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3557 } else { 3558 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3559 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3560 } 3561 3562 /* disable and stall endpoint */ 3563 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3564 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3565 3566 /* clear active OUT ep */ 3567 if (!(ep_no & UE_DIR_IN)) { 3568 3569 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3570 3571 if (sc->sc_last_rx_status != 0 && 3572 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3573 sc->sc_last_rx_status)) { 3574 /* dump data */ 3575 dwc_otg_common_rx_ack(sc); 3576 /* poll interrupt */ 3577 dwc_otg_interrupt_poll_locked(sc); 3578 dwc_otg_interrupt_complete_locked(sc); 3579 } 3580 } 3581 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3582 } 3583 3584 static void 3585 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3586 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3587 { 3588 uint32_t reg; 3589 uint32_t temp; 3590 3591 if (ep_type == UE_CONTROL) { 3592 /* clearing stall is not needed */ 3593 return; 3594 } 3595 3596 if (ep_dir) { 3597 reg = DOTG_DIEPCTL(ep_no); 3598 } else { 3599 reg = DOTG_DOEPCTL(ep_no); 3600 sc->sc_active_rx_ep |= (1U << ep_no); 3601 } 3602 3603 /* round up and mask away the multiplier count */ 3604 mps = (mps + 3) & 0x7FC; 3605 3606 if (ep_type == UE_BULK) { 3607 temp = DIEPCTL_EPTYPE_SET( 3608 DIEPCTL_EPTYPE_BULK) | 3609 DIEPCTL_USBACTEP; 3610 } else if (ep_type == UE_INTERRUPT) { 3611 temp = DIEPCTL_EPTYPE_SET( 3612 DIEPCTL_EPTYPE_INTERRUPT) | 3613 DIEPCTL_USBACTEP; 3614 } else { 3615 temp = DIEPCTL_EPTYPE_SET( 3616 DIEPCTL_EPTYPE_ISOC) | 3617 DIEPCTL_USBACTEP; 3618 } 3619 3620 temp |= DIEPCTL_MPS_SET(mps); 3621 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3622 3623 if (ep_dir) 3624 sc->sc_in_ctl[ep_no] = temp; 3625 else 3626 sc->sc_out_ctl[ep_no] = temp; 3627 3628 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3629 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3630 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3631 3632 /* we only reset the transmit FIFO */ 3633 if (ep_dir) { 3634 dwc_otg_tx_fifo_reset(sc, 3635 GRSTCTL_TXFIFO(ep_no) | 3636 GRSTCTL_TXFFLSH); 3637 3638 DWC_OTG_WRITE_4(sc, 3639 DOTG_DIEPTSIZ(ep_no), 0); 3640 } 3641 3642 /* poll interrupt */ 3643 dwc_otg_interrupt_poll_locked(sc); 3644 dwc_otg_interrupt_complete_locked(sc); 3645 } 3646 3647 static void 3648 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3649 { 3650 struct dwc_otg_softc *sc; 3651 struct usb_endpoint_descriptor *ed; 3652 3653 DPRINTFN(5, "endpoint=%p\n", ep); 3654 3655 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3656 3657 /* check mode */ 3658 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3659 /* not supported */ 3660 return; 3661 } 3662 /* get softc */ 3663 sc = DWC_OTG_BUS2SC(udev->bus); 3664 3665 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3666 3667 /* get endpoint descriptor */ 3668 ed = ep->edesc; 3669 3670 /* reset endpoint */ 3671 dwc_otg_clear_stall_sub_locked(sc, 3672 UGETW(ed->wMaxPacketSize), 3673 (ed->bEndpointAddress & UE_ADDR), 3674 (ed->bmAttributes & UE_XFERTYPE), 3675 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3676 3677 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3678 } 3679 3680 static void 3681 dwc_otg_device_state_change(struct usb_device *udev) 3682 { 3683 struct dwc_otg_softc *sc; 3684 uint8_t x; 3685 3686 /* check mode */ 3687 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3688 /* not supported */ 3689 return; 3690 } 3691 3692 /* get softc */ 3693 sc = DWC_OTG_BUS2SC(udev->bus); 3694 3695 /* deactivate all other endpoint but the control endpoint */ 3696 if (udev->state == USB_STATE_CONFIGURED || 3697 udev->state == USB_STATE_ADDRESSED) { 3698 3699 USB_BUS_LOCK(&sc->sc_bus); 3700 3701 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3702 3703 if (x < sc->sc_dev_in_ep_max) { 3704 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3705 DIEPCTL_EPDIS); 3706 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3707 } 3708 3709 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3710 DOEPCTL_EPDIS); 3711 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3712 } 3713 USB_BUS_UNLOCK(&sc->sc_bus); 3714 } 3715 } 3716 3717 int 3718 dwc_otg_init(struct dwc_otg_softc *sc) 3719 { 3720 uint32_t temp; 3721 3722 DPRINTF("start\n"); 3723 3724 /* set up the bus structure */ 3725 sc->sc_bus.usbrev = USB_REV_2_0; 3726 sc->sc_bus.methods = &dwc_otg_bus_methods; 3727 3728 usb_callout_init_mtx(&sc->sc_timer, 3729 &sc->sc_bus.bus_mtx, 0); 3730 3731 USB_BUS_LOCK(&sc->sc_bus); 3732 3733 /* turn on clocks */ 3734 dwc_otg_clocks_on(sc); 3735 3736 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3737 DPRINTF("Version = 0x%08x\n", temp); 3738 3739 /* disconnect */ 3740 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3741 DCTL_SFTDISCON); 3742 3743 /* wait for host to detect disconnect */ 3744 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3745 3746 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3747 GRSTCTL_CSFTRST); 3748 3749 /* wait a little bit for block to reset */ 3750 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3751 3752 switch (sc->sc_mode) { 3753 case DWC_MODE_DEVICE: 3754 temp = GUSBCFG_FORCEDEVMODE; 3755 break; 3756 case DWC_MODE_HOST: 3757 temp = GUSBCFG_FORCEHOSTMODE; 3758 break; 3759 default: 3760 temp = 0; 3761 break; 3762 } 3763 3764 /* select HSIC, ULPI or internal PHY mode */ 3765 switch (dwc_otg_phy_type) { 3766 case DWC_OTG_PHY_HSIC: 3767 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3768 GUSBCFG_PHYIF | 3769 GUSBCFG_TRD_TIM_SET(5) | temp); 3770 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3771 0x000000EC); 3772 3773 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3774 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3775 temp & ~GLPMCFG_HSIC_CONN); 3776 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3777 temp | GLPMCFG_HSIC_CONN); 3778 break; 3779 case DWC_OTG_PHY_ULPI: 3780 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3781 GUSBCFG_ULPI_UTMI_SEL | 3782 GUSBCFG_TRD_TIM_SET(5) | temp); 3783 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3784 3785 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3786 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3787 temp & ~GLPMCFG_HSIC_CONN); 3788 break; 3789 case DWC_OTG_PHY_INTERNAL: 3790 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3791 GUSBCFG_PHYSEL | 3792 GUSBCFG_TRD_TIM_SET(5) | temp); 3793 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3794 3795 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3796 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3797 temp & ~GLPMCFG_HSIC_CONN); 3798 3799 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3800 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3801 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3802 DOTG_GGPIO_PWRDWN); 3803 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3804 break; 3805 default: 3806 break; 3807 } 3808 3809 /* clear global nak */ 3810 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3811 DCTL_CGOUTNAK | 3812 DCTL_CGNPINNAK); 3813 3814 /* disable USB port */ 3815 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3816 3817 /* wait 10ms */ 3818 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3819 3820 /* enable USB port */ 3821 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3822 3823 /* wait 10ms */ 3824 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3825 3826 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3827 3828 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3829 3830 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3831 3832 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3833 3834 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3835 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3836 3837 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3838 3839 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3840 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3841 3842 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3843 3844 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3845 3846 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3847 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3848 sc->sc_host_ch_max); 3849 3850 /* setup FIFO */ 3851 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3852 USB_BUS_UNLOCK(&sc->sc_bus); 3853 return (EINVAL); 3854 } 3855 3856 /* enable interrupts */ 3857 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3858 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3859 3860 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3861 3862 /* enable all endpoint interrupts */ 3863 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3864 if (temp & GHWCFG2_MPI) { 3865 uint8_t x; 3866 3867 DPRINTF("Disable Multi Process Interrupts\n"); 3868 3869 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3870 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 3871 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3872 } 3873 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 3874 } 3875 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3876 DIEPMSK_XFERCOMPLMSK); 3877 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3878 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3879 } 3880 3881 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3882 /* setup clocks */ 3883 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3884 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3885 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3886 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3887 } 3888 3889 /* only enable global IRQ */ 3890 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3891 GAHBCFG_GLBLINTRMSK); 3892 3893 /* turn off clocks */ 3894 dwc_otg_clocks_off(sc); 3895 3896 /* read initial VBUS state */ 3897 3898 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3899 3900 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3901 3902 dwc_otg_vbus_interrupt(sc, 3903 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3904 3905 USB_BUS_UNLOCK(&sc->sc_bus); 3906 3907 /* catch any lost interrupts */ 3908 3909 dwc_otg_do_poll(&sc->sc_bus); 3910 3911 return (0); /* success */ 3912 } 3913 3914 void 3915 dwc_otg_uninit(struct dwc_otg_softc *sc) 3916 { 3917 USB_BUS_LOCK(&sc->sc_bus); 3918 3919 /* stop host timer */ 3920 dwc_otg_timer_stop(sc); 3921 3922 /* set disconnect */ 3923 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3924 DCTL_SFTDISCON); 3925 3926 /* turn off global IRQ */ 3927 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3928 3929 sc->sc_flags.port_enabled = 0; 3930 sc->sc_flags.port_powered = 0; 3931 sc->sc_flags.status_vbus = 0; 3932 sc->sc_flags.status_bus_reset = 0; 3933 sc->sc_flags.status_suspend = 0; 3934 sc->sc_flags.change_suspend = 0; 3935 sc->sc_flags.change_connect = 1; 3936 3937 dwc_otg_pull_down(sc); 3938 dwc_otg_clocks_off(sc); 3939 3940 USB_BUS_UNLOCK(&sc->sc_bus); 3941 3942 usb_callout_drain(&sc->sc_timer); 3943 } 3944 3945 static void 3946 dwc_otg_suspend(struct dwc_otg_softc *sc) 3947 { 3948 return; 3949 } 3950 3951 static void 3952 dwc_otg_resume(struct dwc_otg_softc *sc) 3953 { 3954 return; 3955 } 3956 3957 static void 3958 dwc_otg_do_poll(struct usb_bus *bus) 3959 { 3960 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3961 3962 USB_BUS_LOCK(&sc->sc_bus); 3963 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3964 dwc_otg_interrupt_poll_locked(sc); 3965 dwc_otg_interrupt_complete_locked(sc); 3966 if (sc->sc_flags.status_device_mode == 0) { 3967 /* update host transfer schedule, so that new transfers can be issued */ 3968 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 3969 dwc_otg_interrupt_poll_locked(sc); 3970 } 3971 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3972 USB_BUS_UNLOCK(&sc->sc_bus); 3973 } 3974 3975 /*------------------------------------------------------------------------* 3976 * DWC OTG bulk support 3977 * DWC OTG control support 3978 * DWC OTG interrupt support 3979 *------------------------------------------------------------------------*/ 3980 static void 3981 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3982 { 3983 } 3984 3985 static void 3986 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3987 { 3988 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3989 } 3990 3991 static void 3992 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3993 { 3994 } 3995 3996 static void 3997 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3998 { 3999 /* setup TDs */ 4000 dwc_otg_setup_standard_chain(xfer); 4001 dwc_otg_start_standard_chain(xfer); 4002 } 4003 4004 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4005 { 4006 .open = dwc_otg_device_non_isoc_open, 4007 .close = dwc_otg_device_non_isoc_close, 4008 .enter = dwc_otg_device_non_isoc_enter, 4009 .start = dwc_otg_device_non_isoc_start, 4010 }; 4011 4012 /*------------------------------------------------------------------------* 4013 * DWC OTG full speed isochronous support 4014 *------------------------------------------------------------------------*/ 4015 static void 4016 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4017 { 4018 } 4019 4020 static void 4021 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4022 { 4023 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4024 } 4025 4026 static void 4027 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4028 { 4029 } 4030 4031 static void 4032 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4033 { 4034 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4035 uint32_t temp; 4036 uint32_t msframes; 4037 uint32_t framenum; 4038 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4039 4040 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4041 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4042 4043 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4044 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4045 4046 /* get the current frame index */ 4047 framenum = (temp & HFNUM_FRNUM_MASK); 4048 } else { 4049 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4050 4051 /* get the current frame index */ 4052 framenum = DSTS_SOFFN_GET(temp); 4053 } 4054 4055 if (xfer->xroot->udev->parent_hs_hub != NULL) 4056 framenum /= 8; 4057 4058 framenum &= DWC_OTG_FRAME_MASK; 4059 4060 /* 4061 * Compute number of milliseconds worth of data traffic for 4062 * this USB transfer: 4063 */ 4064 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4065 msframes = ((xfer->nframes << shift) + 7) / 8; 4066 else 4067 msframes = xfer->nframes; 4068 4069 /* 4070 * check if the frame index is within the window where the frames 4071 * will be inserted 4072 */ 4073 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4074 4075 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4076 /* 4077 * If there is data underflow or the pipe queue is 4078 * empty we schedule the transfer a few frames ahead 4079 * of the current frame position. Else two isochronous 4080 * transfers might overlap. 4081 */ 4082 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4083 xfer->endpoint->is_synced = 1; 4084 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4085 } 4086 /* 4087 * compute how many milliseconds the insertion is ahead of the 4088 * current frame position: 4089 */ 4090 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4091 4092 /* 4093 * pre-compute when the isochronous transfer will be finished: 4094 */ 4095 xfer->isoc_time_complete = 4096 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4097 4098 /* setup TDs */ 4099 dwc_otg_setup_standard_chain(xfer); 4100 4101 /* compute frame number for next insertion */ 4102 xfer->endpoint->isoc_next += msframes; 4103 4104 /* start TD chain */ 4105 dwc_otg_start_standard_chain(xfer); 4106 } 4107 4108 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4109 { 4110 .open = dwc_otg_device_isoc_open, 4111 .close = dwc_otg_device_isoc_close, 4112 .enter = dwc_otg_device_isoc_enter, 4113 .start = dwc_otg_device_isoc_start, 4114 }; 4115 4116 /*------------------------------------------------------------------------* 4117 * DWC OTG root control support 4118 *------------------------------------------------------------------------* 4119 * Simulate a hardware HUB by handling all the necessary requests. 4120 *------------------------------------------------------------------------*/ 4121 4122 static const struct usb_device_descriptor dwc_otg_devd = { 4123 .bLength = sizeof(struct usb_device_descriptor), 4124 .bDescriptorType = UDESC_DEVICE, 4125 .bcdUSB = {0x00, 0x02}, 4126 .bDeviceClass = UDCLASS_HUB, 4127 .bDeviceSubClass = UDSUBCLASS_HUB, 4128 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4129 .bMaxPacketSize = 64, 4130 .bcdDevice = {0x00, 0x01}, 4131 .iManufacturer = 1, 4132 .iProduct = 2, 4133 .bNumConfigurations = 1, 4134 }; 4135 4136 static const struct dwc_otg_config_desc dwc_otg_confd = { 4137 .confd = { 4138 .bLength = sizeof(struct usb_config_descriptor), 4139 .bDescriptorType = UDESC_CONFIG, 4140 .wTotalLength[0] = sizeof(dwc_otg_confd), 4141 .bNumInterface = 1, 4142 .bConfigurationValue = 1, 4143 .iConfiguration = 0, 4144 .bmAttributes = UC_SELF_POWERED, 4145 .bMaxPower = 0, 4146 }, 4147 .ifcd = { 4148 .bLength = sizeof(struct usb_interface_descriptor), 4149 .bDescriptorType = UDESC_INTERFACE, 4150 .bNumEndpoints = 1, 4151 .bInterfaceClass = UICLASS_HUB, 4152 .bInterfaceSubClass = UISUBCLASS_HUB, 4153 .bInterfaceProtocol = 0, 4154 }, 4155 .endpd = { 4156 .bLength = sizeof(struct usb_endpoint_descriptor), 4157 .bDescriptorType = UDESC_ENDPOINT, 4158 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4159 .bmAttributes = UE_INTERRUPT, 4160 .wMaxPacketSize[0] = 8, 4161 .bInterval = 255, 4162 }, 4163 }; 4164 4165 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4166 4167 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4168 .bDescLength = sizeof(dwc_otg_hubd), 4169 .bDescriptorType = UDESC_HUB, 4170 .bNbrPorts = 1, 4171 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4172 .bPwrOn2PwrGood = 50, 4173 .bHubContrCurrent = 0, 4174 .DeviceRemovable = {0}, /* port is removable */ 4175 }; 4176 4177 #define STRING_VENDOR \ 4178 "D\0W\0C\0O\0T\0G" 4179 4180 #define STRING_PRODUCT \ 4181 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4182 4183 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4184 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4185 4186 static usb_error_t 4187 dwc_otg_roothub_exec(struct usb_device *udev, 4188 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4189 { 4190 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4191 const void *ptr; 4192 uint16_t len; 4193 uint16_t value; 4194 uint16_t index; 4195 usb_error_t err; 4196 4197 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4198 4199 /* buffer reset */ 4200 ptr = (const void *)&sc->sc_hub_temp; 4201 len = 0; 4202 err = 0; 4203 4204 value = UGETW(req->wValue); 4205 index = UGETW(req->wIndex); 4206 4207 /* demultiplex the control request */ 4208 4209 switch (req->bmRequestType) { 4210 case UT_READ_DEVICE: 4211 switch (req->bRequest) { 4212 case UR_GET_DESCRIPTOR: 4213 goto tr_handle_get_descriptor; 4214 case UR_GET_CONFIG: 4215 goto tr_handle_get_config; 4216 case UR_GET_STATUS: 4217 goto tr_handle_get_status; 4218 default: 4219 goto tr_stalled; 4220 } 4221 break; 4222 4223 case UT_WRITE_DEVICE: 4224 switch (req->bRequest) { 4225 case UR_SET_ADDRESS: 4226 goto tr_handle_set_address; 4227 case UR_SET_CONFIG: 4228 goto tr_handle_set_config; 4229 case UR_CLEAR_FEATURE: 4230 goto tr_valid; /* nop */ 4231 case UR_SET_DESCRIPTOR: 4232 goto tr_valid; /* nop */ 4233 case UR_SET_FEATURE: 4234 default: 4235 goto tr_stalled; 4236 } 4237 break; 4238 4239 case UT_WRITE_ENDPOINT: 4240 switch (req->bRequest) { 4241 case UR_CLEAR_FEATURE: 4242 switch (UGETW(req->wValue)) { 4243 case UF_ENDPOINT_HALT: 4244 goto tr_handle_clear_halt; 4245 case UF_DEVICE_REMOTE_WAKEUP: 4246 goto tr_handle_clear_wakeup; 4247 default: 4248 goto tr_stalled; 4249 } 4250 break; 4251 case UR_SET_FEATURE: 4252 switch (UGETW(req->wValue)) { 4253 case UF_ENDPOINT_HALT: 4254 goto tr_handle_set_halt; 4255 case UF_DEVICE_REMOTE_WAKEUP: 4256 goto tr_handle_set_wakeup; 4257 default: 4258 goto tr_stalled; 4259 } 4260 break; 4261 case UR_SYNCH_FRAME: 4262 goto tr_valid; /* nop */ 4263 default: 4264 goto tr_stalled; 4265 } 4266 break; 4267 4268 case UT_READ_ENDPOINT: 4269 switch (req->bRequest) { 4270 case UR_GET_STATUS: 4271 goto tr_handle_get_ep_status; 4272 default: 4273 goto tr_stalled; 4274 } 4275 break; 4276 4277 case UT_WRITE_INTERFACE: 4278 switch (req->bRequest) { 4279 case UR_SET_INTERFACE: 4280 goto tr_handle_set_interface; 4281 case UR_CLEAR_FEATURE: 4282 goto tr_valid; /* nop */ 4283 case UR_SET_FEATURE: 4284 default: 4285 goto tr_stalled; 4286 } 4287 break; 4288 4289 case UT_READ_INTERFACE: 4290 switch (req->bRequest) { 4291 case UR_GET_INTERFACE: 4292 goto tr_handle_get_interface; 4293 case UR_GET_STATUS: 4294 goto tr_handle_get_iface_status; 4295 default: 4296 goto tr_stalled; 4297 } 4298 break; 4299 4300 case UT_WRITE_CLASS_INTERFACE: 4301 case UT_WRITE_VENDOR_INTERFACE: 4302 /* XXX forward */ 4303 break; 4304 4305 case UT_READ_CLASS_INTERFACE: 4306 case UT_READ_VENDOR_INTERFACE: 4307 /* XXX forward */ 4308 break; 4309 4310 case UT_WRITE_CLASS_DEVICE: 4311 switch (req->bRequest) { 4312 case UR_CLEAR_FEATURE: 4313 goto tr_valid; 4314 case UR_SET_DESCRIPTOR: 4315 case UR_SET_FEATURE: 4316 break; 4317 default: 4318 goto tr_stalled; 4319 } 4320 break; 4321 4322 case UT_WRITE_CLASS_OTHER: 4323 switch (req->bRequest) { 4324 case UR_CLEAR_FEATURE: 4325 goto tr_handle_clear_port_feature; 4326 case UR_SET_FEATURE: 4327 goto tr_handle_set_port_feature; 4328 case UR_CLEAR_TT_BUFFER: 4329 case UR_RESET_TT: 4330 case UR_STOP_TT: 4331 goto tr_valid; 4332 4333 default: 4334 goto tr_stalled; 4335 } 4336 break; 4337 4338 case UT_READ_CLASS_OTHER: 4339 switch (req->bRequest) { 4340 case UR_GET_TT_STATE: 4341 goto tr_handle_get_tt_state; 4342 case UR_GET_STATUS: 4343 goto tr_handle_get_port_status; 4344 default: 4345 goto tr_stalled; 4346 } 4347 break; 4348 4349 case UT_READ_CLASS_DEVICE: 4350 switch (req->bRequest) { 4351 case UR_GET_DESCRIPTOR: 4352 goto tr_handle_get_class_descriptor; 4353 case UR_GET_STATUS: 4354 goto tr_handle_get_class_status; 4355 4356 default: 4357 goto tr_stalled; 4358 } 4359 break; 4360 default: 4361 goto tr_stalled; 4362 } 4363 goto tr_valid; 4364 4365 tr_handle_get_descriptor: 4366 switch (value >> 8) { 4367 case UDESC_DEVICE: 4368 if (value & 0xff) { 4369 goto tr_stalled; 4370 } 4371 len = sizeof(dwc_otg_devd); 4372 ptr = (const void *)&dwc_otg_devd; 4373 goto tr_valid; 4374 case UDESC_CONFIG: 4375 if (value & 0xff) { 4376 goto tr_stalled; 4377 } 4378 len = sizeof(dwc_otg_confd); 4379 ptr = (const void *)&dwc_otg_confd; 4380 goto tr_valid; 4381 case UDESC_STRING: 4382 switch (value & 0xff) { 4383 case 0: /* Language table */ 4384 len = sizeof(usb_string_lang_en); 4385 ptr = (const void *)&usb_string_lang_en; 4386 goto tr_valid; 4387 4388 case 1: /* Vendor */ 4389 len = sizeof(dwc_otg_vendor); 4390 ptr = (const void *)&dwc_otg_vendor; 4391 goto tr_valid; 4392 4393 case 2: /* Product */ 4394 len = sizeof(dwc_otg_product); 4395 ptr = (const void *)&dwc_otg_product; 4396 goto tr_valid; 4397 default: 4398 break; 4399 } 4400 break; 4401 default: 4402 goto tr_stalled; 4403 } 4404 goto tr_stalled; 4405 4406 tr_handle_get_config: 4407 len = 1; 4408 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4409 goto tr_valid; 4410 4411 tr_handle_get_status: 4412 len = 2; 4413 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4414 goto tr_valid; 4415 4416 tr_handle_set_address: 4417 if (value & 0xFF00) { 4418 goto tr_stalled; 4419 } 4420 sc->sc_rt_addr = value; 4421 goto tr_valid; 4422 4423 tr_handle_set_config: 4424 if (value >= 2) { 4425 goto tr_stalled; 4426 } 4427 sc->sc_conf = value; 4428 goto tr_valid; 4429 4430 tr_handle_get_interface: 4431 len = 1; 4432 sc->sc_hub_temp.wValue[0] = 0; 4433 goto tr_valid; 4434 4435 tr_handle_get_tt_state: 4436 tr_handle_get_class_status: 4437 tr_handle_get_iface_status: 4438 tr_handle_get_ep_status: 4439 len = 2; 4440 USETW(sc->sc_hub_temp.wValue, 0); 4441 goto tr_valid; 4442 4443 tr_handle_set_halt: 4444 tr_handle_set_interface: 4445 tr_handle_set_wakeup: 4446 tr_handle_clear_wakeup: 4447 tr_handle_clear_halt: 4448 goto tr_valid; 4449 4450 tr_handle_clear_port_feature: 4451 if (index != 1) 4452 goto tr_stalled; 4453 4454 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4455 4456 switch (value) { 4457 case UHF_PORT_SUSPEND: 4458 dwc_otg_wakeup_peer(sc); 4459 break; 4460 4461 case UHF_PORT_ENABLE: 4462 if (sc->sc_flags.status_device_mode == 0) { 4463 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4464 sc->sc_hprt_val | HPRT_PRTENA); 4465 } 4466 sc->sc_flags.port_enabled = 0; 4467 break; 4468 4469 case UHF_C_PORT_RESET: 4470 sc->sc_flags.change_reset = 0; 4471 break; 4472 4473 case UHF_C_PORT_ENABLE: 4474 sc->sc_flags.change_enabled = 0; 4475 break; 4476 4477 case UHF_C_PORT_OVER_CURRENT: 4478 sc->sc_flags.change_over_current = 0; 4479 break; 4480 4481 case UHF_PORT_TEST: 4482 case UHF_PORT_INDICATOR: 4483 /* nops */ 4484 break; 4485 4486 case UHF_PORT_POWER: 4487 sc->sc_flags.port_powered = 0; 4488 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4489 sc->sc_hprt_val = 0; 4490 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4491 } 4492 dwc_otg_pull_down(sc); 4493 dwc_otg_clocks_off(sc); 4494 break; 4495 4496 case UHF_C_PORT_CONNECTION: 4497 /* clear connect change flag */ 4498 sc->sc_flags.change_connect = 0; 4499 break; 4500 4501 case UHF_C_PORT_SUSPEND: 4502 sc->sc_flags.change_suspend = 0; 4503 break; 4504 4505 default: 4506 err = USB_ERR_IOERROR; 4507 goto done; 4508 } 4509 goto tr_valid; 4510 4511 tr_handle_set_port_feature: 4512 if (index != 1) { 4513 goto tr_stalled; 4514 } 4515 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4516 4517 switch (value) { 4518 case UHF_PORT_ENABLE: 4519 break; 4520 4521 case UHF_PORT_SUSPEND: 4522 if (sc->sc_flags.status_device_mode == 0) { 4523 /* set suspend BIT */ 4524 sc->sc_hprt_val |= HPRT_PRTSUSP; 4525 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4526 4527 /* generate HUB suspend event */ 4528 dwc_otg_suspend_irq(sc); 4529 } 4530 break; 4531 4532 case UHF_PORT_RESET: 4533 if (sc->sc_flags.status_device_mode == 0) { 4534 4535 DPRINTF("PORT RESET\n"); 4536 4537 /* enable PORT reset */ 4538 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4539 4540 /* Wait 62.5ms for reset to complete */ 4541 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4542 4543 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4544 4545 /* Wait 62.5ms for reset to complete */ 4546 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4547 4548 /* reset FIFOs */ 4549 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4550 4551 sc->sc_flags.change_reset = 1; 4552 } else { 4553 err = USB_ERR_IOERROR; 4554 } 4555 break; 4556 4557 case UHF_PORT_TEST: 4558 case UHF_PORT_INDICATOR: 4559 /* nops */ 4560 break; 4561 case UHF_PORT_POWER: 4562 sc->sc_flags.port_powered = 1; 4563 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4564 sc->sc_hprt_val |= HPRT_PRTPWR; 4565 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4566 } 4567 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4568 /* pull up D+, if any */ 4569 dwc_otg_pull_up(sc); 4570 } 4571 break; 4572 default: 4573 err = USB_ERR_IOERROR; 4574 goto done; 4575 } 4576 goto tr_valid; 4577 4578 tr_handle_get_port_status: 4579 4580 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4581 4582 if (index != 1) 4583 goto tr_stalled; 4584 4585 if (sc->sc_flags.status_vbus) 4586 dwc_otg_clocks_on(sc); 4587 else 4588 dwc_otg_clocks_off(sc); 4589 4590 /* Select Device Side Mode */ 4591 4592 if (sc->sc_flags.status_device_mode) { 4593 value = UPS_PORT_MODE_DEVICE; 4594 dwc_otg_timer_stop(sc); 4595 } else { 4596 value = 0; 4597 dwc_otg_timer_start(sc); 4598 } 4599 4600 if (sc->sc_flags.status_high_speed) 4601 value |= UPS_HIGH_SPEED; 4602 else if (sc->sc_flags.status_low_speed) 4603 value |= UPS_LOW_SPEED; 4604 4605 if (sc->sc_flags.port_powered) 4606 value |= UPS_PORT_POWER; 4607 4608 if (sc->sc_flags.port_enabled) 4609 value |= UPS_PORT_ENABLED; 4610 4611 if (sc->sc_flags.port_over_current) 4612 value |= UPS_OVERCURRENT_INDICATOR; 4613 4614 if (sc->sc_flags.status_vbus && 4615 sc->sc_flags.status_bus_reset) 4616 value |= UPS_CURRENT_CONNECT_STATUS; 4617 4618 if (sc->sc_flags.status_suspend) 4619 value |= UPS_SUSPEND; 4620 4621 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4622 4623 value = 0; 4624 4625 if (sc->sc_flags.change_connect) 4626 value |= UPS_C_CONNECT_STATUS; 4627 if (sc->sc_flags.change_suspend) 4628 value |= UPS_C_SUSPEND; 4629 if (sc->sc_flags.change_reset) 4630 value |= UPS_C_PORT_RESET; 4631 if (sc->sc_flags.change_over_current) 4632 value |= UPS_C_OVERCURRENT_INDICATOR; 4633 4634 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4635 len = sizeof(sc->sc_hub_temp.ps); 4636 goto tr_valid; 4637 4638 tr_handle_get_class_descriptor: 4639 if (value & 0xFF) { 4640 goto tr_stalled; 4641 } 4642 ptr = (const void *)&dwc_otg_hubd; 4643 len = sizeof(dwc_otg_hubd); 4644 goto tr_valid; 4645 4646 tr_stalled: 4647 err = USB_ERR_STALLED; 4648 tr_valid: 4649 done: 4650 *plength = len; 4651 *pptr = ptr; 4652 return (err); 4653 } 4654 4655 static void 4656 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4657 { 4658 struct usb_xfer *xfer; 4659 void *last_obj; 4660 uint32_t ntd; 4661 uint32_t n; 4662 uint8_t ep_no; 4663 uint8_t ep_type; 4664 4665 xfer = parm->curr_xfer; 4666 4667 /* 4668 * NOTE: This driver does not use any of the parameters that 4669 * are computed from the following values. Just set some 4670 * reasonable dummies: 4671 */ 4672 parm->hc_max_packet_size = 0x500; 4673 parm->hc_max_packet_count = 3; 4674 parm->hc_max_frame_size = 3 * 0x500; 4675 4676 usbd_transfer_setup_sub(parm); 4677 4678 /* 4679 * compute maximum number of TDs 4680 */ 4681 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4682 4683 if (ep_type == UE_CONTROL) { 4684 4685 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4686 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4687 } else { 4688 4689 ntd = xfer->nframes + 1 /* SYNC */ ; 4690 } 4691 4692 /* 4693 * check if "usbd_transfer_setup_sub" set an error 4694 */ 4695 if (parm->err) 4696 return; 4697 4698 /* 4699 * allocate transfer descriptors 4700 */ 4701 last_obj = NULL; 4702 4703 ep_no = xfer->endpointno & UE_ADDR; 4704 4705 /* 4706 * Check for a valid endpoint profile in USB device mode: 4707 */ 4708 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4709 const struct usb_hw_ep_profile *pf; 4710 4711 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4712 4713 if (pf == NULL) { 4714 /* should not happen */ 4715 parm->err = USB_ERR_INVAL; 4716 return; 4717 } 4718 } 4719 4720 /* align data */ 4721 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4722 4723 for (n = 0; n != ntd; n++) { 4724 4725 struct dwc_otg_td *td; 4726 4727 if (parm->buf) { 4728 4729 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4730 4731 /* compute shared bandwidth resource index for TT */ 4732 if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) { 4733 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4734 td->tt_index = parm->udev->device_index; 4735 else 4736 td->tt_index = parm->udev->parent_hs_hub->device_index; 4737 } else { 4738 td->tt_index = parm->udev->device_index; 4739 } 4740 4741 /* init TD */ 4742 td->max_packet_size = xfer->max_packet_size; 4743 td->max_packet_count = xfer->max_packet_count; 4744 td->ep_no = ep_no; 4745 td->ep_type = ep_type; 4746 td->obj_next = last_obj; 4747 4748 last_obj = td; 4749 } 4750 parm->size[0] += sizeof(*td); 4751 } 4752 4753 xfer->td_start[0] = last_obj; 4754 } 4755 4756 static void 4757 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4758 { 4759 return; 4760 } 4761 4762 static void 4763 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4764 struct usb_endpoint *ep) 4765 { 4766 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4767 4768 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4769 ep, udev->address, 4770 edesc->bEndpointAddress, udev->flags.usb_mode, 4771 sc->sc_rt_addr, udev->device_index); 4772 4773 if (udev->device_index != sc->sc_rt_addr) { 4774 4775 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4776 if (udev->speed != USB_SPEED_FULL && 4777 udev->speed != USB_SPEED_HIGH) { 4778 /* not supported */ 4779 return; 4780 } 4781 } else { 4782 if (udev->speed == USB_SPEED_HIGH) { 4783 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { 4784 /* high bandwidth endpoint - not tested */ 4785 DPRINTF("High Bandwidth Endpoint - not tested\n"); 4786 return; 4787 } 4788 } 4789 } 4790 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4791 ep->methods = &dwc_otg_device_isoc_methods; 4792 else 4793 ep->methods = &dwc_otg_device_non_isoc_methods; 4794 } 4795 } 4796 4797 static void 4798 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4799 { 4800 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4801 4802 switch (state) { 4803 case USB_HW_POWER_SUSPEND: 4804 dwc_otg_suspend(sc); 4805 break; 4806 case USB_HW_POWER_SHUTDOWN: 4807 dwc_otg_uninit(sc); 4808 break; 4809 case USB_HW_POWER_RESUME: 4810 dwc_otg_resume(sc); 4811 break; 4812 default: 4813 break; 4814 } 4815 } 4816 4817 static void 4818 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4819 { 4820 /* DMA delay - wait until any use of memory is finished */ 4821 *pus = (2125); /* microseconds */ 4822 } 4823 4824 static void 4825 dwc_otg_device_resume(struct usb_device *udev) 4826 { 4827 DPRINTF("\n"); 4828 4829 /* poll all transfers again to restart resumed ones */ 4830 dwc_otg_do_poll(udev->bus); 4831 } 4832 4833 static void 4834 dwc_otg_device_suspend(struct usb_device *udev) 4835 { 4836 DPRINTF("\n"); 4837 } 4838 4839 static const struct usb_bus_methods dwc_otg_bus_methods = 4840 { 4841 .endpoint_init = &dwc_otg_ep_init, 4842 .xfer_setup = &dwc_otg_xfer_setup, 4843 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4844 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4845 .xfer_stall = &dwc_otg_xfer_stall, 4846 .set_stall = &dwc_otg_set_stall, 4847 .clear_stall = &dwc_otg_clear_stall, 4848 .roothub_exec = &dwc_otg_roothub_exec, 4849 .xfer_poll = &dwc_otg_do_poll, 4850 .device_state_change = &dwc_otg_device_state_change, 4851 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4852 .get_dma_delay = &dwc_otg_get_dma_delay, 4853 .device_resume = &dwc_otg_device_resume, 4854 .device_suspend = &dwc_otg_device_suspend, 4855 }; 4856