1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <machine/bus.h> 37 38 #include <dev/uart/uart.h> 39 #include <dev/uart/uart_cpu.h> 40 #include <dev/uart/uart_bus.h> 41 42 #include <dev/ic/sab82532.h> 43 44 #include "uart_if.h" 45 46 #define DEFAULT_RCLK 29491200 47 48 /* 49 * NOTE: To allow us to read the baudrate divisor from the chip, we 50 * copy the value written to the write-only BGR register to an unused 51 * read-write register. We use TCR for that. 52 */ 53 54 static int 55 sab82532_delay(struct uart_bas *bas) 56 { 57 int divisor, m, n; 58 uint8_t bgr, ccr2; 59 60 bgr = uart_getreg(bas, SAB_TCR); 61 ccr2 = uart_getreg(bas, SAB_CCR2); 62 n = (bgr & 0x3f) + 1; 63 m = (bgr >> 6) | ((ccr2 >> 4) & 0xC); 64 divisor = n * (1<<m); 65 66 /* 1/10th the time to transmit 1 character (estimate). */ 67 return (16000000 * divisor / bas->rclk); 68 } 69 70 static int 71 sab82532_divisor(int rclk, int baudrate) 72 { 73 int act_baud, act_div, divisor; 74 int error, m, n; 75 76 if (baudrate == 0) 77 return (0); 78 79 divisor = (rclk / (baudrate << 3) + 1) >> 1; 80 if (divisor < 2 || divisor >= 1048576) 81 return (0); 82 83 /* Find the best (N+1,M) pair. */ 84 for (m = 1; m < 15; m++) { 85 n = divisor / (1<<m); 86 if (n < 1 || n > 63) 87 continue; 88 act_div = n * (1<<m); 89 act_baud = rclk / (act_div << 4); 90 91 /* 10 times error in percent: */ 92 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 93 94 /* 3.0% maximum error tolerance: */ 95 if (error < -30 || error > 30) 96 continue; 97 98 /* Got it. */ 99 return ((n - 1) | (m << 6)); 100 } 101 102 return (0); 103 } 104 105 static void 106 sab82532_flush(struct uart_bas *bas, int what) 107 { 108 109 if (what & UART_FLUSH_TRANSMITTER) { 110 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 111 ; 112 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES); 113 uart_barrier(bas); 114 } 115 if (what & UART_FLUSH_RECEIVER) { 116 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 117 ; 118 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES); 119 uart_barrier(bas); 120 } 121 } 122 123 static int 124 sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 125 int parity) 126 { 127 int divisor; 128 uint8_t ccr2, dafo; 129 130 if (databits >= 8) 131 dafo = SAB_DAFO_CHL_CS8; 132 else if (databits == 7) 133 dafo = SAB_DAFO_CHL_CS7; 134 else if (databits == 6) 135 dafo = SAB_DAFO_CHL_CS6; 136 else 137 dafo = SAB_DAFO_CHL_CS5; 138 if (stopbits > 1) 139 dafo |= SAB_DAFO_STOP; 140 switch (parity) { 141 case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break; 142 case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break; 143 case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break; 144 case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break; 145 case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break; 146 default: return (EINVAL); 147 } 148 149 /* Set baudrate. */ 150 if (baudrate > 0) { 151 divisor = sab82532_divisor(bas->rclk, baudrate); 152 if (divisor == 0) 153 return (EINVAL); 154 uart_setreg(bas, SAB_BGR, divisor & 0xff); 155 uart_barrier(bas); 156 /* Allow reading the (n-1,m) tuple from the chip. */ 157 uart_setreg(bas, SAB_TCR, divisor & 0xff); 158 uart_barrier(bas); 159 ccr2 = uart_getreg(bas, SAB_CCR2); 160 ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8); 161 ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8); 162 uart_setreg(bas, SAB_CCR2, ccr2); 163 uart_barrier(bas); 164 } 165 166 uart_setreg(bas, SAB_DAFO, dafo); 167 uart_barrier(bas); 168 return (0); 169 } 170 171 /* 172 * Low-level UART interface. 173 */ 174 static int sab82532_probe(struct uart_bas *bas); 175 static void sab82532_init(struct uart_bas *bas, int, int, int, int); 176 static void sab82532_term(struct uart_bas *bas); 177 static void sab82532_putc(struct uart_bas *bas, int); 178 static int sab82532_rxready(struct uart_bas *bas); 179 static int sab82532_getc(struct uart_bas *bas, struct mtx *); 180 181 static struct uart_ops uart_sab82532_ops = { 182 .probe = sab82532_probe, 183 .init = sab82532_init, 184 .term = sab82532_term, 185 .putc = sab82532_putc, 186 .rxready = sab82532_rxready, 187 .getc = sab82532_getc, 188 }; 189 190 static int 191 sab82532_probe(struct uart_bas *bas) 192 { 193 194 return (0); 195 } 196 197 static void 198 sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 199 int parity) 200 { 201 uint8_t ccr0, pvr; 202 203 if (bas->rclk == 0) 204 bas->rclk = DEFAULT_RCLK; 205 206 /* 207 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs. 208 * Pin 4 is magical, meaning that I don't know what it does, but 209 * it too has to be set to output. 210 */ 211 uart_setreg(bas, SAB_PCR, 212 ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC)); 213 uart_barrier(bas); 214 /* Disable port interrupts. */ 215 uart_setreg(bas, SAB_PIM, 0xff); 216 uart_barrier(bas); 217 /* Interrupts are active low. */ 218 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL); 219 uart_barrier(bas); 220 /* Set DTR. */ 221 pvr = uart_getreg(bas, SAB_PVR); 222 switch (bas->chan) { 223 case 1: 224 pvr &= ~SAB_PVR_DTR_A; 225 break; 226 case 2: 227 pvr &= ~SAB_PVR_DTR_B; 228 break; 229 } 230 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC); 231 uart_barrier(bas); 232 233 /* power down */ 234 uart_setreg(bas, SAB_CCR0, 0); 235 uart_barrier(bas); 236 237 /* set basic configuration */ 238 ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC; 239 uart_setreg(bas, SAB_CCR0, ccr0); 240 uart_barrier(bas); 241 uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7); 242 uart_barrier(bas); 243 uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE); 244 uart_barrier(bas); 245 uart_setreg(bas, SAB_CCR3, 0); 246 uart_barrier(bas); 247 uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD); 248 uart_barrier(bas); 249 uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC); 250 uart_barrier(bas); 251 uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF| 252 SAB_RFC_RFTH_32CHAR); 253 uart_barrier(bas); 254 255 sab82532_param(bas, baudrate, databits, stopbits, parity); 256 257 /* Clear interrupts. */ 258 uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD); 259 uart_setreg(bas, SAB_IMR1, 0xff); 260 uart_barrier(bas); 261 uart_getreg(bas, SAB_ISR0); 262 uart_getreg(bas, SAB_ISR1); 263 uart_barrier(bas); 264 265 sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER); 266 267 /* Power up. */ 268 uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU); 269 uart_barrier(bas); 270 } 271 272 static void 273 sab82532_term(struct uart_bas *bas) 274 { 275 uint8_t pvr; 276 277 pvr = uart_getreg(bas, SAB_PVR); 278 switch (bas->chan) { 279 case 1: 280 pvr |= SAB_PVR_DTR_A; 281 break; 282 case 2: 283 pvr |= SAB_PVR_DTR_B; 284 break; 285 } 286 uart_setreg(bas, SAB_PVR, pvr); 287 uart_barrier(bas); 288 } 289 290 static void 291 sab82532_putc(struct uart_bas *bas, int c) 292 { 293 int delay, limit; 294 295 /* 1/10th the time to transmit 1 character (estimate). */ 296 delay = sab82532_delay(bas); 297 298 limit = 20; 299 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) 300 DELAY(delay); 301 uart_setreg(bas, SAB_TIC, c); 302 limit = 20; 303 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) 304 DELAY(delay); 305 } 306 307 static int 308 sab82532_rxready(struct uart_bas *bas) 309 { 310 311 return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0); 312 } 313 314 static int 315 sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx) 316 { 317 int c, delay; 318 319 uart_lock(hwmtx); 320 321 /* 1/10th the time to transmit 1 character (estimate). */ 322 delay = sab82532_delay(bas); 323 324 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) { 325 uart_unlock(hwmtx); 326 DELAY(delay); 327 uart_lock(hwmtx); 328 } 329 330 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 331 ; 332 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); 333 uart_barrier(bas); 334 335 while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD)) 336 DELAY(delay); 337 338 c = uart_getreg(bas, SAB_RFIFO); 339 uart_barrier(bas); 340 341 /* Blow away everything left in the FIFO... */ 342 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 343 ; 344 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); 345 uart_barrier(bas); 346 347 uart_unlock(hwmtx); 348 349 return (c); 350 } 351 352 /* 353 * High-level UART interface. 354 */ 355 struct sab82532_softc { 356 struct uart_softc base; 357 }; 358 359 static int sab82532_bus_attach(struct uart_softc *); 360 static int sab82532_bus_detach(struct uart_softc *); 361 static int sab82532_bus_flush(struct uart_softc *, int); 362 static int sab82532_bus_getsig(struct uart_softc *); 363 static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t); 364 static int sab82532_bus_ipend(struct uart_softc *); 365 static int sab82532_bus_param(struct uart_softc *, int, int, int, int); 366 static int sab82532_bus_probe(struct uart_softc *); 367 static int sab82532_bus_receive(struct uart_softc *); 368 static int sab82532_bus_setsig(struct uart_softc *, int); 369 static int sab82532_bus_transmit(struct uart_softc *); 370 static void sab82532_bus_grab(struct uart_softc *); 371 static void sab82532_bus_ungrab(struct uart_softc *); 372 373 static kobj_method_t sab82532_methods[] = { 374 KOBJMETHOD(uart_attach, sab82532_bus_attach), 375 KOBJMETHOD(uart_detach, sab82532_bus_detach), 376 KOBJMETHOD(uart_flush, sab82532_bus_flush), 377 KOBJMETHOD(uart_getsig, sab82532_bus_getsig), 378 KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl), 379 KOBJMETHOD(uart_ipend, sab82532_bus_ipend), 380 KOBJMETHOD(uart_param, sab82532_bus_param), 381 KOBJMETHOD(uart_probe, sab82532_bus_probe), 382 KOBJMETHOD(uart_receive, sab82532_bus_receive), 383 KOBJMETHOD(uart_setsig, sab82532_bus_setsig), 384 KOBJMETHOD(uart_transmit, sab82532_bus_transmit), 385 KOBJMETHOD(uart_grab, sab82532_bus_grab), 386 KOBJMETHOD(uart_ungrab, sab82532_bus_ungrab), 387 { 0, 0 } 388 }; 389 390 struct uart_class uart_sab82532_class = { 391 "sab82532", 392 sab82532_methods, 393 sizeof(struct sab82532_softc), 394 .uc_ops = &uart_sab82532_ops, 395 .uc_range = 64, 396 .uc_rclk = DEFAULT_RCLK, 397 .uc_rshift = 0 398 }; 399 400 #define SIGCHG(c, i, s, d) \ 401 if (c) { \ 402 i |= (i & s) ? s : s | d; \ 403 } else { \ 404 i = (i & s) ? (i & ~s) | d : i; \ 405 } 406 407 static int 408 sab82532_bus_attach(struct uart_softc *sc) 409 { 410 struct uart_bas *bas; 411 uint8_t imr0, imr1; 412 413 bas = &sc->sc_bas; 414 if (sc->sc_sysdev == NULL) 415 sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE); 416 417 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO| 418 SAB_IMR0_RPF; 419 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); 420 imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC; 421 uart_setreg(bas, SAB_IMR1, 0xff & ~imr1); 422 uart_barrier(bas); 423 424 if (sc->sc_sysdev == NULL) 425 sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS); 426 (void)sab82532_bus_getsig(sc); 427 return (0); 428 } 429 430 static int 431 sab82532_bus_detach(struct uart_softc *sc) 432 { 433 struct uart_bas *bas; 434 435 bas = &sc->sc_bas; 436 uart_setreg(bas, SAB_IMR0, 0xff); 437 uart_setreg(bas, SAB_IMR1, 0xff); 438 uart_barrier(bas); 439 uart_getreg(bas, SAB_ISR0); 440 uart_getreg(bas, SAB_ISR1); 441 uart_barrier(bas); 442 uart_setreg(bas, SAB_CCR0, 0); 443 uart_barrier(bas); 444 return (0); 445 } 446 447 static int 448 sab82532_bus_flush(struct uart_softc *sc, int what) 449 { 450 451 uart_lock(sc->sc_hwmtx); 452 sab82532_flush(&sc->sc_bas, what); 453 uart_unlock(sc->sc_hwmtx); 454 return (0); 455 } 456 457 static int 458 sab82532_bus_getsig(struct uart_softc *sc) 459 { 460 struct uart_bas *bas; 461 uint32_t new, old, sig; 462 uint8_t pvr, star, vstr; 463 464 bas = &sc->sc_bas; 465 do { 466 old = sc->sc_hwsig; 467 sig = old; 468 uart_lock(sc->sc_hwmtx); 469 star = uart_getreg(bas, SAB_STAR); 470 SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS); 471 vstr = uart_getreg(bas, SAB_VSTR); 472 SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD); 473 pvr = ~uart_getreg(bas, SAB_PVR); 474 switch (bas->chan) { 475 case 1: 476 pvr &= SAB_PVR_DSR_A; 477 break; 478 case 2: 479 pvr &= SAB_PVR_DSR_B; 480 break; 481 } 482 SIGCHG(pvr, sig, SER_DSR, SER_DDSR); 483 uart_unlock(sc->sc_hwmtx); 484 new = sig & ~SER_MASK_DELTA; 485 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 486 return (sig); 487 } 488 489 static int 490 sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 491 { 492 struct uart_bas *bas; 493 uint8_t dafo, mode; 494 int error; 495 496 bas = &sc->sc_bas; 497 error = 0; 498 uart_lock(sc->sc_hwmtx); 499 switch (request) { 500 case UART_IOCTL_BREAK: 501 dafo = uart_getreg(bas, SAB_DAFO); 502 if (data) 503 dafo |= SAB_DAFO_XBRK; 504 else 505 dafo &= ~SAB_DAFO_XBRK; 506 uart_setreg(bas, SAB_DAFO, dafo); 507 uart_barrier(bas); 508 break; 509 case UART_IOCTL_IFLOW: 510 mode = uart_getreg(bas, SAB_MODE); 511 if (data) { 512 mode &= ~SAB_MODE_RTS; 513 mode |= SAB_MODE_FRTS; 514 } else { 515 mode |= SAB_MODE_RTS; 516 mode &= ~SAB_MODE_FRTS; 517 } 518 uart_setreg(bas, SAB_MODE, mode); 519 uart_barrier(bas); 520 break; 521 case UART_IOCTL_OFLOW: 522 mode = uart_getreg(bas, SAB_MODE); 523 if (data) 524 mode &= ~SAB_MODE_FCTS; 525 else 526 mode |= SAB_MODE_FCTS; 527 uart_setreg(bas, SAB_MODE, mode); 528 uart_barrier(bas); 529 break; 530 default: 531 error = EINVAL; 532 break; 533 } 534 uart_unlock(sc->sc_hwmtx); 535 return (error); 536 } 537 538 static int 539 sab82532_bus_ipend(struct uart_softc *sc) 540 { 541 struct uart_bas *bas; 542 int ipend; 543 uint8_t isr0, isr1; 544 545 bas = &sc->sc_bas; 546 uart_lock(sc->sc_hwmtx); 547 isr0 = uart_getreg(bas, SAB_ISR0); 548 isr1 = uart_getreg(bas, SAB_ISR1); 549 uart_barrier(bas); 550 if (isr0 & SAB_ISR0_TIME) { 551 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 552 ; 553 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD); 554 uart_barrier(bas); 555 } 556 uart_unlock(sc->sc_hwmtx); 557 558 ipend = 0; 559 if (isr1 & SAB_ISR1_BRKT) 560 ipend |= SER_INT_BREAK; 561 if (isr0 & SAB_ISR0_RFO) 562 ipend |= SER_INT_OVERRUN; 563 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF)) 564 ipend |= SER_INT_RXREADY; 565 if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC)) 566 ipend |= SER_INT_SIGCHG; 567 if (isr1 & SAB_ISR1_ALLS) 568 ipend |= SER_INT_TXIDLE; 569 570 return (ipend); 571 } 572 573 static int 574 sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits, 575 int stopbits, int parity) 576 { 577 struct uart_bas *bas; 578 int error; 579 580 bas = &sc->sc_bas; 581 uart_lock(sc->sc_hwmtx); 582 error = sab82532_param(bas, baudrate, databits, stopbits, parity); 583 uart_unlock(sc->sc_hwmtx); 584 return (error); 585 } 586 587 static int 588 sab82532_bus_probe(struct uart_softc *sc) 589 { 590 char buf[80]; 591 const char *vstr; 592 int error; 593 char ch; 594 595 error = sab82532_probe(&sc->sc_bas); 596 if (error) 597 return (error); 598 599 sc->sc_rxfifosz = 32; 600 sc->sc_txfifosz = 32; 601 602 ch = sc->sc_bas.chan - 1 + 'A'; 603 604 switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) { 605 case SAB_VSTR_V_1: 606 vstr = "v1"; 607 break; 608 case SAB_VSTR_V_2: 609 vstr = "v2"; 610 break; 611 case SAB_VSTR_V_32: 612 vstr = "v3.2"; 613 sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */ 614 sc->sc_hwoflow = 1; 615 break; 616 default: 617 vstr = "v4?"; 618 break; 619 } 620 621 snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch); 622 device_set_desc_copy(sc->sc_dev, buf); 623 return (0); 624 } 625 626 static int 627 sab82532_bus_receive(struct uart_softc *sc) 628 { 629 struct uart_bas *bas; 630 int i, rbcl, xc; 631 uint8_t s; 632 633 bas = &sc->sc_bas; 634 uart_lock(sc->sc_hwmtx); 635 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) { 636 rbcl = uart_getreg(bas, SAB_RBCL) & 31; 637 if (rbcl == 0) 638 rbcl = 32; 639 for (i = 0; i < rbcl; i += 2) { 640 if (uart_rx_full(sc)) { 641 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 642 break; 643 } 644 xc = uart_getreg(bas, SAB_RFIFO); 645 s = uart_getreg(bas, SAB_RFIFO + 1); 646 if (s & SAB_RSTAT_FE) 647 xc |= UART_STAT_FRAMERR; 648 if (s & SAB_RSTAT_PE) 649 xc |= UART_STAT_PARERR; 650 uart_rx_put(sc, xc); 651 } 652 } 653 654 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 655 ; 656 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC); 657 uart_barrier(bas); 658 uart_unlock(sc->sc_hwmtx); 659 return (0); 660 } 661 662 static int 663 sab82532_bus_setsig(struct uart_softc *sc, int sig) 664 { 665 struct uart_bas *bas; 666 uint32_t new, old; 667 uint8_t mode, pvr; 668 669 bas = &sc->sc_bas; 670 do { 671 old = sc->sc_hwsig; 672 new = old; 673 if (sig & SER_DDTR) { 674 SIGCHG(sig & SER_DTR, new, SER_DTR, 675 SER_DDTR); 676 } 677 if (sig & SER_DRTS) { 678 SIGCHG(sig & SER_RTS, new, SER_RTS, 679 SER_DRTS); 680 } 681 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 682 683 uart_lock(sc->sc_hwmtx); 684 /* Set DTR pin. */ 685 pvr = uart_getreg(bas, SAB_PVR); 686 switch (bas->chan) { 687 case 1: 688 if (new & SER_DTR) 689 pvr &= ~SAB_PVR_DTR_A; 690 else 691 pvr |= SAB_PVR_DTR_A; 692 break; 693 case 2: 694 if (new & SER_DTR) 695 pvr &= ~SAB_PVR_DTR_B; 696 else 697 pvr |= SAB_PVR_DTR_B; 698 break; 699 } 700 uart_setreg(bas, SAB_PVR, pvr); 701 702 /* Set RTS pin. */ 703 mode = uart_getreg(bas, SAB_MODE); 704 if (new & SER_RTS) 705 mode &= ~SAB_MODE_FRTS; 706 else 707 mode |= SAB_MODE_FRTS; 708 uart_setreg(bas, SAB_MODE, mode); 709 uart_barrier(bas); 710 uart_unlock(sc->sc_hwmtx); 711 return (0); 712 } 713 714 static int 715 sab82532_bus_transmit(struct uart_softc *sc) 716 { 717 struct uart_bas *bas; 718 int i; 719 720 bas = &sc->sc_bas; 721 uart_lock(sc->sc_hwmtx); 722 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW)) 723 ; 724 for (i = 0; i < sc->sc_txdatasz; i++) 725 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]); 726 uart_barrier(bas); 727 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) 728 ; 729 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF); 730 sc->sc_txbusy = 1; 731 uart_unlock(sc->sc_hwmtx); 732 return (0); 733 } 734 735 static void 736 sab82532_bus_grab(struct uart_softc *sc) 737 { 738 struct uart_bas *bas; 739 uint8_t imr0; 740 741 bas = &sc->sc_bas; 742 imr0 = SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO; /* No TCD or RPF */ 743 uart_lock(sc->sc_hwmtx); 744 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); 745 uart_barrier(bas); 746 uart_unlock(sc->sc_hwmtx); 747 } 748 749 static void 750 sab82532_bus_ungrab(struct uart_softc *sc) 751 { 752 struct uart_bas *bas; 753 uint8_t imr0; 754 755 bas = &sc->sc_bas; 756 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO| 757 SAB_IMR0_RPF; 758 uart_lock(sc->sc_hwmtx); 759 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0); 760 uart_barrier(bas); 761 uart_unlock(sc->sc_hwmtx); 762 } 763