1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <machine/bus.h> 40 41 #include <dev/uart/uart.h> 42 #include <dev/uart/uart_cpu.h> 43 #ifdef FDT 44 #include <dev/uart/uart_cpu_fdt.h> 45 #include <dev/ofw/ofw_bus.h> 46 #endif 47 #include <dev/uart/uart_bus.h> 48 #include "uart_if.h" 49 50 #ifdef DEV_ACPI 51 #include <dev/uart/uart_cpu_acpi.h> 52 #include <contrib/dev/acpica/include/acpi.h> 53 #include <contrib/dev/acpica/include/accommon.h> 54 #include <contrib/dev/acpica/include/actables.h> 55 #endif 56 57 #include <sys/kdb.h> 58 59 /* PL011 UART registers and masks*/ 60 #define UART_DR 0x00 /* Data register */ 61 #define DR_FE (1 << 8) /* Framing error */ 62 #define DR_PE (1 << 9) /* Parity error */ 63 #define DR_BE (1 << 10) /* Break error */ 64 #define DR_OE (1 << 11) /* Overrun error */ 65 66 #define UART_FR 0x06 /* Flag register */ 67 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */ 68 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 69 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 70 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 71 72 #define UART_IBRD 0x09 /* Integer baud rate register */ 73 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 74 75 #define UART_FBRD 0x0a /* Fractional baud rate register */ 76 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 77 78 #define UART_LCR_H 0x0b /* Line control register */ 79 #define LCR_H_WLEN8 (0x3 << 5) 80 #define LCR_H_WLEN7 (0x2 << 5) 81 #define LCR_H_WLEN6 (0x1 << 5) 82 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 83 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 84 #define LCR_H_EPS (1 << 2) /* Even parity select */ 85 #define LCR_H_PEN (1 << 1) /* Parity enable */ 86 87 #define UART_CR 0x0c /* Control register */ 88 #define CR_RXE (1 << 9) /* Receive enable */ 89 #define CR_TXE (1 << 8) /* Transmit enable */ 90 #define CR_UARTEN (1 << 0) /* UART enable */ 91 92 #define UART_IFLS 0x0d /* FIFO level select register */ 93 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */ 94 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */ 95 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */ 96 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */ 97 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */ 98 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */ 99 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */ 100 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */ 101 102 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 103 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 104 105 #define UART_RIS 0x0f /* Raw interrupt status register */ 106 #define UART_RXREADY (1 << 4) /* RX buffer full */ 107 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 108 #define RIS_RTIM (1 << 6) /* Receive timeout */ 109 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 110 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 111 #define RIS_BE (1 << 9) /* Break error interrupt status */ 112 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 113 114 #define UART_MIS 0x10 /* Masked interrupt status register */ 115 #define UART_ICR 0x11 /* Interrupt clear register */ 116 117 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */ 118 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */ 119 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */ 120 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */ 121 122 /* 123 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes 124 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For 125 * RX we set the size to the full hardware capacity so that the uart core 126 * allocates enough buffer space to hold a complete fifo full of incoming data. 127 * For TX, we need to limit the size to the capacity we know will be available 128 * when the interrupt occurs; uart_core will feed exactly that many bytes to 129 * uart_pl011_bus_transmit() which must consume them all. 130 */ 131 #define FIFO_RX_SIZE_R2 16 132 #define FIFO_TX_SIZE_R2 12 133 #define FIFO_RX_SIZE_R3 32 134 #define FIFO_TX_SIZE_R3 24 135 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th)) 136 137 /* 138 * FIXME: actual register size is SoC-dependent, we need to handle it 139 */ 140 #define __uart_getreg(bas, reg) \ 141 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 142 #define __uart_setreg(bas, reg, value) \ 143 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 144 145 /* 146 * Low-level UART interface. 147 */ 148 static int uart_pl011_probe(struct uart_bas *bas); 149 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 150 static void uart_pl011_term(struct uart_bas *bas); 151 static void uart_pl011_putc(struct uart_bas *bas, int); 152 static int uart_pl011_rxready(struct uart_bas *bas); 153 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 154 155 static struct uart_ops uart_pl011_ops = { 156 .probe = uart_pl011_probe, 157 .init = uart_pl011_init, 158 .term = uart_pl011_term, 159 .putc = uart_pl011_putc, 160 .rxready = uart_pl011_rxready, 161 .getc = uart_pl011_getc, 162 }; 163 164 static int 165 uart_pl011_probe(struct uart_bas *bas) 166 { 167 168 return (0); 169 } 170 171 static void 172 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 173 int parity) 174 { 175 uint32_t ctrl, line; 176 uint32_t baud; 177 178 /* 179 * Zero all settings to make sure 180 * UART is disabled and not configured 181 */ 182 ctrl = line = 0x0; 183 __uart_setreg(bas, UART_CR, ctrl); 184 185 /* As we know UART is disabled we may setup the line */ 186 switch (databits) { 187 case 7: 188 line |= LCR_H_WLEN7; 189 break; 190 case 6: 191 line |= LCR_H_WLEN6; 192 break; 193 case 8: 194 default: 195 line |= LCR_H_WLEN8; 196 break; 197 } 198 199 if (stopbits == 2) 200 line |= LCR_H_STP2; 201 else 202 line &= ~LCR_H_STP2; 203 204 if (parity) 205 line |= LCR_H_PEN; 206 else 207 line &= ~LCR_H_PEN; 208 line |= LCR_H_FEN; 209 210 /* Configure the rest */ 211 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 212 213 if (bas->rclk != 0 && baudrate != 0) { 214 baud = bas->rclk * 4 / baudrate; 215 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 216 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 217 } 218 219 /* Add config. to line before reenabling UART */ 220 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 221 ~0xff) | line); 222 223 /* Set rx and tx fifo levels. */ 224 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS); 225 226 __uart_setreg(bas, UART_CR, ctrl); 227 } 228 229 static void 230 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 231 int parity) 232 { 233 /* Mask all interrupts */ 234 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 235 ~IMSC_MASK_ALL); 236 237 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 238 } 239 240 static void 241 uart_pl011_term(struct uart_bas *bas) 242 { 243 } 244 245 static void 246 uart_pl011_putc(struct uart_bas *bas, int c) 247 { 248 249 /* Wait when TX FIFO full. Push character otherwise. */ 250 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 251 ; 252 __uart_setreg(bas, UART_DR, c & 0xff); 253 } 254 255 static int 256 uart_pl011_rxready(struct uart_bas *bas) 257 { 258 259 return !(__uart_getreg(bas, UART_FR) & FR_RXFE); 260 } 261 262 static int 263 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 264 { 265 int c; 266 267 while (!uart_pl011_rxready(bas)) 268 ; 269 c = __uart_getreg(bas, UART_DR) & 0xff; 270 271 return (c); 272 } 273 274 /* 275 * High-level UART interface. 276 */ 277 struct uart_pl011_softc { 278 struct uart_softc base; 279 uint16_t imsc; /* Interrupt mask */ 280 }; 281 282 static int uart_pl011_bus_attach(struct uart_softc *); 283 static int uart_pl011_bus_detach(struct uart_softc *); 284 static int uart_pl011_bus_flush(struct uart_softc *, int); 285 static int uart_pl011_bus_getsig(struct uart_softc *); 286 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 287 static int uart_pl011_bus_ipend(struct uart_softc *); 288 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 289 static int uart_pl011_bus_probe(struct uart_softc *); 290 static int uart_pl011_bus_receive(struct uart_softc *); 291 static int uart_pl011_bus_setsig(struct uart_softc *, int); 292 static int uart_pl011_bus_transmit(struct uart_softc *); 293 static void uart_pl011_bus_grab(struct uart_softc *); 294 static void uart_pl011_bus_ungrab(struct uart_softc *); 295 296 static kobj_method_t uart_pl011_methods[] = { 297 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 298 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 299 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 300 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 301 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 302 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 303 KOBJMETHOD(uart_param, uart_pl011_bus_param), 304 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 305 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 306 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 307 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 308 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 309 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 310 311 { 0, 0 } 312 }; 313 314 static struct uart_class uart_pl011_class = { 315 "uart_pl011", 316 uart_pl011_methods, 317 sizeof(struct uart_pl011_softc), 318 .uc_ops = &uart_pl011_ops, 319 .uc_range = 0x48, 320 .uc_rclk = 0, 321 .uc_rshift = 2 322 }; 323 324 325 #ifdef FDT 326 static struct ofw_compat_data fdt_compat_data[] = { 327 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 328 {NULL, (uintptr_t)NULL}, 329 }; 330 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data); 331 #endif 332 333 #ifdef DEV_ACPI 334 static struct acpi_uart_compat_data acpi_compat_data[] = { 335 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011}, 336 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC}, 337 {NULL, NULL, 0}, 338 }; 339 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 340 #endif 341 342 static int 343 uart_pl011_bus_attach(struct uart_softc *sc) 344 { 345 struct uart_pl011_softc *psc; 346 struct uart_bas *bas; 347 348 psc = (struct uart_pl011_softc *)sc; 349 bas = &sc->sc_bas; 350 351 /* Enable interrupts */ 352 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 353 __uart_setreg(bas, UART_IMSC, psc->imsc); 354 355 /* Clear interrupts */ 356 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 357 358 return (0); 359 } 360 361 static int 362 uart_pl011_bus_detach(struct uart_softc *sc) 363 { 364 365 return (0); 366 } 367 368 static int 369 uart_pl011_bus_flush(struct uart_softc *sc, int what) 370 { 371 372 return (0); 373 } 374 375 static int 376 uart_pl011_bus_getsig(struct uart_softc *sc) 377 { 378 379 return (0); 380 } 381 382 static int 383 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 384 { 385 int error; 386 387 error = 0; 388 uart_lock(sc->sc_hwmtx); 389 switch (request) { 390 case UART_IOCTL_BREAK: 391 break; 392 case UART_IOCTL_BAUD: 393 *(int*)data = 115200; 394 break; 395 default: 396 error = EINVAL; 397 break; 398 } 399 uart_unlock(sc->sc_hwmtx); 400 401 return (error); 402 } 403 404 static int 405 uart_pl011_bus_ipend(struct uart_softc *sc) 406 { 407 struct uart_pl011_softc *psc; 408 struct uart_bas *bas; 409 uint32_t ints; 410 int ipend; 411 412 psc = (struct uart_pl011_softc *)sc; 413 bas = &sc->sc_bas; 414 415 uart_lock(sc->sc_hwmtx); 416 ints = __uart_getreg(bas, UART_MIS); 417 ipend = 0; 418 419 if (ints & (UART_RXREADY | RIS_RTIM)) 420 ipend |= SER_INT_RXREADY; 421 if (ints & RIS_BE) 422 ipend |= SER_INT_BREAK; 423 if (ints & RIS_OE) 424 ipend |= SER_INT_OVERRUN; 425 if (ints & UART_TXEMPTY) { 426 if (sc->sc_txbusy) 427 ipend |= SER_INT_TXIDLE; 428 429 /* Disable TX interrupt */ 430 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); 431 } 432 433 uart_unlock(sc->sc_hwmtx); 434 435 return (ipend); 436 } 437 438 static int 439 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 440 int stopbits, int parity) 441 { 442 443 uart_lock(sc->sc_hwmtx); 444 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 445 uart_unlock(sc->sc_hwmtx); 446 447 return (0); 448 } 449 450 static int 451 uart_pl011_bus_probe(struct uart_softc *sc) 452 { 453 uint8_t hwrev; 454 #ifdef FDT 455 pcell_t node; 456 uint32_t periphid; 457 458 /* 459 * The FIFO sizes vary depending on hardware; rev 2 and below have 16 460 * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the 461 * primecell periphid register, but we get a bit of drama, as always, 462 * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte 463 * FIFOs. We check for both the old freebsd-historic and the proper 464 * bindings-defined compatible strings for bcm2835, and also check the 465 * workaround the linux drivers use for rpi3, which is to override the 466 * primecell periphid register value with a property. 467 */ 468 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || 469 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { 470 hwrev = 2; 471 } else { 472 node = ofw_bus_get_node(sc->sc_dev); 473 if (OF_getencprop(node, "arm,primecell-periphid", &periphid, 474 sizeof(periphid)) > 0) { 475 hwrev = (periphid >> 20) & 0x0f; 476 } else { 477 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 478 } 479 } 480 #else 481 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 482 #endif 483 if (hwrev <= 2) { 484 sc->sc_rxfifosz = FIFO_RX_SIZE_R2; 485 sc->sc_txfifosz = FIFO_TX_SIZE_R2; 486 } else { 487 sc->sc_rxfifosz = FIFO_RX_SIZE_R3; 488 sc->sc_txfifosz = FIFO_TX_SIZE_R3; 489 } 490 491 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 492 493 return (0); 494 } 495 496 static int 497 uart_pl011_bus_receive(struct uart_softc *sc) 498 { 499 struct uart_bas *bas; 500 uint32_t ints, xc; 501 int rx; 502 503 bas = &sc->sc_bas; 504 uart_lock(sc->sc_hwmtx); 505 506 for (;;) { 507 ints = __uart_getreg(bas, UART_FR); 508 if (ints & FR_RXFE) 509 break; 510 if (uart_rx_full(sc)) { 511 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 512 break; 513 } 514 515 xc = __uart_getreg(bas, UART_DR); 516 rx = xc & 0xff; 517 518 if (xc & DR_FE) 519 rx |= UART_STAT_FRAMERR; 520 if (xc & DR_PE) 521 rx |= UART_STAT_PARERR; 522 523 uart_rx_put(sc, rx); 524 } 525 526 uart_unlock(sc->sc_hwmtx); 527 528 return (0); 529 } 530 531 static int 532 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 533 { 534 535 return (0); 536 } 537 538 static int 539 uart_pl011_bus_transmit(struct uart_softc *sc) 540 { 541 struct uart_pl011_softc *psc; 542 struct uart_bas *bas; 543 int i; 544 545 psc = (struct uart_pl011_softc *)sc; 546 bas = &sc->sc_bas; 547 uart_lock(sc->sc_hwmtx); 548 549 for (i = 0; i < sc->sc_txdatasz; i++) { 550 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 551 uart_barrier(bas); 552 } 553 554 /* Mark busy and enable TX interrupt */ 555 sc->sc_txbusy = 1; 556 __uart_setreg(bas, UART_IMSC, psc->imsc); 557 558 uart_unlock(sc->sc_hwmtx); 559 560 return (0); 561 } 562 563 static void 564 uart_pl011_bus_grab(struct uart_softc *sc) 565 { 566 struct uart_pl011_softc *psc; 567 struct uart_bas *bas; 568 569 psc = (struct uart_pl011_softc *)sc; 570 bas = &sc->sc_bas; 571 572 /* Disable interrupts on switch to polling */ 573 uart_lock(sc->sc_hwmtx); 574 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); 575 uart_unlock(sc->sc_hwmtx); 576 } 577 578 static void 579 uart_pl011_bus_ungrab(struct uart_softc *sc) 580 { 581 struct uart_pl011_softc *psc; 582 struct uart_bas *bas; 583 584 psc = (struct uart_pl011_softc *)sc; 585 bas = &sc->sc_bas; 586 587 /* Switch to using interrupts while not grabbed */ 588 uart_lock(sc->sc_hwmtx); 589 __uart_setreg(bas, UART_IMSC, psc->imsc); 590 uart_unlock(sc->sc_hwmtx); 591 } 592