1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997 Semen Ustimenko ([email protected]) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie) 34 * 35 * These cards are based on SMC83c17x (EPIC) chip and one of the various 36 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on 37 * card model. All cards support 10baseT/UTP and 100baseTX half- and full- 38 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also 39 * supports fibre optics. 40 * 41 * Thanks are going to Steve Bauer and Jason Wright. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/sockio.h> 47 #include <sys/mbuf.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/module.h> 51 #include <sys/socket.h> 52 #include <sys/queue.h> 53 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_arp.h> 57 #include <net/ethernet.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_types.h> 61 62 #include <net/bpf.h> 63 64 #include <net/if_vlan_var.h> 65 66 #include <machine/bus.h> 67 #include <machine/resource.h> 68 #include <sys/bus.h> 69 #include <sys/rman.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/mii/mii.h> 75 #include <dev/mii/miivar.h> 76 #include "miidevs.h" 77 78 #include <dev/mii/lxtphyreg.h> 79 80 #include "miibus_if.h" 81 82 #include <dev/tx/if_txreg.h> 83 #include <dev/tx/if_txvar.h> 84 85 MODULE_DEPEND(tx, pci, 1, 1, 1); 86 MODULE_DEPEND(tx, ether, 1, 1, 1); 87 MODULE_DEPEND(tx, miibus, 1, 1, 1); 88 89 static int epic_ifioctl(struct ifnet *, u_long, caddr_t); 90 static void epic_intr(void *); 91 static void epic_tx_underrun(epic_softc_t *); 92 static void epic_ifstart(struct ifnet *); 93 static void epic_ifstart_locked(struct ifnet *); 94 static void epic_timer(void *); 95 static void epic_init(void *); 96 static void epic_init_locked(epic_softc_t *); 97 static void epic_stop(epic_softc_t *); 98 static void epic_rx_done(epic_softc_t *); 99 static void epic_tx_done(epic_softc_t *); 100 static int epic_init_rings(epic_softc_t *); 101 static void epic_free_rings(epic_softc_t *); 102 static void epic_stop_activity(epic_softc_t *); 103 static int epic_queue_last_packet(epic_softc_t *); 104 static void epic_start_activity(epic_softc_t *); 105 static void epic_set_rx_mode(epic_softc_t *); 106 static void epic_set_tx_mode(epic_softc_t *); 107 static void epic_set_mc_table(epic_softc_t *); 108 static int epic_read_eeprom(epic_softc_t *,u_int16_t); 109 static void epic_output_eepromw(epic_softc_t *, u_int16_t); 110 static u_int16_t epic_input_eepromw(epic_softc_t *); 111 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t); 112 static void epic_write_eepromreg(epic_softc_t *,u_int8_t); 113 static u_int8_t epic_read_eepromreg(epic_softc_t *); 114 115 static int epic_read_phy_reg(epic_softc_t *, int, int); 116 static void epic_write_phy_reg(epic_softc_t *, int, int, int); 117 118 static int epic_miibus_readreg(device_t, int, int); 119 static int epic_miibus_writereg(device_t, int, int, int); 120 static void epic_miibus_statchg(device_t); 121 static void epic_miibus_mediainit(device_t); 122 123 static int epic_ifmedia_upd(struct ifnet *); 124 static int epic_ifmedia_upd_locked(struct ifnet *); 125 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *); 126 127 static int epic_probe(device_t); 128 static int epic_attach(device_t); 129 static int epic_shutdown(device_t); 130 static int epic_detach(device_t); 131 static void epic_release(epic_softc_t *); 132 static struct epic_type *epic_devtype(device_t); 133 134 static device_method_t epic_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, epic_probe), 137 DEVMETHOD(device_attach, epic_attach), 138 DEVMETHOD(device_detach, epic_detach), 139 DEVMETHOD(device_shutdown, epic_shutdown), 140 141 /* MII interface */ 142 DEVMETHOD(miibus_readreg, epic_miibus_readreg), 143 DEVMETHOD(miibus_writereg, epic_miibus_writereg), 144 DEVMETHOD(miibus_statchg, epic_miibus_statchg), 145 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit), 146 147 { 0, 0 } 148 }; 149 150 static driver_t epic_driver = { 151 "tx", 152 epic_methods, 153 sizeof(epic_softc_t) 154 }; 155 156 static devclass_t epic_devclass; 157 158 DRIVER_MODULE(tx, pci, epic_driver, epic_devclass, 0, 0); 159 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0); 160 161 static struct epic_type epic_devs[] = { 162 { SMC_VENDORID, SMC_DEVICEID_83C170, "SMC EtherPower II 10/100" }, 163 { 0, 0, NULL } 164 }; 165 166 static int 167 epic_probe(device_t dev) 168 { 169 struct epic_type *t; 170 171 t = epic_devtype(dev); 172 173 if (t != NULL) { 174 device_set_desc(dev, t->name); 175 return (BUS_PROBE_DEFAULT); 176 } 177 178 return (ENXIO); 179 } 180 181 static struct epic_type * 182 epic_devtype(device_t dev) 183 { 184 struct epic_type *t; 185 186 t = epic_devs; 187 188 while (t->name != NULL) { 189 if ((pci_get_vendor(dev) == t->ven_id) && 190 (pci_get_device(dev) == t->dev_id)) { 191 return (t); 192 } 193 t++; 194 } 195 return (NULL); 196 } 197 198 #ifdef EPIC_USEIOSPACE 199 #define EPIC_RES SYS_RES_IOPORT 200 #define EPIC_RID PCIR_BASEIO 201 #else 202 #define EPIC_RES SYS_RES_MEMORY 203 #define EPIC_RID PCIR_BASEMEM 204 #endif 205 206 static void 207 epic_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 208 { 209 u_int32_t *addr; 210 211 if (error) 212 return; 213 214 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 215 addr = arg; 216 *addr = segs->ds_addr; 217 } 218 219 /* 220 * Attach routine: map registers, allocate softc, rings and descriptors. 221 * Reset to known state. 222 */ 223 static int 224 epic_attach(device_t dev) 225 { 226 struct ifnet *ifp; 227 epic_softc_t *sc; 228 int error; 229 int i, rid, tmp; 230 u_char eaddr[6]; 231 232 sc = device_get_softc(dev); 233 234 /* Preinitialize softc structure. */ 235 sc->dev = dev; 236 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK, 237 MTX_DEF); 238 239 /* Fill ifnet structure. */ 240 ifp = sc->ifp = if_alloc(IFT_ETHER); 241 if (ifp == NULL) { 242 device_printf(dev, "can not if_alloc()\n"); 243 error = ENOSPC; 244 goto fail; 245 } 246 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 247 ifp->if_softc = sc; 248 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST; 249 ifp->if_ioctl = epic_ifioctl; 250 ifp->if_start = epic_ifstart; 251 ifp->if_init = epic_init; 252 IFQ_SET_MAXLEN(&ifp->if_snd, TX_RING_SIZE - 1); 253 254 /* Enable busmastering. */ 255 pci_enable_busmaster(dev); 256 257 rid = EPIC_RID; 258 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE); 259 if (sc->res == NULL) { 260 device_printf(dev, "couldn't map ports/memory\n"); 261 error = ENXIO; 262 goto fail; 263 } 264 265 /* Allocate interrupt. */ 266 rid = 0; 267 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 268 RF_SHAREABLE | RF_ACTIVE); 269 if (sc->irq == NULL) { 270 device_printf(dev, "couldn't map interrupt\n"); 271 error = ENXIO; 272 goto fail; 273 } 274 275 /* Allocate DMA tags. */ 276 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 277 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 278 MCLBYTES * EPIC_MAX_FRAGS, EPIC_MAX_FRAGS, MCLBYTES, 0, NULL, NULL, 279 &sc->mtag); 280 if (error) { 281 device_printf(dev, "couldn't allocate dma tag\n"); 282 goto fail; 283 } 284 285 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 286 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 287 sizeof(struct epic_rx_desc) * RX_RING_SIZE, 288 1, sizeof(struct epic_rx_desc) * RX_RING_SIZE, 0, NULL, 289 NULL, &sc->rtag); 290 if (error) { 291 device_printf(dev, "couldn't allocate dma tag\n"); 292 goto fail; 293 } 294 295 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 296 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 297 sizeof(struct epic_tx_desc) * TX_RING_SIZE, 298 1, sizeof(struct epic_tx_desc) * TX_RING_SIZE, 0, 299 NULL, NULL, &sc->ttag); 300 if (error) { 301 device_printf(dev, "couldn't allocate dma tag\n"); 302 goto fail; 303 } 304 305 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 306 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 307 sizeof(struct epic_frag_list) * TX_RING_SIZE, 308 1, sizeof(struct epic_frag_list) * TX_RING_SIZE, 0, 309 NULL, NULL, &sc->ftag); 310 if (error) { 311 device_printf(dev, "couldn't allocate dma tag\n"); 312 goto fail; 313 } 314 315 /* Allocate DMA safe memory and get the DMA addresses. */ 316 error = bus_dmamem_alloc(sc->ftag, (void **)&sc->tx_flist, 317 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fmap); 318 if (error) { 319 device_printf(dev, "couldn't allocate dma memory\n"); 320 goto fail; 321 } 322 error = bus_dmamap_load(sc->ftag, sc->fmap, sc->tx_flist, 323 sizeof(struct epic_frag_list) * TX_RING_SIZE, epic_dma_map_addr, 324 &sc->frag_addr, 0); 325 if (error) { 326 device_printf(dev, "couldn't map dma memory\n"); 327 goto fail; 328 } 329 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc, 330 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tmap); 331 if (error) { 332 device_printf(dev, "couldn't allocate dma memory\n"); 333 goto fail; 334 } 335 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc, 336 sizeof(struct epic_tx_desc) * TX_RING_SIZE, epic_dma_map_addr, 337 &sc->tx_addr, 0); 338 if (error) { 339 device_printf(dev, "couldn't map dma memory\n"); 340 goto fail; 341 } 342 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc, 343 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rmap); 344 if (error) { 345 device_printf(dev, "couldn't allocate dma memory\n"); 346 goto fail; 347 } 348 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc, 349 sizeof(struct epic_rx_desc) * RX_RING_SIZE, epic_dma_map_addr, 350 &sc->rx_addr, 0); 351 if (error) { 352 device_printf(dev, "couldn't map dma memory\n"); 353 goto fail; 354 } 355 356 /* Bring the chip out of low-power mode. */ 357 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 358 DELAY(500); 359 360 /* Workaround for Application Note 7-15. */ 361 for (i = 0; i < 16; i++) 362 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 363 364 /* Read MAC address from EEPROM. */ 365 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++) 366 ((u_int16_t *)eaddr)[i] = epic_read_eeprom(sc,i); 367 368 /* Set Non-Volatile Control Register from EEPROM. */ 369 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F); 370 371 /* Set defaults. */ 372 sc->tx_threshold = TRANSMIT_THRESHOLD; 373 sc->txcon = TXCON_DEFAULT; 374 sc->miicfg = MIICFG_SMI_ENABLE; 375 sc->phyid = EPIC_UNKN_PHY; 376 sc->serinst = -1; 377 378 /* Fetch card id. */ 379 sc->cardvend = pci_read_config(dev, PCIR_SUBVEND_0, 2); 380 sc->cardid = pci_read_config(dev, PCIR_SUBDEV_0, 2); 381 382 if (sc->cardvend != SMC_VENDORID) 383 device_printf(dev, "unknown card vendor %04xh\n", sc->cardvend); 384 385 /* Do ifmedia setup. */ 386 error = mii_attach(dev, &sc->miibus, ifp, epic_ifmedia_upd, 387 epic_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 388 if (error != 0) { 389 device_printf(dev, "attaching PHYs failed\n"); 390 goto fail; 391 } 392 393 /* board type and ... */ 394 printf(" type "); 395 for(i = 0x2c; i < 0x32; i++) { 396 tmp = epic_read_eeprom(sc, i); 397 if (' ' == (u_int8_t)tmp) 398 break; 399 printf("%c", (u_int8_t)tmp); 400 tmp >>= 8; 401 if (' ' == (u_int8_t)tmp) 402 break; 403 printf("%c", (u_int8_t)tmp); 404 } 405 printf("\n"); 406 407 /* Initialize rings. */ 408 if (epic_init_rings(sc)) { 409 device_printf(dev, "failed to init rings\n"); 410 error = ENXIO; 411 goto fail; 412 } 413 414 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 415 ifp->if_capabilities |= IFCAP_VLAN_MTU; 416 ifp->if_capenable |= IFCAP_VLAN_MTU; 417 callout_init_mtx(&sc->timer, &sc->lock, 0); 418 419 /* Attach to OS's managers. */ 420 ether_ifattach(ifp, eaddr); 421 422 /* Activate our interrupt handler. */ 423 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 424 NULL, epic_intr, sc, &sc->sc_ih); 425 if (error) { 426 device_printf(dev, "couldn't set up irq\n"); 427 ether_ifdetach(ifp); 428 goto fail; 429 } 430 431 return (0); 432 fail: 433 epic_release(sc); 434 return (error); 435 } 436 437 /* 438 * Free any resources allocated by the driver. 439 */ 440 static void 441 epic_release(epic_softc_t *sc) 442 { 443 if (sc->ifp != NULL) 444 if_free(sc->ifp); 445 if (sc->irq) 446 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 447 if (sc->res) 448 bus_release_resource(sc->dev, EPIC_RES, EPIC_RID, sc->res); 449 epic_free_rings(sc); 450 if (sc->tx_flist) { 451 bus_dmamap_unload(sc->ftag, sc->fmap); 452 bus_dmamem_free(sc->ftag, sc->tx_flist, sc->fmap); 453 } 454 if (sc->tx_desc) { 455 bus_dmamap_unload(sc->ttag, sc->tmap); 456 bus_dmamem_free(sc->ttag, sc->tx_desc, sc->tmap); 457 } 458 if (sc->rx_desc) { 459 bus_dmamap_unload(sc->rtag, sc->rmap); 460 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap); 461 } 462 if (sc->mtag) 463 bus_dma_tag_destroy(sc->mtag); 464 if (sc->ftag) 465 bus_dma_tag_destroy(sc->ftag); 466 if (sc->ttag) 467 bus_dma_tag_destroy(sc->ttag); 468 if (sc->rtag) 469 bus_dma_tag_destroy(sc->rtag); 470 mtx_destroy(&sc->lock); 471 } 472 473 /* 474 * Detach driver and free resources. 475 */ 476 static int 477 epic_detach(device_t dev) 478 { 479 struct ifnet *ifp; 480 epic_softc_t *sc; 481 482 sc = device_get_softc(dev); 483 ifp = sc->ifp; 484 485 EPIC_LOCK(sc); 486 epic_stop(sc); 487 EPIC_UNLOCK(sc); 488 callout_drain(&sc->timer); 489 ether_ifdetach(ifp); 490 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 491 492 bus_generic_detach(dev); 493 device_delete_child(dev, sc->miibus); 494 495 epic_release(sc); 496 return (0); 497 } 498 499 #undef EPIC_RES 500 #undef EPIC_RID 501 502 /* 503 * Stop all chip I/O so that the kernel's probe routines don't 504 * get confused by errant DMAs when rebooting. 505 */ 506 static int 507 epic_shutdown(device_t dev) 508 { 509 epic_softc_t *sc; 510 511 sc = device_get_softc(dev); 512 513 EPIC_LOCK(sc); 514 epic_stop(sc); 515 EPIC_UNLOCK(sc); 516 return (0); 517 } 518 519 /* 520 * This is if_ioctl handler. 521 */ 522 static int 523 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data) 524 { 525 epic_softc_t *sc = ifp->if_softc; 526 struct mii_data *mii; 527 struct ifreq *ifr = (struct ifreq *) data; 528 int error = 0; 529 530 switch (command) { 531 case SIOCSIFMTU: 532 if (ifp->if_mtu == ifr->ifr_mtu) 533 break; 534 535 /* XXX Though the datasheet doesn't imply any 536 * limitations on RX and TX sizes beside max 64Kb 537 * DMA transfer, seems we can't send more then 1600 538 * data bytes per ethernet packet (transmitter hangs 539 * up if more data is sent). 540 */ 541 EPIC_LOCK(sc); 542 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) { 543 ifp->if_mtu = ifr->ifr_mtu; 544 epic_stop(sc); 545 epic_init_locked(sc); 546 } else 547 error = EINVAL; 548 EPIC_UNLOCK(sc); 549 break; 550 551 case SIOCSIFFLAGS: 552 /* 553 * If the interface is marked up and stopped, then start it. 554 * If it is marked down and running, then stop it. 555 */ 556 EPIC_LOCK(sc); 557 if (ifp->if_flags & IFF_UP) { 558 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 559 epic_init_locked(sc); 560 EPIC_UNLOCK(sc); 561 break; 562 } 563 } else { 564 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 565 epic_stop(sc); 566 EPIC_UNLOCK(sc); 567 break; 568 } 569 } 570 571 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */ 572 epic_stop_activity(sc); 573 epic_set_mc_table(sc); 574 epic_set_rx_mode(sc); 575 epic_start_activity(sc); 576 EPIC_UNLOCK(sc); 577 break; 578 579 case SIOCADDMULTI: 580 case SIOCDELMULTI: 581 EPIC_LOCK(sc); 582 epic_set_mc_table(sc); 583 EPIC_UNLOCK(sc); 584 error = 0; 585 break; 586 587 case SIOCSIFMEDIA: 588 case SIOCGIFMEDIA: 589 mii = device_get_softc(sc->miibus); 590 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 591 break; 592 593 default: 594 error = ether_ioctl(ifp, command, data); 595 break; 596 } 597 return (error); 598 } 599 600 static void 601 epic_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, 602 bus_size_t mapsize, int error) 603 { 604 struct epic_frag_list *flist; 605 int i; 606 607 if (error) 608 return; 609 610 KASSERT(nseg <= EPIC_MAX_FRAGS, ("too many DMA segments")); 611 flist = arg; 612 /* Fill fragments list. */ 613 for (i = 0; i < nseg; i++) { 614 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); 615 flist->frag[i].fraglen = segs[i].ds_len; 616 flist->frag[i].fragaddr = segs[i].ds_addr; 617 } 618 flist->numfrags = nseg; 619 } 620 621 static void 622 epic_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, 623 bus_size_t mapsize, int error) 624 { 625 struct epic_rx_desc *desc; 626 627 if (error) 628 return; 629 630 KASSERT(nseg == 1, ("too many DMA segments")); 631 desc = arg; 632 desc->bufaddr = segs->ds_addr; 633 } 634 635 /* 636 * This is if_start handler. It takes mbufs from if_snd queue 637 * and queue them for transmit, one by one, until TX ring become full 638 * or queue become empty. 639 */ 640 static void 641 epic_ifstart(struct ifnet * ifp) 642 { 643 epic_softc_t *sc = ifp->if_softc; 644 645 EPIC_LOCK(sc); 646 epic_ifstart_locked(ifp); 647 EPIC_UNLOCK(sc); 648 } 649 650 static void 651 epic_ifstart_locked(struct ifnet * ifp) 652 { 653 epic_softc_t *sc = ifp->if_softc; 654 struct epic_tx_buffer *buf; 655 struct epic_tx_desc *desc; 656 struct epic_frag_list *flist; 657 struct mbuf *m0, *m; 658 int error; 659 660 while (sc->pending_txs < TX_RING_SIZE) { 661 buf = sc->tx_buffer + sc->cur_tx; 662 desc = sc->tx_desc + sc->cur_tx; 663 flist = sc->tx_flist + sc->cur_tx; 664 665 /* Get next packet to send. */ 666 IF_DEQUEUE(&ifp->if_snd, m0); 667 668 /* If nothing to send, return. */ 669 if (m0 == NULL) 670 return; 671 672 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0, 673 epic_dma_map_txbuf, flist, 0); 674 675 if (error && error != EFBIG) { 676 m_freem(m0); 677 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 678 continue; 679 } 680 681 /* 682 * If packet was more than EPIC_MAX_FRAGS parts, 683 * recopy packet to a newly allocated mbuf cluster. 684 */ 685 if (error) { 686 m = m_defrag(m0, M_NOWAIT); 687 if (m == NULL) { 688 m_freem(m0); 689 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 690 continue; 691 } 692 m_freem(m0); 693 m0 = m; 694 695 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m, 696 epic_dma_map_txbuf, flist, 0); 697 if (error) { 698 m_freem(m); 699 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 700 continue; 701 } 702 } 703 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE); 704 705 buf->mbuf = m0; 706 sc->pending_txs++; 707 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 708 desc->control = 0x01; 709 desc->txlength = 710 max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN); 711 desc->status = 0x8000; 712 bus_dmamap_sync(sc->ttag, sc->tmap, 713 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 714 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE); 715 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED); 716 717 /* Set watchdog timer. */ 718 sc->tx_timeout = 8; 719 720 BPF_MTAP(ifp, m0); 721 } 722 723 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 724 } 725 726 /* 727 * Synopsis: Finish all received frames. 728 */ 729 static void 730 epic_rx_done(epic_softc_t *sc) 731 { 732 struct ifnet *ifp = sc->ifp; 733 u_int16_t len; 734 struct epic_rx_buffer *buf; 735 struct epic_rx_desc *desc; 736 struct mbuf *m; 737 bus_dmamap_t map; 738 int error; 739 740 bus_dmamap_sync(sc->rtag, sc->rmap, BUS_DMASYNC_POSTREAD); 741 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) { 742 buf = sc->rx_buffer + sc->cur_rx; 743 desc = sc->rx_desc + sc->cur_rx; 744 745 /* Switch to next descriptor. */ 746 sc->cur_rx = (sc->cur_rx + 1) & RX_RING_MASK; 747 748 /* 749 * Check for RX errors. This should only happen if 750 * SAVE_ERRORED_PACKETS is set. RX errors generate 751 * RXE interrupt usually. 752 */ 753 if ((desc->status & 1) == 0) { 754 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 755 desc->status = 0x8000; 756 continue; 757 } 758 759 /* Save packet length and mbuf contained packet. */ 760 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD); 761 len = desc->rxlength - ETHER_CRC_LEN; 762 m = buf->mbuf; 763 764 /* Try to get an mbuf cluster. */ 765 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 766 if (buf->mbuf == NULL) { 767 buf->mbuf = m; 768 desc->status = 0x8000; 769 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 770 continue; 771 } 772 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES; 773 m_adj(buf->mbuf, ETHER_ALIGN); 774 775 /* Point to new mbuf, and give descriptor to chip. */ 776 error = bus_dmamap_load_mbuf(sc->mtag, sc->sparemap, buf->mbuf, 777 epic_dma_map_rxbuf, desc, 0); 778 if (error) { 779 buf->mbuf = m; 780 desc->status = 0x8000; 781 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 782 continue; 783 } 784 785 desc->status = 0x8000; 786 bus_dmamap_unload(sc->mtag, buf->map); 787 map = buf->map; 788 buf->map = sc->sparemap; 789 sc->sparemap = map; 790 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD); 791 792 /* First mbuf in packet holds the ethernet and packet headers */ 793 m->m_pkthdr.rcvif = ifp; 794 m->m_pkthdr.len = m->m_len = len; 795 796 /* Give mbuf to OS. */ 797 EPIC_UNLOCK(sc); 798 (*ifp->if_input)(ifp, m); 799 EPIC_LOCK(sc); 800 801 /* Successfully received frame */ 802 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 803 } 804 bus_dmamap_sync(sc->rtag, sc->rmap, 805 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 806 } 807 808 /* 809 * Synopsis: Do last phase of transmission. I.e. if desc is 810 * transmitted, decrease pending_txs counter, free mbuf contained 811 * packet, switch to next descriptor and repeat until no packets 812 * are pending or descriptor is not transmitted yet. 813 */ 814 static void 815 epic_tx_done(epic_softc_t *sc) 816 { 817 struct epic_tx_buffer *buf; 818 struct epic_tx_desc *desc; 819 u_int16_t status; 820 821 bus_dmamap_sync(sc->ttag, sc->tmap, BUS_DMASYNC_POSTREAD); 822 while (sc->pending_txs > 0) { 823 buf = sc->tx_buffer + sc->dirty_tx; 824 desc = sc->tx_desc + sc->dirty_tx; 825 status = desc->status; 826 827 /* 828 * If packet is not transmitted, thou followed 829 * packets are not transmitted too. 830 */ 831 if (status & 0x8000) 832 break; 833 834 /* Packet is transmitted. Switch to next and free mbuf. */ 835 sc->pending_txs--; 836 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK; 837 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE); 838 bus_dmamap_unload(sc->mtag, buf->map); 839 m_freem(buf->mbuf); 840 buf->mbuf = NULL; 841 842 /* Check for errors and collisions. */ 843 if (status & 0x0001) 844 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1); 845 else 846 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 847 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, (status >> 8) & 0x1F); 848 #ifdef EPIC_DIAG 849 if ((status & 0x1001) == 0x1001) 850 device_printf(sc->dev, 851 "Tx ERROR: excessive coll. number\n"); 852 #endif 853 } 854 855 if (sc->pending_txs < TX_RING_SIZE) 856 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 857 bus_dmamap_sync(sc->ttag, sc->tmap, 858 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 859 } 860 861 /* 862 * Interrupt function 863 */ 864 static void 865 epic_intr(void *arg) 866 { 867 epic_softc_t *sc; 868 int status, i; 869 870 sc = arg; 871 i = 4; 872 EPIC_LOCK(sc); 873 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) { 874 CSR_WRITE_4(sc, INTSTAT, status); 875 876 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) { 877 epic_rx_done(sc); 878 if (status & (INTSTAT_RQE|INTSTAT_OVW)) { 879 #ifdef EPIC_DIAG 880 if (status & INTSTAT_OVW) 881 device_printf(sc->dev, "RX buffer overflow\n"); 882 if (status & INTSTAT_RQE) 883 device_printf(sc->dev, "RX FIFO overflow\n"); 884 #endif 885 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0) 886 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED); 887 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1); 888 } 889 } 890 891 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) { 892 epic_tx_done(sc); 893 if (sc->ifp->if_snd.ifq_head != NULL) 894 epic_ifstart_locked(sc->ifp); 895 } 896 897 /* Check for rare errors */ 898 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 899 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) { 900 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA| 901 INTSTAT_APE|INTSTAT_DPE)) { 902 device_printf(sc->dev, "PCI fatal errors occurred: %s%s%s%s\n", 903 (status & INTSTAT_PMA) ? "PMA " : "", 904 (status & INTSTAT_PTA) ? "PTA " : "", 905 (status & INTSTAT_APE) ? "APE " : "", 906 (status & INTSTAT_DPE) ? "DPE" : ""); 907 908 epic_stop(sc); 909 epic_init_locked(sc); 910 break; 911 } 912 913 if (status & INTSTAT_RXE) { 914 #ifdef EPIC_DIAG 915 device_printf(sc->dev, "CRC/Alignment error\n"); 916 #endif 917 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1); 918 } 919 920 if (status & INTSTAT_TXU) { 921 epic_tx_underrun(sc); 922 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 923 } 924 } 925 } 926 927 /* If no packets are pending, then no timeouts. */ 928 if (sc->pending_txs == 0) 929 sc->tx_timeout = 0; 930 EPIC_UNLOCK(sc); 931 } 932 933 /* 934 * Handle the TX underrun error: increase the TX threshold 935 * and restart the transmitter. 936 */ 937 static void 938 epic_tx_underrun(epic_softc_t *sc) 939 { 940 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) { 941 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE; 942 #ifdef EPIC_DIAG 943 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n"); 944 #endif 945 } else { 946 sc->tx_threshold += 0x40; 947 #ifdef EPIC_DIAG 948 device_printf(sc->dev, 949 "Tx UNDERRUN: TX threshold increased to %d\n", 950 sc->tx_threshold); 951 #endif 952 } 953 954 /* We must set TXUGO to reset the stuck transmitter. */ 955 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO); 956 957 /* Update the TX threshold */ 958 epic_stop_activity(sc); 959 epic_set_tx_mode(sc); 960 epic_start_activity(sc); 961 } 962 963 /* 964 * This function is called once a second when the interface is running 965 * and performs two functions. First, it provides a timer for the mii 966 * to help with autonegotiation. Second, it checks for transmit 967 * timeouts. 968 */ 969 static void 970 epic_timer(void *arg) 971 { 972 epic_softc_t *sc = arg; 973 struct mii_data *mii; 974 struct ifnet *ifp; 975 976 ifp = sc->ifp; 977 EPIC_ASSERT_LOCKED(sc); 978 if (sc->tx_timeout && --sc->tx_timeout == 0) { 979 device_printf(sc->dev, "device timeout %d packets\n", 980 sc->pending_txs); 981 982 /* Try to finish queued packets. */ 983 epic_tx_done(sc); 984 985 /* If not successful. */ 986 if (sc->pending_txs > 0) { 987 if_inc_counter(ifp, IFCOUNTER_OERRORS, sc->pending_txs); 988 989 /* Reinitialize board. */ 990 device_printf(sc->dev, "reinitialization\n"); 991 epic_stop(sc); 992 epic_init_locked(sc); 993 } else 994 device_printf(sc->dev, 995 "seems we can continue normaly\n"); 996 997 /* Start output. */ 998 if (ifp->if_snd.ifq_head) 999 epic_ifstart_locked(ifp); 1000 } 1001 1002 mii = device_get_softc(sc->miibus); 1003 mii_tick(mii); 1004 1005 callout_reset(&sc->timer, hz, epic_timer, sc); 1006 } 1007 1008 /* 1009 * Set media options. 1010 */ 1011 static int 1012 epic_ifmedia_upd(struct ifnet *ifp) 1013 { 1014 epic_softc_t *sc; 1015 int error; 1016 1017 sc = ifp->if_softc; 1018 EPIC_LOCK(sc); 1019 error = epic_ifmedia_upd_locked(ifp); 1020 EPIC_UNLOCK(sc); 1021 return (error); 1022 } 1023 1024 static int 1025 epic_ifmedia_upd_locked(struct ifnet *ifp) 1026 { 1027 epic_softc_t *sc; 1028 struct mii_data *mii; 1029 struct ifmedia *ifm; 1030 struct mii_softc *miisc; 1031 int cfg, media; 1032 1033 sc = ifp->if_softc; 1034 mii = device_get_softc(sc->miibus); 1035 ifm = &mii->mii_media; 1036 media = ifm->ifm_cur->ifm_media; 1037 1038 /* Do not do anything if interface is not up. */ 1039 if ((ifp->if_flags & IFF_UP) == 0) 1040 return (0); 1041 1042 /* 1043 * Lookup current selected PHY. 1044 */ 1045 if (IFM_INST(media) == sc->serinst) { 1046 sc->phyid = EPIC_SERIAL; 1047 sc->physc = NULL; 1048 } else { 1049 /* If we're not selecting serial interface, select MII mode. */ 1050 sc->miicfg &= ~MIICFG_SERIAL_ENABLE; 1051 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1052 1053 /* Default to unknown PHY. */ 1054 sc->phyid = EPIC_UNKN_PHY; 1055 1056 /* Lookup selected PHY. */ 1057 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1058 if (IFM_INST(media) == miisc->mii_inst) { 1059 sc->physc = miisc; 1060 break; 1061 } 1062 } 1063 1064 /* Identify selected PHY. */ 1065 if (sc->physc) { 1066 int id1, id2, model, oui; 1067 1068 id1 = PHY_READ(sc->physc, MII_PHYIDR1); 1069 id2 = PHY_READ(sc->physc, MII_PHYIDR2); 1070 1071 oui = MII_OUI(id1, id2); 1072 model = MII_MODEL(id2); 1073 switch (oui) { 1074 case MII_OUI_xxQUALSEMI: 1075 if (model == MII_MODEL_xxQUALSEMI_QS6612) 1076 sc->phyid = EPIC_QS6612_PHY; 1077 break; 1078 case MII_OUI_ALTIMA: 1079 if (model == MII_MODEL_ALTIMA_AC101) 1080 sc->phyid = EPIC_AC101_PHY; 1081 break; 1082 case MII_OUI_xxLEVEL1: 1083 if (model == MII_MODEL_xxLEVEL1_LXT970) 1084 sc->phyid = EPIC_LXT970_PHY; 1085 break; 1086 } 1087 } 1088 } 1089 1090 /* 1091 * Do PHY specific card setup. 1092 */ 1093 1094 /* 1095 * Call this, to isolate all not selected PHYs and 1096 * set up selected. 1097 */ 1098 mii_mediachg(mii); 1099 1100 /* Do our own setup. */ 1101 switch (sc->phyid) { 1102 case EPIC_QS6612_PHY: 1103 break; 1104 case EPIC_AC101_PHY: 1105 /* We have to powerup fiber tranceivers. */ 1106 if (IFM_SUBTYPE(media) == IFM_100_FX) 1107 sc->miicfg |= MIICFG_694_ENABLE; 1108 else 1109 sc->miicfg &= ~MIICFG_694_ENABLE; 1110 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1111 1112 break; 1113 case EPIC_LXT970_PHY: 1114 /* We have to powerup fiber tranceivers. */ 1115 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG); 1116 if (IFM_SUBTYPE(media) == IFM_100_FX) 1117 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0; 1118 else 1119 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1120 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg); 1121 1122 break; 1123 case EPIC_SERIAL: 1124 /* Select serial PHY (10base2/BNC usually). */ 1125 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE; 1126 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1127 1128 /* There is no driver to fill this. */ 1129 mii->mii_media_active = media; 1130 mii->mii_media_status = 0; 1131 1132 /* 1133 * We need to call this manually as it wasn't called 1134 * in mii_mediachg(). 1135 */ 1136 epic_miibus_statchg(sc->dev); 1137 break; 1138 default: 1139 device_printf(sc->dev, "ERROR! Unknown PHY selected\n"); 1140 return (EINVAL); 1141 } 1142 1143 return (0); 1144 } 1145 1146 /* 1147 * Report current media status. 1148 */ 1149 static void 1150 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1151 { 1152 epic_softc_t *sc; 1153 struct mii_data *mii; 1154 1155 sc = ifp->if_softc; 1156 mii = device_get_softc(sc->miibus); 1157 EPIC_LOCK(sc); 1158 1159 /* Nothing should be selected if interface is down. */ 1160 if ((ifp->if_flags & IFF_UP) == 0) { 1161 ifmr->ifm_active = IFM_NONE; 1162 ifmr->ifm_status = 0; 1163 EPIC_UNLOCK(sc); 1164 return; 1165 } 1166 1167 /* Call underlying pollstat, if not serial PHY. */ 1168 if (sc->phyid != EPIC_SERIAL) 1169 mii_pollstat(mii); 1170 1171 /* Simply copy media info. */ 1172 ifmr->ifm_active = mii->mii_media_active; 1173 ifmr->ifm_status = mii->mii_media_status; 1174 EPIC_UNLOCK(sc); 1175 } 1176 1177 /* 1178 * Callback routine, called on media change. 1179 */ 1180 static void 1181 epic_miibus_statchg(device_t dev) 1182 { 1183 epic_softc_t *sc; 1184 struct mii_data *mii; 1185 int media; 1186 1187 sc = device_get_softc(dev); 1188 mii = device_get_softc(sc->miibus); 1189 media = mii->mii_media_active; 1190 1191 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX); 1192 1193 /* 1194 * If we are in full-duplex mode or loopback operation, 1195 * we need to decouple receiver and transmitter. 1196 */ 1197 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP)) 1198 sc->txcon |= TXCON_FULL_DUPLEX; 1199 1200 /* On some cards we need manualy set fullduplex led. */ 1201 if (sc->cardid == SMC9432FTX || 1202 sc->cardid == SMC9432FTX_SC) { 1203 if (IFM_OPTIONS(media) & IFM_FDX) 1204 sc->miicfg |= MIICFG_694_ENABLE; 1205 else 1206 sc->miicfg &= ~MIICFG_694_ENABLE; 1207 1208 CSR_WRITE_4(sc, MIICFG, sc->miicfg); 1209 } 1210 1211 epic_stop_activity(sc); 1212 epic_set_tx_mode(sc); 1213 epic_start_activity(sc); 1214 } 1215 1216 static void 1217 epic_miibus_mediainit(device_t dev) 1218 { 1219 epic_softc_t *sc; 1220 struct mii_data *mii; 1221 struct ifmedia *ifm; 1222 int media; 1223 1224 sc = device_get_softc(dev); 1225 mii = device_get_softc(sc->miibus); 1226 ifm = &mii->mii_media; 1227 1228 /* 1229 * Add Serial Media Interface if present, this applies to 1230 * SMC9432BTX serie. 1231 */ 1232 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) { 1233 /* Store its instance. */ 1234 sc->serinst = mii->mii_instance++; 1235 1236 /* Add as 10base2/BNC media. */ 1237 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst); 1238 ifmedia_add(ifm, media, 0, NULL); 1239 1240 /* Report to user. */ 1241 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n"); 1242 } 1243 } 1244 1245 /* 1246 * Reset chip and update media. 1247 */ 1248 static void 1249 epic_init(void *xsc) 1250 { 1251 epic_softc_t *sc = xsc; 1252 1253 EPIC_LOCK(sc); 1254 epic_init_locked(sc); 1255 EPIC_UNLOCK(sc); 1256 } 1257 1258 static void 1259 epic_init_locked(epic_softc_t *sc) 1260 { 1261 struct ifnet *ifp = sc->ifp; 1262 int i; 1263 1264 /* If interface is already running, then we need not do anything. */ 1265 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1266 return; 1267 } 1268 1269 /* Soft reset the chip (we have to power up card before). */ 1270 CSR_WRITE_4(sc, GENCTL, 0); 1271 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1272 1273 /* 1274 * Reset takes 15 pci ticks which depends on PCI bus speed. 1275 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec. 1276 */ 1277 DELAY(500); 1278 1279 /* Wake up */ 1280 CSR_WRITE_4(sc, GENCTL, 0); 1281 1282 /* Workaround for Application Note 7-15 */ 1283 for (i = 0; i < 16; i++) 1284 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); 1285 1286 /* Give rings to EPIC */ 1287 CSR_WRITE_4(sc, PRCDAR, sc->rx_addr); 1288 CSR_WRITE_4(sc, PTCDAR, sc->tx_addr); 1289 1290 /* Put node address to EPIC. */ 1291 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)IF_LLADDR(sc->ifp))[0]); 1292 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)IF_LLADDR(sc->ifp))[1]); 1293 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)IF_LLADDR(sc->ifp))[2]); 1294 1295 /* Set tx mode, includeing transmit threshold. */ 1296 epic_set_tx_mode(sc); 1297 1298 /* Compute and set RXCON. */ 1299 epic_set_rx_mode(sc); 1300 1301 /* Set multicast table. */ 1302 epic_set_mc_table(sc); 1303 1304 /* Enable interrupts by setting the interrupt mask. */ 1305 CSR_WRITE_4(sc, INTMASK, 1306 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */ 1307 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU | 1308 INTSTAT_FATAL); 1309 1310 /* Acknowledge all pending interrupts. */ 1311 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT)); 1312 1313 /* Enable interrupts, set for PCI read multiple and etc */ 1314 CSR_WRITE_4(sc, GENCTL, 1315 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE | 1316 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64); 1317 1318 /* Mark interface running ... */ 1319 if (ifp->if_flags & IFF_UP) 1320 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1321 else 1322 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1323 1324 /* ... and free */ 1325 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1326 1327 /* Start Rx process */ 1328 epic_start_activity(sc); 1329 1330 /* Set appropriate media */ 1331 epic_ifmedia_upd_locked(ifp); 1332 1333 callout_reset(&sc->timer, hz, epic_timer, sc); 1334 } 1335 1336 /* 1337 * Synopsis: calculate and set Rx mode. Chip must be in idle state to 1338 * access RXCON. 1339 */ 1340 static void 1341 epic_set_rx_mode(epic_softc_t *sc) 1342 { 1343 u_int32_t flags; 1344 u_int32_t rxcon; 1345 1346 flags = sc->ifp->if_flags; 1347 rxcon = RXCON_DEFAULT; 1348 1349 #ifdef EPIC_EARLY_RX 1350 rxcon |= RXCON_EARLY_RX; 1351 #endif 1352 1353 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0; 1354 1355 CSR_WRITE_4(sc, RXCON, rxcon); 1356 } 1357 1358 /* 1359 * Synopsis: Set transmit control register. Chip must be in idle state to 1360 * access TXCON. 1361 */ 1362 static void 1363 epic_set_tx_mode(epic_softc_t *sc) 1364 { 1365 1366 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE) 1367 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold); 1368 1369 CSR_WRITE_4(sc, TXCON, sc->txcon); 1370 } 1371 1372 /* 1373 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC 1374 * flags (note that setting PROMISC bit in EPIC's RXCON will only touch 1375 * individual frames, multicast filter must be manually programmed). 1376 * 1377 * Note: EPIC must be in idle state. 1378 */ 1379 static void 1380 epic_set_mc_table(epic_softc_t *sc) 1381 { 1382 struct ifnet *ifp; 1383 struct ifmultiaddr *ifma; 1384 u_int16_t filter[4]; 1385 u_int8_t h; 1386 1387 ifp = sc->ifp; 1388 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1389 CSR_WRITE_4(sc, MC0, 0xFFFF); 1390 CSR_WRITE_4(sc, MC1, 0xFFFF); 1391 CSR_WRITE_4(sc, MC2, 0xFFFF); 1392 CSR_WRITE_4(sc, MC3, 0xFFFF); 1393 return; 1394 } 1395 1396 filter[0] = 0; 1397 filter[1] = 0; 1398 filter[2] = 0; 1399 filter[3] = 0; 1400 1401 if_maddr_rlock(ifp); 1402 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1403 if (ifma->ifma_addr->sa_family != AF_LINK) 1404 continue; 1405 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1406 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 1407 filter[h >> 4] |= 1 << (h & 0xF); 1408 } 1409 if_maddr_runlock(ifp); 1410 1411 CSR_WRITE_4(sc, MC0, filter[0]); 1412 CSR_WRITE_4(sc, MC1, filter[1]); 1413 CSR_WRITE_4(sc, MC2, filter[2]); 1414 CSR_WRITE_4(sc, MC3, filter[3]); 1415 } 1416 1417 1418 /* 1419 * Synopsis: Start receive process and transmit one, if they need. 1420 */ 1421 static void 1422 epic_start_activity(epic_softc_t *sc) 1423 { 1424 1425 /* Start rx process. */ 1426 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED | COMMAND_START_RX | 1427 (sc->pending_txs ? COMMAND_TXQUEUED : 0)); 1428 } 1429 1430 /* 1431 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional 1432 * packet needs to be queued to stop Tx DMA. 1433 */ 1434 static void 1435 epic_stop_activity(epic_softc_t *sc) 1436 { 1437 int status, i; 1438 1439 /* Stop Tx and Rx DMA. */ 1440 CSR_WRITE_4(sc, COMMAND, 1441 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA); 1442 1443 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX). */ 1444 for (i = 0; i < 0x1000; i++) { 1445 status = CSR_READ_4(sc, INTSTAT) & 1446 (INTSTAT_TXIDLE | INTSTAT_RXIDLE); 1447 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE)) 1448 break; 1449 DELAY(1); 1450 } 1451 1452 /* Catch all finished packets. */ 1453 epic_rx_done(sc); 1454 epic_tx_done(sc); 1455 1456 status = CSR_READ_4(sc, INTSTAT); 1457 1458 if ((status & INTSTAT_RXIDLE) == 0) 1459 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n"); 1460 1461 if ((status & INTSTAT_TXIDLE) == 0) 1462 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n"); 1463 1464 /* 1465 * May need to queue one more packet if TQE, this is rare 1466 * but existing case. 1467 */ 1468 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE)) 1469 (void)epic_queue_last_packet(sc); 1470 } 1471 1472 /* 1473 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until 1474 * a packet from current descriptor will be copied to internal RAM. We 1475 * compose a dummy packet here and queue it for transmission. 1476 * 1477 * XXX the packet will then be actually sent over network... 1478 */ 1479 static int 1480 epic_queue_last_packet(epic_softc_t *sc) 1481 { 1482 struct epic_tx_desc *desc; 1483 struct epic_frag_list *flist; 1484 struct epic_tx_buffer *buf; 1485 struct mbuf *m0; 1486 int error, i; 1487 1488 device_printf(sc->dev, "queue last packet\n"); 1489 1490 desc = sc->tx_desc + sc->cur_tx; 1491 flist = sc->tx_flist + sc->cur_tx; 1492 buf = sc->tx_buffer + sc->cur_tx; 1493 1494 if ((desc->status & 0x8000) || (buf->mbuf != NULL)) 1495 return (EBUSY); 1496 1497 MGETHDR(m0, M_NOWAIT, MT_DATA); 1498 if (m0 == NULL) 1499 return (ENOBUFS); 1500 1501 /* Prepare mbuf. */ 1502 m0->m_len = min(MHLEN, ETHER_MIN_LEN - ETHER_CRC_LEN); 1503 m0->m_pkthdr.len = m0->m_len; 1504 m0->m_pkthdr.rcvif = sc->ifp; 1505 bzero(mtod(m0, caddr_t), m0->m_len); 1506 1507 /* Fill fragments list. */ 1508 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0, 1509 epic_dma_map_txbuf, flist, 0); 1510 if (error) { 1511 m_freem(m0); 1512 return (error); 1513 } 1514 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE); 1515 1516 /* Fill in descriptor. */ 1517 buf->mbuf = m0; 1518 sc->pending_txs++; 1519 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK; 1520 desc->control = 0x01; 1521 desc->txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN); 1522 desc->status = 0x8000; 1523 bus_dmamap_sync(sc->ttag, sc->tmap, 1524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1525 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE); 1526 1527 /* Launch transmission. */ 1528 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED); 1529 1530 /* Wait Tx DMA to stop (for how long??? XXX) */ 1531 for (i = 0; i < 1000; i++) { 1532 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) 1533 break; 1534 DELAY(1); 1535 } 1536 1537 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0) 1538 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n"); 1539 else 1540 epic_tx_done(sc); 1541 1542 return (0); 1543 } 1544 1545 /* 1546 * Synopsis: Shut down board and deallocates rings. 1547 */ 1548 static void 1549 epic_stop(epic_softc_t *sc) 1550 { 1551 1552 EPIC_ASSERT_LOCKED(sc); 1553 1554 sc->tx_timeout = 0; 1555 callout_stop(&sc->timer); 1556 1557 /* Disable interrupts */ 1558 CSR_WRITE_4(sc, INTMASK, 0); 1559 CSR_WRITE_4(sc, GENCTL, 0); 1560 1561 /* Try to stop Rx and TX processes */ 1562 epic_stop_activity(sc); 1563 1564 /* Reset chip */ 1565 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); 1566 DELAY(1000); 1567 1568 /* Make chip go to bed */ 1569 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN); 1570 1571 /* Mark as stopped */ 1572 sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1573 } 1574 1575 /* 1576 * Synopsis: This function should free all memory allocated for rings. 1577 */ 1578 static void 1579 epic_free_rings(epic_softc_t *sc) 1580 { 1581 int i; 1582 1583 for (i = 0; i < RX_RING_SIZE; i++) { 1584 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1585 struct epic_rx_desc *desc = sc->rx_desc + i; 1586 1587 desc->status = 0; 1588 desc->buflength = 0; 1589 desc->bufaddr = 0; 1590 1591 if (buf->mbuf) { 1592 bus_dmamap_unload(sc->mtag, buf->map); 1593 bus_dmamap_destroy(sc->mtag, buf->map); 1594 m_freem(buf->mbuf); 1595 } 1596 buf->mbuf = NULL; 1597 } 1598 1599 if (sc->sparemap != NULL) 1600 bus_dmamap_destroy(sc->mtag, sc->sparemap); 1601 1602 for (i = 0; i < TX_RING_SIZE; i++) { 1603 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1604 struct epic_tx_desc *desc = sc->tx_desc + i; 1605 1606 desc->status = 0; 1607 desc->buflength = 0; 1608 desc->bufaddr = 0; 1609 1610 if (buf->mbuf) { 1611 bus_dmamap_unload(sc->mtag, buf->map); 1612 bus_dmamap_destroy(sc->mtag, buf->map); 1613 m_freem(buf->mbuf); 1614 } 1615 buf->mbuf = NULL; 1616 } 1617 } 1618 1619 /* 1620 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them. 1621 * Point Tx descs to fragment lists. Check that all descs and fraglists 1622 * are bounded and aligned properly. 1623 */ 1624 static int 1625 epic_init_rings(epic_softc_t *sc) 1626 { 1627 int error, i; 1628 1629 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0; 1630 1631 /* Initialize the RX descriptor ring. */ 1632 for (i = 0; i < RX_RING_SIZE; i++) { 1633 struct epic_rx_buffer *buf = sc->rx_buffer + i; 1634 struct epic_rx_desc *desc = sc->rx_desc + i; 1635 1636 desc->status = 0; /* Owned by driver */ 1637 desc->next = sc->rx_addr + 1638 ((i + 1) & RX_RING_MASK) * sizeof(struct epic_rx_desc); 1639 1640 if ((desc->next & 3) || 1641 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1642 epic_free_rings(sc); 1643 return (EFAULT); 1644 } 1645 1646 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1647 if (buf->mbuf == NULL) { 1648 epic_free_rings(sc); 1649 return (ENOBUFS); 1650 } 1651 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES; 1652 m_adj(buf->mbuf, ETHER_ALIGN); 1653 1654 error = bus_dmamap_create(sc->mtag, 0, &buf->map); 1655 if (error) { 1656 epic_free_rings(sc); 1657 return (error); 1658 } 1659 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf, 1660 epic_dma_map_rxbuf, desc, 0); 1661 if (error) { 1662 epic_free_rings(sc); 1663 return (error); 1664 } 1665 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD); 1666 1667 desc->buflength = buf->mbuf->m_len; /* Max RX buffer length */ 1668 desc->status = 0x8000; /* Set owner bit to NIC */ 1669 } 1670 bus_dmamap_sync(sc->rtag, sc->rmap, 1671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1672 1673 /* Create the spare DMA map. */ 1674 error = bus_dmamap_create(sc->mtag, 0, &sc->sparemap); 1675 if (error) { 1676 epic_free_rings(sc); 1677 return (error); 1678 } 1679 1680 /* Initialize the TX descriptor ring. */ 1681 for (i = 0; i < TX_RING_SIZE; i++) { 1682 struct epic_tx_buffer *buf = sc->tx_buffer + i; 1683 struct epic_tx_desc *desc = sc->tx_desc + i; 1684 1685 desc->status = 0; 1686 desc->next = sc->tx_addr + 1687 ((i + 1) & TX_RING_MASK) * sizeof(struct epic_tx_desc); 1688 1689 if ((desc->next & 3) || 1690 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) { 1691 epic_free_rings(sc); 1692 return (EFAULT); 1693 } 1694 1695 buf->mbuf = NULL; 1696 desc->bufaddr = sc->frag_addr + 1697 i * sizeof(struct epic_frag_list); 1698 1699 if ((desc->bufaddr & 3) || 1700 ((desc->bufaddr & PAGE_MASK) + 1701 sizeof(struct epic_frag_list)) > PAGE_SIZE) { 1702 epic_free_rings(sc); 1703 return (EFAULT); 1704 } 1705 1706 error = bus_dmamap_create(sc->mtag, 0, &buf->map); 1707 if (error) { 1708 epic_free_rings(sc); 1709 return (error); 1710 } 1711 } 1712 bus_dmamap_sync(sc->ttag, sc->tmap, 1713 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1714 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE); 1715 1716 return (0); 1717 } 1718 1719 /* 1720 * EEPROM operation functions 1721 */ 1722 static void 1723 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val) 1724 { 1725 u_int16_t i; 1726 1727 CSR_WRITE_1(sc, EECTL, val); 1728 1729 for (i = 0; i < 0xFF; i++) { 1730 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) 1731 break; 1732 } 1733 } 1734 1735 static u_int8_t 1736 epic_read_eepromreg(epic_softc_t *sc) 1737 { 1738 1739 return (CSR_READ_1(sc, EECTL)); 1740 } 1741 1742 static u_int8_t 1743 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val) 1744 { 1745 1746 epic_write_eepromreg(sc, val); 1747 epic_write_eepromreg(sc, (val | 0x4)); 1748 epic_write_eepromreg(sc, val); 1749 1750 return (epic_read_eepromreg(sc)); 1751 } 1752 1753 static void 1754 epic_output_eepromw(epic_softc_t *sc, u_int16_t val) 1755 { 1756 int i; 1757 1758 for (i = 0xF; i >= 0; i--) { 1759 if (val & (1 << i)) 1760 epic_eeprom_clock(sc, 0x0B); 1761 else 1762 epic_eeprom_clock(sc, 0x03); 1763 } 1764 } 1765 1766 static u_int16_t 1767 epic_input_eepromw(epic_softc_t *sc) 1768 { 1769 u_int16_t retval = 0; 1770 int i; 1771 1772 for (i = 0xF; i >= 0; i--) { 1773 if (epic_eeprom_clock(sc, 0x3) & 0x10) 1774 retval |= (1 << i); 1775 } 1776 1777 return (retval); 1778 } 1779 1780 static int 1781 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc) 1782 { 1783 u_int16_t dataval; 1784 u_int16_t read_cmd; 1785 1786 epic_write_eepromreg(sc, 3); 1787 1788 if (epic_read_eepromreg(sc) & 0x40) 1789 read_cmd = (loc & 0x3F) | 0x180; 1790 else 1791 read_cmd = (loc & 0xFF) | 0x600; 1792 1793 epic_output_eepromw(sc, read_cmd); 1794 1795 dataval = epic_input_eepromw(sc); 1796 1797 epic_write_eepromreg(sc, 1); 1798 1799 return (dataval); 1800 } 1801 1802 /* 1803 * Here goes MII read/write routines. 1804 */ 1805 static int 1806 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg) 1807 { 1808 int i; 1809 1810 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01)); 1811 1812 for (i = 0; i < 0x100; i++) { 1813 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) 1814 break; 1815 DELAY(1); 1816 } 1817 1818 return (CSR_READ_4(sc, MIIDATA)); 1819 } 1820 1821 static void 1822 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val) 1823 { 1824 int i; 1825 1826 CSR_WRITE_4(sc, MIIDATA, val); 1827 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02)); 1828 1829 for(i = 0; i < 0x100; i++) { 1830 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) 1831 break; 1832 DELAY(1); 1833 } 1834 } 1835 1836 static int 1837 epic_miibus_readreg(device_t dev, int phy, int reg) 1838 { 1839 epic_softc_t *sc; 1840 1841 sc = device_get_softc(dev); 1842 1843 return (PHY_READ_2(sc, phy, reg)); 1844 } 1845 1846 static int 1847 epic_miibus_writereg(device_t dev, int phy, int reg, int data) 1848 { 1849 epic_softc_t *sc; 1850 1851 sc = device_get_softc(dev); 1852 1853 PHY_WRITE_2(sc, phy, reg, data); 1854 1855 return (0); 1856 } 1857