1 /* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang ([email protected]) 5 * Erich Chen ([email protected]) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 */ 12 13 #include <sys/cdefs.h> 14 __FBSDID("$FreeBSD$"); 15 16 /* 17 * HISTORY: 18 * 19 * REV# DATE NAME DESCRIPTION 20 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 21 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 22 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 23 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 24 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 25 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 26 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 27 */ 28 29 /*- 30 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 3. The name of the author may not be used to endorse or promote products 41 * derived from this software without specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 44 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 48 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 52 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 */ 55 56 /* 57 * Imported into FreeBSD source repository, and updated to compile under 58 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <[email protected]>, 1996-12-17 59 */ 60 61 /* 62 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 63 * <[email protected]>, 2002-03-04 64 */ 65 66 #include <sys/param.h> 67 68 #include <sys/systm.h> 69 #include <sys/malloc.h> 70 #include <sys/queue.h> 71 #if __FreeBSD_version >= 500000 72 #include <sys/bio.h> 73 #endif 74 #include <sys/buf.h> 75 #include <sys/bus.h> 76 #include <sys/kernel.h> 77 #include <sys/module.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/pci/pcivar.h> 83 #include <dev/pci/pcireg.h> 84 #include <machine/resource.h> 85 #include <machine/bus.h> 86 #include <sys/rman.h> 87 88 #include <cam/cam.h> 89 #include <cam/cam_ccb.h> 90 #include <cam/cam_sim.h> 91 #include <cam/cam_xpt_sim.h> 92 #include <cam/cam_debug.h> 93 94 #include <cam/scsi/scsi_all.h> 95 #include <cam/scsi/scsi_message.h> 96 97 #include <dev/trm/trm.h> 98 99 #define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 100 #define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 101 #define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 102 #define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 103 reg, value) 104 #define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 105 reg, value) 106 #define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 107 reg, value) 108 109 #define PCI_Vendor_ID_TEKRAM 0x1DE1 110 #define PCI_Device_ID_TRM_S1040 0x0391 111 #define PCI_DEVICEID_TRMS1040 0x03911DE1 112 #define PCI_DEVICEID_TRMS2080 0x03921DE1 113 114 #ifdef trm_DEBUG1 115 #define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 116 #else 117 #define TRM_DPRINTF(fmt, arg...) {} 118 #endif /* TRM_DEBUG */ 119 120 static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 121 static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 122 static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 123 static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124 static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 125 static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 126 static void NVRAM_trm_wait_30us(PACB pACB); 127 128 static void trm_Interrupt(void *vpACB); 129 static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 130 u_int16_t * pscsi_status); 131 static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133 static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135 static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137 static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139 static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141 static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143 static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145 static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147 static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149 static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151 static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153 static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 154 static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 155 static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 156 static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 157 static void trm_Disconnect(PACB pACB); 158 static void trm_Reselect(PACB pACB); 159 static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 160 static void trm_DoingSRB_Done(PACB pACB); 161 static void trm_ScsiRstDetect(PACB pACB); 162 static void trm_ResetSCSIBus(PACB pACB); 163 static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 164 static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 165 static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 166 static void trm_SendSRB(PACB pACB, PSRB pSRB); 167 static int trm_probe(device_t tag); 168 static int trm_attach(device_t tag); 169 static void trm_reset(PACB pACB); 170 171 static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 172 173 static int trm_initAdapter(PACB pACB, u_int16_t unit); 174 static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 175 u_int32_t i, u_int32_t j); 176 static int trm_initSRB(PACB pACB); 177 static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 178 /* CAM SIM entry points */ 179 #define ccb_trmsrb_ptr spriv_ptr0 180 #define ccb_trmacb_ptr spriv_ptr1 181 static void trm_action(struct cam_sim *psim, union ccb *pccb); 182 static void trm_poll(struct cam_sim *psim); 183 184 185 static void * trm_SCSI_phase0[] = { 186 trm_DataOutPhase0, /* phase:0 */ 187 trm_DataInPhase0, /* phase:1 */ 188 trm_CommandPhase0, /* phase:2 */ 189 trm_StatusPhase0, /* phase:3 */ 190 trm_Nop0, /* phase:4 */ 191 trm_Nop1, /* phase:5 */ 192 trm_MsgOutPhase0, /* phase:6 */ 193 trm_MsgInPhase0, /* phase:7 */ 194 }; 195 196 /* 197 * 198 * stateV = (void *) trm_SCSI_phase1[phase] 199 * 200 */ 201 static void * trm_SCSI_phase1[] = { 202 trm_DataOutPhase1, /* phase:0 */ 203 trm_DataInPhase1, /* phase:1 */ 204 trm_CommandPhase1, /* phase:2 */ 205 trm_StatusPhase1, /* phase:3 */ 206 trm_Nop0, /* phase:4 */ 207 trm_Nop1, /* phase:5 */ 208 trm_MsgOutPhase1, /* phase:6 */ 209 trm_MsgInPhase1, /* phase:7 */ 210 }; 211 212 213 NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 214 /* 215 *Fast20: 000 50ns, 20.0 Mbytes/s 216 * 001 75ns, 13.3 Mbytes/s 217 * 010 100ns, 10.0 Mbytes/s 218 * 011 125ns, 8.0 Mbytes/s 219 * 100 150ns, 6.6 Mbytes/s 220 * 101 175ns, 5.7 Mbytes/s 221 * 110 200ns, 5.0 Mbytes/s 222 * 111 250ns, 4.0 Mbytes/s 223 * 224 *Fast40: 000 25ns, 40.0 Mbytes/s 225 * 001 50ns, 20.0 Mbytes/s 226 * 010 75ns, 13.3 Mbytes/s 227 * 011 100ns, 10.0 Mbytes/s 228 * 100 125ns, 8.0 Mbytes/s 229 * 101 150ns, 6.6 Mbytes/s 230 * 110 175ns, 5.7 Mbytes/s 231 * 111 200ns, 5.0 Mbytes/s 232 */ 233 /* real period: */ 234 u_int8_t dc395x_clock_period[] = { 235 12,/* 48 ns 20 MB/sec */ 236 18,/* 72 ns 13.3 MB/sec */ 237 25,/* 100 ns 10.0 MB/sec */ 238 31,/* 124 ns 8.0 MB/sec */ 239 37,/* 148 ns 6.6 MB/sec */ 240 43,/* 172 ns 5.7 MB/sec */ 241 50,/* 200 ns 5.0 MB/sec */ 242 62 /* 248 ns 4.0 MB/sec */ 243 }; 244 245 u_int8_t dc395u2x_clock_period[]={ 246 10,/* 25 ns 40.0 MB/sec */ 247 12,/* 48 ns 20.0 MB/sec */ 248 18,/* 72 ns 13.3 MB/sec */ 249 25,/* 100 ns 10.0 MB/sec */ 250 31,/* 124 ns 8.0 MB/sec */ 251 37,/* 148 ns 6.6 MB/sec */ 252 43,/* 172 ns 5.7 MB/sec */ 253 50,/* 200 ns 5.0 MB/sec */ 254 }; 255 256 #define dc395x_tinfo_period dc395x_clock_period 257 #define dc395u2x_tinfo_period dc395u2x_clock_period 258 259 static PSRB 260 trm_GetSRB(PACB pACB) 261 { 262 int intflag; 263 PSRB pSRB; 264 265 intflag = splcam(); 266 pSRB = pACB->pFreeSRB; 267 if (pSRB) { 268 pACB->pFreeSRB = pSRB->pNextSRB; 269 pSRB->pNextSRB = NULL; 270 } 271 splx(intflag); 272 return (pSRB); 273 } 274 275 static void 276 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 277 { 278 PSRB psrb1; 279 int intflag; 280 281 intflag = splcam(); 282 if ((psrb1 = pDCB->pWaitingSRB)) { 283 pSRB->pNextSRB = psrb1; 284 pDCB->pWaitingSRB = pSRB; 285 } else { 286 pSRB->pNextSRB = NULL; 287 pDCB->pWaitingSRB = pSRB; 288 pDCB->pWaitingLastSRB = pSRB; 289 } 290 splx(intflag); 291 } 292 293 static void 294 trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 295 { 296 PSRB psrb1; 297 int intflag; 298 299 intflag = splcam(); 300 pDCB->GoingSRBCnt--; 301 psrb1 = pDCB->pGoingSRB; 302 if (pSRB == psrb1) 303 /* 304 * if this SRB is GoingSRB 305 * remove this SRB from GoingSRB Q 306 */ 307 pDCB->pGoingSRB = psrb1->pNextSRB; 308 else { 309 /* 310 * if this SRB is not current GoingSRB 311 * remove this SRB from GoingSRB Q 312 */ 313 while (pSRB != psrb1->pNextSRB) 314 psrb1 = psrb1->pNextSRB; 315 psrb1->pNextSRB = pSRB->pNextSRB; 316 if (pSRB == pDCB->pGoingLastSRB) 317 pDCB->pGoingLastSRB = psrb1; 318 } 319 if ((psrb1 = pDCB->pWaitingSRB)) { 320 /* 321 * if WaitingSRB Q is not NULL 322 * Q back this SRB into WaitingSRB 323 */ 324 325 pSRB->pNextSRB = psrb1; 326 pDCB->pWaitingSRB = pSRB; 327 } else { 328 pSRB->pNextSRB = NULL; 329 pDCB->pWaitingSRB = pSRB; 330 pDCB->pWaitingLastSRB = pSRB; 331 } 332 splx(intflag); 333 } 334 335 static void 336 trm_DoWaitingSRB(PACB pACB) 337 { 338 int intflag; 339 PDCB ptr, ptr1; 340 PSRB pSRB; 341 342 intflag = splcam(); 343 if (!(pACB->pActiveDCB) && 344 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 345 ptr = pACB->pDCBRunRobin; 346 if (!ptr) { 347 ptr = pACB->pLinkDCB; 348 pACB->pDCBRunRobin = ptr; 349 } 350 ptr1 = ptr; 351 for (;ptr1 ;) { 352 pACB->pDCBRunRobin = ptr1->pNextDCB; 353 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 354 || !(pSRB = ptr1->pWaitingSRB)) { 355 if (pACB->pDCBRunRobin == ptr) 356 break; 357 ptr1 = ptr1->pNextDCB; 358 } else { 359 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 360 /* 361 * If trm_StartSCSI return 0 : 362 * current interrupt status is interrupt enable 363 * It's said that SCSI processor is unoccupied 364 */ 365 ptr1->GoingSRBCnt++; 366 if (ptr1->pWaitingLastSRB == pSRB) { 367 ptr1->pWaitingSRB = NULL; 368 ptr1->pWaitingLastSRB = NULL; 369 } else 370 ptr1->pWaitingSRB = pSRB->pNextSRB; 371 pSRB->pNextSRB = NULL; 372 if (ptr1->pGoingSRB) 373 ptr1->pGoingLastSRB->pNextSRB = pSRB; 374 else 375 ptr1->pGoingSRB = pSRB; 376 ptr1->pGoingLastSRB = pSRB; 377 } 378 break; 379 } 380 } 381 } 382 splx(intflag); 383 return; 384 } 385 386 static void 387 trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 388 { 389 390 if (pDCB->pWaitingSRB) { 391 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 392 pDCB->pWaitingLastSRB = pSRB; 393 pSRB->pNextSRB = NULL; 394 } else { 395 pDCB->pWaitingSRB = pSRB; 396 pDCB->pWaitingLastSRB = pSRB; 397 } 398 } 399 400 static u_int32_t 401 trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 402 { 403 int offset; 404 405 offset = pSRB->TagNumber; 406 return (pACB->sense_busaddr + 407 (offset * sizeof(struct scsi_sense_data))); 408 } 409 410 static struct scsi_sense_data * 411 trm_get_sense_buf(PACB pACB, PSRB pSRB) 412 { 413 int offset; 414 415 offset = pSRB->TagNumber; 416 return (&pACB->sense_buffers[offset]); 417 } 418 static void 419 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 420 { 421 int flags; 422 PACB pACB; 423 PSRB pSRB; 424 union ccb *ccb; 425 u_long totalxferlen=0; 426 427 flags = splcam(); 428 pSRB = (PSRB)arg; 429 ccb = pSRB->pccb; 430 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 431 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 432 if (nseg != 0) { 433 PSEG psg; 434 bus_dma_segment_t *end_seg; 435 int op; 436 437 /* Copy the segments into our SG list */ 438 end_seg = dm_segs + nseg; 439 psg = pSRB->pSRBSGL; 440 while (dm_segs < end_seg) { 441 psg->address = dm_segs->ds_addr; 442 psg->length = (u_long)dm_segs->ds_len; 443 totalxferlen += dm_segs->ds_len; 444 psg++; 445 dm_segs++; 446 } 447 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 448 op = BUS_DMASYNC_PREREAD; 449 } else { 450 op = BUS_DMASYNC_PREWRITE; 451 } 452 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 453 } 454 pSRB->RetryCnt = 0; 455 pSRB->SRBTotalXferLength = totalxferlen; 456 pSRB->SRBSGCount = nseg; 457 pSRB->SRBSGIndex = 0; 458 pSRB->AdaptStatus = 0; 459 pSRB->TargetStatus = 0; 460 pSRB->MsgCnt = 0; 461 pSRB->SRBStatus = 0; 462 pSRB->SRBFlag = 0; 463 pSRB->SRBState = 0; 464 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 465 466 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 467 if (nseg != 0) 468 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 469 pSRB->pNextSRB = pACB->pFreeSRB; 470 pACB->pFreeSRB = pSRB; 471 xpt_done(ccb); 472 splx(flags); 473 return; 474 } 475 ccb->ccb_h.status |= CAM_SIM_QUEUED; 476 #if 0 477 /* XXX Need a timeout handler */ 478 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000); 479 #endif 480 trm_SendSRB(pACB, pSRB); 481 splx(flags); 482 return; 483 } 484 485 static void 486 trm_SendSRB(PACB pACB, PSRB pSRB) 487 { 488 PDCB pDCB; 489 490 pDCB = pSRB->pSRBDCB; 491 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 492 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 493 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 494 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 495 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 496 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 497 trm_SRBwaiting(pDCB, pSRB); 498 goto SND_EXIT; 499 } 500 501 if (pDCB->pWaitingSRB) { 502 trm_SRBwaiting(pDCB, pSRB); 503 pSRB = pDCB->pWaitingSRB; 504 pDCB->pWaitingSRB = pSRB->pNextSRB; 505 pSRB->pNextSRB = NULL; 506 } 507 508 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 509 /* 510 * If trm_StartSCSI return 0 : 511 * current interrupt status is interrupt enable 512 * It's said that SCSI processor is unoccupied 513 */ 514 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 515 if (pDCB->pGoingSRB) { 516 pDCB->pGoingLastSRB->pNextSRB = pSRB; 517 pDCB->pGoingLastSRB = pSRB; 518 } else { 519 pDCB->pGoingSRB = pSRB; 520 pDCB->pGoingLastSRB = pSRB; 521 } 522 } else { 523 /* 524 * If trm_StartSCSI return 1 : 525 * current interrupt status is interrupt disreenable 526 * It's said that SCSI processor has more one SRB need to do 527 */ 528 trm_RewaitSRB0(pDCB, pSRB); 529 } 530 SND_EXIT: 531 return; 532 } 533 534 535 static void 536 trm_action(struct cam_sim *psim, union ccb *pccb) 537 { 538 PACB pACB; 539 int actionflags; 540 u_int target_id,target_lun; 541 542 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 543 544 actionflags = splcam(); 545 pACB = (PACB) cam_sim_softc(psim); 546 target_id = pccb->ccb_h.target_id; 547 target_lun = pccb->ccb_h.target_lun; 548 549 switch (pccb->ccb_h.func_code) { 550 case XPT_NOOP: 551 TRM_DPRINTF(" XPT_NOOP \n"); 552 pccb->ccb_h.status = CAM_REQ_INVALID; 553 xpt_done(pccb); 554 break; 555 /* 556 * Execute the requested I/O operation 557 */ 558 case XPT_SCSI_IO: { 559 PDCB pDCB = NULL; 560 PSRB pSRB; 561 struct ccb_scsiio *pcsio; 562 int error; 563 564 pcsio = &pccb->csio; 565 TRM_DPRINTF(" XPT_SCSI_IO \n"); 566 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 567 ,target_id, target_lun); 568 TRM_DPRINTF( 569 "pACB->scan_devices[target_id][target_lun]= %d \n" 570 ,pACB->scan_devices[target_id][target_lun]); 571 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 572 CAM_REQ_INPROG) { 573 xpt_done(pccb); 574 splx(actionflags); 575 return; 576 } 577 pDCB = &pACB->DCBarray[target_id][target_lun]; 578 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 579 pACB->scan_devices[target_id][target_lun] = 1; 580 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 581 target_id, target_lun); 582 } 583 /* 584 * Assign an SRB and connect it with this ccb. 585 */ 586 pSRB = trm_GetSRB(pACB); 587 if (!pSRB) { 588 /* Freeze SIMQ */ 589 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 590 xpt_done(pccb); 591 splx(actionflags); 592 return; 593 } 594 pSRB->pSRBDCB = pDCB; 595 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 596 pccb->ccb_h.ccb_trmacb_ptr = pACB; 597 pSRB->pccb = pccb; 598 pSRB->ScsiCmdLen = pcsio->cdb_len; 599 /* 600 * move layer of CAM command block to layer of SCSI 601 * Request Block for SCSI processor command doing 602 */ 603 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 604 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 605 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 606 ,pcsio->cdb_len); 607 } else { 608 pccb->ccb_h.status = CAM_REQ_INVALID; 609 pSRB->pNextSRB = pACB->pFreeSRB; 610 pACB->pFreeSRB= pSRB; 611 xpt_done(pccb); 612 splx(actionflags); 613 return; 614 } 615 } else 616 bcopy(pcsio->cdb_io.cdb_bytes, 617 pSRB->CmdBlock, pcsio->cdb_len); 618 error = bus_dmamap_load_ccb(pACB->buffer_dmat, 619 pSRB->dmamap, 620 pccb, 621 trm_ExecuteSRB, 622 pSRB, 623 0); 624 if (error == EINPROGRESS) { 625 xpt_freeze_simq(pACB->psim, 1); 626 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 627 } 628 break; 629 } 630 case XPT_GDEV_TYPE: 631 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 632 pccb->ccb_h.status = CAM_REQ_INVALID; 633 xpt_done(pccb); 634 break; 635 case XPT_GDEVLIST: 636 TRM_DPRINTF(" XPT_GDEVLIST \n"); 637 pccb->ccb_h.status = CAM_REQ_INVALID; 638 xpt_done(pccb); 639 break; 640 /* 641 * Path routing inquiry 642 * Path Inquiry CCB 643 */ 644 case XPT_PATH_INQ: { 645 struct ccb_pathinq *cpi = &pccb->cpi; 646 647 TRM_DPRINTF(" XPT_PATH_INQ \n"); 648 cpi->version_num = 1; 649 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 650 cpi->target_sprt = 0; 651 cpi->hba_misc = 0; 652 cpi->hba_eng_cnt = 0; 653 cpi->max_target = 15 ; 654 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 655 cpi->initiator_id = pACB->AdaptSCSIID; 656 cpi->bus_id = cam_sim_bus(psim); 657 cpi->base_transfer_speed = 3300; 658 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 659 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 660 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 661 cpi->unit_number = cam_sim_unit(psim); 662 cpi->transport = XPORT_SPI; 663 cpi->transport_version = 2; 664 cpi->protocol = PROTO_SCSI; 665 cpi->protocol_version = SCSI_REV_2; 666 cpi->ccb_h.status = CAM_REQ_CMP; 667 xpt_done(pccb); 668 } 669 break; 670 /* 671 * Release a frozen SIM queue 672 * Release SIM Queue 673 */ 674 case XPT_REL_SIMQ: 675 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 676 pccb->ccb_h.status = CAM_REQ_INVALID; 677 xpt_done(pccb); 678 break; 679 /* 680 * Set Asynchronous Callback Parameters 681 * Set Asynchronous Callback CCB 682 */ 683 case XPT_SASYNC_CB: 684 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 685 pccb->ccb_h.status = CAM_REQ_INVALID; 686 xpt_done(pccb); 687 break; 688 /* 689 * Set device type information 690 * Set Device Type CCB 691 */ 692 case XPT_SDEV_TYPE: 693 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 694 pccb->ccb_h.status = CAM_REQ_INVALID; 695 xpt_done(pccb); 696 break; 697 /* 698 * Get EDT entries matching the given pattern 699 */ 700 case XPT_DEV_MATCH: 701 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 702 pccb->ccb_h.status = CAM_REQ_INVALID; 703 xpt_done(pccb); 704 break; 705 /* 706 * Turn on debugging for a bus, target or lun 707 */ 708 case XPT_DEBUG: 709 TRM_DPRINTF(" XPT_DEBUG \n"); 710 pccb->ccb_h.status = CAM_REQ_INVALID; 711 xpt_done(pccb); 712 break; 713 /* 714 * XPT_ABORT = 0x10, Abort the specified CCB 715 * Abort XPT request CCB 716 */ 717 case XPT_ABORT: 718 TRM_DPRINTF(" XPT_ABORT \n"); 719 pccb->ccb_h.status = CAM_REQ_INVALID; 720 xpt_done(pccb); 721 break; 722 /* 723 * Reset the specified SCSI bus 724 * Reset SCSI Bus CCB 725 */ 726 case XPT_RESET_BUS: { 727 int i; 728 729 TRM_DPRINTF(" XPT_RESET_BUS \n"); 730 trm_reset(pACB); 731 pACB->ACBFlag=0; 732 for (i=0; i<500; i++) 733 DELAY(1000); 734 pccb->ccb_h.status = CAM_REQ_CMP; 735 xpt_done(pccb); 736 } 737 break; 738 /* 739 * Bus Device Reset the specified SCSI device 740 * Reset SCSI Device CCB 741 */ 742 case XPT_RESET_DEV: 743 /* 744 * Don't (yet?) support vendor 745 * specific commands. 746 */ 747 TRM_DPRINTF(" XPT_RESET_DEV \n"); 748 pccb->ccb_h.status = CAM_REQ_INVALID; 749 xpt_done(pccb); 750 break; 751 /* 752 * Terminate the I/O process 753 * Terminate I/O Process Request CCB 754 */ 755 case XPT_TERM_IO: 756 TRM_DPRINTF(" XPT_TERM_IO \n"); 757 pccb->ccb_h.status = CAM_REQ_INVALID; 758 xpt_done(pccb); 759 break; 760 /* 761 * Get/Set transfer rate/width/disconnection/tag queueing 762 * settings 763 * (GET) default/user transfer settings for the target 764 */ 765 case XPT_GET_TRAN_SETTINGS: { 766 struct ccb_trans_settings *cts = &pccb->cts; 767 int intflag; 768 struct trm_transinfo *tinfo; 769 PDCB pDCB; 770 struct ccb_trans_settings_scsi *scsi = 771 &cts->proto_specific.scsi; 772 struct ccb_trans_settings_spi *spi = 773 &cts->xport_specific.spi; 774 775 cts->protocol = PROTO_SCSI; 776 cts->protocol_version = SCSI_REV_2; 777 cts->transport = XPORT_SPI; 778 cts->transport_version = 2; 779 780 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 781 pDCB = &pACB->DCBarray[target_id][target_lun]; 782 intflag = splcam(); 783 /* 784 * disable interrupt 785 */ 786 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 787 /* current transfer settings */ 788 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 789 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 790 else 791 spi->flags = 0;/* no tag & disconnect */ 792 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 793 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 794 tinfo = &pDCB->tinfo.current; 795 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 796 cts->flags); 797 } else { 798 /* default(user) transfer settings */ 799 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 800 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 801 else 802 spi->flags = 0; 803 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 804 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 805 tinfo = &pDCB->tinfo.user; 806 TRM_DPRINTF("USER: cts->flags= %2x \n", 807 cts->flags); 808 } 809 spi->sync_period = tinfo->period; 810 spi->sync_offset = tinfo->offset; 811 spi->bus_width = tinfo->width; 812 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 813 pDCB->SyncPeriod); 814 TRM_DPRINTF("period: %d \n", tinfo->period); 815 TRM_DPRINTF("offset: %d \n", tinfo->offset); 816 TRM_DPRINTF("width: %d \n", tinfo->width); 817 818 splx(intflag); 819 spi->valid = CTS_SPI_VALID_SYNC_RATE | 820 CTS_SPI_VALID_SYNC_OFFSET | 821 CTS_SPI_VALID_BUS_WIDTH | 822 CTS_SPI_VALID_DISC; 823 scsi->valid = CTS_SCSI_VALID_TQ; 824 pccb->ccb_h.status = CAM_REQ_CMP; 825 xpt_done(pccb); 826 } 827 break; 828 /* 829 * Get/Set transfer rate/width/disconnection/tag queueing 830 * settings 831 * (Set) transfer rate/width negotiation settings 832 */ 833 case XPT_SET_TRAN_SETTINGS: { 834 struct ccb_trans_settings *cts = &pccb->cts; 835 u_int update_type; 836 int intflag; 837 PDCB pDCB; 838 struct ccb_trans_settings_scsi *scsi = 839 &cts->proto_specific.scsi; 840 struct ccb_trans_settings_spi *spi = 841 &cts->xport_specific.spi; 842 843 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 844 update_type = 0; 845 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 846 update_type |= TRM_TRANS_GOAL; 847 if (cts->type == CTS_TYPE_USER_SETTINGS) 848 update_type |= TRM_TRANS_USER; 849 intflag = splcam(); 850 pDCB = &pACB->DCBarray[target_id][target_lun]; 851 852 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 853 /*ccb disc enables */ 854 if (update_type & TRM_TRANS_GOAL) { 855 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 856 != 0) 857 pDCB->tinfo.disc_tag 858 |= TRM_CUR_DISCENB; 859 else 860 pDCB->tinfo.disc_tag &= 861 ~TRM_CUR_DISCENB; 862 } 863 if (update_type & TRM_TRANS_USER) { 864 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 865 != 0) 866 pDCB->tinfo.disc_tag 867 |= TRM_USR_DISCENB; 868 else 869 pDCB->tinfo.disc_tag &= 870 ~TRM_USR_DISCENB; 871 } 872 } 873 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 874 /* if ccb tag q active */ 875 if (update_type & TRM_TRANS_GOAL) { 876 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 877 != 0) 878 pDCB->tinfo.disc_tag |= 879 TRM_CUR_TAGENB; 880 else 881 pDCB->tinfo.disc_tag &= 882 ~TRM_CUR_TAGENB; 883 } 884 if (update_type & TRM_TRANS_USER) { 885 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 886 != 0) 887 pDCB->tinfo.disc_tag |= 888 TRM_USR_TAGENB; 889 else 890 pDCB->tinfo.disc_tag &= 891 ~TRM_USR_TAGENB; 892 } 893 } 894 /* Minimum sync period factor */ 895 896 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 897 /* if ccb sync active */ 898 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 899 if ((spi->sync_period != 0) && 900 (spi->sync_period < 125)) 901 spi->sync_period = 125; 902 /* 1/(125*4) minsync 2 MByte/sec */ 903 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) 904 != 0) { 905 if (spi->sync_offset == 0) 906 spi->sync_period = 0; 907 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 908 if (spi->sync_offset > 15) 909 spi->sync_offset = 15; 910 } 911 } 912 if ((update_type & TRM_TRANS_USER) != 0) { 913 pDCB->tinfo.user.period = spi->sync_period; 914 pDCB->tinfo.user.offset = spi->sync_offset; 915 pDCB->tinfo.user.width = spi->bus_width; 916 } 917 if ((update_type & TRM_TRANS_GOAL) != 0) { 918 pDCB->tinfo.goal.period = spi->sync_period; 919 pDCB->tinfo.goal.offset = spi->sync_offset; 920 pDCB->tinfo.goal.width = spi->bus_width; 921 } 922 splx(intflag); 923 pccb->ccb_h.status = CAM_REQ_CMP; 924 xpt_done(pccb); 925 break; 926 } 927 /* 928 * Calculate the geometry parameters for a device give 929 * the sector size and volume size. 930 */ 931 case XPT_CALC_GEOMETRY: 932 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 933 cam_calc_geometry(&pccb->ccg, /*extended*/1); 934 xpt_done(pccb); 935 break; 936 case XPT_ENG_INQ: 937 TRM_DPRINTF(" XPT_ENG_INQ \n"); 938 pccb->ccb_h.status = CAM_REQ_INVALID; 939 xpt_done(pccb); 940 break; 941 /* 942 * HBA execute engine request 943 * This structure must match SCSIIO size 944 */ 945 case XPT_ENG_EXEC: 946 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 947 pccb->ccb_h.status = CAM_REQ_INVALID; 948 xpt_done(pccb); 949 break; 950 /* 951 * XPT_EN_LUN = 0x30, Enable LUN as a target 952 * Target mode structures. 953 */ 954 case XPT_EN_LUN: 955 /* 956 * Don't (yet?) support vendor 957 * specific commands. 958 */ 959 TRM_DPRINTF(" XPT_EN_LUN \n"); 960 pccb->ccb_h.status = CAM_REQ_INVALID; 961 xpt_done(pccb); 962 break; 963 /* 964 * Execute target I/O request 965 */ 966 case XPT_TARGET_IO: 967 /* 968 * Don't (yet?) support vendor 969 * specific commands. 970 */ 971 TRM_DPRINTF(" XPT_TARGET_IO \n"); 972 pccb->ccb_h.status = CAM_REQ_INVALID; 973 xpt_done(pccb); 974 break; 975 /* 976 * Accept Host Target Mode CDB 977 */ 978 case XPT_ACCEPT_TARGET_IO: 979 /* 980 * Don't (yet?) support vendor 981 * specific commands. 982 */ 983 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 984 pccb->ccb_h.status = CAM_REQ_INVALID; 985 xpt_done(pccb); 986 break; 987 /* 988 * Continue Host Target I/O Connection 989 */ 990 case XPT_CONT_TARGET_IO: 991 /* 992 * Don't (yet?) support vendor 993 * specific commands. 994 */ 995 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 996 pccb->ccb_h.status = CAM_REQ_INVALID; 997 xpt_done(pccb); 998 break; 999 /* 1000 * Notify Host Target driver of event 1001 */ 1002 case XPT_IMMED_NOTIFY: 1003 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1004 pccb->ccb_h.status = CAM_REQ_INVALID; 1005 xpt_done(pccb); 1006 break; 1007 /* 1008 * Acknowledgement of event 1009 */ 1010 case XPT_NOTIFY_ACK: 1011 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1012 pccb->ccb_h.status = CAM_REQ_INVALID; 1013 xpt_done(pccb); 1014 break; 1015 /* 1016 * XPT_VUNIQUE = 0x80 1017 */ 1018 case XPT_VUNIQUE: 1019 pccb->ccb_h.status = CAM_REQ_INVALID; 1020 xpt_done(pccb); 1021 break; 1022 default: 1023 pccb->ccb_h.status = CAM_REQ_INVALID; 1024 xpt_done(pccb); 1025 break; 1026 } 1027 splx(actionflags); 1028 } 1029 1030 static void 1031 trm_poll(struct cam_sim *psim) 1032 { 1033 trm_Interrupt(cam_sim_softc(psim)); 1034 } 1035 1036 static void 1037 trm_ResetDevParam(PACB pACB) 1038 { 1039 PDCB pDCB, pdcb; 1040 PNVRAMTYPE pEEpromBuf; 1041 u_int8_t PeriodIndex; 1042 1043 pDCB = pACB->pLinkDCB; 1044 if (pDCB == NULL) 1045 return; 1046 pdcb = pDCB; 1047 do { 1048 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1049 pDCB->SyncPeriod = 0; 1050 pDCB->SyncOffset = 0; 1051 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1052 pDCB->DevMode = 1053 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1054 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1055 PeriodIndex = 1056 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1057 if (pACB->AdaptType == 1) /* is U2? */ 1058 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1059 else 1060 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1061 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1062 (pACB->Config & HCC_WIDE_CARD)) 1063 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1064 pDCB = pDCB->pNextDCB; 1065 } 1066 while (pdcb != pDCB); 1067 } 1068 1069 static void 1070 trm_RecoverSRB(PACB pACB) 1071 { 1072 PDCB pDCB, pdcb; 1073 PSRB psrb, psrb2; 1074 u_int16_t cnt, i; 1075 1076 pDCB = pACB->pLinkDCB; 1077 if (pDCB == NULL) 1078 return; 1079 pdcb = pDCB; 1080 do { 1081 cnt = pdcb->GoingSRBCnt; 1082 psrb = pdcb->pGoingSRB; 1083 for (i = 0; i < cnt; i++) { 1084 psrb2 = psrb; 1085 psrb = psrb->pNextSRB; 1086 if (pdcb->pWaitingSRB) { 1087 psrb2->pNextSRB = pdcb->pWaitingSRB; 1088 pdcb->pWaitingSRB = psrb2; 1089 } else { 1090 pdcb->pWaitingSRB = psrb2; 1091 pdcb->pWaitingLastSRB = psrb2; 1092 psrb2->pNextSRB = NULL; 1093 } 1094 } 1095 pdcb->GoingSRBCnt = 0; 1096 pdcb->pGoingSRB = NULL; 1097 pdcb = pdcb->pNextDCB; 1098 } 1099 while (pdcb != pDCB); 1100 } 1101 1102 static void 1103 trm_reset(PACB pACB) 1104 { 1105 int intflag; 1106 u_int16_t i; 1107 1108 TRM_DPRINTF("trm: RESET"); 1109 intflag = splcam(); 1110 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1111 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1112 1113 trm_ResetSCSIBus(pACB); 1114 for (i = 0; i < 500; i++) 1115 DELAY(1000); 1116 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1117 /* Enable DMA interrupt */ 1118 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1119 /* Clear DMA FIFO */ 1120 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1121 /* Clear SCSI FIFO */ 1122 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1123 trm_ResetDevParam(pACB); 1124 trm_DoingSRB_Done(pACB); 1125 pACB->pActiveDCB = NULL; 1126 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1127 trm_DoWaitingSRB(pACB); 1128 /* Tell the XPT layer that a bus reset occured */ 1129 if (pACB->ppath != NULL) 1130 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1131 splx(intflag); 1132 return; 1133 } 1134 1135 static u_int16_t 1136 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1137 { 1138 u_int16_t return_code; 1139 u_int8_t scsicommand, i,command,identify_message; 1140 u_int8_t * ptr; 1141 union ccb *pccb; 1142 struct ccb_scsiio *pcsio; 1143 1144 pccb = pSRB->pccb; 1145 pcsio = &pccb->csio; 1146 1147 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1148 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1149 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1150 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1151 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1152 /* Flush FIFO */ 1153 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1154 1155 identify_message = pDCB->IdentifyMsg; 1156 1157 if ((pSRB->CmdBlock[0] == INQUIRY) || 1158 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1159 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1160 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1161 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1162 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1163 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1164 if (!(pDCB->IdentifyMsg & 7) || 1165 (pSRB->CmdBlock[0] != INQUIRY)) { 1166 scsicommand = SCMD_SEL_ATNSTOP; 1167 pSRB->SRBState = SRB_MSGOUT; 1168 goto polling; 1169 } 1170 } 1171 /* 1172 * Send identify message 1173 */ 1174 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1175 scsicommand = SCMD_SEL_ATN; 1176 pSRB->SRBState = SRB_START_; 1177 } else { 1178 /* not inquiry,request sense,auto request sense */ 1179 /* 1180 * Send identify message 1181 */ 1182 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1183 scsicommand = SCMD_SEL_ATN; 1184 pSRB->SRBState = SRB_START_; 1185 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1186 /* Send Tag message */ 1187 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1188 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1189 scsicommand = SCMD_SEL_ATN3; 1190 } 1191 } 1192 polling: 1193 /* 1194 * Send CDB ..command block ......... 1195 */ 1196 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1197 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1198 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1199 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1200 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1201 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1202 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1203 } else { 1204 ptr = (u_int8_t *) pSRB->CmdBlock; 1205 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1206 command = *ptr++; 1207 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1208 } 1209 } 1210 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1211 /* 1212 * If trm_StartSCSI return 1 : 1213 * current interrupt status is interrupt disreenable 1214 * It's said that SCSI processor has more one SRB need to do, 1215 * SCSI processor has been occupied by one SRB. 1216 */ 1217 pSRB->SRBState = SRB_READY; 1218 return_code = 1; 1219 } else { 1220 /* 1221 * If trm_StartSCSI return 0 : 1222 * current interrupt status is interrupt enable 1223 * It's said that SCSI processor is unoccupied 1224 */ 1225 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1226 pACB->pActiveDCB = pDCB; 1227 pDCB->pActiveSRB = pSRB; 1228 return_code = 0; 1229 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1230 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1231 /* 1232 * SCSI cammand 1233 */ 1234 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1235 } 1236 return (return_code); 1237 } 1238 1239 static void 1240 trm_Interrupt(vpACB) 1241 void *vpACB; 1242 { 1243 PACB pACB; 1244 PDCB pDCB; 1245 PSRB pSRB; 1246 u_int16_t phase; 1247 void (*stateV)(PACB, PSRB, u_int16_t *); 1248 u_int16_t scsi_status=0; 1249 u_int8_t scsi_intstatus; 1250 1251 pACB = vpACB; 1252 1253 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1254 if (!(scsi_status & SCSIINTERRUPT)) { 1255 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1256 return; 1257 } 1258 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1259 1260 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1261 1262 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1263 1264 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1265 trm_Disconnect(pACB); 1266 return; 1267 } 1268 1269 if (scsi_intstatus & INT_RESELECTED) { 1270 trm_Reselect(pACB); 1271 return; 1272 } 1273 if (scsi_intstatus & INT_SCSIRESET) { 1274 trm_ScsiRstDetect(pACB); 1275 return; 1276 } 1277 1278 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1279 pDCB = pACB->pActiveDCB; 1280 KASSERT(pDCB != NULL, ("no active DCB")); 1281 pSRB = pDCB->pActiveSRB; 1282 if (pDCB->DCBFlag & ABORT_DEV_) 1283 trm_EnableMsgOutAbort1(pACB, pSRB); 1284 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1285 stateV = (void *) trm_SCSI_phase0[phase]; 1286 stateV(pACB, pSRB, &scsi_status); 1287 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1288 /* phase:0,1,2,3,4,5,6,7 */ 1289 phase = (u_int16_t) scsi_status & PHASEMASK; 1290 stateV = (void *) trm_SCSI_phase1[phase]; 1291 stateV(pACB, pSRB, &scsi_status); 1292 } 1293 } 1294 1295 static void 1296 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1297 { 1298 1299 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1300 *pscsi_status = PH_BUS_FREE; 1301 /*.. initial phase*/ 1302 } 1303 1304 static void 1305 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1306 { 1307 u_int8_t bval; 1308 u_int16_t i, cnt; 1309 u_int8_t * ptr; 1310 PDCB pDCB; 1311 1312 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1313 pDCB = pACB->pActiveDCB; 1314 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1315 cnt = pSRB->MsgCnt; 1316 if (cnt) { 1317 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1318 for (i = 0; i < cnt; i++) { 1319 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1320 ptr++; 1321 } 1322 pSRB->MsgCnt = 0; 1323 if ((pDCB->DCBFlag & ABORT_DEV_) && 1324 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1325 pSRB->SRBState = SRB_ABORT_SENT; 1326 } 1327 } else { 1328 bval = MSG_ABORT; 1329 if ((pSRB->CmdBlock[0] == INQUIRY) || 1330 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1331 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1332 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1333 goto mop1; 1334 } 1335 } 1336 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1337 } 1338 } else { 1339 mop1: /* message out phase */ 1340 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1341 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1342 /* 1343 * WIDE DATA TRANSFER REQUEST code (03h) 1344 */ 1345 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1346 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1347 TRMREG_SCSI_FIFO); 1348 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1349 /* (01h) */ 1350 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1351 /* Message length (02h) */ 1352 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1353 /* wide data xfer (03h) */ 1354 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1355 /* width:0(8bit),1(16bit),2(32bit) */ 1356 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1357 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1358 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1359 /* 1360 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1361 */ 1362 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1363 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1364 TRMREG_SCSI_FIFO); 1365 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1366 /* (01h) */ 1367 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1368 /* Message length (03h) */ 1369 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1370 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1371 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1372 /* Transfer peeriod factor */ 1373 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1374 TRMREG_SCSI_FIFO); 1375 /* REQ/ACK offset */ 1376 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1377 } 1378 } 1379 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1380 /* it's important for atn stop */ 1381 /* 1382 * SCSI cammand 1383 */ 1384 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1385 } 1386 1387 static void 1388 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1389 { 1390 1391 } 1392 1393 static void 1394 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1395 { 1396 PDCB pDCB; 1397 u_int8_t * ptr; 1398 u_int16_t i, cnt; 1399 union ccb *pccb; 1400 struct ccb_scsiio *pcsio; 1401 1402 pccb = pSRB->pccb; 1403 pcsio = &pccb->csio; 1404 1405 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1406 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1407 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1408 ptr = (u_int8_t *) pSRB->CmdBlock; 1409 for (i = 0; i < cnt; i++) { 1410 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1411 ptr++; 1412 } 1413 } else { 1414 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1415 pDCB = pACB->pActiveDCB; 1416 /* target id */ 1417 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1418 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1419 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1420 /* sizeof(struct scsi_sense_data) */ 1421 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1422 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1423 } 1424 pSRB->SRBState = SRB_COMMAND; 1425 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1426 /* it's important for atn stop*/ 1427 /* 1428 * SCSI cammand 1429 */ 1430 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1431 } 1432 1433 static void 1434 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1435 { 1436 PDCB pDCB; 1437 u_int8_t TempDMAstatus,SGIndexTemp; 1438 u_int16_t scsi_status; 1439 PSEG pseg; 1440 u_long TempSRBXferredLength,dLeftCounter=0; 1441 1442 pDCB = pSRB->pSRBDCB; 1443 scsi_status = *pscsi_status; 1444 1445 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1446 if (scsi_status & PARITYERROR) 1447 pSRB->SRBStatus |= PARITY_ERROR; 1448 if (!(scsi_status & SCSIXFERDONE)) { 1449 /* 1450 * when data transfer from DMA FIFO to SCSI FIFO 1451 * if there was some data left in SCSI FIFO 1452 */ 1453 dLeftCounter = (u_long) 1454 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1455 if (pDCB->SyncPeriod & WIDE_SYNC) { 1456 /* 1457 * if WIDE scsi SCSI FIFOCNT unit is word 1458 * so need to * 2 1459 */ 1460 dLeftCounter <<= 1; 1461 } 1462 } 1463 /* 1464 * caculate all the residue data that not yet tranfered 1465 * SCSI transfer counter + left in SCSI FIFO data 1466 * 1467 * .....TRM_SCSI_COUNTER (24bits) 1468 * The counter always decrement by one for every SCSI byte 1469 *transfer. 1470 * .....TRM_SCSI_FIFOCNT (5bits) 1471 * The counter is SCSI FIFO offset counter 1472 */ 1473 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1474 if (dLeftCounter == 1) { 1475 dLeftCounter = 0; 1476 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1477 } 1478 if ((dLeftCounter == 0) || 1479 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1480 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1481 while (!(TempDMAstatus & DMAXFERCOMP)) { 1482 TempDMAstatus = 1483 trm_reg_read8(TRMREG_DMA_STATUS); 1484 } 1485 pSRB->SRBTotalXferLength = 0; 1486 } else { 1487 /* Update SG list */ 1488 /* 1489 * if transfer not yet complete 1490 * there were some data residue in SCSI FIFO or 1491 * SCSI transfer counter not empty 1492 */ 1493 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1494 /* 1495 * data that had transferred length 1496 */ 1497 TempSRBXferredLength = 1498 pSRB->SRBTotalXferLength - dLeftCounter; 1499 /* 1500 * next time to be transferred length 1501 */ 1502 pSRB->SRBTotalXferLength = dLeftCounter; 1503 /* 1504 * parsing from last time disconnect SRBSGIndex 1505 */ 1506 pseg = 1507 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1508 for (SGIndexTemp = pSRB->SRBSGIndex; 1509 SGIndexTemp < pSRB->SRBSGCount; 1510 SGIndexTemp++) { 1511 /* 1512 * find last time which SG transfer be 1513 * disconnect 1514 */ 1515 if (TempSRBXferredLength >= 1516 pseg->length) 1517 TempSRBXferredLength -= 1518 pseg->length; 1519 else { 1520 /* 1521 * update last time disconnected SG 1522 * list 1523 */ 1524 pseg->length -= 1525 TempSRBXferredLength; 1526 /* residue data length */ 1527 pseg->address += 1528 TempSRBXferredLength; 1529 /* residue data pointer */ 1530 pSRB->SRBSGIndex = SGIndexTemp; 1531 break; 1532 } 1533 pseg++; 1534 } 1535 } 1536 } 1537 } 1538 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1539 } 1540 1541 1542 static void 1543 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1544 { 1545 u_int16_t ioDir; 1546 /* 1547 * do prepare befor transfer when data out phase 1548 */ 1549 1550 ioDir = XFERDATAOUT; 1551 trm_DataIO_transfer(pACB, pSRB, ioDir); 1552 } 1553 1554 static void 1555 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1556 { 1557 u_int8_t TempDMAstatus, SGIndexTemp; 1558 u_int16_t scsi_status; 1559 PSEG pseg; 1560 u_long TempSRBXferredLength,dLeftCounter = 0; 1561 1562 scsi_status = *pscsi_status; 1563 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1564 if (scsi_status & PARITYERROR) 1565 pSRB->SRBStatus |= PARITY_ERROR; 1566 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1567 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1568 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1569 while (!(TempDMAstatus & DMAXFERCOMP)) 1570 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1571 pSRB->SRBTotalXferLength = 0; 1572 } else { 1573 /* 1574 * parsing the case: 1575 * when a transfer not yet complete 1576 * but be disconnected by uper layer 1577 * if transfer not yet complete 1578 * there were some data residue in SCSI FIFO or 1579 * SCSI transfer counter not empty 1580 */ 1581 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1582 /* 1583 * data that had transferred length 1584 */ 1585 TempSRBXferredLength = 1586 pSRB->SRBTotalXferLength - dLeftCounter; 1587 /* 1588 * next time to be transferred length 1589 */ 1590 pSRB->SRBTotalXferLength = dLeftCounter; 1591 /* 1592 * parsing from last time disconnect SRBSGIndex 1593 */ 1594 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1595 for (SGIndexTemp = pSRB->SRBSGIndex; 1596 SGIndexTemp < pSRB->SRBSGCount; 1597 SGIndexTemp++) { 1598 /* 1599 * find last time which SG transfer be disconnect 1600 */ 1601 if (TempSRBXferredLength >= pseg->length) 1602 TempSRBXferredLength -= pseg->length; 1603 else { 1604 /* 1605 * update last time disconnected SG list 1606 */ 1607 pseg->length -= TempSRBXferredLength; 1608 /* residue data length */ 1609 pseg->address += TempSRBXferredLength; 1610 /* residue data pointer */ 1611 pSRB->SRBSGIndex = SGIndexTemp; 1612 break; 1613 } 1614 pseg++; 1615 } 1616 } 1617 } 1618 } 1619 } 1620 1621 static void 1622 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1623 { 1624 u_int16_t ioDir; 1625 /* 1626 * do prepare befor transfer when data in phase 1627 */ 1628 1629 ioDir = XFERDATAIN; 1630 trm_DataIO_transfer(pACB, pSRB, ioDir); 1631 } 1632 1633 static void 1634 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1635 { 1636 u_int8_t bval; 1637 PDCB pDCB; 1638 1639 pDCB = pSRB->pSRBDCB; 1640 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1641 if (pSRB->SRBTotalXferLength != 0) { 1642 /* 1643 * load what physical address of Scatter/Gather list 1644 table want to be transfer 1645 */ 1646 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1647 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1648 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1649 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1650 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1651 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1652 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1653 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1654 1655 pSRB->SRBState = SRB_DATA_XFER; 1656 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1657 trm_reg_write32( 1658 (pSRB->SRBSGPhyAddr + 1659 ((u_long)pSRB->SRBSGIndex << 3)), 1660 TRMREG_DMA_XLOWADDR); 1661 /* 1662 * load how many bytes in the Scatter/Gather 1663 * list table 1664 */ 1665 trm_reg_write32( 1666 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1667 TRMREG_DMA_XCNT); 1668 /* 1669 * load total transfer length (24bits) max value 1670 * 16Mbyte 1671 */ 1672 trm_reg_write32(pSRB->SRBTotalXferLength, 1673 TRMREG_SCSI_COUNTER); 1674 /* Start DMA transfer */ 1675 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1676 /* Start SCSI transfer */ 1677 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1678 /* it's important for atn stop */ 1679 /* 1680 * SCSI cammand 1681 */ 1682 bval = (ioDir == XFERDATAOUT) ? 1683 SCMD_DMA_OUT : SCMD_DMA_IN; 1684 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1685 } else { 1686 /* xfer pad */ 1687 if (pSRB->SRBSGCount) { 1688 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1689 pSRB->SRBStatus |= OVER_RUN; 1690 } 1691 if (pDCB->SyncPeriod & WIDE_SYNC) 1692 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1693 else 1694 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1695 if (ioDir == XFERDATAOUT) 1696 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1697 else 1698 trm_reg_read16(TRMREG_SCSI_FIFO); 1699 pSRB->SRBState |= SRB_XFERPAD; 1700 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1701 /* it's important for atn stop */ 1702 /* 1703 * SCSI cammand 1704 */ 1705 bval = (ioDir == XFERDATAOUT) ? 1706 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1707 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1708 } 1709 } 1710 } 1711 1712 static void 1713 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1714 { 1715 1716 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1717 pSRB->SRBState = SRB_COMPLETED; 1718 *pscsi_status = PH_BUS_FREE; 1719 /*.. initial phase*/ 1720 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1721 /* it's important for atn stop */ 1722 /* 1723 * SCSI cammand 1724 */ 1725 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1726 } 1727 1728 1729 1730 static void 1731 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1732 { 1733 1734 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1735 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1736 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1737 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1738 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1739 } else { 1740 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1741 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1742 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1743 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1744 } 1745 pSRB->SRBState = SRB_STATUS; 1746 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1747 /* it's important for atn stop */ 1748 /* 1749 * SCSI cammand 1750 */ 1751 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1752 } 1753 1754 /* 1755 *scsiiom 1756 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1757 * stateV = (void *) trm_SCSI_phase0[phase] 1758 * if phase =7 1759 * extended message codes: 1760 * 1761 * code description 1762 * 1763 * 02h Reserved 1764 * 00h MODIFY DATA POINTER 1765 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1766 * 03h WIDE DATA TRANSFER REQUEST 1767 * 04h - 7Fh Reserved 1768 * 80h - FFh Vendor specific 1769 * 1770 */ 1771 1772 static void 1773 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1774 { 1775 u_int8_t message_in_code,bIndex,message_in_tag_id; 1776 PDCB pDCB; 1777 PSRB pSRBTemp; 1778 1779 pDCB = pACB->pActiveDCB; 1780 1781 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1782 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1783 if (message_in_code == MSG_DISCONNECT) { 1784 pSRB->SRBState = SRB_DISCONNECT; 1785 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1786 /* it's important for atn stop */ 1787 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1788 /* 1789 * SCSI command 1790 */ 1791 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1792 return; 1793 } else if (message_in_code == MSG_SAVE_PTR) { 1794 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1795 /* it's important for atn stop */ 1796 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1797 /* 1798 * SCSI command 1799 */ 1800 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1801 return; 1802 } else if ((message_in_code == MSG_EXTENDED) || 1803 ((message_in_code >= MSG_SIMPLE_QTAG) && 1804 (message_in_code <= MSG_ORDER_QTAG))) { 1805 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1806 pSRB->MsgInBuf[0] = message_in_code; 1807 /* extended message (01h) */ 1808 pSRB->MsgCnt = 1; 1809 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1810 /* extended message length (n) */ 1811 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1812 /* it's important for atn stop */ 1813 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1814 /* 1815 * SCSI command 1816 */ 1817 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1818 return; 1819 } else if (message_in_code == MSG_REJECT_) { 1820 /* Reject message */ 1821 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1822 /* do wide nego reject */ 1823 pDCB = pSRB->pSRBDCB; 1824 pDCB->SyncMode |= WIDE_NEGO_DONE; 1825 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1826 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1827 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1828 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1829 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1830 /* Set ATN, in case ATN was clear */ 1831 pSRB->SRBState |= SRB_MSGOUT; 1832 trm_reg_write16( 1833 DO_SETATN, 1834 TRMREG_SCSI_CONTROL); 1835 } else { 1836 /* Clear ATN */ 1837 trm_reg_write16( 1838 DO_CLRATN, 1839 TRMREG_SCSI_CONTROL); 1840 } 1841 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1842 /* do sync nego reject */ 1843 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1844 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1845 pDCB = pSRB->pSRBDCB; 1846 pDCB->SyncMode &= 1847 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1848 pDCB->SyncPeriod = 0; 1849 pDCB->SyncOffset = 0; 1850 /* 1851 * 1852 * program SCSI control register 1853 * 1854 */ 1855 trm_reg_write8(pDCB->SyncPeriod, 1856 TRMREG_SCSI_SYNC); 1857 trm_reg_write8(pDCB->SyncOffset, 1858 TRMREG_SCSI_OFFSET); 1859 trm_SetXferRate(pACB,pSRB,pDCB); 1860 } 1861 } 1862 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1863 /* it's important for atn stop */ 1864 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1865 /* 1866 * SCSI command 1867 */ 1868 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1869 return; 1870 } else if (message_in_code == MSG_IGNOREWIDE) { 1871 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1872 trm_reg_read8(TRMREG_SCSI_FIFO); 1873 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1874 /* it's important for atn stop */ 1875 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1876 /* 1877 * SCSI command 1878 */ 1879 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1880 return; 1881 } else { 1882 /* Restore data pointer message */ 1883 /* Save data pointer message */ 1884 /* Completion message */ 1885 /* NOP message */ 1886 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1887 /* it's important for atn stop */ 1888 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1889 /* 1890 * SCSI command 1891 */ 1892 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1893 return; 1894 } 1895 } else { 1896 /* 1897 * Parsing incomming extented messages 1898 */ 1899 *pSRB->pMsgPtr = message_in_code; 1900 pSRB->MsgCnt++; 1901 pSRB->pMsgPtr++; 1902 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1903 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1904 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1905 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1906 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1907 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1908 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1909 /* 1910 * is QUEUE tag message : 1911 * 1912 * byte 0: 1913 * HEAD QUEUE TAG (20h) 1914 * ORDERED QUEUE TAG (21h) 1915 * SIMPLE QUEUE TAG (22h) 1916 * byte 1: 1917 * Queue tag (00h - FFh) 1918 */ 1919 if (pSRB->MsgCnt == 2) { 1920 pSRB->SRBState = 0; 1921 message_in_tag_id = pSRB->MsgInBuf[1]; 1922 pSRB = pDCB->pGoingSRB; 1923 pSRBTemp = pDCB->pGoingLastSRB; 1924 if (pSRB) { 1925 for (;;) { 1926 if (pSRB->TagNumber != 1927 message_in_tag_id) { 1928 if (pSRB == pSRBTemp) { 1929 goto mingx0; 1930 } 1931 pSRB = pSRB->pNextSRB; 1932 } else 1933 break; 1934 } 1935 if (pDCB->DCBFlag & ABORT_DEV_) { 1936 pSRB->SRBState = SRB_ABORT_SENT; 1937 trm_EnableMsgOutAbort1( 1938 pACB, pSRB); 1939 } 1940 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 1941 TRM_DPRINTF("SRB not yet disconnect........ \n "); 1942 goto mingx0; 1943 } 1944 pDCB->pActiveSRB = pSRB; 1945 pSRB->SRBState = SRB_DATA_XFER; 1946 } else { 1947 mingx0: 1948 pSRB = &pACB->TmpSRB; 1949 pSRB->SRBState = SRB_UNEXPECT_RESEL; 1950 pDCB->pActiveSRB = pSRB; 1951 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 1952 trm_EnableMsgOutAbort2( 1953 pACB, 1954 pSRB); 1955 } 1956 } 1957 *pscsi_status = PH_BUS_FREE; 1958 /* .. initial phase */ 1959 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1960 /* it's important for atn stop */ 1961 /* 1962 * SCSI command 1963 */ 1964 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1965 return; 1966 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 1967 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 1968 /* 1969 * is Wide data xfer Extended message : 1970 * ====================================== 1971 * WIDE DATA TRANSFER REQUEST 1972 * ====================================== 1973 * byte 0 : Extended message (01h) 1974 * byte 1 : Extended message length (02h) 1975 * byte 2 : WIDE DATA TRANSFER code (03h) 1976 * byte 3 : Transfer width exponent 1977 */ 1978 pDCB = pSRB->pSRBDCB; 1979 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 1980 if ((pSRB->MsgInBuf[1] != 2)) { 1981 /* Length is wrong, reject it */ 1982 pDCB->SyncMode &= 1983 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1984 pSRB->MsgCnt = 1; 1985 pSRB->MsgInBuf[0] = MSG_REJECT_; 1986 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 1987 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1988 /* it's important for atn stop */ 1989 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1990 /* 1991 * SCSI command 1992 */ 1993 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1994 return; 1995 } 1996 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1997 /* Do wide negoniation */ 1998 if (pSRB->MsgInBuf[3] > 2) { 1999 /* > 32 bit */ 2000 /* reject_msg: */ 2001 pDCB->SyncMode &= 2002 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 2003 pSRB->MsgCnt = 1; 2004 pSRB->MsgInBuf[0] = MSG_REJECT_; 2005 trm_reg_write16(DO_SETATN, 2006 TRMREG_SCSI_CONTROL); 2007 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2008 /* it's important for atn stop */ 2009 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2010 /* 2011 * SCSI command 2012 */ 2013 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2014 return; 2015 } 2016 if (pSRB->MsgInBuf[3] == 2) { 2017 pSRB->MsgInBuf[3] = 1; 2018 /* do 16 bits */ 2019 } else { 2020 if (!(pDCB->SyncMode 2021 & WIDE_NEGO_DONE)) { 2022 pSRB->SRBState &= 2023 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2024 pDCB->SyncMode |= 2025 WIDE_NEGO_DONE; 2026 pDCB->SyncMode &= 2027 ~(SYNC_NEGO_DONE | 2028 EN_ATN_STOP | 2029 WIDE_NEGO_ENABLE); 2030 if (pSRB->MsgInBuf[3] != 0) { 2031 /* is Wide data xfer */ 2032 pDCB->SyncPeriod |= 2033 WIDE_SYNC; 2034 pDCB->tinfo.current.width 2035 = MSG_EXT_WDTR_BUS_16_BIT; 2036 pDCB->tinfo.goal.width 2037 = MSG_EXT_WDTR_BUS_16_BIT; 2038 } 2039 } 2040 } 2041 } else 2042 pSRB->MsgInBuf[3] = 0; 2043 pSRB->SRBState |= SRB_MSGOUT; 2044 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2045 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2046 /* it's important for atn stop */ 2047 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2048 /* 2049 * SCSI command 2050 */ 2051 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2052 return; 2053 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2054 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2055 /* 2056 * is 8bit transfer Extended message : 2057 * ================================= 2058 * SYNCHRONOUS DATA TRANSFER REQUEST 2059 * ================================= 2060 * byte 0 : Extended message (01h) 2061 * byte 1 : Extended message length (03) 2062 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2063 * byte 3 : Transfer period factor 2064 * byte 4 : REQ/ACK offset 2065 */ 2066 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2067 if ((pSRB->MsgInBuf[1] != 3) || 2068 (pSRB->MsgInBuf[2] != 1)) { 2069 /* reject_msg: */ 2070 pSRB->MsgCnt = 1; 2071 pSRB->MsgInBuf[0] = MSG_REJECT_; 2072 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2073 *pscsi_status = PH_BUS_FREE; 2074 /* .. initial phase */ 2075 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2076 /* it's important for atn stop */ 2077 /* 2078 * SCSI cammand 2079 */ 2080 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2081 return; 2082 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2083 /* set async */ 2084 pDCB = pSRB->pSRBDCB; 2085 /* disable sync & sync nego */ 2086 pDCB->SyncMode &= 2087 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2088 pDCB->SyncPeriod = 0; 2089 pDCB->SyncOffset = 0; 2090 pDCB->tinfo.goal.period = 0; 2091 pDCB->tinfo.goal.offset = 0; 2092 pDCB->tinfo.current.period = 0; 2093 pDCB->tinfo.current.offset = 0; 2094 pDCB->tinfo.current.width = 2095 MSG_EXT_WDTR_BUS_8_BIT; 2096 /* 2097 * 2098 * program SCSI control register 2099 * 2100 */ 2101 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2102 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2103 trm_SetXferRate(pACB,pSRB,pDCB); 2104 *pscsi_status = PH_BUS_FREE; 2105 /* .. initial phase */ 2106 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2107 /* it's important for atn stop */ 2108 /* 2109 * SCSI cammand 2110 */ 2111 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2112 return; 2113 } else { 2114 /* set sync */ 2115 pDCB = pSRB->pSRBDCB; 2116 pDCB->SyncMode |= 2117 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2118 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2119 /* Transfer period factor */ 2120 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2121 /* REQ/ACK offset */ 2122 if (pACB->AdaptType == 1) { 2123 for(bIndex = 0; bIndex < 7; bIndex++) { 2124 if (pSRB->MsgInBuf[3] <= 2125 dc395u2x_clock_period[bIndex]) { 2126 pDCB->tinfo.goal.period = 2127 dc395u2x_tinfo_period[bIndex]; 2128 pDCB->tinfo.current.period = 2129 dc395u2x_tinfo_period[bIndex]; 2130 pDCB->tinfo.goal.offset = 2131 pDCB->SyncOffset; 2132 pDCB->tinfo.current.offset = 2133 pDCB->SyncOffset; 2134 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2135 break; 2136 } 2137 } 2138 } else { 2139 for(bIndex = 0; bIndex < 7; bIndex++) { 2140 if (pSRB->MsgInBuf[3] <= 2141 dc395x_clock_period[bIndex]) { 2142 pDCB->tinfo.goal.period = 2143 dc395x_tinfo_period[bIndex]; 2144 pDCB->tinfo.current.period = 2145 dc395x_tinfo_period[bIndex]; 2146 pDCB->tinfo.goal.offset = 2147 pDCB->SyncOffset; 2148 pDCB->tinfo.current.offset = 2149 pDCB->SyncOffset; 2150 pDCB->SyncPeriod |= 2151 (bIndex|ALT_SYNC); 2152 break; 2153 } 2154 } 2155 } 2156 /* 2157 * 2158 * program SCSI control register 2159 * 2160 */ 2161 trm_reg_write8(pDCB->SyncPeriod, 2162 TRMREG_SCSI_SYNC); 2163 trm_reg_write8(pDCB->SyncOffset, 2164 TRMREG_SCSI_OFFSET); 2165 trm_SetXferRate(pACB,pSRB,pDCB); 2166 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2167 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2168 /* 2169 ** SCSI command 2170 */ 2171 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2172 return; 2173 } 2174 } 2175 *pscsi_status = PH_BUS_FREE; 2176 /* .. initial phase */ 2177 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2178 /* it's important for atn stop */ 2179 /* 2180 * SCSI cammand 2181 */ 2182 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2183 } 2184 } 2185 2186 static void 2187 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2188 { 2189 2190 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2191 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2192 if (!(pSRB->SRBState & SRB_MSGIN)) { 2193 pSRB->SRBState &= SRB_DISCONNECT; 2194 pSRB->SRBState |= SRB_MSGIN; 2195 } 2196 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2197 /* it's important for atn stop*/ 2198 /* 2199 * SCSI cammand 2200 */ 2201 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2202 } 2203 2204 static void 2205 trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2206 { 2207 2208 } 2209 2210 static void 2211 trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2212 { 2213 2214 } 2215 2216 static void 2217 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2218 { 2219 union ccb *pccb; 2220 struct ccb_trans_settings neg; 2221 u_int16_t cnt, i; 2222 u_int8_t bval; 2223 PDCB pDCBTemp; 2224 2225 /* 2226 * set all lun device's period , offset 2227 */ 2228 TRM_DPRINTF("trm_SetXferRate\n"); 2229 pccb = pSRB->pccb; 2230 memset(&neg, 0, sizeof (neg)); 2231 neg.xport_specific.spi.sync_period = pDCB->tinfo.goal.period; 2232 neg.xport_specific.spi.sync_offset = pDCB->tinfo.goal.offset; 2233 neg.xport_specific.spi.valid = 2234 CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET; 2235 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2236 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2237 if (!(pDCB->IdentifyMsg & 0x07)) { 2238 pDCBTemp = pACB->pLinkDCB; 2239 cnt = pACB->DeviceCnt; 2240 bval = pDCB->TargetID; 2241 for (i = 0; i < cnt; i++) { 2242 if (pDCBTemp->TargetID == bval) { 2243 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2244 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2245 pDCBTemp->SyncMode = pDCB->SyncMode; 2246 } 2247 pDCBTemp = pDCBTemp->pNextDCB; 2248 } 2249 } 2250 return; 2251 } 2252 2253 /* 2254 * scsiiom 2255 * trm_Interrupt 2256 * 2257 * 2258 * ---SCSI bus phase 2259 * 2260 * PH_DATA_OUT 0x00 Data out phase 2261 * PH_DATA_IN 0x01 Data in phase 2262 * PH_COMMAND 0x02 Command phase 2263 * PH_STATUS 0x03 Status phase 2264 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2265 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2266 * PH_MSG_OUT 0x06 Message out phase 2267 * PH_MSG_IN 0x07 Message in phase 2268 * 2269 */ 2270 static void 2271 trm_Disconnect(PACB pACB) 2272 { 2273 PDCB pDCB; 2274 PSRB pSRB, psrb; 2275 u_int16_t i,j, cnt; 2276 u_int target_id,target_lun; 2277 2278 TRM_DPRINTF("trm_Disconnect...............\n "); 2279 2280 pDCB = pACB->pActiveDCB; 2281 if (!pDCB) { 2282 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2283 j = 400; 2284 while (--j) 2285 DELAY(1); 2286 /* 1 msec */ 2287 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2288 TRMREG_SCSI_CONTROL); 2289 return; 2290 } 2291 pSRB = pDCB->pActiveSRB; 2292 /* bug pSRB=0 */ 2293 target_id = pSRB->pccb->ccb_h.target_id; 2294 target_lun = pSRB->pccb->ccb_h.target_lun; 2295 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2296 pACB->pActiveDCB = 0; 2297 pSRB->ScsiPhase = PH_BUS_FREE; 2298 /* SCSI bus free Phase */ 2299 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2300 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2301 pSRB->SRBState = 0; 2302 trm_DoWaitingSRB(pACB); 2303 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2304 pDCB->DCBFlag = 0; 2305 cnt = pDCB->GoingSRBCnt; 2306 pDCB->GoingSRBCnt = 0; 2307 pSRB = pDCB->pGoingSRB; 2308 for (i = 0; i < cnt; i++) { 2309 psrb = pSRB->pNextSRB; 2310 pSRB->pNextSRB = pACB->pFreeSRB; 2311 pACB->pFreeSRB = pSRB; 2312 pSRB = psrb; 2313 } 2314 pDCB->pGoingSRB = 0; 2315 trm_DoWaitingSRB(pACB); 2316 } else { 2317 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2318 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2319 /* Selection time out */ 2320 if (!(pACB->scan_devices[target_id][target_lun]) && 2321 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2322 pSRB->CmdBlock[0] != INQUIRY) { 2323 pSRB->SRBState = SRB_READY; 2324 trm_RewaitSRB(pDCB, pSRB); 2325 } else { 2326 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2327 goto disc1; 2328 } 2329 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2330 /* 2331 * SRB_DISCONNECT 2332 */ 2333 trm_DoWaitingSRB(pACB); 2334 } else if (pSRB->SRBState & SRB_COMPLETED) { 2335 disc1: 2336 /* 2337 * SRB_COMPLETED 2338 */ 2339 pDCB->pActiveSRB = 0; 2340 pSRB->SRBState = SRB_FREE; 2341 trm_SRBdone(pACB, pDCB, pSRB); 2342 } 2343 } 2344 return; 2345 } 2346 2347 static void 2348 trm_Reselect(PACB pACB) 2349 { 2350 PDCB pDCB; 2351 PSRB pSRB; 2352 u_int16_t RselTarLunId; 2353 2354 TRM_DPRINTF("trm_Reselect................. \n"); 2355 pDCB = pACB->pActiveDCB; 2356 if (pDCB) { 2357 /* Arbitration lost but Reselection win */ 2358 pSRB = pDCB->pActiveSRB; 2359 pSRB->SRBState = SRB_READY; 2360 trm_RewaitSRB(pDCB, pSRB); 2361 } 2362 /* Read Reselected Target Id and LUN */ 2363 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2364 pDCB = pACB->pLinkDCB; 2365 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2366 /* get pDCB of the reselect id */ 2367 pDCB = pDCB->pNextDCB; 2368 } 2369 2370 pACB->pActiveDCB = pDCB; 2371 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2372 pSRB = &pACB->TmpSRB; 2373 pDCB->pActiveSRB = pSRB; 2374 } else { 2375 pSRB = pDCB->pActiveSRB; 2376 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2377 /* 2378 * abort command 2379 */ 2380 pSRB = &pACB->TmpSRB; 2381 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2382 pDCB->pActiveSRB = pSRB; 2383 trm_EnableMsgOutAbort1(pACB, pSRB); 2384 } else { 2385 if (pDCB->DCBFlag & ABORT_DEV_) { 2386 pSRB->SRBState = SRB_ABORT_SENT; 2387 trm_EnableMsgOutAbort1(pACB, pSRB); 2388 } else 2389 pSRB->SRBState = SRB_DATA_XFER; 2390 } 2391 } 2392 pSRB->ScsiPhase = PH_BUS_FREE; 2393 /* SCSI bus free Phase */ 2394 /* 2395 * Program HA ID, target ID, period and offset 2396 */ 2397 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2398 /* target ID */ 2399 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2400 /* host ID */ 2401 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2402 /* period */ 2403 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2404 /* offset */ 2405 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2406 /* it's important for atn stop*/ 2407 /* 2408 * SCSI cammand 2409 */ 2410 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2411 /* to rls the /ACK signal */ 2412 } 2413 2414 static void 2415 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2416 { 2417 PSRB psrb; 2418 u_int8_t bval, bval1,status; 2419 union ccb *pccb; 2420 struct ccb_scsiio *pcsio; 2421 PSCSI_INQDATA ptr; 2422 int intflag; 2423 u_int target_id,target_lun; 2424 PDCB pTempDCB; 2425 2426 pccb = pSRB->pccb; 2427 if (pccb == NULL) 2428 return; 2429 pcsio = &pccb->csio; 2430 target_id = pSRB->pccb->ccb_h.target_id; 2431 target_lun = pSRB->pccb->ccb_h.target_lun; 2432 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2433 bus_dmasync_op_t op; 2434 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2435 op = BUS_DMASYNC_POSTREAD; 2436 else 2437 op = BUS_DMASYNC_POSTWRITE; 2438 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2439 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2440 } 2441 /* 2442 * 2443 * target status 2444 * 2445 */ 2446 status = pSRB->TargetStatus; 2447 pcsio->scsi_status=SCSI_STAT_GOOD; 2448 pccb->ccb_h.status = CAM_REQ_CMP; 2449 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2450 /* 2451 * status of auto request sense 2452 */ 2453 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2454 pSRB->AdaptStatus = 0; 2455 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2456 2457 if (status == SCSI_STATUS_CHECK_COND) { 2458 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2459 goto ckc_e; 2460 } 2461 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2462 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2463 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2464 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2465 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2466 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2467 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2468 pcsio->sense_len); 2469 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2470 | CAM_AUTOSNS_VALID; 2471 goto ckc_e; 2472 } 2473 /* 2474 * target status 2475 */ 2476 if (status) { 2477 if (status == SCSI_STATUS_CHECK_COND) { 2478 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2479 TRM_DPRINTF("trm_RequestSense..................\n"); 2480 trm_RequestSense(pACB, pDCB, pSRB); 2481 return; 2482 } 2483 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2484 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2485 goto ckc_e; 2486 } else if (status == SCSI_STAT_QUEUEFULL) { 2487 bval = (u_int8_t) pDCB->GoingSRBCnt; 2488 bval--; 2489 pDCB->MaxActiveCommandCnt = bval; 2490 trm_RewaitSRB(pDCB, pSRB); 2491 pSRB->AdaptStatus = 0; 2492 pSRB->TargetStatus = 0; 2493 return; 2494 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2495 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2496 pSRB->TargetStatus = 0; 2497 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2498 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2499 } else if (status == SCSI_STAT_BUSY) { 2500 TRM_DPRINTF("trm: target busy at %s %d\n", 2501 __FILE__, __LINE__); 2502 pcsio->scsi_status = SCSI_STAT_BUSY; 2503 pccb->ccb_h.status = CAM_SCSI_BUSY; 2504 return; 2505 /* The device busy, try again later? */ 2506 } else if (status == SCSI_STAT_RESCONFLICT) { 2507 TRM_DPRINTF("trm: target reserved at %s %d\n", 2508 __FILE__, __LINE__); 2509 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2510 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2511 return; 2512 } else { 2513 pSRB->AdaptStatus = 0; 2514 if (pSRB->RetryCnt) { 2515 pSRB->RetryCnt--; 2516 pSRB->TargetStatus = 0; 2517 pSRB->SRBSGIndex = 0; 2518 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2519 /* 2520 * If trm_StartSCSI return 1 : 2521 * current interrupt status is interrupt 2522 * disreenable 2523 * It's said that SCSI processor has more 2524 * one SRB need to do 2525 */ 2526 trm_RewaitSRB(pDCB, pSRB); 2527 } 2528 return; 2529 } else { 2530 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2531 __FILE__, __LINE__); 2532 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2533 } 2534 } 2535 } else { 2536 /* 2537 * process initiator status.......................... 2538 * Adapter (initiator) status 2539 */ 2540 status = pSRB->AdaptStatus; 2541 if (status & H_OVER_UNDER_RUN) { 2542 pSRB->TargetStatus = 0; 2543 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2544 /* Illegal length (over/under run) */ 2545 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2546 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2547 __FILE__, __LINE__); 2548 pDCB->tinfo.goal.period = 0; 2549 pDCB->tinfo.goal.offset = 0; 2550 /* Driver failed to perform operation */ 2551 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2552 } else { 2553 /* no error */ 2554 pSRB->AdaptStatus = 0; 2555 pSRB->TargetStatus = 0; 2556 pccb->ccb_h.status = CAM_REQ_CMP; 2557 /* there is no error, (sense is invalid) */ 2558 } 2559 } 2560 ckc_e: 2561 if (pACB->scan_devices[target_id][target_lun]) { 2562 /* 2563 * if SCSI command in "scan devices" duty 2564 */ 2565 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2566 pACB->scan_devices[target_id][target_lun] = 0; 2567 /* SCSI command phase :test unit ready */ 2568 else if (pSRB->CmdBlock[0] == INQUIRY) { 2569 /* 2570 * SCSI command phase :inquiry scsi device data 2571 * (type,capacity,manufacture.... 2572 */ 2573 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2574 goto NO_DEV; 2575 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2576 /* page fault */ 2577 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2578 ptr->DevType); 2579 bval1 = ptr->DevType & SCSI_DEVTYPE; 2580 if (bval1 == SCSI_NODEV) { 2581 NO_DEV: 2582 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2583 target_id, 2584 target_lun); 2585 intflag = splcam(); 2586 pACB->scan_devices[target_id][target_lun] = 0; 2587 /* no device set scan device flag =0*/ 2588 /* pDCB Q link */ 2589 /* move the head of DCB to tempDCB*/ 2590 pTempDCB=pACB->pLinkDCB; 2591 /* search current DCB for pass link */ 2592 while (pTempDCB->pNextDCB != pDCB) { 2593 pTempDCB = pTempDCB->pNextDCB; 2594 } 2595 /* 2596 * when the current DCB found than connect 2597 * current DCB tail 2598 */ 2599 /* to the DCB tail that before current DCB */ 2600 pTempDCB->pNextDCB = pDCB->pNextDCB; 2601 /* 2602 * if there was only one DCB ,connect his tail 2603 * to his head 2604 */ 2605 if (pACB->pLinkDCB == pDCB) 2606 pACB->pLinkDCB = pTempDCB->pNextDCB; 2607 if (pACB->pDCBRunRobin == pDCB) 2608 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2609 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2610 pACB->DeviceCnt--; 2611 if (pACB->DeviceCnt == 0) { 2612 pACB->pLinkDCB = NULL; 2613 pACB->pDCBRunRobin = NULL; 2614 } 2615 splx(intflag); 2616 } else { 2617 #ifdef trm_DEBUG1 2618 int j; 2619 for (j = 0; j < 28; j++) { 2620 TRM_DPRINTF("ptr=%2x ", 2621 ((u_int8_t *)ptr)[j]); 2622 } 2623 #endif 2624 pDCB->DevType = bval1; 2625 if (bval1 == SCSI_DASD || 2626 bval1 == SCSI_OPTICAL) { 2627 if ((((ptr->Vers & 0x07) >= 2) || 2628 ((ptr->RDF & 0x0F) == 2)) && 2629 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2630 (pDCB->DevMode & TAG_QUEUING_) && 2631 (pDCB->DevMode & EN_DISCONNECT_)) { 2632 if (pDCB->DevMode & 2633 TAG_QUEUING_) { 2634 pDCB-> 2635 MaxActiveCommandCnt = 2636 pACB->TagMaxNum; 2637 pDCB->SyncMode |= 2638 EN_TAG_QUEUING; 2639 pDCB->tinfo.disc_tag |= 2640 TRM_CUR_TAGENB; 2641 } else { 2642 pDCB->SyncMode |= 2643 EN_ATN_STOP; 2644 pDCB->tinfo.disc_tag &= 2645 ~TRM_CUR_TAGENB; 2646 } 2647 } 2648 } 2649 } 2650 /* pSRB->CmdBlock[0] == INQUIRY */ 2651 } 2652 /* pACB->scan_devices[target_id][target_lun] */ 2653 } 2654 intflag = splcam(); 2655 /* ReleaseSRB(pDCB, pSRB); */ 2656 if (pSRB == pDCB->pGoingSRB) 2657 pDCB->pGoingSRB = pSRB->pNextSRB; 2658 else { 2659 psrb = pDCB->pGoingSRB; 2660 while (psrb->pNextSRB != pSRB) { 2661 psrb = psrb->pNextSRB; 2662 } 2663 psrb->pNextSRB = pSRB->pNextSRB; 2664 if (pSRB == pDCB->pGoingLastSRB) { 2665 pDCB->pGoingLastSRB = psrb; 2666 } 2667 } 2668 pSRB->pNextSRB = pACB->pFreeSRB; 2669 pACB->pFreeSRB = pSRB; 2670 pDCB->GoingSRBCnt--; 2671 trm_DoWaitingSRB(pACB); 2672 2673 splx(intflag); 2674 /* Notify cmd done */ 2675 xpt_done (pccb); 2676 } 2677 2678 static void 2679 trm_DoingSRB_Done(PACB pACB) 2680 { 2681 PDCB pDCB, pdcb; 2682 PSRB psrb, psrb2; 2683 u_int16_t cnt, i; 2684 union ccb *pccb; 2685 2686 pDCB = pACB->pLinkDCB; 2687 if (pDCB == NULL) 2688 return; 2689 pdcb = pDCB; 2690 do { 2691 cnt = pdcb->GoingSRBCnt; 2692 psrb = pdcb->pGoingSRB; 2693 for (i = 0; i < cnt; i++) { 2694 psrb2 = psrb->pNextSRB; 2695 pccb = psrb->pccb; 2696 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2697 /* ReleaseSRB(pDCB, pSRB); */ 2698 psrb->pNextSRB = pACB->pFreeSRB; 2699 pACB->pFreeSRB = psrb; 2700 xpt_done(pccb); 2701 psrb = psrb2; 2702 } 2703 pdcb->GoingSRBCnt = 0; 2704 pdcb->pGoingSRB = NULL; 2705 pdcb = pdcb->pNextDCB; 2706 } 2707 while (pdcb != pDCB); 2708 } 2709 2710 static void 2711 trm_ResetSCSIBus(PACB pACB) 2712 { 2713 int intflag; 2714 2715 intflag = splcam(); 2716 pACB->ACBFlag |= RESET_DEV; 2717 2718 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2719 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2720 splx(intflag); 2721 return; 2722 } 2723 2724 static void 2725 trm_ScsiRstDetect(PACB pACB) 2726 { 2727 int intflag; 2728 u_long wlval; 2729 2730 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2731 wlval = 1000; 2732 while (--wlval) 2733 DELAY(1000); 2734 intflag = splcam(); 2735 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2736 2737 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2738 2739 if (pACB->ACBFlag & RESET_DEV) 2740 pACB->ACBFlag |= RESET_DONE; 2741 else { 2742 pACB->ACBFlag |= RESET_DETECT; 2743 trm_ResetDevParam(pACB); 2744 /* trm_DoingSRB_Done(pACB); ???? */ 2745 trm_RecoverSRB(pACB); 2746 pACB->pActiveDCB = NULL; 2747 pACB->ACBFlag = 0; 2748 trm_DoWaitingSRB(pACB); 2749 } 2750 splx(intflag); 2751 return; 2752 } 2753 2754 static void 2755 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2756 { 2757 union ccb *pccb; 2758 struct ccb_scsiio *pcsio; 2759 2760 pccb = pSRB->pccb; 2761 pcsio = &pccb->csio; 2762 2763 pSRB->SRBFlag |= AUTO_REQSENSE; 2764 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2765 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2766 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2767 pSRB->SRBSGCount); 2768 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2769 2770 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2771 pSRB->AdaptStatus = 0; 2772 pSRB->TargetStatus = 0; 2773 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2774 2775 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2776 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2777 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2778 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2779 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2780 pSRB->SRBSGCount = 1; 2781 pSRB->SRBSGIndex = 0; 2782 2783 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2784 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2785 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2786 pSRB->ScsiCmdLen = 6; 2787 2788 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2789 /* 2790 * If trm_StartSCSI return 1 : 2791 * current interrupt status is interrupt disreenable 2792 * It's said that SCSI processor has more one SRB need to do 2793 */ 2794 trm_RewaitSRB(pDCB, pSRB); 2795 } 2796 2797 static void 2798 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2799 { 2800 2801 pSRB->MsgCnt = 1; 2802 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2803 } 2804 2805 static void 2806 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2807 { 2808 2809 pSRB->MsgOutBuf[0] = MSG_ABORT; 2810 trm_EnableMsgOutAbort2(pACB, pSRB); 2811 } 2812 2813 static void 2814 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2815 { 2816 PNVRAMTYPE pEEpromBuf; 2817 u_int8_t bval,PeriodIndex; 2818 u_int target_id,target_lun; 2819 PDCB pTempDCB; 2820 int intflag; 2821 2822 target_id = i; 2823 target_lun = j; 2824 2825 /* 2826 * Using the lun 0 device to init other DCB first, if the device 2827 * has been initialized. 2828 * I don't want init sync arguments one by one, it is the same. 2829 */ 2830 if (target_lun != 0 && 2831 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2832 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2833 sizeof(TRM_DCB)); 2834 intflag = splcam(); 2835 if (pACB->pLinkDCB == 0) { 2836 pACB->pLinkDCB = pDCB; 2837 /* 2838 * RunRobin impersonate the role 2839 * that let each device had good proportion 2840 * about SCSI command proceeding 2841 */ 2842 pACB->pDCBRunRobin = pDCB; 2843 pDCB->pNextDCB = pDCB; 2844 } else { 2845 pTempDCB=pACB->pLinkDCB; 2846 /* search the last nod of DCB link */ 2847 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2848 pTempDCB = pTempDCB->pNextDCB; 2849 /* connect current DCB with last DCB tail */ 2850 pTempDCB->pNextDCB = pDCB; 2851 /* connect current DCB tail to this DCB Q head */ 2852 pDCB->pNextDCB=pACB->pLinkDCB; 2853 } 2854 splx(intflag); 2855 2856 pACB->DeviceCnt++; 2857 pDCB->TargetID = target_id; 2858 pDCB->TargetLUN = target_lun; 2859 pDCB->pWaitingSRB = NULL; 2860 pDCB->pGoingSRB = NULL; 2861 pDCB->GoingSRBCnt = 0; 2862 pDCB->pActiveSRB = NULL; 2863 pDCB->MaxActiveCommandCnt = 1; 2864 pDCB->DCBFlag = 0; 2865 pDCB->DCBstatus |= DS_IN_QUEUE; 2866 /* $$$$$$$ */ 2867 pEEpromBuf = &trm_eepromBuf[unit]; 2868 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2869 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2870 /* $$$$$$$ */ 2871 /* 2872 * disconnect enable ? 2873 */ 2874 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2875 bval = 0xC0; 2876 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2877 } else { 2878 bval = 0x80; 2879 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2880 } 2881 bval |= target_lun; 2882 pDCB->IdentifyMsg = bval; 2883 if (target_lun != 0 && 2884 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2885 return; 2886 /* $$$$$$$ */ 2887 /* 2888 * tag Qing enable ? 2889 */ 2890 if (pDCB->DevMode & TAG_QUEUING_) { 2891 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2892 } else 2893 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2894 /* $$$$$$$ */ 2895 /* 2896 * wide nego ,sync nego enable ? 2897 */ 2898 pDCB->SyncPeriod = 0; 2899 pDCB->SyncOffset = 0; 2900 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2901 if (pACB->AdaptType==1) {/* is U2? */ 2902 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2903 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2904 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2905 } else { 2906 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2907 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2908 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2909 } 2910 pDCB->SyncMode = 0; 2911 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2912 (pACB->Config & HCC_WIDE_CARD)) 2913 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2914 /* enable wide nego */ 2915 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2916 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2917 /* enable sync nego */ 2918 /* $$$$$$$ */ 2919 /* 2920 * Fill in tinfo structure. 2921 */ 2922 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2923 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2924 2925 pDCB->tinfo.current.period = 0; 2926 pDCB->tinfo.current.offset = 0; 2927 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2928 } 2929 2930 static void 2931 trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2932 { 2933 PSRB pSRB; 2934 2935 pSRB=(PSRB) arg; 2936 pSRB->SRBSGPhyAddr=segs->ds_addr; 2937 return; 2938 } 2939 2940 static void 2941 trm_destroySRB(PACB pACB) 2942 { 2943 PSRB pSRB; 2944 2945 pSRB = pACB->pFreeSRB; 2946 while (pSRB) { 2947 if (pSRB->SRBSGPhyAddr) 2948 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap); 2949 if (pSRB->pSRBSGL) 2950 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL, 2951 pSRB->sg_dmamap); 2952 if (pSRB->dmamap) 2953 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap); 2954 pSRB = pSRB->pNextSRB; 2955 } 2956 } 2957 2958 static int 2959 trm_initSRB(PACB pACB) 2960 { 2961 u_int16_t i; 2962 PSRB pSRB; 2963 int error; 2964 2965 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2966 pSRB = (PSRB)&pACB->pFreeSRB[i]; 2967 2968 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL, 2969 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 2970 return ENXIO; 2971 } 2972 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 2973 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 2974 trm_srbmapSG, pSRB, /*flags*/0); 2975 if (i != TRM_MAX_SRB_CNT - 1) { 2976 /* 2977 * link all SRB 2978 */ 2979 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 2980 } else { 2981 /* 2982 * load NULL to NextSRB of the last SRB 2983 */ 2984 pSRB->pNextSRB = NULL; 2985 } 2986 pSRB->TagNumber = i; 2987 2988 /* 2989 * Create the dmamap. This is no longer optional! 2990 */ 2991 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0, 2992 &pSRB->dmamap)) != 0) 2993 return (error); 2994 2995 } 2996 return (0); 2997 } 2998 2999 3000 3001 3002 static void 3003 trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3004 { 3005 PNVRAMTYPE pEEpromBuf; 3006 3007 pEEpromBuf = &trm_eepromBuf[unit]; 3008 pACB->max_id = 15; 3009 3010 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3011 pACB->max_lun = 7; 3012 else 3013 pACB->max_lun = 0; 3014 3015 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3016 pACB->max_id, pACB->max_lun); 3017 pACB->pLinkDCB = NULL; 3018 pACB->pDCBRunRobin = NULL; 3019 pACB->pActiveDCB = NULL; 3020 pACB->AdapterUnit = (u_int8_t)unit; 3021 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3022 pACB->AdaptSCSILUN = 0; 3023 pACB->DeviceCnt = 0; 3024 pACB->AdaptType = adaptType; 3025 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3026 pACB->ACBFlag = 0; 3027 return; 3028 } 3029 3030 static void 3031 NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3032 { 3033 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3034 u_int8_t bAddr; 3035 3036 /* Enable SEEPROM */ 3037 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3038 TRMREG_GEN_CONTROL); 3039 /* 3040 * Write enable 3041 */ 3042 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3043 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3044 NVRAM_trm_wait_30us(pACB); 3045 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3046 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3047 } 3048 /* 3049 * Write disable 3050 */ 3051 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3052 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3053 NVRAM_trm_wait_30us(pACB); 3054 /* Disable SEEPROM */ 3055 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3056 TRMREG_GEN_CONTROL); 3057 return; 3058 } 3059 3060 static void 3061 NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3062 { 3063 int i; 3064 u_int8_t bSendData; 3065 /* 3066 * Send write command & address 3067 */ 3068 3069 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3070 /* 3071 * Write data 3072 */ 3073 for (i = 0; i < 8; i++, bData <<= 1) { 3074 bSendData = NVR_SELECT; 3075 if (bData & 0x80) 3076 /* Start from bit 7 */ 3077 bSendData |= NVR_BITOUT; 3078 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3079 NVRAM_trm_wait_30us(pACB); 3080 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3081 NVRAM_trm_wait_30us(pACB); 3082 } 3083 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3084 NVRAM_trm_wait_30us(pACB); 3085 /* 3086 * Disable chip select 3087 */ 3088 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3089 NVRAM_trm_wait_30us(pACB); 3090 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3091 NVRAM_trm_wait_30us(pACB); 3092 /* 3093 * Wait for write ready 3094 */ 3095 while (1) { 3096 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3097 NVRAM_trm_wait_30us(pACB); 3098 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3099 NVRAM_trm_wait_30us(pACB); 3100 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3101 break; 3102 } 3103 } 3104 /* 3105 * Disable chip select 3106 */ 3107 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3108 return; 3109 } 3110 3111 static void 3112 NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3113 { 3114 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3115 u_int8_t bAddr; 3116 3117 /* 3118 * Enable SEEPROM 3119 */ 3120 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3121 TRMREG_GEN_CONTROL); 3122 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3123 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3124 /* 3125 * Disable SEEPROM 3126 */ 3127 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3128 TRMREG_GEN_CONTROL); 3129 return; 3130 } 3131 3132 static u_int8_t 3133 NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3134 { 3135 int i; 3136 u_int8_t bReadData, bData = 0; 3137 /* 3138 * Send read command & address 3139 */ 3140 3141 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3142 3143 for (i = 0; i < 8; i++) { 3144 /* 3145 * Read data 3146 */ 3147 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3148 NVRAM_trm_wait_30us(pACB); 3149 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3150 /* 3151 * Get data bit while falling edge 3152 */ 3153 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3154 bData <<= 1; 3155 if (bReadData & NVR_BITIN) { 3156 bData |= 1; 3157 } 3158 NVRAM_trm_wait_30us(pACB); 3159 } 3160 /* 3161 * Disable chip select 3162 */ 3163 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3164 return (bData); 3165 } 3166 3167 static void 3168 NVRAM_trm_wait_30us(PACB pACB) 3169 { 3170 3171 /* ScsiPortStallExecution(30); wait 30 us */ 3172 trm_reg_write8(5, TRMREG_GEN_TIMER); 3173 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3174 return; 3175 } 3176 3177 static void 3178 NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3179 { 3180 int i; 3181 u_int8_t bSendData; 3182 3183 for (i = 0; i < 3; i++, bCmd <<= 1) { 3184 /* 3185 * Program SB+OP code 3186 */ 3187 bSendData = NVR_SELECT; 3188 if (bCmd & 0x04) 3189 bSendData |= NVR_BITOUT; 3190 /* start from bit 2 */ 3191 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3192 NVRAM_trm_wait_30us(pACB); 3193 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3194 NVRAM_trm_wait_30us(pACB); 3195 } 3196 for (i = 0; i < 7; i++, bAddr <<= 1) { 3197 /* 3198 * Program address 3199 */ 3200 bSendData = NVR_SELECT; 3201 if (bAddr & 0x40) 3202 /* Start from bit 6 */ 3203 bSendData |= NVR_BITOUT; 3204 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3205 NVRAM_trm_wait_30us(pACB); 3206 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3207 NVRAM_trm_wait_30us(pACB); 3208 } 3209 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3210 NVRAM_trm_wait_30us(pACB); 3211 } 3212 3213 static void 3214 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3215 { 3216 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3217 u_int16_t wAddr, wCheckSum; 3218 u_long dAddr, *dpEeprom; 3219 3220 NVRAM_trm_read_all(pEEpromBuf,pACB); 3221 wCheckSum = 0; 3222 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3223 wAddr < 64; wAddr++, wpEeprom++) { 3224 wCheckSum += *wpEeprom; 3225 } 3226 if (wCheckSum != 0x1234) { 3227 /* 3228 * Checksum error, load default 3229 */ 3230 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3231 pEEpromBuf->NvramSubVendorID[1] = 3232 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3233 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3234 pEEpromBuf->NvramSubSysID[1] = 3235 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3236 pEEpromBuf->NvramSubClass = 0x00; 3237 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3238 pEEpromBuf->NvramVendorID[1] = 3239 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3240 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3241 pEEpromBuf->NvramDeviceID[1] = 3242 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3243 pEEpromBuf->NvramReserved = 0x00; 3244 3245 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3246 dAddr < 16; dAddr++, dpEeprom++) { 3247 *dpEeprom = 0x00000077; 3248 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3249 } 3250 3251 *dpEeprom++ = 0x04000F07; 3252 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3253 *dpEeprom++ = 0x00000015; 3254 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3255 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3256 *dpEeprom = 0x00; 3257 pEEpromBuf->NvramCheckSum = 0x00; 3258 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3259 wAddr < 63; wAddr++, wpEeprom++) 3260 wCheckSum += *wpEeprom; 3261 *wpEeprom = 0x1234 - wCheckSum; 3262 NVRAM_trm_write_all(pEEpromBuf,pACB); 3263 } 3264 return; 3265 } 3266 static int 3267 trm_initAdapter(PACB pACB, u_int16_t unit) 3268 { 3269 PNVRAMTYPE pEEpromBuf; 3270 u_int16_t wval; 3271 u_int8_t bval; 3272 3273 pEEpromBuf = &trm_eepromBuf[unit]; 3274 3275 /* 250ms selection timeout */ 3276 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3277 /* Mask all the interrupt */ 3278 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3279 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3280 /* Reset SCSI module */ 3281 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3282 /* program configuration 0 */ 3283 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3284 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3285 pACB->Config |= HCC_WIDE_CARD; 3286 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3287 pACB->Config |= HCC_SCSI_RESET; 3288 if (pACB->Config & HCC_PARITY) 3289 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3290 else 3291 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3292 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3293 /* program configuration 1 */ 3294 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3295 /* program Host ID */ 3296 bval = pEEpromBuf->NvramScsiId; 3297 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3298 /* set ansynchronous transfer */ 3299 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3300 /* Trun LED control off*/ 3301 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3302 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3303 /* DMA config */ 3304 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3305 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3306 /* Clear pending interrupt status */ 3307 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3308 /* Enable SCSI interrupt */ 3309 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3310 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3311 return (0); 3312 } 3313 3314 static void 3315 trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3316 { 3317 PACB pACB; 3318 3319 pACB = (PACB)arg; 3320 pACB->srb_physbase = segs->ds_addr; 3321 } 3322 3323 static void 3324 trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3325 { 3326 bus_addr_t *baddr; 3327 3328 baddr = (bus_addr_t *)arg; 3329 *baddr = segs->ds_addr; 3330 } 3331 3332 static PACB 3333 trm_init(u_int16_t unit, device_t dev) 3334 { 3335 PACB pACB; 3336 int rid = PCIR_BAR(0), i = 0, j = 0; 3337 u_int16_t adaptType = 0; 3338 3339 pACB = (PACB) device_get_softc(dev); 3340 if (!pACB) { 3341 printf("trm%d: cannot allocate ACB !\n", unit); 3342 return (NULL); 3343 } 3344 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 3345 &rid, RF_ACTIVE); 3346 if (pACB->iores == NULL) { 3347 printf("trm_init: bus_alloc_resource failed!\n"); 3348 return (NULL); 3349 } 3350 switch (pci_get_devid(dev)) { 3351 case PCI_DEVICEID_TRMS1040: 3352 adaptType = 0; 3353 break; 3354 case PCI_DEVICEID_TRMS2080: 3355 adaptType = 1; 3356 break; 3357 default: 3358 printf("trm_init %d: unknown adapter type!\n", unit); 3359 goto bad; 3360 } 3361 pACB->dev = dev; 3362 pACB->tag = rman_get_bustag(pACB->iores); 3363 pACB->bsh = rman_get_bushandle(pACB->iores); 3364 if (bus_dma_tag_create( 3365 /*parent_dmat*/ bus_get_dma_tag(dev), 3366 /*alignment*/ 1, 3367 /*boundary*/ 0, 3368 /*lowaddr*/ BUS_SPACE_MAXADDR, 3369 /*highaddr*/ BUS_SPACE_MAXADDR, 3370 /*filter*/ NULL, 3371 /*filterarg*/ NULL, 3372 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 3373 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 3374 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3375 /*flags*/ 0, 3376 /*lockfunc*/ NULL, 3377 /*lockarg*/ NULL, 3378 /* dmat */ &pACB->parent_dmat) != 0) 3379 goto bad; 3380 if (bus_dma_tag_create( 3381 /*parent_dmat*/ pACB->parent_dmat, 3382 /*alignment*/ 1, 3383 /*boundary*/ 0, 3384 /*lowaddr*/ BUS_SPACE_MAXADDR, 3385 /*highaddr*/ BUS_SPACE_MAXADDR, 3386 /*filter*/ NULL, 3387 /*filterarg*/ NULL, 3388 /*maxsize*/ MAXBSIZE, 3389 /*nsegments*/ TRM_NSEG, 3390 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3391 /*flags*/ BUS_DMA_ALLOCNOW, 3392 /*lockfunc*/ busdma_lock_mutex, 3393 /*lockarg*/ &Giant, 3394 /* dmat */ &pACB->buffer_dmat) != 0) 3395 goto bad; 3396 /* DMA tag for our ccb structures */ 3397 if (bus_dma_tag_create( 3398 /*parent_dmat*/pACB->parent_dmat, 3399 /*alignment*/ 1, 3400 /*boundary*/ 0, 3401 /*lowaddr*/ BUS_SPACE_MAXADDR, 3402 /*highaddr*/ BUS_SPACE_MAXADDR, 3403 /*filter*/ NULL, 3404 /*filterarg*/ NULL, 3405 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3406 /*nsegments*/ 1, 3407 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3408 /*flags*/ 0, 3409 /*lockfunc*/ busdma_lock_mutex, 3410 /*lockarg*/ &Giant, 3411 /*dmat*/ &pACB->srb_dmat) != 0) { 3412 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3413 goto bad; 3414 } 3415 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3416 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3417 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3418 goto bad; 3419 } 3420 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3421 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3422 /* flags */0); 3423 /* Create, allocate, and map DMA buffers for autosense data */ 3424 if (bus_dma_tag_create( 3425 /*parent_dmat*/pACB->parent_dmat, 3426 /*alignment*/1, 3427 /*boundary*/0, 3428 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3429 /*highaddr*/BUS_SPACE_MAXADDR, 3430 /*filter*/NULL, /*filterarg*/NULL, 3431 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3432 /*nsegments*/1, 3433 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3434 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 3435 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) { 3436 if (bootverbose) 3437 device_printf(dev, "cannot create sense buffer dmat\n"); 3438 goto bad; 3439 } 3440 3441 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3442 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3443 goto bad; 3444 3445 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3446 pACB->sense_buffers, 3447 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3448 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3449 3450 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3451 trm_initACB(pACB, adaptType, unit); 3452 for (i = 0; i < (pACB->max_id + 1); i++) { 3453 if (pACB->AdaptSCSIID == i) 3454 continue; 3455 for(j = 0; j < (pACB->max_lun + 1); j++) { 3456 pACB->scan_devices[i][j] = 1; 3457 /* we assume we need to scan all devices */ 3458 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3459 } 3460 } 3461 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3462 if (bus_dma_tag_create( 3463 /*parent_dmat*/pACB->parent_dmat, 3464 /*alignment*/ 1, 3465 /*boundary*/ 0, 3466 /*lowaddr*/ BUS_SPACE_MAXADDR, 3467 /*highaddr*/ BUS_SPACE_MAXADDR, 3468 /*filter*/ NULL, 3469 /*filterarg*/ NULL, 3470 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3471 /*nsegments*/ 1, 3472 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3473 /*flags*/ 0, 3474 /*lockfunc*/ busdma_lock_mutex, 3475 /*lockarg*/ &Giant, 3476 /*dmat*/ &pACB->sg_dmat) != 0) 3477 goto bad; 3478 3479 if (trm_initSRB(pACB)) { 3480 printf("trm_initSRB: error\n"); 3481 goto bad; 3482 } 3483 if (trm_initAdapter(pACB, unit)) { 3484 printf("trm_initAdapter: initial ERROR\n"); 3485 goto bad; 3486 } 3487 return (pACB); 3488 bad: 3489 if (pACB->iores) 3490 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3491 pACB->iores); 3492 if (pACB->sense_dmamap) { 3493 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3494 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3495 pACB->sense_dmamap); 3496 } 3497 if (pACB->sense_dmat) 3498 bus_dma_tag_destroy(pACB->sense_dmat); 3499 if (pACB->sg_dmat) { 3500 trm_destroySRB(pACB); 3501 bus_dma_tag_destroy(pACB->sg_dmat); 3502 } 3503 if (pACB->pFreeSRB) { 3504 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3505 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3506 pACB->srb_dmamap); 3507 } 3508 if (pACB->srb_dmat) 3509 bus_dma_tag_destroy(pACB->srb_dmat); 3510 if (pACB->buffer_dmat) 3511 bus_dma_tag_destroy(pACB->buffer_dmat); 3512 if (pACB->parent_dmat) 3513 bus_dma_tag_destroy(pACB->parent_dmat); 3514 return (NULL); 3515 } 3516 3517 static int 3518 trm_attach(device_t dev) 3519 { 3520 struct cam_devq *device_Q; 3521 u_long device_id; 3522 PACB pACB = 0; 3523 int rid = 0; 3524 int unit = device_get_unit(dev); 3525 3526 device_id = pci_get_devid(dev); 3527 /* 3528 * These cards do not allow memory mapped accesses 3529 */ 3530 if ((pACB = trm_init((u_int16_t) unit, 3531 dev)) == NULL) { 3532 printf("trm%d: trm_init error!\n",unit); 3533 return (ENXIO); 3534 } 3535 /* After setting up the adapter, map our interrupt */ 3536 /* 3537 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3538 * start queue to reset to the idle loop. 3539 * Create device queue of SIM(s) 3540 * (MAX_START_JOB - 1) : max_sim_transactions 3541 */ 3542 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3543 RF_SHAREABLE | RF_ACTIVE); 3544 if (pACB->irq == NULL || 3545 bus_setup_intr(dev, pACB->irq, 3546 INTR_TYPE_CAM, NULL, trm_Interrupt, pACB, &pACB->ih)) { 3547 printf("trm%d: register Interrupt handler error!\n", unit); 3548 goto bad; 3549 } 3550 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3551 if (device_Q == NULL){ 3552 printf("trm%d: device_Q == NULL !\n",unit); 3553 goto bad; 3554 } 3555 /* 3556 * Now tell the generic SCSI layer 3557 * about our bus. 3558 * If this is the xpt layer creating a sim, then it's OK 3559 * to wait for an allocation. 3560 * XXX Should we pass in a flag to indicate that wait is OK? 3561 * 3562 * SIM allocation 3563 * 3564 * SCSI Interface Modules 3565 * The sim driver creates a sim for each controller. The sim device 3566 * queue is separately created in order to allow resource sharing betwee 3567 * sims. For instance, a driver may create one sim for each channel of 3568 * a multi-channel controller and use the same queue for each channel. 3569 * In this way, the queue resources are shared across all the channels 3570 * of the multi-channel controller. 3571 * trm_action : sim_action_func 3572 * trm_poll : sim_poll_func 3573 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3574 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3575 * pACB->unit : unit 3576 * 1 : max_dev_transactions 3577 * MAX_TAGS : max_tagged_dev_transactions 3578 * 3579 * *******Construct our first channel SIM entry 3580 */ 3581 pACB->psim = cam_sim_alloc(trm_action, 3582 trm_poll, 3583 "trm", 3584 pACB, 3585 unit, 3586 &Giant, 3587 1, 3588 TRM_MAX_TAGS_CMD_QUEUE, 3589 device_Q); 3590 if (pACB->psim == NULL) { 3591 printf("trm%d: SIM allocate fault !\n",unit); 3592 cam_simq_free(device_Q); /* SIM allocate fault*/ 3593 goto bad; 3594 } 3595 if (xpt_bus_register(pACB->psim, dev, 0) != CAM_SUCCESS) { 3596 printf("trm%d: xpt_bus_register fault !\n",unit); 3597 goto bad; 3598 } 3599 if (xpt_create_path(&pACB->ppath, 3600 NULL, 3601 cam_sim_path(pACB->psim), 3602 CAM_TARGET_WILDCARD, 3603 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3604 printf("trm%d: xpt_create_path fault !\n",unit); 3605 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3606 goto bad; 3607 } 3608 return (0); 3609 bad: 3610 if (pACB->iores) 3611 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3612 pACB->iores); 3613 if (pACB->sg_dmat) { 3614 trm_destroySRB(pACB); 3615 bus_dma_tag_destroy(pACB->sg_dmat); 3616 } 3617 3618 if (pACB->pFreeSRB) { 3619 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3620 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3621 pACB->srb_dmamap); 3622 } 3623 if (pACB->srb_dmat) 3624 bus_dma_tag_destroy(pACB->srb_dmat); 3625 if (pACB->sense_buffers) { 3626 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3627 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3628 pACB->sense_dmamap); 3629 } 3630 if (pACB->sense_dmat) 3631 bus_dma_tag_destroy(pACB->sense_dmat); 3632 if (pACB->buffer_dmat) 3633 bus_dma_tag_destroy(pACB->buffer_dmat); 3634 if (pACB->ih) 3635 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3636 if (pACB->irq) 3637 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3638 if (pACB->psim) 3639 cam_sim_free(pACB->psim, TRUE); 3640 3641 return (ENXIO); 3642 3643 } 3644 3645 /* 3646 * pci_device 3647 * trm_probe (device_t tag, pcidi_t type) 3648 * 3649 */ 3650 static int 3651 trm_probe(device_t dev) 3652 { 3653 switch (pci_get_devid(dev)) { 3654 case PCI_DEVICEID_TRMS1040: 3655 device_set_desc(dev, 3656 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3657 return (BUS_PROBE_DEFAULT); 3658 case PCI_DEVICEID_TRMS2080: 3659 device_set_desc(dev, 3660 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3661 return (BUS_PROBE_DEFAULT); 3662 default: 3663 return (ENXIO); 3664 } 3665 } 3666 3667 static int 3668 trm_detach(device_t dev) 3669 { 3670 PACB pACB = device_get_softc(dev); 3671 3672 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores); 3673 trm_destroySRB(pACB); 3674 bus_dma_tag_destroy(pACB->sg_dmat); 3675 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3676 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3677 pACB->srb_dmamap); 3678 bus_dma_tag_destroy(pACB->srb_dmat); 3679 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3680 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3681 pACB->sense_dmamap); 3682 bus_dma_tag_destroy(pACB->sense_dmat); 3683 bus_dma_tag_destroy(pACB->buffer_dmat); 3684 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3685 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3686 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3687 xpt_free_path(pACB->ppath); 3688 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3689 cam_sim_free(pACB->psim, TRUE); 3690 return (0); 3691 } 3692 static device_method_t trm_methods[] = { 3693 /* Device interface */ 3694 DEVMETHOD(device_probe, trm_probe), 3695 DEVMETHOD(device_attach, trm_attach), 3696 DEVMETHOD(device_detach, trm_detach), 3697 { 0, 0 } 3698 }; 3699 3700 static driver_t trm_driver = { 3701 "trm", trm_methods, sizeof(struct _ACB) 3702 }; 3703 3704 static devclass_t trm_devclass; 3705 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3706 MODULE_DEPEND(trm, pci, 1, 1, 1); 3707 MODULE_DEPEND(trm, cam, 1, 1, 1); 3708