1 /* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang ([email protected]) 5 * Erich Chen ([email protected]) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 */ 12 13 #include <sys/cdefs.h> 14 __FBSDID("$FreeBSD$"); 15 16 /* 17 * HISTORY: 18 * 19 * REV# DATE NAME DESCRIPTION 20 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 21 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 22 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 23 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 24 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 25 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 26 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 27 */ 28 29 /*- 30 * SPDX-License-Identifier: BSD-3-Clause 31 * 32 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 */ 57 58 /* 59 * Imported into FreeBSD source repository, and updated to compile under 60 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <[email protected]>, 1996-12-17 61 */ 62 63 /* 64 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 65 * <[email protected]>, 2002-03-04 66 */ 67 68 #include <sys/param.h> 69 70 #include <sys/systm.h> 71 #include <sys/malloc.h> 72 #include <sys/queue.h> 73 #if __FreeBSD_version >= 500000 74 #include <sys/bio.h> 75 #endif 76 #include <sys/buf.h> 77 #include <sys/bus.h> 78 #include <sys/kernel.h> 79 #include <sys/module.h> 80 81 #include <vm/vm.h> 82 #include <vm/pmap.h> 83 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <machine/resource.h> 87 #include <machine/bus.h> 88 #include <sys/rman.h> 89 90 #include <cam/cam.h> 91 #include <cam/cam_ccb.h> 92 #include <cam/cam_sim.h> 93 #include <cam/cam_xpt_sim.h> 94 #include <cam/cam_debug.h> 95 96 #include <cam/scsi/scsi_all.h> 97 #include <cam/scsi/scsi_message.h> 98 99 #include <dev/trm/trm.h> 100 101 #define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 102 #define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 103 #define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 104 #define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 105 reg, value) 106 #define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 107 reg, value) 108 #define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 109 reg, value) 110 111 #define PCI_Vendor_ID_TEKRAM 0x1DE1 112 #define PCI_Device_ID_TRM_S1040 0x0391 113 #define PCI_DEVICEID_TRMS1040 0x03911DE1 114 #define PCI_DEVICEID_TRMS2080 0x03921DE1 115 116 #ifdef trm_DEBUG1 117 #define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 118 #else 119 #define TRM_DPRINTF(fmt, arg...) {} 120 #endif /* TRM_DEBUG */ 121 122 static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 123 static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124 static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 125 static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 126 static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 127 static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 128 static void NVRAM_trm_wait_30us(PACB pACB); 129 130 static void trm_Interrupt(void *vpACB); 131 static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133 static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135 static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137 static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139 static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141 static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143 static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145 static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147 static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149 static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151 static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153 static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 154 u_int16_t * pscsi_status); 155 static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 156 static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 157 static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 158 static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 159 static void trm_Disconnect(PACB pACB); 160 static void trm_Reselect(PACB pACB); 161 static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 162 static void trm_DoingSRB_Done(PACB pACB); 163 static void trm_ScsiRstDetect(PACB pACB); 164 static void trm_ResetSCSIBus(PACB pACB); 165 static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 166 static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 167 static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 168 static void trm_SendSRB(PACB pACB, PSRB pSRB); 169 static int trm_probe(device_t tag); 170 static int trm_attach(device_t tag); 171 static void trm_reset(PACB pACB); 172 173 static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 174 175 static int trm_initAdapter(PACB pACB, u_int16_t unit); 176 static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 177 u_int32_t i, u_int32_t j); 178 static int trm_initSRB(PACB pACB); 179 static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 180 /* CAM SIM entry points */ 181 #define ccb_trmsrb_ptr spriv_ptr0 182 #define ccb_trmacb_ptr spriv_ptr1 183 static void trm_action(struct cam_sim *psim, union ccb *pccb); 184 static void trm_poll(struct cam_sim *psim); 185 186 187 static void * trm_SCSI_phase0[] = { 188 trm_DataOutPhase0, /* phase:0 */ 189 trm_DataInPhase0, /* phase:1 */ 190 trm_CommandPhase0, /* phase:2 */ 191 trm_StatusPhase0, /* phase:3 */ 192 trm_Nop0, /* phase:4 */ 193 trm_Nop1, /* phase:5 */ 194 trm_MsgOutPhase0, /* phase:6 */ 195 trm_MsgInPhase0, /* phase:7 */ 196 }; 197 198 /* 199 * 200 * stateV = (void *) trm_SCSI_phase1[phase] 201 * 202 */ 203 static void * trm_SCSI_phase1[] = { 204 trm_DataOutPhase1, /* phase:0 */ 205 trm_DataInPhase1, /* phase:1 */ 206 trm_CommandPhase1, /* phase:2 */ 207 trm_StatusPhase1, /* phase:3 */ 208 trm_Nop0, /* phase:4 */ 209 trm_Nop1, /* phase:5 */ 210 trm_MsgOutPhase1, /* phase:6 */ 211 trm_MsgInPhase1, /* phase:7 */ 212 }; 213 214 215 NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 216 /* 217 *Fast20: 000 50ns, 20.0 Mbytes/s 218 * 001 75ns, 13.3 Mbytes/s 219 * 010 100ns, 10.0 Mbytes/s 220 * 011 125ns, 8.0 Mbytes/s 221 * 100 150ns, 6.6 Mbytes/s 222 * 101 175ns, 5.7 Mbytes/s 223 * 110 200ns, 5.0 Mbytes/s 224 * 111 250ns, 4.0 Mbytes/s 225 * 226 *Fast40: 000 25ns, 40.0 Mbytes/s 227 * 001 50ns, 20.0 Mbytes/s 228 * 010 75ns, 13.3 Mbytes/s 229 * 011 100ns, 10.0 Mbytes/s 230 * 100 125ns, 8.0 Mbytes/s 231 * 101 150ns, 6.6 Mbytes/s 232 * 110 175ns, 5.7 Mbytes/s 233 * 111 200ns, 5.0 Mbytes/s 234 */ 235 /* real period: */ 236 u_int8_t dc395x_clock_period[] = { 237 12,/* 48 ns 20 MB/sec */ 238 18,/* 72 ns 13.3 MB/sec */ 239 25,/* 100 ns 10.0 MB/sec */ 240 31,/* 124 ns 8.0 MB/sec */ 241 37,/* 148 ns 6.6 MB/sec */ 242 43,/* 172 ns 5.7 MB/sec */ 243 50,/* 200 ns 5.0 MB/sec */ 244 62 /* 248 ns 4.0 MB/sec */ 245 }; 246 247 u_int8_t dc395u2x_clock_period[]={ 248 10,/* 25 ns 40.0 MB/sec */ 249 12,/* 48 ns 20.0 MB/sec */ 250 18,/* 72 ns 13.3 MB/sec */ 251 25,/* 100 ns 10.0 MB/sec */ 252 31,/* 124 ns 8.0 MB/sec */ 253 37,/* 148 ns 6.6 MB/sec */ 254 43,/* 172 ns 5.7 MB/sec */ 255 50,/* 200 ns 5.0 MB/sec */ 256 }; 257 258 #define dc395x_tinfo_period dc395x_clock_period 259 #define dc395u2x_tinfo_period dc395u2x_clock_period 260 261 static PSRB 262 trm_GetSRB(PACB pACB) 263 { 264 int intflag; 265 PSRB pSRB; 266 267 intflag = splcam(); 268 pSRB = pACB->pFreeSRB; 269 if (pSRB) { 270 pACB->pFreeSRB = pSRB->pNextSRB; 271 pSRB->pNextSRB = NULL; 272 } 273 splx(intflag); 274 return (pSRB); 275 } 276 277 static void 278 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 279 { 280 PSRB psrb1; 281 int intflag; 282 283 intflag = splcam(); 284 if ((psrb1 = pDCB->pWaitingSRB)) { 285 pSRB->pNextSRB = psrb1; 286 pDCB->pWaitingSRB = pSRB; 287 } else { 288 pSRB->pNextSRB = NULL; 289 pDCB->pWaitingSRB = pSRB; 290 pDCB->pWaitingLastSRB = pSRB; 291 } 292 splx(intflag); 293 } 294 295 static void 296 trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 297 { 298 PSRB psrb1; 299 int intflag; 300 301 intflag = splcam(); 302 pDCB->GoingSRBCnt--; 303 psrb1 = pDCB->pGoingSRB; 304 if (pSRB == psrb1) 305 /* 306 * if this SRB is GoingSRB 307 * remove this SRB from GoingSRB Q 308 */ 309 pDCB->pGoingSRB = psrb1->pNextSRB; 310 else { 311 /* 312 * if this SRB is not current GoingSRB 313 * remove this SRB from GoingSRB Q 314 */ 315 while (pSRB != psrb1->pNextSRB) 316 psrb1 = psrb1->pNextSRB; 317 psrb1->pNextSRB = pSRB->pNextSRB; 318 if (pSRB == pDCB->pGoingLastSRB) 319 pDCB->pGoingLastSRB = psrb1; 320 } 321 if ((psrb1 = pDCB->pWaitingSRB)) { 322 /* 323 * if WaitingSRB Q is not NULL 324 * Q back this SRB into WaitingSRB 325 */ 326 327 pSRB->pNextSRB = psrb1; 328 pDCB->pWaitingSRB = pSRB; 329 } else { 330 pSRB->pNextSRB = NULL; 331 pDCB->pWaitingSRB = pSRB; 332 pDCB->pWaitingLastSRB = pSRB; 333 } 334 splx(intflag); 335 } 336 337 static void 338 trm_DoWaitingSRB(PACB pACB) 339 { 340 int intflag; 341 PDCB ptr, ptr1; 342 PSRB pSRB; 343 344 intflag = splcam(); 345 if (!(pACB->pActiveDCB) && 346 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 347 ptr = pACB->pDCBRunRobin; 348 if (!ptr) { 349 ptr = pACB->pLinkDCB; 350 pACB->pDCBRunRobin = ptr; 351 } 352 ptr1 = ptr; 353 for (;ptr1 ;) { 354 pACB->pDCBRunRobin = ptr1->pNextDCB; 355 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 356 || !(pSRB = ptr1->pWaitingSRB)) { 357 if (pACB->pDCBRunRobin == ptr) 358 break; 359 ptr1 = ptr1->pNextDCB; 360 } else { 361 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 362 /* 363 * If trm_StartSCSI return 0 : 364 * current interrupt status is interrupt enable 365 * It's said that SCSI processor is unoccupied 366 */ 367 ptr1->GoingSRBCnt++; 368 if (ptr1->pWaitingLastSRB == pSRB) { 369 ptr1->pWaitingSRB = NULL; 370 ptr1->pWaitingLastSRB = NULL; 371 } else 372 ptr1->pWaitingSRB = pSRB->pNextSRB; 373 pSRB->pNextSRB = NULL; 374 if (ptr1->pGoingSRB) 375 ptr1->pGoingLastSRB->pNextSRB = pSRB; 376 else 377 ptr1->pGoingSRB = pSRB; 378 ptr1->pGoingLastSRB = pSRB; 379 } 380 break; 381 } 382 } 383 } 384 splx(intflag); 385 return; 386 } 387 388 static void 389 trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 390 { 391 392 if (pDCB->pWaitingSRB) { 393 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 394 pDCB->pWaitingLastSRB = pSRB; 395 pSRB->pNextSRB = NULL; 396 } else { 397 pDCB->pWaitingSRB = pSRB; 398 pDCB->pWaitingLastSRB = pSRB; 399 } 400 } 401 402 static u_int32_t 403 trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 404 { 405 int offset; 406 407 offset = pSRB->TagNumber; 408 return (pACB->sense_busaddr + 409 (offset * sizeof(struct scsi_sense_data))); 410 } 411 412 static struct scsi_sense_data * 413 trm_get_sense_buf(PACB pACB, PSRB pSRB) 414 { 415 int offset; 416 417 offset = pSRB->TagNumber; 418 return (&pACB->sense_buffers[offset]); 419 } 420 static void 421 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 422 { 423 int flags; 424 PACB pACB; 425 PSRB pSRB; 426 union ccb *ccb; 427 u_long totalxferlen=0; 428 429 flags = splcam(); 430 pSRB = (PSRB)arg; 431 ccb = pSRB->pccb; 432 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 433 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 434 if (nseg != 0) { 435 PSEG psg; 436 bus_dma_segment_t *end_seg; 437 int op; 438 439 /* Copy the segments into our SG list */ 440 end_seg = dm_segs + nseg; 441 psg = pSRB->pSRBSGL; 442 while (dm_segs < end_seg) { 443 psg->address = dm_segs->ds_addr; 444 psg->length = (u_long)dm_segs->ds_len; 445 totalxferlen += dm_segs->ds_len; 446 psg++; 447 dm_segs++; 448 } 449 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 450 op = BUS_DMASYNC_PREREAD; 451 } else { 452 op = BUS_DMASYNC_PREWRITE; 453 } 454 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 455 } 456 pSRB->RetryCnt = 0; 457 pSRB->SRBTotalXferLength = totalxferlen; 458 pSRB->SRBSGCount = nseg; 459 pSRB->SRBSGIndex = 0; 460 pSRB->AdaptStatus = 0; 461 pSRB->TargetStatus = 0; 462 pSRB->MsgCnt = 0; 463 pSRB->SRBStatus = 0; 464 pSRB->SRBFlag = 0; 465 pSRB->SRBState = 0; 466 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 467 468 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 469 if (nseg != 0) 470 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 471 pSRB->pNextSRB = pACB->pFreeSRB; 472 pACB->pFreeSRB = pSRB; 473 xpt_done(ccb); 474 splx(flags); 475 return; 476 } 477 ccb->ccb_h.status |= CAM_SIM_QUEUED; 478 trm_SendSRB(pACB, pSRB); 479 splx(flags); 480 return; 481 } 482 483 static void 484 trm_SendSRB(PACB pACB, PSRB pSRB) 485 { 486 PDCB pDCB; 487 488 pDCB = pSRB->pSRBDCB; 489 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 490 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 491 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 492 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 493 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 494 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 495 trm_SRBwaiting(pDCB, pSRB); 496 goto SND_EXIT; 497 } 498 499 if (pDCB->pWaitingSRB) { 500 trm_SRBwaiting(pDCB, pSRB); 501 pSRB = pDCB->pWaitingSRB; 502 pDCB->pWaitingSRB = pSRB->pNextSRB; 503 pSRB->pNextSRB = NULL; 504 } 505 506 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 507 /* 508 * If trm_StartSCSI return 0 : 509 * current interrupt status is interrupt enable 510 * It's said that SCSI processor is unoccupied 511 */ 512 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 513 if (pDCB->pGoingSRB) { 514 pDCB->pGoingLastSRB->pNextSRB = pSRB; 515 pDCB->pGoingLastSRB = pSRB; 516 } else { 517 pDCB->pGoingSRB = pSRB; 518 pDCB->pGoingLastSRB = pSRB; 519 } 520 } else { 521 /* 522 * If trm_StartSCSI return 1 : 523 * current interrupt status is interrupt disreenable 524 * It's said that SCSI processor has more one SRB need to do 525 */ 526 trm_RewaitSRB0(pDCB, pSRB); 527 } 528 SND_EXIT: 529 return; 530 } 531 532 533 static void 534 trm_action(struct cam_sim *psim, union ccb *pccb) 535 { 536 PACB pACB; 537 int actionflags; 538 u_int target_id,target_lun; 539 540 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 541 542 actionflags = splcam(); 543 pACB = (PACB) cam_sim_softc(psim); 544 target_id = pccb->ccb_h.target_id; 545 target_lun = pccb->ccb_h.target_lun; 546 547 switch (pccb->ccb_h.func_code) { 548 /* 549 * Execute the requested I/O operation 550 */ 551 case XPT_SCSI_IO: { 552 PDCB pDCB = NULL; 553 PSRB pSRB; 554 struct ccb_scsiio *pcsio; 555 int error; 556 557 pcsio = &pccb->csio; 558 TRM_DPRINTF(" XPT_SCSI_IO \n"); 559 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 560 ,target_id, target_lun); 561 TRM_DPRINTF( 562 "pACB->scan_devices[target_id][target_lun]= %d \n" 563 ,pACB->scan_devices[target_id][target_lun]); 564 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 565 CAM_REQ_INPROG) { 566 xpt_done(pccb); 567 splx(actionflags); 568 return; 569 } 570 pDCB = &pACB->DCBarray[target_id][target_lun]; 571 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 572 pACB->scan_devices[target_id][target_lun] = 1; 573 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 574 target_id, target_lun); 575 } 576 /* 577 * Assign an SRB and connect it with this ccb. 578 */ 579 pSRB = trm_GetSRB(pACB); 580 if (!pSRB) { 581 /* Freeze SIMQ */ 582 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 583 xpt_done(pccb); 584 splx(actionflags); 585 return; 586 } 587 pSRB->pSRBDCB = pDCB; 588 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 589 pccb->ccb_h.ccb_trmacb_ptr = pACB; 590 pSRB->pccb = pccb; 591 pSRB->ScsiCmdLen = pcsio->cdb_len; 592 /* 593 * move layer of CAM command block to layer of SCSI 594 * Request Block for SCSI processor command doing 595 */ 596 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 597 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 598 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 599 ,pcsio->cdb_len); 600 } else { 601 pccb->ccb_h.status = CAM_REQ_INVALID; 602 pSRB->pNextSRB = pACB->pFreeSRB; 603 pACB->pFreeSRB= pSRB; 604 xpt_done(pccb); 605 splx(actionflags); 606 return; 607 } 608 } else 609 bcopy(pcsio->cdb_io.cdb_bytes, 610 pSRB->CmdBlock, pcsio->cdb_len); 611 error = bus_dmamap_load_ccb(pACB->buffer_dmat, 612 pSRB->dmamap, 613 pccb, 614 trm_ExecuteSRB, 615 pSRB, 616 0); 617 if (error == EINPROGRESS) { 618 xpt_freeze_simq(pACB->psim, 1); 619 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 620 } 621 break; 622 } 623 /* 624 * Path routing inquiry 625 * Path Inquiry CCB 626 */ 627 case XPT_PATH_INQ: { 628 struct ccb_pathinq *cpi = &pccb->cpi; 629 630 TRM_DPRINTF(" XPT_PATH_INQ \n"); 631 cpi->version_num = 1; 632 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 633 cpi->target_sprt = 0; 634 cpi->hba_misc = 0; 635 cpi->hba_eng_cnt = 0; 636 cpi->max_target = 15 ; 637 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 638 cpi->initiator_id = pACB->AdaptSCSIID; 639 cpi->bus_id = cam_sim_bus(psim); 640 cpi->base_transfer_speed = 3300; 641 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 642 strlcpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 643 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 644 cpi->unit_number = cam_sim_unit(psim); 645 cpi->transport = XPORT_SPI; 646 cpi->transport_version = 2; 647 cpi->protocol = PROTO_SCSI; 648 cpi->protocol_version = SCSI_REV_2; 649 cpi->ccb_h.status = CAM_REQ_CMP; 650 xpt_done(pccb); 651 break; 652 } 653 /* 654 * XPT_ABORT = 0x10, Abort the specified CCB 655 * Abort XPT request CCB 656 */ 657 case XPT_ABORT: 658 TRM_DPRINTF(" XPT_ABORT \n"); 659 pccb->ccb_h.status = CAM_REQ_INVALID; 660 xpt_done(pccb); 661 break; 662 /* 663 * Reset the specified SCSI bus 664 * Reset SCSI Bus CCB 665 */ 666 case XPT_RESET_BUS: { 667 int i; 668 669 TRM_DPRINTF(" XPT_RESET_BUS \n"); 670 trm_reset(pACB); 671 pACB->ACBFlag=0; 672 for (i=0; i<500; i++) 673 DELAY(1000); 674 pccb->ccb_h.status = CAM_REQ_CMP; 675 xpt_done(pccb); 676 break; 677 } 678 /* 679 * Bus Device Reset the specified SCSI device 680 * Reset SCSI Device CCB 681 */ 682 case XPT_RESET_DEV: 683 /* 684 * Don't (yet?) support vendor 685 * specific commands. 686 */ 687 TRM_DPRINTF(" XPT_RESET_DEV \n"); 688 pccb->ccb_h.status = CAM_REQ_INVALID; 689 xpt_done(pccb); 690 break; 691 /* 692 * Terminate the I/O process 693 * Terminate I/O Process Request CCB 694 */ 695 case XPT_TERM_IO: 696 TRM_DPRINTF(" XPT_TERM_IO \n"); 697 pccb->ccb_h.status = CAM_REQ_INVALID; 698 xpt_done(pccb); 699 break; 700 /* 701 * Get/Set transfer rate/width/disconnection/tag queueing 702 * settings 703 * (GET) default/user transfer settings for the target 704 */ 705 case XPT_GET_TRAN_SETTINGS: { 706 struct ccb_trans_settings *cts = &pccb->cts; 707 int intflag; 708 struct trm_transinfo *tinfo; 709 PDCB pDCB; 710 struct ccb_trans_settings_scsi *scsi = 711 &cts->proto_specific.scsi; 712 struct ccb_trans_settings_spi *spi = 713 &cts->xport_specific.spi; 714 715 cts->protocol = PROTO_SCSI; 716 cts->protocol_version = SCSI_REV_2; 717 cts->transport = XPORT_SPI; 718 cts->transport_version = 2; 719 720 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 721 pDCB = &pACB->DCBarray[target_id][target_lun]; 722 intflag = splcam(); 723 /* 724 * disable interrupt 725 */ 726 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 727 /* current transfer settings */ 728 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 729 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 730 else 731 spi->flags = 0;/* no tag & disconnect */ 732 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 733 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 734 tinfo = &pDCB->tinfo.current; 735 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 736 cts->flags); 737 } else { 738 /* default(user) transfer settings */ 739 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 740 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 741 else 742 spi->flags = 0; 743 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 744 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 745 tinfo = &pDCB->tinfo.user; 746 TRM_DPRINTF("USER: cts->flags= %2x \n", 747 cts->flags); 748 } 749 spi->sync_period = tinfo->period; 750 spi->sync_offset = tinfo->offset; 751 spi->bus_width = tinfo->width; 752 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 753 pDCB->SyncPeriod); 754 TRM_DPRINTF("period: %d \n", tinfo->period); 755 TRM_DPRINTF("offset: %d \n", tinfo->offset); 756 TRM_DPRINTF("width: %d \n", tinfo->width); 757 758 splx(intflag); 759 spi->valid = CTS_SPI_VALID_SYNC_RATE | 760 CTS_SPI_VALID_SYNC_OFFSET | 761 CTS_SPI_VALID_BUS_WIDTH | 762 CTS_SPI_VALID_DISC; 763 scsi->valid = CTS_SCSI_VALID_TQ; 764 pccb->ccb_h.status = CAM_REQ_CMP; 765 xpt_done(pccb); 766 } 767 break; 768 /* 769 * Get/Set transfer rate/width/disconnection/tag queueing 770 * settings 771 * (Set) transfer rate/width negotiation settings 772 */ 773 case XPT_SET_TRAN_SETTINGS: { 774 struct ccb_trans_settings *cts = &pccb->cts; 775 u_int update_type; 776 int intflag; 777 PDCB pDCB; 778 struct ccb_trans_settings_scsi *scsi = 779 &cts->proto_specific.scsi; 780 struct ccb_trans_settings_spi *spi = 781 &cts->xport_specific.spi; 782 783 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 784 update_type = 0; 785 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 786 update_type |= TRM_TRANS_GOAL; 787 if (cts->type == CTS_TYPE_USER_SETTINGS) 788 update_type |= TRM_TRANS_USER; 789 intflag = splcam(); 790 pDCB = &pACB->DCBarray[target_id][target_lun]; 791 792 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 793 /*ccb disc enables */ 794 if (update_type & TRM_TRANS_GOAL) { 795 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 796 != 0) 797 pDCB->tinfo.disc_tag 798 |= TRM_CUR_DISCENB; 799 else 800 pDCB->tinfo.disc_tag &= 801 ~TRM_CUR_DISCENB; 802 } 803 if (update_type & TRM_TRANS_USER) { 804 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 805 != 0) 806 pDCB->tinfo.disc_tag 807 |= TRM_USR_DISCENB; 808 else 809 pDCB->tinfo.disc_tag &= 810 ~TRM_USR_DISCENB; 811 } 812 } 813 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 814 /* if ccb tag q active */ 815 if (update_type & TRM_TRANS_GOAL) { 816 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 817 != 0) 818 pDCB->tinfo.disc_tag |= 819 TRM_CUR_TAGENB; 820 else 821 pDCB->tinfo.disc_tag &= 822 ~TRM_CUR_TAGENB; 823 } 824 if (update_type & TRM_TRANS_USER) { 825 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 826 != 0) 827 pDCB->tinfo.disc_tag |= 828 TRM_USR_TAGENB; 829 else 830 pDCB->tinfo.disc_tag &= 831 ~TRM_USR_TAGENB; 832 } 833 } 834 /* Minimum sync period factor */ 835 836 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 837 /* if ccb sync active */ 838 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 839 if ((spi->sync_period != 0) && 840 (spi->sync_period < 125)) 841 spi->sync_period = 125; 842 /* 1/(125*4) minsync 2 MByte/sec */ 843 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) 844 != 0) { 845 if (spi->sync_offset == 0) 846 spi->sync_period = 0; 847 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 848 if (spi->sync_offset > 15) 849 spi->sync_offset = 15; 850 } 851 } 852 if ((update_type & TRM_TRANS_USER) != 0) { 853 pDCB->tinfo.user.period = spi->sync_period; 854 pDCB->tinfo.user.offset = spi->sync_offset; 855 pDCB->tinfo.user.width = spi->bus_width; 856 } 857 if ((update_type & TRM_TRANS_GOAL) != 0) { 858 pDCB->tinfo.goal.period = spi->sync_period; 859 pDCB->tinfo.goal.offset = spi->sync_offset; 860 pDCB->tinfo.goal.width = spi->bus_width; 861 } 862 splx(intflag); 863 pccb->ccb_h.status = CAM_REQ_CMP; 864 xpt_done(pccb); 865 break; 866 } 867 /* 868 * Calculate the geometry parameters for a device give 869 * the sector size and volume size. 870 */ 871 case XPT_CALC_GEOMETRY: 872 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 873 cam_calc_geometry(&pccb->ccg, /*extended*/1); 874 xpt_done(pccb); 875 break; 876 default: 877 pccb->ccb_h.status = CAM_REQ_INVALID; 878 xpt_done(pccb); 879 break; 880 } 881 splx(actionflags); 882 } 883 884 static void 885 trm_poll(struct cam_sim *psim) 886 { 887 trm_Interrupt(cam_sim_softc(psim)); 888 } 889 890 static void 891 trm_ResetDevParam(PACB pACB) 892 { 893 PDCB pDCB, pdcb; 894 PNVRAMTYPE pEEpromBuf; 895 u_int8_t PeriodIndex; 896 897 pDCB = pACB->pLinkDCB; 898 if (pDCB == NULL) 899 return; 900 pdcb = pDCB; 901 do { 902 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 903 pDCB->SyncPeriod = 0; 904 pDCB->SyncOffset = 0; 905 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 906 pDCB->DevMode = 907 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 908 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 909 PeriodIndex = 910 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 911 if (pACB->AdaptType == 1) /* is U2? */ 912 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 913 else 914 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 915 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 916 (pACB->Config & HCC_WIDE_CARD)) 917 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 918 pDCB = pDCB->pNextDCB; 919 } 920 while (pdcb != pDCB); 921 } 922 923 static void 924 trm_RecoverSRB(PACB pACB) 925 { 926 PDCB pDCB, pdcb; 927 PSRB psrb, psrb2; 928 u_int16_t cnt, i; 929 930 pDCB = pACB->pLinkDCB; 931 if (pDCB == NULL) 932 return; 933 pdcb = pDCB; 934 do { 935 cnt = pdcb->GoingSRBCnt; 936 psrb = pdcb->pGoingSRB; 937 for (i = 0; i < cnt; i++) { 938 psrb2 = psrb; 939 psrb = psrb->pNextSRB; 940 if (pdcb->pWaitingSRB) { 941 psrb2->pNextSRB = pdcb->pWaitingSRB; 942 pdcb->pWaitingSRB = psrb2; 943 } else { 944 pdcb->pWaitingSRB = psrb2; 945 pdcb->pWaitingLastSRB = psrb2; 946 psrb2->pNextSRB = NULL; 947 } 948 } 949 pdcb->GoingSRBCnt = 0; 950 pdcb->pGoingSRB = NULL; 951 pdcb = pdcb->pNextDCB; 952 } 953 while (pdcb != pDCB); 954 } 955 956 static void 957 trm_reset(PACB pACB) 958 { 959 int intflag; 960 u_int16_t i; 961 962 TRM_DPRINTF("trm: RESET"); 963 intflag = splcam(); 964 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 965 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 966 967 trm_ResetSCSIBus(pACB); 968 for (i = 0; i < 500; i++) 969 DELAY(1000); 970 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 971 /* Enable DMA interrupt */ 972 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 973 /* Clear DMA FIFO */ 974 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 975 /* Clear SCSI FIFO */ 976 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 977 trm_ResetDevParam(pACB); 978 trm_DoingSRB_Done(pACB); 979 pACB->pActiveDCB = NULL; 980 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 981 trm_DoWaitingSRB(pACB); 982 /* Tell the XPT layer that a bus reset occurred */ 983 if (pACB->ppath != NULL) 984 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 985 splx(intflag); 986 return; 987 } 988 989 static u_int16_t 990 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 991 { 992 u_int16_t return_code; 993 u_int8_t scsicommand, i,command,identify_message; 994 u_int8_t * ptr; 995 union ccb *pccb; 996 struct ccb_scsiio *pcsio; 997 998 pccb = pSRB->pccb; 999 pcsio = &pccb->csio; 1000 1001 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1002 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1003 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1004 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1005 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1006 /* Flush FIFO */ 1007 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1008 1009 identify_message = pDCB->IdentifyMsg; 1010 1011 if ((pSRB->CmdBlock[0] == INQUIRY) || 1012 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1013 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1014 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1015 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1016 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1017 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1018 if (!(pDCB->IdentifyMsg & 7) || 1019 (pSRB->CmdBlock[0] != INQUIRY)) { 1020 scsicommand = SCMD_SEL_ATNSTOP; 1021 pSRB->SRBState = SRB_MSGOUT; 1022 goto polling; 1023 } 1024 } 1025 /* 1026 * Send identify message 1027 */ 1028 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1029 scsicommand = SCMD_SEL_ATN; 1030 pSRB->SRBState = SRB_START_; 1031 } else { 1032 /* not inquiry,request sense,auto request sense */ 1033 /* 1034 * Send identify message 1035 */ 1036 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1037 scsicommand = SCMD_SEL_ATN; 1038 pSRB->SRBState = SRB_START_; 1039 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1040 /* Send Tag message */ 1041 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1042 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1043 scsicommand = SCMD_SEL_ATN3; 1044 } 1045 } 1046 polling: 1047 /* 1048 * Send CDB ..command block ......... 1049 */ 1050 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1051 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1052 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1053 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1054 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1055 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1056 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1057 } else { 1058 ptr = (u_int8_t *) pSRB->CmdBlock; 1059 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1060 command = *ptr++; 1061 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1062 } 1063 } 1064 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1065 /* 1066 * If trm_StartSCSI return 1 : 1067 * current interrupt status is interrupt disreenable 1068 * It's said that SCSI processor has more one SRB need to do, 1069 * SCSI processor has been occupied by one SRB. 1070 */ 1071 pSRB->SRBState = SRB_READY; 1072 return_code = 1; 1073 } else { 1074 /* 1075 * If trm_StartSCSI return 0 : 1076 * current interrupt status is interrupt enable 1077 * It's said that SCSI processor is unoccupied 1078 */ 1079 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1080 pACB->pActiveDCB = pDCB; 1081 pDCB->pActiveSRB = pSRB; 1082 return_code = 0; 1083 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1084 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1085 /* 1086 * SCSI cammand 1087 */ 1088 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1089 } 1090 return (return_code); 1091 } 1092 1093 static void 1094 trm_Interrupt(vpACB) 1095 void *vpACB; 1096 { 1097 PACB pACB; 1098 PDCB pDCB; 1099 PSRB pSRB; 1100 u_int16_t phase; 1101 void (*stateV)(PACB, PSRB, u_int16_t *); 1102 u_int16_t scsi_status=0; 1103 u_int8_t scsi_intstatus; 1104 1105 pACB = vpACB; 1106 1107 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1108 if (!(scsi_status & SCSIINTERRUPT)) { 1109 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1110 return; 1111 } 1112 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1113 1114 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1115 1116 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1117 1118 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1119 trm_Disconnect(pACB); 1120 return; 1121 } 1122 1123 if (scsi_intstatus & INT_RESELECTED) { 1124 trm_Reselect(pACB); 1125 return; 1126 } 1127 if (scsi_intstatus & INT_SCSIRESET) { 1128 trm_ScsiRstDetect(pACB); 1129 return; 1130 } 1131 1132 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1133 pDCB = pACB->pActiveDCB; 1134 KASSERT(pDCB != NULL, ("no active DCB")); 1135 pSRB = pDCB->pActiveSRB; 1136 if (pDCB->DCBFlag & ABORT_DEV_) 1137 trm_EnableMsgOutAbort1(pACB, pSRB); 1138 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1139 stateV = (void *) trm_SCSI_phase0[phase]; 1140 stateV(pACB, pSRB, &scsi_status); 1141 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1142 /* phase:0,1,2,3,4,5,6,7 */ 1143 phase = (u_int16_t) scsi_status & PHASEMASK; 1144 stateV = (void *) trm_SCSI_phase1[phase]; 1145 stateV(pACB, pSRB, &scsi_status); 1146 } 1147 } 1148 1149 static void 1150 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1151 { 1152 1153 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1154 *pscsi_status = PH_BUS_FREE; 1155 /*.. initial phase*/ 1156 } 1157 1158 static void 1159 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1160 { 1161 u_int8_t bval; 1162 u_int16_t i, cnt; 1163 u_int8_t * ptr; 1164 PDCB pDCB; 1165 1166 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1167 pDCB = pACB->pActiveDCB; 1168 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1169 cnt = pSRB->MsgCnt; 1170 if (cnt) { 1171 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1172 for (i = 0; i < cnt; i++) { 1173 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1174 ptr++; 1175 } 1176 pSRB->MsgCnt = 0; 1177 if ((pDCB->DCBFlag & ABORT_DEV_) && 1178 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1179 pSRB->SRBState = SRB_ABORT_SENT; 1180 } 1181 } else { 1182 bval = MSG_ABORT; 1183 if ((pSRB->CmdBlock[0] == INQUIRY) || 1184 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1185 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1186 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1187 goto mop1; 1188 } 1189 } 1190 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1191 } 1192 } else { 1193 mop1: /* message out phase */ 1194 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1195 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1196 /* 1197 * WIDE DATA TRANSFER REQUEST code (03h) 1198 */ 1199 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1200 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1201 TRMREG_SCSI_FIFO); 1202 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1203 /* (01h) */ 1204 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1205 /* Message length (02h) */ 1206 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1207 /* wide data xfer (03h) */ 1208 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1209 /* width:0(8bit),1(16bit),2(32bit) */ 1210 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1211 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1212 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1213 /* 1214 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1215 */ 1216 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1217 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1218 TRMREG_SCSI_FIFO); 1219 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1220 /* (01h) */ 1221 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1222 /* Message length (03h) */ 1223 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1224 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1225 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1226 /* Transfer peeriod factor */ 1227 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1228 TRMREG_SCSI_FIFO); 1229 /* REQ/ACK offset */ 1230 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1231 } 1232 } 1233 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1234 /* it's important for atn stop */ 1235 /* 1236 * SCSI cammand 1237 */ 1238 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1239 } 1240 1241 static void 1242 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1243 { 1244 1245 } 1246 1247 static void 1248 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1249 { 1250 PDCB pDCB; 1251 u_int8_t * ptr; 1252 u_int16_t i, cnt; 1253 union ccb *pccb; 1254 struct ccb_scsiio *pcsio; 1255 1256 pccb = pSRB->pccb; 1257 pcsio = &pccb->csio; 1258 1259 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1260 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1261 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1262 ptr = (u_int8_t *) pSRB->CmdBlock; 1263 for (i = 0; i < cnt; i++) { 1264 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1265 ptr++; 1266 } 1267 } else { 1268 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1269 pDCB = pACB->pActiveDCB; 1270 /* target id */ 1271 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1272 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1273 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1274 /* sizeof(struct scsi_sense_data) */ 1275 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1276 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1277 } 1278 pSRB->SRBState = SRB_COMMAND; 1279 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1280 /* it's important for atn stop*/ 1281 /* 1282 * SCSI cammand 1283 */ 1284 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1285 } 1286 1287 static void 1288 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1289 { 1290 PDCB pDCB; 1291 u_int8_t TempDMAstatus,SGIndexTemp; 1292 u_int16_t scsi_status; 1293 PSEG pseg; 1294 u_long TempSRBXferredLength,dLeftCounter=0; 1295 1296 pDCB = pSRB->pSRBDCB; 1297 scsi_status = *pscsi_status; 1298 1299 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1300 if (scsi_status & PARITYERROR) 1301 pSRB->SRBStatus |= PARITY_ERROR; 1302 if (!(scsi_status & SCSIXFERDONE)) { 1303 /* 1304 * when data transfer from DMA FIFO to SCSI FIFO 1305 * if there was some data left in SCSI FIFO 1306 */ 1307 dLeftCounter = (u_long) 1308 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1309 if (pDCB->SyncPeriod & WIDE_SYNC) { 1310 /* 1311 * if WIDE scsi SCSI FIFOCNT unit is word 1312 * so need to * 2 1313 */ 1314 dLeftCounter <<= 1; 1315 } 1316 } 1317 /* 1318 * caculate all the residue data that not yet tranfered 1319 * SCSI transfer counter + left in SCSI FIFO data 1320 * 1321 * .....TRM_SCSI_COUNTER (24bits) 1322 * The counter always decrement by one for every SCSI byte 1323 *transfer. 1324 * .....TRM_SCSI_FIFOCNT (5bits) 1325 * The counter is SCSI FIFO offset counter 1326 */ 1327 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1328 if (dLeftCounter == 1) { 1329 dLeftCounter = 0; 1330 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1331 } 1332 if ((dLeftCounter == 0) || 1333 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1334 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1335 while (!(TempDMAstatus & DMAXFERCOMP)) { 1336 TempDMAstatus = 1337 trm_reg_read8(TRMREG_DMA_STATUS); 1338 } 1339 pSRB->SRBTotalXferLength = 0; 1340 } else { 1341 /* Update SG list */ 1342 /* 1343 * if transfer not yet complete 1344 * there were some data residue in SCSI FIFO or 1345 * SCSI transfer counter not empty 1346 */ 1347 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1348 /* 1349 * data that had transferred length 1350 */ 1351 TempSRBXferredLength = 1352 pSRB->SRBTotalXferLength - dLeftCounter; 1353 /* 1354 * next time to be transferred length 1355 */ 1356 pSRB->SRBTotalXferLength = dLeftCounter; 1357 /* 1358 * parsing from last time disconnect SRBSGIndex 1359 */ 1360 pseg = 1361 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1362 for (SGIndexTemp = pSRB->SRBSGIndex; 1363 SGIndexTemp < pSRB->SRBSGCount; 1364 SGIndexTemp++) { 1365 /* 1366 * find last time which SG transfer be 1367 * disconnect 1368 */ 1369 if (TempSRBXferredLength >= 1370 pseg->length) 1371 TempSRBXferredLength -= 1372 pseg->length; 1373 else { 1374 /* 1375 * update last time disconnected SG 1376 * list 1377 */ 1378 pseg->length -= 1379 TempSRBXferredLength; 1380 /* residue data length */ 1381 pseg->address += 1382 TempSRBXferredLength; 1383 /* residue data pointer */ 1384 pSRB->SRBSGIndex = SGIndexTemp; 1385 break; 1386 } 1387 pseg++; 1388 } 1389 } 1390 } 1391 } 1392 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1393 } 1394 1395 1396 static void 1397 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1398 { 1399 u_int16_t ioDir; 1400 /* 1401 * do prepare befor transfer when data out phase 1402 */ 1403 1404 ioDir = XFERDATAOUT; 1405 trm_DataIO_transfer(pACB, pSRB, ioDir); 1406 } 1407 1408 static void 1409 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1410 { 1411 u_int8_t TempDMAstatus, SGIndexTemp; 1412 u_int16_t scsi_status; 1413 PSEG pseg; 1414 u_long TempSRBXferredLength,dLeftCounter = 0; 1415 1416 scsi_status = *pscsi_status; 1417 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1418 if (scsi_status & PARITYERROR) 1419 pSRB->SRBStatus |= PARITY_ERROR; 1420 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1421 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1422 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1423 while (!(TempDMAstatus & DMAXFERCOMP)) 1424 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1425 pSRB->SRBTotalXferLength = 0; 1426 } else { 1427 /* 1428 * parsing the case: 1429 * when a transfer not yet complete 1430 * but be disconnected by uper layer 1431 * if transfer not yet complete 1432 * there were some data residue in SCSI FIFO or 1433 * SCSI transfer counter not empty 1434 */ 1435 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1436 /* 1437 * data that had transferred length 1438 */ 1439 TempSRBXferredLength = 1440 pSRB->SRBTotalXferLength - dLeftCounter; 1441 /* 1442 * next time to be transferred length 1443 */ 1444 pSRB->SRBTotalXferLength = dLeftCounter; 1445 /* 1446 * parsing from last time disconnect SRBSGIndex 1447 */ 1448 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1449 for (SGIndexTemp = pSRB->SRBSGIndex; 1450 SGIndexTemp < pSRB->SRBSGCount; 1451 SGIndexTemp++) { 1452 /* 1453 * find last time which SG transfer be disconnect 1454 */ 1455 if (TempSRBXferredLength >= pseg->length) 1456 TempSRBXferredLength -= pseg->length; 1457 else { 1458 /* 1459 * update last time disconnected SG list 1460 */ 1461 pseg->length -= TempSRBXferredLength; 1462 /* residue data length */ 1463 pseg->address += TempSRBXferredLength; 1464 /* residue data pointer */ 1465 pSRB->SRBSGIndex = SGIndexTemp; 1466 break; 1467 } 1468 pseg++; 1469 } 1470 } 1471 } 1472 } 1473 } 1474 1475 static void 1476 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1477 { 1478 u_int16_t ioDir; 1479 /* 1480 * do prepare befor transfer when data in phase 1481 */ 1482 1483 ioDir = XFERDATAIN; 1484 trm_DataIO_transfer(pACB, pSRB, ioDir); 1485 } 1486 1487 static void 1488 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1489 { 1490 u_int8_t bval; 1491 PDCB pDCB; 1492 1493 pDCB = pSRB->pSRBDCB; 1494 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1495 if (pSRB->SRBTotalXferLength != 0) { 1496 /* 1497 * load what physical address of Scatter/Gather list 1498 table want to be transfer 1499 */ 1500 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1501 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1502 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1503 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1504 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1505 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1506 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1507 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1508 1509 pSRB->SRBState = SRB_DATA_XFER; 1510 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1511 trm_reg_write32( 1512 (pSRB->SRBSGPhyAddr + 1513 ((u_long)pSRB->SRBSGIndex << 3)), 1514 TRMREG_DMA_XLOWADDR); 1515 /* 1516 * load how many bytes in the Scatter/Gather 1517 * list table 1518 */ 1519 trm_reg_write32( 1520 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1521 TRMREG_DMA_XCNT); 1522 /* 1523 * load total transfer length (24bits) max value 1524 * 16Mbyte 1525 */ 1526 trm_reg_write32(pSRB->SRBTotalXferLength, 1527 TRMREG_SCSI_COUNTER); 1528 /* Start DMA transfer */ 1529 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1530 /* Start SCSI transfer */ 1531 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1532 /* it's important for atn stop */ 1533 /* 1534 * SCSI cammand 1535 */ 1536 bval = (ioDir == XFERDATAOUT) ? 1537 SCMD_DMA_OUT : SCMD_DMA_IN; 1538 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1539 } else { 1540 /* xfer pad */ 1541 if (pSRB->SRBSGCount) { 1542 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1543 pSRB->SRBStatus |= OVER_RUN; 1544 } 1545 if (pDCB->SyncPeriod & WIDE_SYNC) 1546 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1547 else 1548 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1549 if (ioDir == XFERDATAOUT) 1550 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1551 else 1552 trm_reg_read16(TRMREG_SCSI_FIFO); 1553 pSRB->SRBState |= SRB_XFERPAD; 1554 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1555 /* it's important for atn stop */ 1556 /* 1557 * SCSI cammand 1558 */ 1559 bval = (ioDir == XFERDATAOUT) ? 1560 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1561 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1562 } 1563 } 1564 } 1565 1566 static void 1567 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1568 { 1569 1570 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1571 pSRB->SRBState = SRB_COMPLETED; 1572 *pscsi_status = PH_BUS_FREE; 1573 /*.. initial phase*/ 1574 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1575 /* it's important for atn stop */ 1576 /* 1577 * SCSI cammand 1578 */ 1579 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1580 } 1581 1582 1583 1584 static void 1585 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1586 { 1587 1588 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1589 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1590 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1591 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1592 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1593 } else { 1594 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1595 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1596 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1597 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1598 } 1599 pSRB->SRBState = SRB_STATUS; 1600 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1601 /* it's important for atn stop */ 1602 /* 1603 * SCSI cammand 1604 */ 1605 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1606 } 1607 1608 /* 1609 *scsiiom 1610 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1611 * stateV = (void *) trm_SCSI_phase0[phase] 1612 * if phase =7 1613 * extended message codes: 1614 * 1615 * code description 1616 * 1617 * 02h Reserved 1618 * 00h MODIFY DATA POINTER 1619 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1620 * 03h WIDE DATA TRANSFER REQUEST 1621 * 04h - 7Fh Reserved 1622 * 80h - FFh Vendor specific 1623 * 1624 */ 1625 1626 static void 1627 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1628 { 1629 u_int8_t message_in_code,bIndex,message_in_tag_id; 1630 PDCB pDCB; 1631 PSRB pSRBTemp; 1632 1633 pDCB = pACB->pActiveDCB; 1634 1635 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1636 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1637 if (message_in_code == MSG_DISCONNECT) { 1638 pSRB->SRBState = SRB_DISCONNECT; 1639 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1640 /* it's important for atn stop */ 1641 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1642 /* 1643 * SCSI command 1644 */ 1645 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1646 return; 1647 } else if (message_in_code == MSG_SAVE_PTR) { 1648 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1649 /* it's important for atn stop */ 1650 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1651 /* 1652 * SCSI command 1653 */ 1654 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1655 return; 1656 } else if ((message_in_code == MSG_EXTENDED) || 1657 ((message_in_code >= MSG_SIMPLE_QTAG) && 1658 (message_in_code <= MSG_ORDER_QTAG))) { 1659 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1660 pSRB->MsgInBuf[0] = message_in_code; 1661 /* extended message (01h) */ 1662 pSRB->MsgCnt = 1; 1663 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1664 /* extended message length (n) */ 1665 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1666 /* it's important for atn stop */ 1667 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1668 /* 1669 * SCSI command 1670 */ 1671 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1672 return; 1673 } else if (message_in_code == MSG_REJECT_) { 1674 /* Reject message */ 1675 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1676 /* do wide nego reject */ 1677 pDCB = pSRB->pSRBDCB; 1678 pDCB->SyncMode |= WIDE_NEGO_DONE; 1679 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1680 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1681 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1682 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1683 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1684 /* Set ATN, in case ATN was clear */ 1685 pSRB->SRBState |= SRB_MSGOUT; 1686 trm_reg_write16( 1687 DO_SETATN, 1688 TRMREG_SCSI_CONTROL); 1689 } else { 1690 /* Clear ATN */ 1691 trm_reg_write16( 1692 DO_CLRATN, 1693 TRMREG_SCSI_CONTROL); 1694 } 1695 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1696 /* do sync nego reject */ 1697 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1698 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1699 pDCB = pSRB->pSRBDCB; 1700 pDCB->SyncMode &= 1701 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1702 pDCB->SyncPeriod = 0; 1703 pDCB->SyncOffset = 0; 1704 /* 1705 * 1706 * program SCSI control register 1707 * 1708 */ 1709 trm_reg_write8(pDCB->SyncPeriod, 1710 TRMREG_SCSI_SYNC); 1711 trm_reg_write8(pDCB->SyncOffset, 1712 TRMREG_SCSI_OFFSET); 1713 trm_SetXferRate(pACB,pSRB,pDCB); 1714 } 1715 } 1716 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1717 /* it's important for atn stop */ 1718 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1719 /* 1720 * SCSI command 1721 */ 1722 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1723 return; 1724 } else if (message_in_code == MSG_IGNOREWIDE) { 1725 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1726 trm_reg_read8(TRMREG_SCSI_FIFO); 1727 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1728 /* it's important for atn stop */ 1729 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1730 /* 1731 * SCSI command 1732 */ 1733 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1734 return; 1735 } else { 1736 /* Restore data pointer message */ 1737 /* Save data pointer message */ 1738 /* Completion message */ 1739 /* NOP message */ 1740 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1741 /* it's important for atn stop */ 1742 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1743 /* 1744 * SCSI command 1745 */ 1746 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1747 return; 1748 } 1749 } else { 1750 /* 1751 * Parsing incoming extented messages 1752 */ 1753 *pSRB->pMsgPtr = message_in_code; 1754 pSRB->MsgCnt++; 1755 pSRB->pMsgPtr++; 1756 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1757 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1758 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1759 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1760 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1761 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1762 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1763 /* 1764 * is QUEUE tag message : 1765 * 1766 * byte 0: 1767 * HEAD QUEUE TAG (20h) 1768 * ORDERED QUEUE TAG (21h) 1769 * SIMPLE QUEUE TAG (22h) 1770 * byte 1: 1771 * Queue tag (00h - FFh) 1772 */ 1773 if (pSRB->MsgCnt == 2) { 1774 pSRB->SRBState = 0; 1775 message_in_tag_id = pSRB->MsgInBuf[1]; 1776 pSRB = pDCB->pGoingSRB; 1777 pSRBTemp = pDCB->pGoingLastSRB; 1778 if (pSRB) { 1779 for (;;) { 1780 if (pSRB->TagNumber != 1781 message_in_tag_id) { 1782 if (pSRB == pSRBTemp) { 1783 goto mingx0; 1784 } 1785 pSRB = pSRB->pNextSRB; 1786 } else 1787 break; 1788 } 1789 if (pDCB->DCBFlag & ABORT_DEV_) { 1790 pSRB->SRBState = SRB_ABORT_SENT; 1791 trm_EnableMsgOutAbort1( 1792 pACB, pSRB); 1793 } 1794 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 1795 TRM_DPRINTF("SRB not yet disconnect........ \n "); 1796 goto mingx0; 1797 } 1798 pDCB->pActiveSRB = pSRB; 1799 pSRB->SRBState = SRB_DATA_XFER; 1800 } else { 1801 mingx0: 1802 pSRB = &pACB->TmpSRB; 1803 pSRB->SRBState = SRB_UNEXPECT_RESEL; 1804 pDCB->pActiveSRB = pSRB; 1805 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 1806 trm_EnableMsgOutAbort2( 1807 pACB, 1808 pSRB); 1809 } 1810 } 1811 *pscsi_status = PH_BUS_FREE; 1812 /* .. initial phase */ 1813 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1814 /* it's important for atn stop */ 1815 /* 1816 * SCSI command 1817 */ 1818 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1819 return; 1820 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 1821 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 1822 /* 1823 * is Wide data xfer Extended message : 1824 * ====================================== 1825 * WIDE DATA TRANSFER REQUEST 1826 * ====================================== 1827 * byte 0 : Extended message (01h) 1828 * byte 1 : Extended message length (02h) 1829 * byte 2 : WIDE DATA TRANSFER code (03h) 1830 * byte 3 : Transfer width exponent 1831 */ 1832 pDCB = pSRB->pSRBDCB; 1833 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 1834 if ((pSRB->MsgInBuf[1] != 2)) { 1835 /* Length is wrong, reject it */ 1836 pDCB->SyncMode &= 1837 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1838 pSRB->MsgCnt = 1; 1839 pSRB->MsgInBuf[0] = MSG_REJECT_; 1840 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 1841 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1842 /* it's important for atn stop */ 1843 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1844 /* 1845 * SCSI command 1846 */ 1847 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1848 return; 1849 } 1850 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1851 /* Do wide negoniation */ 1852 if (pSRB->MsgInBuf[3] > 2) { 1853 /* > 32 bit */ 1854 /* reject_msg: */ 1855 pDCB->SyncMode &= 1856 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1857 pSRB->MsgCnt = 1; 1858 pSRB->MsgInBuf[0] = MSG_REJECT_; 1859 trm_reg_write16(DO_SETATN, 1860 TRMREG_SCSI_CONTROL); 1861 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1862 /* it's important for atn stop */ 1863 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1864 /* 1865 * SCSI command 1866 */ 1867 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1868 return; 1869 } 1870 if (pSRB->MsgInBuf[3] == 2) { 1871 pSRB->MsgInBuf[3] = 1; 1872 /* do 16 bits */ 1873 } else { 1874 if (!(pDCB->SyncMode 1875 & WIDE_NEGO_DONE)) { 1876 pSRB->SRBState &= 1877 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1878 pDCB->SyncMode |= 1879 WIDE_NEGO_DONE; 1880 pDCB->SyncMode &= 1881 ~(SYNC_NEGO_DONE | 1882 EN_ATN_STOP | 1883 WIDE_NEGO_ENABLE); 1884 if (pSRB->MsgInBuf[3] != 0) { 1885 /* is Wide data xfer */ 1886 pDCB->SyncPeriod |= 1887 WIDE_SYNC; 1888 pDCB->tinfo.current.width 1889 = MSG_EXT_WDTR_BUS_16_BIT; 1890 pDCB->tinfo.goal.width 1891 = MSG_EXT_WDTR_BUS_16_BIT; 1892 } 1893 } 1894 } 1895 } else 1896 pSRB->MsgInBuf[3] = 0; 1897 pSRB->SRBState |= SRB_MSGOUT; 1898 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 1899 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1900 /* it's important for atn stop */ 1901 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1902 /* 1903 * SCSI command 1904 */ 1905 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1906 return; 1907 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 1908 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 1909 /* 1910 * is 8bit transfer Extended message : 1911 * ================================= 1912 * SYNCHRONOUS DATA TRANSFER REQUEST 1913 * ================================= 1914 * byte 0 : Extended message (01h) 1915 * byte 1 : Extended message length (03) 1916 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1917 * byte 3 : Transfer period factor 1918 * byte 4 : REQ/ACK offset 1919 */ 1920 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 1921 if ((pSRB->MsgInBuf[1] != 3) || 1922 (pSRB->MsgInBuf[2] != 1)) { 1923 /* reject_msg: */ 1924 pSRB->MsgCnt = 1; 1925 pSRB->MsgInBuf[0] = MSG_REJECT_; 1926 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 1927 *pscsi_status = PH_BUS_FREE; 1928 /* .. initial phase */ 1929 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1930 /* it's important for atn stop */ 1931 /* 1932 * SCSI cammand 1933 */ 1934 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1935 return; 1936 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 1937 /* set async */ 1938 pDCB = pSRB->pSRBDCB; 1939 /* disable sync & sync nego */ 1940 pDCB->SyncMode &= 1941 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1942 pDCB->SyncPeriod = 0; 1943 pDCB->SyncOffset = 0; 1944 pDCB->tinfo.goal.period = 0; 1945 pDCB->tinfo.goal.offset = 0; 1946 pDCB->tinfo.current.period = 0; 1947 pDCB->tinfo.current.offset = 0; 1948 pDCB->tinfo.current.width = 1949 MSG_EXT_WDTR_BUS_8_BIT; 1950 /* 1951 * 1952 * program SCSI control register 1953 * 1954 */ 1955 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 1956 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 1957 trm_SetXferRate(pACB,pSRB,pDCB); 1958 *pscsi_status = PH_BUS_FREE; 1959 /* .. initial phase */ 1960 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1961 /* it's important for atn stop */ 1962 /* 1963 * SCSI cammand 1964 */ 1965 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1966 return; 1967 } else { 1968 /* set sync */ 1969 pDCB = pSRB->pSRBDCB; 1970 pDCB->SyncMode |= 1971 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 1972 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 1973 /* Transfer period factor */ 1974 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 1975 /* REQ/ACK offset */ 1976 if (pACB->AdaptType == 1) { 1977 for(bIndex = 0; bIndex < 7; bIndex++) { 1978 if (pSRB->MsgInBuf[3] <= 1979 dc395u2x_clock_period[bIndex]) { 1980 pDCB->tinfo.goal.period = 1981 dc395u2x_tinfo_period[bIndex]; 1982 pDCB->tinfo.current.period = 1983 dc395u2x_tinfo_period[bIndex]; 1984 pDCB->tinfo.goal.offset = 1985 pDCB->SyncOffset; 1986 pDCB->tinfo.current.offset = 1987 pDCB->SyncOffset; 1988 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 1989 break; 1990 } 1991 } 1992 } else { 1993 for(bIndex = 0; bIndex < 7; bIndex++) { 1994 if (pSRB->MsgInBuf[3] <= 1995 dc395x_clock_period[bIndex]) { 1996 pDCB->tinfo.goal.period = 1997 dc395x_tinfo_period[bIndex]; 1998 pDCB->tinfo.current.period = 1999 dc395x_tinfo_period[bIndex]; 2000 pDCB->tinfo.goal.offset = 2001 pDCB->SyncOffset; 2002 pDCB->tinfo.current.offset = 2003 pDCB->SyncOffset; 2004 pDCB->SyncPeriod |= 2005 (bIndex|ALT_SYNC); 2006 break; 2007 } 2008 } 2009 } 2010 /* 2011 * 2012 * program SCSI control register 2013 * 2014 */ 2015 trm_reg_write8(pDCB->SyncPeriod, 2016 TRMREG_SCSI_SYNC); 2017 trm_reg_write8(pDCB->SyncOffset, 2018 TRMREG_SCSI_OFFSET); 2019 trm_SetXferRate(pACB,pSRB,pDCB); 2020 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2021 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2022 /* 2023 ** SCSI command 2024 */ 2025 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2026 return; 2027 } 2028 } 2029 *pscsi_status = PH_BUS_FREE; 2030 /* .. initial phase */ 2031 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2032 /* it's important for atn stop */ 2033 /* 2034 * SCSI cammand 2035 */ 2036 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2037 } 2038 } 2039 2040 static void 2041 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2042 { 2043 2044 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2045 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2046 if (!(pSRB->SRBState & SRB_MSGIN)) { 2047 pSRB->SRBState &= SRB_DISCONNECT; 2048 pSRB->SRBState |= SRB_MSGIN; 2049 } 2050 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2051 /* it's important for atn stop*/ 2052 /* 2053 * SCSI cammand 2054 */ 2055 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2056 } 2057 2058 static void 2059 trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2060 { 2061 2062 } 2063 2064 static void 2065 trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2066 { 2067 2068 } 2069 2070 static void 2071 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2072 { 2073 union ccb *pccb; 2074 struct ccb_trans_settings neg; 2075 u_int16_t cnt, i; 2076 u_int8_t bval; 2077 PDCB pDCBTemp; 2078 2079 /* 2080 * set all lun device's period , offset 2081 */ 2082 TRM_DPRINTF("trm_SetXferRate\n"); 2083 pccb = pSRB->pccb; 2084 memset(&neg, 0, sizeof (neg)); 2085 neg.xport_specific.spi.sync_period = pDCB->tinfo.goal.period; 2086 neg.xport_specific.spi.sync_offset = pDCB->tinfo.goal.offset; 2087 neg.xport_specific.spi.valid = 2088 CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET; 2089 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2090 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2091 if (!(pDCB->IdentifyMsg & 0x07)) { 2092 pDCBTemp = pACB->pLinkDCB; 2093 cnt = pACB->DeviceCnt; 2094 bval = pDCB->TargetID; 2095 for (i = 0; i < cnt; i++) { 2096 if (pDCBTemp->TargetID == bval) { 2097 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2098 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2099 pDCBTemp->SyncMode = pDCB->SyncMode; 2100 } 2101 pDCBTemp = pDCBTemp->pNextDCB; 2102 } 2103 } 2104 return; 2105 } 2106 2107 /* 2108 * scsiiom 2109 * trm_Interrupt 2110 * 2111 * 2112 * ---SCSI bus phase 2113 * 2114 * PH_DATA_OUT 0x00 Data out phase 2115 * PH_DATA_IN 0x01 Data in phase 2116 * PH_COMMAND 0x02 Command phase 2117 * PH_STATUS 0x03 Status phase 2118 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2119 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2120 * PH_MSG_OUT 0x06 Message out phase 2121 * PH_MSG_IN 0x07 Message in phase 2122 * 2123 */ 2124 static void 2125 trm_Disconnect(PACB pACB) 2126 { 2127 PDCB pDCB; 2128 PSRB pSRB, psrb; 2129 u_int16_t i,j, cnt; 2130 u_int target_id,target_lun; 2131 2132 TRM_DPRINTF("trm_Disconnect...............\n "); 2133 2134 pDCB = pACB->pActiveDCB; 2135 if (!pDCB) { 2136 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2137 j = 400; 2138 while (--j) 2139 DELAY(1); 2140 /* 1 msec */ 2141 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2142 TRMREG_SCSI_CONTROL); 2143 return; 2144 } 2145 pSRB = pDCB->pActiveSRB; 2146 /* bug pSRB=0 */ 2147 target_id = pSRB->pccb->ccb_h.target_id; 2148 target_lun = pSRB->pccb->ccb_h.target_lun; 2149 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2150 pACB->pActiveDCB = 0; 2151 pSRB->ScsiPhase = PH_BUS_FREE; 2152 /* SCSI bus free Phase */ 2153 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2154 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2155 pSRB->SRBState = 0; 2156 trm_DoWaitingSRB(pACB); 2157 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2158 pDCB->DCBFlag = 0; 2159 cnt = pDCB->GoingSRBCnt; 2160 pDCB->GoingSRBCnt = 0; 2161 pSRB = pDCB->pGoingSRB; 2162 for (i = 0; i < cnt; i++) { 2163 psrb = pSRB->pNextSRB; 2164 pSRB->pNextSRB = pACB->pFreeSRB; 2165 pACB->pFreeSRB = pSRB; 2166 pSRB = psrb; 2167 } 2168 pDCB->pGoingSRB = 0; 2169 trm_DoWaitingSRB(pACB); 2170 } else { 2171 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2172 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2173 /* Selection time out */ 2174 if (!(pACB->scan_devices[target_id][target_lun]) && 2175 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2176 pSRB->CmdBlock[0] != INQUIRY) { 2177 pSRB->SRBState = SRB_READY; 2178 trm_RewaitSRB(pDCB, pSRB); 2179 } else { 2180 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2181 goto disc1; 2182 } 2183 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2184 /* 2185 * SRB_DISCONNECT 2186 */ 2187 trm_DoWaitingSRB(pACB); 2188 } else if (pSRB->SRBState & SRB_COMPLETED) { 2189 disc1: 2190 /* 2191 * SRB_COMPLETED 2192 */ 2193 pDCB->pActiveSRB = 0; 2194 pSRB->SRBState = SRB_FREE; 2195 trm_SRBdone(pACB, pDCB, pSRB); 2196 } 2197 } 2198 return; 2199 } 2200 2201 static void 2202 trm_Reselect(PACB pACB) 2203 { 2204 PDCB pDCB; 2205 PSRB pSRB; 2206 u_int16_t RselTarLunId; 2207 2208 TRM_DPRINTF("trm_Reselect................. \n"); 2209 pDCB = pACB->pActiveDCB; 2210 if (pDCB) { 2211 /* Arbitration lost but Reselection win */ 2212 pSRB = pDCB->pActiveSRB; 2213 pSRB->SRBState = SRB_READY; 2214 trm_RewaitSRB(pDCB, pSRB); 2215 } 2216 /* Read Reselected Target Id and LUN */ 2217 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2218 pDCB = pACB->pLinkDCB; 2219 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2220 /* get pDCB of the reselect id */ 2221 pDCB = pDCB->pNextDCB; 2222 } 2223 2224 pACB->pActiveDCB = pDCB; 2225 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2226 pSRB = &pACB->TmpSRB; 2227 pDCB->pActiveSRB = pSRB; 2228 } else { 2229 pSRB = pDCB->pActiveSRB; 2230 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2231 /* 2232 * abort command 2233 */ 2234 pSRB = &pACB->TmpSRB; 2235 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2236 pDCB->pActiveSRB = pSRB; 2237 trm_EnableMsgOutAbort1(pACB, pSRB); 2238 } else { 2239 if (pDCB->DCBFlag & ABORT_DEV_) { 2240 pSRB->SRBState = SRB_ABORT_SENT; 2241 trm_EnableMsgOutAbort1(pACB, pSRB); 2242 } else 2243 pSRB->SRBState = SRB_DATA_XFER; 2244 } 2245 } 2246 pSRB->ScsiPhase = PH_BUS_FREE; 2247 /* SCSI bus free Phase */ 2248 /* 2249 * Program HA ID, target ID, period and offset 2250 */ 2251 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2252 /* target ID */ 2253 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2254 /* host ID */ 2255 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2256 /* period */ 2257 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2258 /* offset */ 2259 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2260 /* it's important for atn stop*/ 2261 /* 2262 * SCSI cammand 2263 */ 2264 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2265 /* to rls the /ACK signal */ 2266 } 2267 2268 static void 2269 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2270 { 2271 PSRB psrb; 2272 u_int8_t bval, bval1,status; 2273 union ccb *pccb; 2274 struct ccb_scsiio *pcsio; 2275 PSCSI_INQDATA ptr; 2276 int intflag; 2277 u_int target_id,target_lun; 2278 PDCB pTempDCB; 2279 2280 pccb = pSRB->pccb; 2281 if (pccb == NULL) 2282 return; 2283 pcsio = &pccb->csio; 2284 target_id = pSRB->pccb->ccb_h.target_id; 2285 target_lun = pSRB->pccb->ccb_h.target_lun; 2286 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2287 bus_dmasync_op_t op; 2288 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2289 op = BUS_DMASYNC_POSTREAD; 2290 else 2291 op = BUS_DMASYNC_POSTWRITE; 2292 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2293 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2294 } 2295 /* 2296 * 2297 * target status 2298 * 2299 */ 2300 status = pSRB->TargetStatus; 2301 pcsio->scsi_status=SCSI_STAT_GOOD; 2302 pccb->ccb_h.status = CAM_REQ_CMP; 2303 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2304 /* 2305 * status of auto request sense 2306 */ 2307 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2308 pSRB->AdaptStatus = 0; 2309 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2310 2311 if (status == SCSI_STATUS_CHECK_COND) { 2312 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2313 goto ckc_e; 2314 } 2315 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2316 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2317 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2318 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2319 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2320 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2321 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2322 pcsio->sense_len); 2323 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2324 | CAM_AUTOSNS_VALID; 2325 goto ckc_e; 2326 } 2327 /* 2328 * target status 2329 */ 2330 if (status) { 2331 if (status == SCSI_STATUS_CHECK_COND) { 2332 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2333 TRM_DPRINTF("trm_RequestSense..................\n"); 2334 trm_RequestSense(pACB, pDCB, pSRB); 2335 return; 2336 } 2337 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2338 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2339 goto ckc_e; 2340 } else if (status == SCSI_STAT_QUEUEFULL) { 2341 bval = (u_int8_t) pDCB->GoingSRBCnt; 2342 bval--; 2343 pDCB->MaxActiveCommandCnt = bval; 2344 trm_RewaitSRB(pDCB, pSRB); 2345 pSRB->AdaptStatus = 0; 2346 pSRB->TargetStatus = 0; 2347 return; 2348 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2349 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2350 pSRB->TargetStatus = 0; 2351 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2352 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2353 } else if (status == SCSI_STAT_BUSY) { 2354 TRM_DPRINTF("trm: target busy at %s %d\n", 2355 __FILE__, __LINE__); 2356 pcsio->scsi_status = SCSI_STAT_BUSY; 2357 pccb->ccb_h.status = CAM_SCSI_BUSY; 2358 return; 2359 /* The device busy, try again later? */ 2360 } else if (status == SCSI_STAT_RESCONFLICT) { 2361 TRM_DPRINTF("trm: target reserved at %s %d\n", 2362 __FILE__, __LINE__); 2363 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2364 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2365 return; 2366 } else { 2367 pSRB->AdaptStatus = 0; 2368 if (pSRB->RetryCnt) { 2369 pSRB->RetryCnt--; 2370 pSRB->TargetStatus = 0; 2371 pSRB->SRBSGIndex = 0; 2372 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2373 /* 2374 * If trm_StartSCSI return 1 : 2375 * current interrupt status is interrupt 2376 * disreenable 2377 * It's said that SCSI processor has more 2378 * one SRB need to do 2379 */ 2380 trm_RewaitSRB(pDCB, pSRB); 2381 } 2382 return; 2383 } else { 2384 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2385 __FILE__, __LINE__); 2386 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2387 } 2388 } 2389 } else { 2390 /* 2391 * process initiator status.......................... 2392 * Adapter (initiator) status 2393 */ 2394 status = pSRB->AdaptStatus; 2395 if (status & H_OVER_UNDER_RUN) { 2396 pSRB->TargetStatus = 0; 2397 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2398 /* Illegal length (over/under run) */ 2399 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2400 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2401 __FILE__, __LINE__); 2402 pDCB->tinfo.goal.period = 0; 2403 pDCB->tinfo.goal.offset = 0; 2404 /* Driver failed to perform operation */ 2405 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2406 } else { 2407 /* no error */ 2408 pSRB->AdaptStatus = 0; 2409 pSRB->TargetStatus = 0; 2410 pccb->ccb_h.status = CAM_REQ_CMP; 2411 /* there is no error, (sense is invalid) */ 2412 } 2413 } 2414 ckc_e: 2415 if (pACB->scan_devices[target_id][target_lun]) { 2416 /* 2417 * if SCSI command in "scan devices" duty 2418 */ 2419 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2420 pACB->scan_devices[target_id][target_lun] = 0; 2421 /* SCSI command phase :test unit ready */ 2422 else if (pSRB->CmdBlock[0] == INQUIRY) { 2423 /* 2424 * SCSI command phase :inquiry scsi device data 2425 * (type,capacity,manufacture.... 2426 */ 2427 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2428 goto NO_DEV; 2429 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2430 /* page fault */ 2431 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2432 ptr->DevType); 2433 bval1 = ptr->DevType & SCSI_DEVTYPE; 2434 if (bval1 == SCSI_NODEV) { 2435 NO_DEV: 2436 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2437 target_id, 2438 target_lun); 2439 intflag = splcam(); 2440 pACB->scan_devices[target_id][target_lun] = 0; 2441 /* no device set scan device flag =0*/ 2442 /* pDCB Q link */ 2443 /* move the head of DCB to tempDCB*/ 2444 pTempDCB=pACB->pLinkDCB; 2445 /* search current DCB for pass link */ 2446 while (pTempDCB->pNextDCB != pDCB) { 2447 pTempDCB = pTempDCB->pNextDCB; 2448 } 2449 /* 2450 * when the current DCB found than connect 2451 * current DCB tail 2452 */ 2453 /* to the DCB tail that before current DCB */ 2454 pTempDCB->pNextDCB = pDCB->pNextDCB; 2455 /* 2456 * if there was only one DCB ,connect his tail 2457 * to his head 2458 */ 2459 if (pACB->pLinkDCB == pDCB) 2460 pACB->pLinkDCB = pTempDCB->pNextDCB; 2461 if (pACB->pDCBRunRobin == pDCB) 2462 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2463 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2464 pACB->DeviceCnt--; 2465 if (pACB->DeviceCnt == 0) { 2466 pACB->pLinkDCB = NULL; 2467 pACB->pDCBRunRobin = NULL; 2468 } 2469 splx(intflag); 2470 } else { 2471 #ifdef trm_DEBUG1 2472 int j; 2473 for (j = 0; j < 28; j++) { 2474 TRM_DPRINTF("ptr=%2x ", 2475 ((u_int8_t *)ptr)[j]); 2476 } 2477 #endif 2478 pDCB->DevType = bval1; 2479 if (bval1 == SCSI_DASD || 2480 bval1 == SCSI_OPTICAL) { 2481 if ((((ptr->Vers & 0x07) >= 2) || 2482 ((ptr->RDF & 0x0F) == 2)) && 2483 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2484 (pDCB->DevMode & TAG_QUEUING_) && 2485 (pDCB->DevMode & EN_DISCONNECT_)) { 2486 if (pDCB->DevMode & 2487 TAG_QUEUING_) { 2488 pDCB-> 2489 MaxActiveCommandCnt = 2490 pACB->TagMaxNum; 2491 pDCB->SyncMode |= 2492 EN_TAG_QUEUING; 2493 pDCB->tinfo.disc_tag |= 2494 TRM_CUR_TAGENB; 2495 } else { 2496 pDCB->SyncMode |= 2497 EN_ATN_STOP; 2498 pDCB->tinfo.disc_tag &= 2499 ~TRM_CUR_TAGENB; 2500 } 2501 } 2502 } 2503 } 2504 /* pSRB->CmdBlock[0] == INQUIRY */ 2505 } 2506 /* pACB->scan_devices[target_id][target_lun] */ 2507 } 2508 intflag = splcam(); 2509 /* ReleaseSRB(pDCB, pSRB); */ 2510 if (pSRB == pDCB->pGoingSRB) 2511 pDCB->pGoingSRB = pSRB->pNextSRB; 2512 else { 2513 psrb = pDCB->pGoingSRB; 2514 while (psrb->pNextSRB != pSRB) { 2515 psrb = psrb->pNextSRB; 2516 } 2517 psrb->pNextSRB = pSRB->pNextSRB; 2518 if (pSRB == pDCB->pGoingLastSRB) { 2519 pDCB->pGoingLastSRB = psrb; 2520 } 2521 } 2522 pSRB->pNextSRB = pACB->pFreeSRB; 2523 pACB->pFreeSRB = pSRB; 2524 pDCB->GoingSRBCnt--; 2525 trm_DoWaitingSRB(pACB); 2526 2527 splx(intflag); 2528 /* Notify cmd done */ 2529 xpt_done (pccb); 2530 } 2531 2532 static void 2533 trm_DoingSRB_Done(PACB pACB) 2534 { 2535 PDCB pDCB, pdcb; 2536 PSRB psrb, psrb2; 2537 u_int16_t cnt, i; 2538 union ccb *pccb; 2539 2540 pDCB = pACB->pLinkDCB; 2541 if (pDCB == NULL) 2542 return; 2543 pdcb = pDCB; 2544 do { 2545 cnt = pdcb->GoingSRBCnt; 2546 psrb = pdcb->pGoingSRB; 2547 for (i = 0; i < cnt; i++) { 2548 psrb2 = psrb->pNextSRB; 2549 pccb = psrb->pccb; 2550 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2551 /* ReleaseSRB(pDCB, pSRB); */ 2552 psrb->pNextSRB = pACB->pFreeSRB; 2553 pACB->pFreeSRB = psrb; 2554 xpt_done(pccb); 2555 psrb = psrb2; 2556 } 2557 pdcb->GoingSRBCnt = 0; 2558 pdcb->pGoingSRB = NULL; 2559 pdcb = pdcb->pNextDCB; 2560 } 2561 while (pdcb != pDCB); 2562 } 2563 2564 static void 2565 trm_ResetSCSIBus(PACB pACB) 2566 { 2567 int intflag; 2568 2569 intflag = splcam(); 2570 pACB->ACBFlag |= RESET_DEV; 2571 2572 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2573 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2574 splx(intflag); 2575 return; 2576 } 2577 2578 static void 2579 trm_ScsiRstDetect(PACB pACB) 2580 { 2581 int intflag; 2582 u_long wlval; 2583 2584 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2585 wlval = 1000; 2586 while (--wlval) 2587 DELAY(1000); 2588 intflag = splcam(); 2589 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2590 2591 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2592 2593 if (pACB->ACBFlag & RESET_DEV) 2594 pACB->ACBFlag |= RESET_DONE; 2595 else { 2596 pACB->ACBFlag |= RESET_DETECT; 2597 trm_ResetDevParam(pACB); 2598 /* trm_DoingSRB_Done(pACB); ???? */ 2599 trm_RecoverSRB(pACB); 2600 pACB->pActiveDCB = NULL; 2601 pACB->ACBFlag = 0; 2602 trm_DoWaitingSRB(pACB); 2603 } 2604 splx(intflag); 2605 return; 2606 } 2607 2608 static void 2609 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2610 { 2611 union ccb *pccb; 2612 struct ccb_scsiio *pcsio; 2613 2614 pccb = pSRB->pccb; 2615 pcsio = &pccb->csio; 2616 2617 pSRB->SRBFlag |= AUTO_REQSENSE; 2618 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2619 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2620 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2621 pSRB->SRBSGCount); 2622 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2623 2624 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2625 pSRB->AdaptStatus = 0; 2626 pSRB->TargetStatus = 0; 2627 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2628 2629 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2630 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2631 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2632 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2633 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2634 pSRB->SRBSGCount = 1; 2635 pSRB->SRBSGIndex = 0; 2636 2637 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2638 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2639 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2640 pSRB->ScsiCmdLen = 6; 2641 2642 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2643 /* 2644 * If trm_StartSCSI return 1 : 2645 * current interrupt status is interrupt disreenable 2646 * It's said that SCSI processor has more one SRB need to do 2647 */ 2648 trm_RewaitSRB(pDCB, pSRB); 2649 } 2650 2651 static void 2652 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2653 { 2654 2655 pSRB->MsgCnt = 1; 2656 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2657 } 2658 2659 static void 2660 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2661 { 2662 2663 pSRB->MsgOutBuf[0] = MSG_ABORT; 2664 trm_EnableMsgOutAbort2(pACB, pSRB); 2665 } 2666 2667 static void 2668 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2669 { 2670 PNVRAMTYPE pEEpromBuf; 2671 u_int8_t bval,PeriodIndex; 2672 u_int target_id,target_lun; 2673 PDCB pTempDCB; 2674 int intflag; 2675 2676 target_id = i; 2677 target_lun = j; 2678 2679 /* 2680 * Using the lun 0 device to init other DCB first, if the device 2681 * has been initialized. 2682 * I don't want init sync arguments one by one, it is the same. 2683 */ 2684 if (target_lun != 0 && 2685 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2686 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2687 sizeof(TRM_DCB)); 2688 intflag = splcam(); 2689 if (pACB->pLinkDCB == 0) { 2690 pACB->pLinkDCB = pDCB; 2691 /* 2692 * RunRobin impersonate the role 2693 * that let each device had good proportion 2694 * about SCSI command proceeding 2695 */ 2696 pACB->pDCBRunRobin = pDCB; 2697 pDCB->pNextDCB = pDCB; 2698 } else { 2699 pTempDCB=pACB->pLinkDCB; 2700 /* search the last nod of DCB link */ 2701 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2702 pTempDCB = pTempDCB->pNextDCB; 2703 /* connect current DCB with last DCB tail */ 2704 pTempDCB->pNextDCB = pDCB; 2705 /* connect current DCB tail to this DCB Q head */ 2706 pDCB->pNextDCB=pACB->pLinkDCB; 2707 } 2708 splx(intflag); 2709 2710 pACB->DeviceCnt++; 2711 pDCB->TargetID = target_id; 2712 pDCB->TargetLUN = target_lun; 2713 pDCB->pWaitingSRB = NULL; 2714 pDCB->pGoingSRB = NULL; 2715 pDCB->GoingSRBCnt = 0; 2716 pDCB->pActiveSRB = NULL; 2717 pDCB->MaxActiveCommandCnt = 1; 2718 pDCB->DCBFlag = 0; 2719 pDCB->DCBstatus |= DS_IN_QUEUE; 2720 /* $$$$$$$ */ 2721 pEEpromBuf = &trm_eepromBuf[unit]; 2722 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2723 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2724 /* $$$$$$$ */ 2725 /* 2726 * disconnect enable ? 2727 */ 2728 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2729 bval = 0xC0; 2730 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2731 } else { 2732 bval = 0x80; 2733 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2734 } 2735 bval |= target_lun; 2736 pDCB->IdentifyMsg = bval; 2737 if (target_lun != 0 && 2738 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2739 return; 2740 /* $$$$$$$ */ 2741 /* 2742 * tag Qing enable ? 2743 */ 2744 if (pDCB->DevMode & TAG_QUEUING_) { 2745 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2746 } else 2747 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2748 /* $$$$$$$ */ 2749 /* 2750 * wide nego ,sync nego enable ? 2751 */ 2752 pDCB->SyncPeriod = 0; 2753 pDCB->SyncOffset = 0; 2754 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2755 if (pACB->AdaptType==1) {/* is U2? */ 2756 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2757 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2758 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2759 } else { 2760 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2761 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2762 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2763 } 2764 pDCB->SyncMode = 0; 2765 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2766 (pACB->Config & HCC_WIDE_CARD)) 2767 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2768 /* enable wide nego */ 2769 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2770 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2771 /* enable sync nego */ 2772 /* $$$$$$$ */ 2773 /* 2774 * Fill in tinfo structure. 2775 */ 2776 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2777 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2778 2779 pDCB->tinfo.current.period = 0; 2780 pDCB->tinfo.current.offset = 0; 2781 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2782 } 2783 2784 static void 2785 trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2786 { 2787 PSRB pSRB; 2788 2789 pSRB=(PSRB) arg; 2790 pSRB->SRBSGPhyAddr=segs->ds_addr; 2791 return; 2792 } 2793 2794 static void 2795 trm_destroySRB(PACB pACB) 2796 { 2797 PSRB pSRB; 2798 2799 pSRB = pACB->pFreeSRB; 2800 while (pSRB) { 2801 if (pSRB->SRBSGPhyAddr) 2802 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap); 2803 if (pSRB->pSRBSGL) 2804 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL, 2805 pSRB->sg_dmamap); 2806 if (pSRB->dmamap) 2807 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap); 2808 pSRB = pSRB->pNextSRB; 2809 } 2810 } 2811 2812 static int 2813 trm_initSRB(PACB pACB) 2814 { 2815 u_int16_t i; 2816 PSRB pSRB; 2817 int error; 2818 2819 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2820 pSRB = (PSRB)&pACB->pFreeSRB[i]; 2821 2822 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL, 2823 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 2824 return ENXIO; 2825 } 2826 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 2827 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 2828 trm_srbmapSG, pSRB, /*flags*/0); 2829 if (i != TRM_MAX_SRB_CNT - 1) { 2830 /* 2831 * link all SRB 2832 */ 2833 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 2834 } else { 2835 /* 2836 * load NULL to NextSRB of the last SRB 2837 */ 2838 pSRB->pNextSRB = NULL; 2839 } 2840 pSRB->TagNumber = i; 2841 2842 /* 2843 * Create the dmamap. This is no longer optional! 2844 */ 2845 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0, 2846 &pSRB->dmamap)) != 0) 2847 return (error); 2848 2849 } 2850 return (0); 2851 } 2852 2853 2854 2855 2856 static void 2857 trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 2858 { 2859 PNVRAMTYPE pEEpromBuf; 2860 2861 pEEpromBuf = &trm_eepromBuf[unit]; 2862 pACB->max_id = 15; 2863 2864 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 2865 pACB->max_lun = 7; 2866 else 2867 pACB->max_lun = 0; 2868 2869 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 2870 pACB->max_id, pACB->max_lun); 2871 pACB->pLinkDCB = NULL; 2872 pACB->pDCBRunRobin = NULL; 2873 pACB->pActiveDCB = NULL; 2874 pACB->AdapterUnit = (u_int8_t)unit; 2875 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 2876 pACB->AdaptSCSILUN = 0; 2877 pACB->DeviceCnt = 0; 2878 pACB->AdaptType = adaptType; 2879 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 2880 pACB->ACBFlag = 0; 2881 return; 2882 } 2883 2884 static void 2885 NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 2886 { 2887 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 2888 u_int8_t bAddr; 2889 2890 /* Enable SEEPROM */ 2891 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 2892 TRMREG_GEN_CONTROL); 2893 /* 2894 * Write enable 2895 */ 2896 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 2897 trm_reg_write8(0, TRMREG_GEN_NVRAM); 2898 NVRAM_trm_wait_30us(pACB); 2899 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 2900 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 2901 } 2902 /* 2903 * Write disable 2904 */ 2905 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 2906 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 2907 NVRAM_trm_wait_30us(pACB); 2908 /* Disable SEEPROM */ 2909 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 2910 TRMREG_GEN_CONTROL); 2911 return; 2912 } 2913 2914 static void 2915 NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 2916 { 2917 int i; 2918 u_int8_t bSendData; 2919 /* 2920 * Send write command & address 2921 */ 2922 2923 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 2924 /* 2925 * Write data 2926 */ 2927 for (i = 0; i < 8; i++, bData <<= 1) { 2928 bSendData = NVR_SELECT; 2929 if (bData & 0x80) 2930 /* Start from bit 7 */ 2931 bSendData |= NVR_BITOUT; 2932 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 2933 NVRAM_trm_wait_30us(pACB); 2934 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 2935 NVRAM_trm_wait_30us(pACB); 2936 } 2937 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 2938 NVRAM_trm_wait_30us(pACB); 2939 /* 2940 * Disable chip select 2941 */ 2942 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 2943 NVRAM_trm_wait_30us(pACB); 2944 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 2945 NVRAM_trm_wait_30us(pACB); 2946 /* 2947 * Wait for write ready 2948 */ 2949 while (1) { 2950 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 2951 NVRAM_trm_wait_30us(pACB); 2952 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 2953 NVRAM_trm_wait_30us(pACB); 2954 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 2955 break; 2956 } 2957 } 2958 /* 2959 * Disable chip select 2960 */ 2961 trm_reg_write8(0, TRMREG_GEN_NVRAM); 2962 return; 2963 } 2964 2965 static void 2966 NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 2967 { 2968 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 2969 u_int8_t bAddr; 2970 2971 /* 2972 * Enable SEEPROM 2973 */ 2974 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 2975 TRMREG_GEN_CONTROL); 2976 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2977 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 2978 /* 2979 * Disable SEEPROM 2980 */ 2981 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 2982 TRMREG_GEN_CONTROL); 2983 return; 2984 } 2985 2986 static u_int8_t 2987 NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 2988 { 2989 int i; 2990 u_int8_t bReadData, bData = 0; 2991 /* 2992 * Send read command & address 2993 */ 2994 2995 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 2996 2997 for (i = 0; i < 8; i++) { 2998 /* 2999 * Read data 3000 */ 3001 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3002 NVRAM_trm_wait_30us(pACB); 3003 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3004 /* 3005 * Get data bit while falling edge 3006 */ 3007 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3008 bData <<= 1; 3009 if (bReadData & NVR_BITIN) { 3010 bData |= 1; 3011 } 3012 NVRAM_trm_wait_30us(pACB); 3013 } 3014 /* 3015 * Disable chip select 3016 */ 3017 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3018 return (bData); 3019 } 3020 3021 static void 3022 NVRAM_trm_wait_30us(PACB pACB) 3023 { 3024 3025 /* ScsiPortStallExecution(30); wait 30 us */ 3026 trm_reg_write8(5, TRMREG_GEN_TIMER); 3027 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3028 return; 3029 } 3030 3031 static void 3032 NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3033 { 3034 int i; 3035 u_int8_t bSendData; 3036 3037 for (i = 0; i < 3; i++, bCmd <<= 1) { 3038 /* 3039 * Program SB+OP code 3040 */ 3041 bSendData = NVR_SELECT; 3042 if (bCmd & 0x04) 3043 bSendData |= NVR_BITOUT; 3044 /* start from bit 2 */ 3045 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3046 NVRAM_trm_wait_30us(pACB); 3047 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3048 NVRAM_trm_wait_30us(pACB); 3049 } 3050 for (i = 0; i < 7; i++, bAddr <<= 1) { 3051 /* 3052 * Program address 3053 */ 3054 bSendData = NVR_SELECT; 3055 if (bAddr & 0x40) 3056 /* Start from bit 6 */ 3057 bSendData |= NVR_BITOUT; 3058 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3059 NVRAM_trm_wait_30us(pACB); 3060 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3061 NVRAM_trm_wait_30us(pACB); 3062 } 3063 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3064 NVRAM_trm_wait_30us(pACB); 3065 } 3066 3067 static void 3068 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3069 { 3070 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3071 u_int16_t wAddr, wCheckSum; 3072 u_long dAddr, *dpEeprom; 3073 3074 NVRAM_trm_read_all(pEEpromBuf,pACB); 3075 wCheckSum = 0; 3076 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3077 wAddr < 64; wAddr++, wpEeprom++) { 3078 wCheckSum += *wpEeprom; 3079 } 3080 if (wCheckSum != 0x1234) { 3081 /* 3082 * Checksum error, load default 3083 */ 3084 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3085 pEEpromBuf->NvramSubVendorID[1] = 3086 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3087 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3088 pEEpromBuf->NvramSubSysID[1] = 3089 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3090 pEEpromBuf->NvramSubClass = 0x00; 3091 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3092 pEEpromBuf->NvramVendorID[1] = 3093 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3094 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3095 pEEpromBuf->NvramDeviceID[1] = 3096 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3097 pEEpromBuf->NvramReserved = 0x00; 3098 3099 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3100 dAddr < 16; dAddr++, dpEeprom++) { 3101 *dpEeprom = 0x00000077; 3102 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3103 } 3104 3105 *dpEeprom++ = 0x04000F07; 3106 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3107 *dpEeprom++ = 0x00000015; 3108 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3109 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3110 *dpEeprom = 0x00; 3111 pEEpromBuf->NvramCheckSum = 0x00; 3112 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3113 wAddr < 63; wAddr++, wpEeprom++) 3114 wCheckSum += *wpEeprom; 3115 *wpEeprom = 0x1234 - wCheckSum; 3116 NVRAM_trm_write_all(pEEpromBuf,pACB); 3117 } 3118 return; 3119 } 3120 static int 3121 trm_initAdapter(PACB pACB, u_int16_t unit) 3122 { 3123 PNVRAMTYPE pEEpromBuf; 3124 u_int16_t wval; 3125 u_int8_t bval; 3126 3127 pEEpromBuf = &trm_eepromBuf[unit]; 3128 3129 /* 250ms selection timeout */ 3130 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3131 /* Mask all the interrupt */ 3132 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3133 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3134 /* Reset SCSI module */ 3135 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3136 /* program configuration 0 */ 3137 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3138 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3139 pACB->Config |= HCC_WIDE_CARD; 3140 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3141 pACB->Config |= HCC_SCSI_RESET; 3142 if (pACB->Config & HCC_PARITY) 3143 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3144 else 3145 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3146 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3147 /* program configuration 1 */ 3148 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3149 /* program Host ID */ 3150 bval = pEEpromBuf->NvramScsiId; 3151 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3152 /* set ansynchronous transfer */ 3153 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3154 /* Trun LED control off*/ 3155 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3156 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3157 /* DMA config */ 3158 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3159 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3160 /* Clear pending interrupt status */ 3161 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3162 /* Enable SCSI interrupt */ 3163 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3164 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3165 return (0); 3166 } 3167 3168 static void 3169 trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3170 { 3171 PACB pACB; 3172 3173 pACB = (PACB)arg; 3174 pACB->srb_physbase = segs->ds_addr; 3175 } 3176 3177 static void 3178 trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3179 { 3180 bus_addr_t *baddr; 3181 3182 baddr = (bus_addr_t *)arg; 3183 *baddr = segs->ds_addr; 3184 } 3185 3186 static PACB 3187 trm_init(u_int16_t unit, device_t dev) 3188 { 3189 PACB pACB; 3190 int rid = PCIR_BAR(0), i = 0, j = 0; 3191 u_int16_t adaptType = 0; 3192 3193 pACB = (PACB) device_get_softc(dev); 3194 if (!pACB) { 3195 printf("trm%d: cannot allocate ACB !\n", unit); 3196 return (NULL); 3197 } 3198 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 3199 &rid, RF_ACTIVE); 3200 if (pACB->iores == NULL) { 3201 printf("trm_init: bus_alloc_resource failed!\n"); 3202 return (NULL); 3203 } 3204 switch (pci_get_devid(dev)) { 3205 case PCI_DEVICEID_TRMS1040: 3206 adaptType = 0; 3207 break; 3208 case PCI_DEVICEID_TRMS2080: 3209 adaptType = 1; 3210 break; 3211 default: 3212 printf("trm_init %d: unknown adapter type!\n", unit); 3213 goto bad; 3214 } 3215 pACB->dev = dev; 3216 pACB->tag = rman_get_bustag(pACB->iores); 3217 pACB->bsh = rman_get_bushandle(pACB->iores); 3218 if (bus_dma_tag_create( 3219 /*parent_dmat*/ bus_get_dma_tag(dev), 3220 /*alignment*/ 1, 3221 /*boundary*/ 0, 3222 /*lowaddr*/ BUS_SPACE_MAXADDR, 3223 /*highaddr*/ BUS_SPACE_MAXADDR, 3224 /*filter*/ NULL, 3225 /*filterarg*/ NULL, 3226 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 3227 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 3228 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3229 /*flags*/ 0, 3230 /*lockfunc*/ NULL, 3231 /*lockarg*/ NULL, 3232 /* dmat */ &pACB->parent_dmat) != 0) 3233 goto bad; 3234 if (bus_dma_tag_create( 3235 /*parent_dmat*/ pACB->parent_dmat, 3236 /*alignment*/ 1, 3237 /*boundary*/ 0, 3238 /*lowaddr*/ BUS_SPACE_MAXADDR, 3239 /*highaddr*/ BUS_SPACE_MAXADDR, 3240 /*filter*/ NULL, 3241 /*filterarg*/ NULL, 3242 /*maxsize*/ TRM_MAXPHYS, 3243 /*nsegments*/ TRM_NSEG, 3244 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3245 /*flags*/ BUS_DMA_ALLOCNOW, 3246 /*lockfunc*/ busdma_lock_mutex, 3247 /*lockarg*/ &Giant, 3248 /* dmat */ &pACB->buffer_dmat) != 0) 3249 goto bad; 3250 /* DMA tag for our ccb structures */ 3251 if (bus_dma_tag_create( 3252 /*parent_dmat*/pACB->parent_dmat, 3253 /*alignment*/ 1, 3254 /*boundary*/ 0, 3255 /*lowaddr*/ BUS_SPACE_MAXADDR, 3256 /*highaddr*/ BUS_SPACE_MAXADDR, 3257 /*filter*/ NULL, 3258 /*filterarg*/ NULL, 3259 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3260 /*nsegments*/ 1, 3261 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3262 /*flags*/ 0, 3263 /*lockfunc*/ busdma_lock_mutex, 3264 /*lockarg*/ &Giant, 3265 /*dmat*/ &pACB->srb_dmat) != 0) { 3266 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3267 goto bad; 3268 } 3269 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3270 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3271 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3272 goto bad; 3273 } 3274 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3275 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3276 /* flags */0); 3277 /* Create, allocate, and map DMA buffers for autosense data */ 3278 if (bus_dma_tag_create( 3279 /*parent_dmat*/pACB->parent_dmat, 3280 /*alignment*/1, 3281 /*boundary*/0, 3282 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3283 /*highaddr*/BUS_SPACE_MAXADDR, 3284 /*filter*/NULL, /*filterarg*/NULL, 3285 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3286 /*nsegments*/1, 3287 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3288 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 3289 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) { 3290 if (bootverbose) 3291 device_printf(dev, "cannot create sense buffer dmat\n"); 3292 goto bad; 3293 } 3294 3295 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3296 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3297 goto bad; 3298 3299 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3300 pACB->sense_buffers, 3301 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3302 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3303 3304 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3305 trm_initACB(pACB, adaptType, unit); 3306 for (i = 0; i < (pACB->max_id + 1); i++) { 3307 if (pACB->AdaptSCSIID == i) 3308 continue; 3309 for(j = 0; j < (pACB->max_lun + 1); j++) { 3310 pACB->scan_devices[i][j] = 1; 3311 /* we assume we need to scan all devices */ 3312 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3313 } 3314 } 3315 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3316 if (bus_dma_tag_create( 3317 /*parent_dmat*/pACB->parent_dmat, 3318 /*alignment*/ 1, 3319 /*boundary*/ 0, 3320 /*lowaddr*/ BUS_SPACE_MAXADDR, 3321 /*highaddr*/ BUS_SPACE_MAXADDR, 3322 /*filter*/ NULL, 3323 /*filterarg*/ NULL, 3324 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3325 /*nsegments*/ 1, 3326 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3327 /*flags*/ 0, 3328 /*lockfunc*/ busdma_lock_mutex, 3329 /*lockarg*/ &Giant, 3330 /*dmat*/ &pACB->sg_dmat) != 0) 3331 goto bad; 3332 3333 if (trm_initSRB(pACB)) { 3334 printf("trm_initSRB: error\n"); 3335 goto bad; 3336 } 3337 if (trm_initAdapter(pACB, unit)) { 3338 printf("trm_initAdapter: initial ERROR\n"); 3339 goto bad; 3340 } 3341 return (pACB); 3342 bad: 3343 if (pACB->iores) 3344 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3345 pACB->iores); 3346 if (pACB->sense_dmamap) { 3347 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3348 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3349 pACB->sense_dmamap); 3350 } 3351 if (pACB->sense_dmat) 3352 bus_dma_tag_destroy(pACB->sense_dmat); 3353 if (pACB->sg_dmat) { 3354 trm_destroySRB(pACB); 3355 bus_dma_tag_destroy(pACB->sg_dmat); 3356 } 3357 if (pACB->pFreeSRB) { 3358 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3359 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3360 pACB->srb_dmamap); 3361 } 3362 if (pACB->srb_dmat) 3363 bus_dma_tag_destroy(pACB->srb_dmat); 3364 if (pACB->buffer_dmat) 3365 bus_dma_tag_destroy(pACB->buffer_dmat); 3366 if (pACB->parent_dmat) 3367 bus_dma_tag_destroy(pACB->parent_dmat); 3368 return (NULL); 3369 } 3370 3371 static int 3372 trm_attach(device_t dev) 3373 { 3374 struct cam_devq *device_Q; 3375 u_long device_id; 3376 PACB pACB = 0; 3377 int rid = 0; 3378 int unit = device_get_unit(dev); 3379 3380 device_id = pci_get_devid(dev); 3381 /* 3382 * These cards do not allow memory mapped accesses 3383 */ 3384 if ((pACB = trm_init((u_int16_t) unit, 3385 dev)) == NULL) { 3386 printf("trm%d: trm_init error!\n",unit); 3387 return (ENXIO); 3388 } 3389 /* After setting up the adapter, map our interrupt */ 3390 /* 3391 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3392 * start queue to reset to the idle loop. 3393 * Create device queue of SIM(s) 3394 * (MAX_START_JOB - 1) : max_sim_transactions 3395 */ 3396 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3397 RF_SHAREABLE | RF_ACTIVE); 3398 if (pACB->irq == NULL || 3399 bus_setup_intr(dev, pACB->irq, 3400 INTR_TYPE_CAM, NULL, trm_Interrupt, pACB, &pACB->ih)) { 3401 printf("trm%d: register Interrupt handler error!\n", unit); 3402 goto bad; 3403 } 3404 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3405 if (device_Q == NULL){ 3406 printf("trm%d: device_Q == NULL !\n",unit); 3407 goto bad; 3408 } 3409 /* 3410 * Now tell the generic SCSI layer 3411 * about our bus. 3412 * If this is the xpt layer creating a sim, then it's OK 3413 * to wait for an allocation. 3414 * XXX Should we pass in a flag to indicate that wait is OK? 3415 * 3416 * SIM allocation 3417 * 3418 * SCSI Interface Modules 3419 * The sim driver creates a sim for each controller. The sim device 3420 * queue is separately created in order to allow resource sharing betwee 3421 * sims. For instance, a driver may create one sim for each channel of 3422 * a multi-channel controller and use the same queue for each channel. 3423 * In this way, the queue resources are shared across all the channels 3424 * of the multi-channel controller. 3425 * trm_action : sim_action_func 3426 * trm_poll : sim_poll_func 3427 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3428 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3429 * pACB->unit : unit 3430 * 1 : max_dev_transactions 3431 * MAX_TAGS : max_tagged_dev_transactions 3432 * 3433 * *******Construct our first channel SIM entry 3434 */ 3435 pACB->psim = cam_sim_alloc(trm_action, 3436 trm_poll, 3437 "trm", 3438 pACB, 3439 unit, 3440 &Giant, 3441 1, 3442 TRM_MAX_TAGS_CMD_QUEUE, 3443 device_Q); 3444 if (pACB->psim == NULL) { 3445 printf("trm%d: SIM allocate fault !\n",unit); 3446 cam_simq_free(device_Q); /* SIM allocate fault*/ 3447 goto bad; 3448 } 3449 if (xpt_bus_register(pACB->psim, dev, 0) != CAM_SUCCESS) { 3450 printf("trm%d: xpt_bus_register fault !\n",unit); 3451 goto bad; 3452 } 3453 if (xpt_create_path(&pACB->ppath, 3454 NULL, 3455 cam_sim_path(pACB->psim), 3456 CAM_TARGET_WILDCARD, 3457 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3458 printf("trm%d: xpt_create_path fault !\n",unit); 3459 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3460 goto bad; 3461 } 3462 return (0); 3463 bad: 3464 if (pACB->iores) 3465 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3466 pACB->iores); 3467 if (pACB->sg_dmat) { 3468 trm_destroySRB(pACB); 3469 bus_dma_tag_destroy(pACB->sg_dmat); 3470 } 3471 3472 if (pACB->pFreeSRB) { 3473 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3474 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3475 pACB->srb_dmamap); 3476 } 3477 if (pACB->srb_dmat) 3478 bus_dma_tag_destroy(pACB->srb_dmat); 3479 if (pACB->sense_buffers) { 3480 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3481 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3482 pACB->sense_dmamap); 3483 } 3484 if (pACB->sense_dmat) 3485 bus_dma_tag_destroy(pACB->sense_dmat); 3486 if (pACB->buffer_dmat) 3487 bus_dma_tag_destroy(pACB->buffer_dmat); 3488 if (pACB->ih) 3489 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3490 if (pACB->irq) 3491 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3492 if (pACB->psim) 3493 cam_sim_free(pACB->psim, TRUE); 3494 3495 return (ENXIO); 3496 3497 } 3498 3499 /* 3500 * pci_device 3501 * trm_probe (device_t tag, pcidi_t type) 3502 * 3503 */ 3504 static int 3505 trm_probe(device_t dev) 3506 { 3507 switch (pci_get_devid(dev)) { 3508 case PCI_DEVICEID_TRMS1040: 3509 device_set_desc(dev, 3510 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3511 return (BUS_PROBE_DEFAULT); 3512 case PCI_DEVICEID_TRMS2080: 3513 device_set_desc(dev, 3514 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3515 return (BUS_PROBE_DEFAULT); 3516 default: 3517 return (ENXIO); 3518 } 3519 } 3520 3521 static int 3522 trm_detach(device_t dev) 3523 { 3524 PACB pACB = device_get_softc(dev); 3525 3526 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores); 3527 trm_destroySRB(pACB); 3528 bus_dma_tag_destroy(pACB->sg_dmat); 3529 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3530 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3531 pACB->srb_dmamap); 3532 bus_dma_tag_destroy(pACB->srb_dmat); 3533 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3534 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3535 pACB->sense_dmamap); 3536 bus_dma_tag_destroy(pACB->sense_dmat); 3537 bus_dma_tag_destroy(pACB->buffer_dmat); 3538 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3539 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3540 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3541 xpt_free_path(pACB->ppath); 3542 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3543 cam_sim_free(pACB->psim, TRUE); 3544 return (0); 3545 } 3546 static device_method_t trm_methods[] = { 3547 /* Device interface */ 3548 DEVMETHOD(device_probe, trm_probe), 3549 DEVMETHOD(device_attach, trm_attach), 3550 DEVMETHOD(device_detach, trm_detach), 3551 { 0, 0 } 3552 }; 3553 3554 static driver_t trm_driver = { 3555 "trm", trm_methods, sizeof(struct _ACB) 3556 }; 3557 3558 static devclass_t trm_devclass; 3559 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3560 MODULE_DEPEND(trm, pci, 1, 1, 1); 3561 MODULE_DEPEND(trm, cam, 1, 1, 1); 3562