1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1996 Gardner Buchanan <[email protected]> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Gardner Buchanan. 18 * 4. The name of Gardner Buchanan may not be used to endorse or promote 19 * products derived from this software without specific prior written 20 * permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * This is a driver for SMC's 9000 series of Ethernet adapters. 39 * 40 * This FreeBSD driver is derived from the smc9194 Linux driver by 41 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 42 * This driver also shamelessly borrows from the FreeBSD ep driver 43 * which is Copyright (C) 1994 Herb Peyerl <[email protected]> 44 * All rights reserved. 45 * 46 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 47 * PC. It is adapted from Erik Stahlman's Linux driver which worked 48 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 49 * it will work for the entire SMC 9xxx series. (Ha Ha) 50 * 51 * "Features" of the SMC chip: 52 * 4608 byte packet memory. (for the 91C92. Others have more) 53 * EEPROM for configuration 54 * AUI/TP selection 55 * 56 * Authors: 57 * Erik Stahlman [email protected] 58 * Herb Peyerl [email protected] 59 * Andres Vega Garcia [email protected] 60 * Serge Babkin [email protected] 61 * Gardner Buchanan [email protected] 62 * 63 * Sources: 64 * o SMC databook 65 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman ([email protected])" 66 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 67 * 68 * Known Bugs: 69 * o Setting of the hardware address isn't supported. 70 * o Hardware padding isn't used. 71 */ 72 73 /* 74 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 75 * 76 * Copyright (c) 1996 by Tatsumi Hosokawa <[email protected]> 77 * BSD-nomads, Tokyo, Japan. 78 */ 79 /* 80 * Multicast support by Kei TANAKA <[email protected]> 81 * Special thanks to [email protected] 82 */ 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/errno.h> 87 #include <sys/kernel.h> 88 #include <sys/sockio.h> 89 #include <sys/malloc.h> 90 #include <sys/mbuf.h> 91 #include <sys/socket.h> 92 #include <sys/syslog.h> 93 94 #include <sys/module.h> 95 #include <sys/bus.h> 96 97 #include <machine/bus.h> 98 #include <machine/resource.h> 99 #include <sys/rman.h> 100 101 #include <net/ethernet.h> 102 #include <net/if.h> 103 #include <net/if_var.h> 104 #include <net/if_arp.h> 105 #include <net/if_dl.h> 106 #include <net/if_types.h> 107 #include <net/if_mib.h> 108 109 #ifdef INET 110 #include <netinet/in.h> 111 #include <netinet/in_systm.h> 112 #include <netinet/in_var.h> 113 #include <netinet/ip.h> 114 #endif 115 116 #include <net/bpf.h> 117 #include <net/bpfdesc.h> 118 119 #include <dev/sn/if_snreg.h> 120 #include <dev/sn/if_snvar.h> 121 122 /* Exported variables */ 123 devclass_t sn_devclass; 124 125 static int snioctl(struct ifnet * ifp, u_long, caddr_t); 126 127 static void snresume(struct ifnet *); 128 129 static void snintr_locked(struct sn_softc *); 130 static void sninit_locked(void *); 131 static void snstart_locked(struct ifnet *); 132 133 static void sninit(void *); 134 static void snread(struct ifnet *); 135 static void snstart(struct ifnet *); 136 static void snstop(struct sn_softc *); 137 static void snwatchdog(void *); 138 139 static void sn_setmcast(struct sn_softc *); 140 static int sn_getmcf(struct ifnet *ifp, u_char *mcf); 141 142 /* I (GB) have been unlucky getting the hardware padding 143 * to work properly. 144 */ 145 #define SW_PAD 146 147 static const char *chip_ids[15] = { 148 NULL, NULL, NULL, 149 /* 3 */ "SMC91C90/91C92", 150 /* 4 */ "SMC91C94/91C96", 151 /* 5 */ "SMC91C95", 152 NULL, 153 /* 7 */ "SMC91C100", 154 /* 8 */ "SMC91C100FD", 155 /* 9 */ "SMC91C110", 156 NULL, NULL, 157 NULL, NULL, NULL 158 }; 159 160 int 161 sn_attach(device_t dev) 162 { 163 struct sn_softc *sc = device_get_softc(dev); 164 struct ifnet *ifp; 165 uint16_t i; 166 uint8_t *p; 167 int rev; 168 uint16_t address; 169 int err; 170 u_char eaddr[6]; 171 172 ifp = sc->ifp = if_alloc(IFT_ETHER); 173 if (ifp == NULL) { 174 device_printf(dev, "can not if_alloc()\n"); 175 return (ENOSPC); 176 } 177 178 SN_LOCK_INIT(sc); 179 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0); 180 snstop(sc); 181 sc->pages_wanted = -1; 182 183 if (bootverbose || 1) { 184 SMC_SELECT_BANK(sc, 3); 185 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf; 186 if (chip_ids[rev]) 187 device_printf(dev, " %s ", chip_ids[rev]); 188 else 189 device_printf(dev, " unsupported chip: rev %d ", rev); 190 SMC_SELECT_BANK(sc, 1); 191 i = CSR_READ_2(sc, CONFIG_REG_W); 192 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP"); 193 } 194 195 /* 196 * Read the station address from the chip. The MAC address is bank 1, 197 * regs 4 - 9 198 */ 199 SMC_SELECT_BANK(sc, 1); 200 p = (uint8_t *) eaddr; 201 for (i = 0; i < 6; i += 2) { 202 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i); 203 p[i + 1] = address >> 8; 204 p[i] = address & 0xFF; 205 } 206 ifp->if_softc = sc; 207 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 208 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 209 ifp->if_start = snstart; 210 ifp->if_ioctl = snioctl; 211 ifp->if_init = sninit; 212 ifp->if_baudrate = 10000000; 213 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 214 ifp->if_snd.ifq_maxlen = ifqmaxlen; 215 IFQ_SET_READY(&ifp->if_snd); 216 217 ether_ifattach(ifp, eaddr); 218 219 /* 220 * Activate the interrupt so we can get card interrupts. This 221 * needs to be done last so that we don't have/hold the lock 222 * during startup to avoid LORs in the network layer. 223 */ 224 if ((err = bus_setup_intr(dev, sc->irq_res, 225 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc, 226 &sc->intrhand)) != 0) { 227 sn_detach(dev); 228 return err; 229 } 230 return 0; 231 } 232 233 234 int 235 sn_detach(device_t dev) 236 { 237 struct sn_softc *sc = device_get_softc(dev); 238 struct ifnet *ifp = sc->ifp; 239 240 ether_ifdetach(ifp); 241 SN_LOCK(sc); 242 snstop(sc); 243 SN_UNLOCK(sc); 244 callout_drain(&sc->watchdog); 245 sn_deactivate(dev); 246 if_free(ifp); 247 SN_LOCK_DESTROY(sc); 248 return 0; 249 } 250 251 static void 252 sninit(void *xsc) 253 { 254 struct sn_softc *sc = xsc; 255 SN_LOCK(sc); 256 sninit_locked(sc); 257 SN_UNLOCK(sc); 258 } 259 260 /* 261 * Reset and initialize the chip 262 */ 263 static void 264 sninit_locked(void *xsc) 265 { 266 struct sn_softc *sc = xsc; 267 struct ifnet *ifp = sc->ifp; 268 int flags; 269 int mask; 270 271 SN_ASSERT_LOCKED(sc); 272 273 /* 274 * This resets the registers mostly to defaults, but doesn't affect 275 * EEPROM. After the reset cycle, we pause briefly for the chip to 276 * be happy. 277 */ 278 SMC_SELECT_BANK(sc, 0); 279 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET); 280 SMC_DELAY(sc); 281 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 282 SMC_DELAY(sc); 283 SMC_DELAY(sc); 284 285 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 286 287 /* 288 * Set the control register to automatically release successfully 289 * transmitted packets (making the best use out of our limited 290 * memory) and to enable the EPH interrupt on certain TX errors. 291 */ 292 SMC_SELECT_BANK(sc, 1); 293 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 294 CTR_CR_ENABLE | CTR_LE_ENABLE)); 295 296 /* Set squelch level to 240mV (default 480mV) */ 297 flags = CSR_READ_2(sc, CONFIG_REG_W); 298 flags |= CR_SET_SQLCH; 299 CSR_WRITE_2(sc, CONFIG_REG_W, flags); 300 301 /* 302 * Reset the MMU and wait for it to be un-busy. 303 */ 304 SMC_SELECT_BANK(sc, 2); 305 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET); 306 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 307 ; 308 309 /* 310 * Disable all interrupts 311 */ 312 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 313 314 sn_setmcast(sc); 315 316 /* 317 * Set the transmitter control. We want it enabled. 318 */ 319 flags = TCR_ENABLE; 320 321 #ifndef SW_PAD 322 /* 323 * I (GB) have been unlucky getting this to work. 324 */ 325 flags |= TCR_PAD_ENABLE; 326 #endif /* SW_PAD */ 327 328 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags); 329 330 331 /* 332 * Now, enable interrupts 333 */ 334 SMC_SELECT_BANK(sc, 2); 335 336 mask = IM_EPH_INT | 337 IM_RX_OVRN_INT | 338 IM_RCV_INT | 339 IM_TX_INT; 340 341 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 342 sc->intr_mask = mask; 343 sc->pages_wanted = -1; 344 345 346 /* 347 * Mark the interface running but not active. 348 */ 349 ifp->if_drv_flags |= IFF_DRV_RUNNING; 350 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 351 callout_reset(&sc->watchdog, hz, snwatchdog, sc); 352 353 /* 354 * Attempt to push out any waiting packets. 355 */ 356 snstart_locked(ifp); 357 } 358 359 static void 360 snstart(struct ifnet *ifp) 361 { 362 struct sn_softc *sc = ifp->if_softc; 363 SN_LOCK(sc); 364 snstart_locked(ifp); 365 SN_UNLOCK(sc); 366 } 367 368 369 static void 370 snstart_locked(struct ifnet *ifp) 371 { 372 struct sn_softc *sc = ifp->if_softc; 373 u_int len; 374 struct mbuf *m; 375 struct mbuf *top; 376 int pad; 377 int mask; 378 uint16_t length; 379 uint16_t numPages; 380 uint8_t packet_no; 381 int time_out; 382 int junk = 0; 383 384 SN_ASSERT_LOCKED(sc); 385 386 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 387 return; 388 if (sc->pages_wanted != -1) { 389 if_printf(ifp, "snstart() while memory allocation pending\n"); 390 return; 391 } 392 startagain: 393 394 /* 395 * Sneak a peek at the next packet 396 */ 397 m = ifp->if_snd.ifq_head; 398 if (m == NULL) 399 return; 400 /* 401 * Compute the frame length and set pad to give an overall even 402 * number of bytes. Below we assume that the packet length is even. 403 */ 404 for (len = 0, top = m; m; m = m->m_next) 405 len += m->m_len; 406 407 pad = (len & 1); 408 409 /* 410 * We drop packets that are too large. Perhaps we should truncate 411 * them instead? 412 */ 413 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 414 if_printf(ifp, "large packet discarded (A)\n"); 415 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 416 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 417 m_freem(m); 418 goto readcheck; 419 } 420 #ifdef SW_PAD 421 422 /* 423 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 424 */ 425 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 426 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 427 428 #endif /* SW_PAD */ 429 430 length = pad + len; 431 432 /* 433 * The MMU wants the number of pages to be the number of 256 byte 434 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 435 * include space for the status word, byte count and control bytes in 436 * the allocation request. 437 */ 438 numPages = (length + 6) >> 8; 439 440 441 /* 442 * Now, try to allocate the memory 443 */ 444 SMC_SELECT_BANK(sc, 2); 445 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 446 447 /* 448 * Wait a short amount of time to see if the allocation request 449 * completes. Otherwise, I enable the interrupt and wait for 450 * completion asynchronously. 451 */ 452 453 time_out = MEMORY_WAIT_TIME; 454 do { 455 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT) 456 break; 457 } while (--time_out); 458 459 if (!time_out || junk > 10) { 460 461 /* 462 * No memory now. Oh well, wait until the chip finds memory 463 * later. Remember how many pages we were asking for and 464 * enable the allocation completion interrupt. Also set a 465 * watchdog in case we miss the interrupt. We mark the 466 * interface active since there is no point in attempting an 467 * snstart() until after the memory is available. 468 */ 469 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT; 470 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 471 sc->intr_mask = mask; 472 473 sc->timer = 1; 474 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 475 sc->pages_wanted = numPages; 476 return; 477 } 478 /* 479 * The memory allocation completed. Check the results. 480 */ 481 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 482 if (packet_no & ARR_FAILED) { 483 if (junk++ > 10) 484 if_printf(ifp, "Memory allocation failed\n"); 485 goto startagain; 486 } 487 /* 488 * We have a packet number, so tell the card to use it. 489 */ 490 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 491 492 /* 493 * Point to the beginning of the packet 494 */ 495 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 496 497 /* 498 * Send the packet length (+6 for status, length and control byte) 499 * and the status word (set to zeros) 500 */ 501 CSR_WRITE_2(sc, DATA_REG_W, 0); 502 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 503 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 504 505 /* 506 * Get the packet from the kernel. This will include the Ethernet 507 * frame header, MAC Addresses etc. 508 */ 509 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 510 511 /* 512 * Push out the data to the card. 513 */ 514 for (top = m; m != NULL; m = m->m_next) { 515 516 /* 517 * Push out words. 518 */ 519 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 520 m->m_len / 2); 521 522 /* 523 * Push out remaining byte. 524 */ 525 if (m->m_len & 1) 526 CSR_WRITE_1(sc, DATA_REG_B, 527 *(mtod(m, caddr_t) + m->m_len - 1)); 528 } 529 530 /* 531 * Push out padding. 532 */ 533 while (pad > 1) { 534 CSR_WRITE_2(sc, DATA_REG_W, 0); 535 pad -= 2; 536 } 537 if (pad) 538 CSR_WRITE_1(sc, DATA_REG_B, 0); 539 540 /* 541 * Push out control byte and unused packet byte The control byte is 0 542 * meaning the packet is even lengthed and no special CRC handling is 543 * desired. 544 */ 545 CSR_WRITE_2(sc, DATA_REG_W, 0); 546 547 /* 548 * Enable the interrupts and let the chipset deal with it Also set a 549 * watchdog in case we miss the interrupt. 550 */ 551 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 552 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 553 sc->intr_mask = mask; 554 555 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 556 557 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 558 sc->timer = 1; 559 560 BPF_MTAP(ifp, top); 561 562 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 563 m_freem(top); 564 565 566 readcheck: 567 568 /* 569 * Is another packet coming in? We don't want to overflow the tiny 570 * RX FIFO. If nothing has arrived then attempt to queue another 571 * transmit packet. 572 */ 573 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY) 574 goto startagain; 575 return; 576 } 577 578 579 580 /* Resume a packet transmit operation after a memory allocation 581 * has completed. 582 * 583 * This is basically a hacked up copy of snstart() which handles 584 * a completed memory allocation the same way snstart() does. 585 * It then passes control to snstart to handle any other queued 586 * packets. 587 */ 588 static void 589 snresume(struct ifnet *ifp) 590 { 591 struct sn_softc *sc = ifp->if_softc; 592 u_int len; 593 struct mbuf *m; 594 struct mbuf *top; 595 int pad; 596 int mask; 597 uint16_t length; 598 uint16_t numPages; 599 uint16_t pages_wanted; 600 uint8_t packet_no; 601 602 if (sc->pages_wanted < 0) 603 return; 604 605 pages_wanted = sc->pages_wanted; 606 sc->pages_wanted = -1; 607 608 /* 609 * Sneak a peek at the next packet 610 */ 611 m = ifp->if_snd.ifq_head; 612 if (m == NULL) { 613 if_printf(ifp, "snresume() with nothing to send\n"); 614 return; 615 } 616 /* 617 * Compute the frame length and set pad to give an overall even 618 * number of bytes. Below we assume that the packet length is even. 619 */ 620 for (len = 0, top = m; m; m = m->m_next) 621 len += m->m_len; 622 623 pad = (len & 1); 624 625 /* 626 * We drop packets that are too large. Perhaps we should truncate 627 * them instead? 628 */ 629 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 630 if_printf(ifp, "large packet discarded (B)\n"); 631 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 632 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 633 m_freem(m); 634 return; 635 } 636 #ifdef SW_PAD 637 638 /* 639 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 640 */ 641 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 642 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 643 644 #endif /* SW_PAD */ 645 646 length = pad + len; 647 648 649 /* 650 * The MMU wants the number of pages to be the number of 256 byte 651 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 652 * include space for the status word, byte count and control bytes in 653 * the allocation request. 654 */ 655 numPages = (length + 6) >> 8; 656 657 658 SMC_SELECT_BANK(sc, 2); 659 660 /* 661 * The memory allocation completed. Check the results. If it failed, 662 * we simply set a watchdog timer and hope for the best. 663 */ 664 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 665 if (packet_no & ARR_FAILED) { 666 if_printf(ifp, "Memory allocation failed. Weird.\n"); 667 sc->timer = 1; 668 goto try_start; 669 } 670 /* 671 * We have a packet number, so tell the card to use it. 672 */ 673 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 674 675 /* 676 * Now, numPages should match the pages_wanted recorded when the 677 * memory allocation was initiated. 678 */ 679 if (pages_wanted != numPages) { 680 if_printf(ifp, "memory allocation wrong size. Weird.\n"); 681 /* 682 * If the allocation was the wrong size we simply release the 683 * memory once it is granted. Wait for the MMU to be un-busy. 684 */ 685 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 686 ; 687 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 688 689 return; 690 } 691 /* 692 * Point to the beginning of the packet 693 */ 694 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 695 696 /* 697 * Send the packet length (+6 for status, length and control byte) 698 * and the status word (set to zeros) 699 */ 700 CSR_WRITE_2(sc, DATA_REG_W, 0); 701 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 702 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 703 704 /* 705 * Get the packet from the kernel. This will include the Ethernet 706 * frame header, MAC Addresses etc. 707 */ 708 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 709 710 /* 711 * Push out the data to the card. 712 */ 713 for (top = m; m != NULL; m = m->m_next) { 714 715 /* 716 * Push out words. 717 */ 718 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 719 m->m_len / 2); 720 /* 721 * Push out remaining byte. 722 */ 723 if (m->m_len & 1) 724 CSR_WRITE_1(sc, DATA_REG_B, 725 *(mtod(m, caddr_t) + m->m_len - 1)); 726 } 727 728 /* 729 * Push out padding. 730 */ 731 while (pad > 1) { 732 CSR_WRITE_2(sc, DATA_REG_W, 0); 733 pad -= 2; 734 } 735 if (pad) 736 CSR_WRITE_1(sc, DATA_REG_B, 0); 737 738 /* 739 * Push out control byte and unused packet byte The control byte is 0 740 * meaning the packet is even lengthed and no special CRC handling is 741 * desired. 742 */ 743 CSR_WRITE_2(sc, DATA_REG_W, 0); 744 745 /* 746 * Enable the interrupts and let the chipset deal with it Also set a 747 * watchdog in case we miss the interrupt. 748 */ 749 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 750 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 751 sc->intr_mask = mask; 752 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 753 754 BPF_MTAP(ifp, top); 755 756 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 757 m_freem(top); 758 759 try_start: 760 761 /* 762 * Now pass control to snstart() to queue any additional packets 763 */ 764 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 765 snstart_locked(ifp); 766 767 /* 768 * We've sent something, so we're active. Set a watchdog in case the 769 * TX_EMPTY interrupt is lost. 770 */ 771 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 772 sc->timer = 1; 773 774 return; 775 } 776 777 void 778 sn_intr(void *arg) 779 { 780 struct sn_softc *sc = (struct sn_softc *) arg; 781 782 SN_LOCK(sc); 783 snintr_locked(sc); 784 SN_UNLOCK(sc); 785 } 786 787 static void 788 snintr_locked(struct sn_softc *sc) 789 { 790 int status, interrupts; 791 struct ifnet *ifp = sc->ifp; 792 793 /* 794 * Chip state registers 795 */ 796 uint8_t mask; 797 uint8_t packet_no; 798 uint16_t tx_status; 799 uint16_t card_stats; 800 801 /* 802 * Clear the watchdog. 803 */ 804 sc->timer = 0; 805 806 SMC_SELECT_BANK(sc, 2); 807 808 /* 809 * Obtain the current interrupt mask and clear the hardware mask 810 * while servicing interrupts. 811 */ 812 mask = CSR_READ_1(sc, INTR_MASK_REG_B); 813 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 814 815 /* 816 * Get the set of interrupts which occurred and eliminate any which 817 * are masked. 818 */ 819 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B); 820 status = interrupts & mask; 821 822 /* 823 * Now, process each of the interrupt types. 824 */ 825 826 /* 827 * Receive Overrun. 828 */ 829 if (status & IM_RX_OVRN_INT) { 830 /* 831 * Acknowlege Interrupt 832 */ 833 SMC_SELECT_BANK(sc, 2); 834 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT); 835 836 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 837 } 838 /* 839 * Got a packet. 840 */ 841 if (status & IM_RCV_INT) { 842 int packet_number; 843 844 SMC_SELECT_BANK(sc, 2); 845 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 846 847 if (packet_number & FIFO_REMPTY) { 848 /* 849 * we got called , but nothing was on the FIFO 850 */ 851 printf("sn: Receive interrupt with nothing on FIFO\n"); 852 goto out; 853 } 854 snread(ifp); 855 } 856 /* 857 * An on-card memory allocation came through. 858 */ 859 if (status & IM_ALLOC_INT) { 860 /* 861 * Disable this interrupt. 862 */ 863 mask &= ~IM_ALLOC_INT; 864 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 865 snresume(ifp); 866 } 867 /* 868 * TX Completion. Handle a transmit error message. This will only be 869 * called when there is an error, because of the AUTO_RELEASE mode. 870 */ 871 if (status & IM_TX_INT) { 872 /* 873 * Acknowlege Interrupt 874 */ 875 SMC_SELECT_BANK(sc, 2); 876 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT); 877 878 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W); 879 packet_no &= FIFO_TX_MASK; 880 881 /* 882 * select this as the packet to read from 883 */ 884 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 885 886 /* 887 * Position the pointer to the first word from this packet 888 */ 889 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 890 891 /* 892 * Fetch the TX status word. The value found here will be a 893 * copy of the EPH_STATUS_REG_W at the time the transmit 894 * failed. 895 */ 896 tx_status = CSR_READ_2(sc, DATA_REG_W); 897 898 if (tx_status & EPHSR_TX_SUC) { 899 device_printf(sc->dev, 900 "Successful packet caused interrupt\n"); 901 } else { 902 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 903 } 904 905 if (tx_status & EPHSR_LATCOL) 906 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 907 908 /* 909 * Some of these errors will have disabled transmit. 910 * Re-enable transmit now. 911 */ 912 SMC_SELECT_BANK(sc, 0); 913 914 #ifdef SW_PAD 915 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE); 916 #else 917 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 918 #endif /* SW_PAD */ 919 920 /* 921 * kill the failed packet. Wait for the MMU to be un-busy. 922 */ 923 SMC_SELECT_BANK(sc, 2); 924 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 925 ; 926 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 927 928 /* 929 * Attempt to queue more transmits. 930 */ 931 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 932 snstart_locked(ifp); 933 } 934 /* 935 * Transmit underrun. We use this opportunity to update transmit 936 * statistics from the card. 937 */ 938 if (status & IM_TX_EMPTY_INT) { 939 940 /* 941 * Acknowlege Interrupt 942 */ 943 SMC_SELECT_BANK(sc, 2); 944 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 945 946 /* 947 * Disable this interrupt. 948 */ 949 mask &= ~IM_TX_EMPTY_INT; 950 951 SMC_SELECT_BANK(sc, 0); 952 card_stats = CSR_READ_2(sc, COUNTER_REG_W); 953 954 /* 955 * Single collisions 956 */ 957 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, card_stats & ECR_COLN_MASK); 958 959 /* 960 * Multiple collisions 961 */ 962 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (card_stats & ECR_MCOLN_MASK) >> 4); 963 964 SMC_SELECT_BANK(sc, 2); 965 966 /* 967 * Attempt to enqueue some more stuff. 968 */ 969 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 970 snstart_locked(ifp); 971 } 972 /* 973 * Some other error. Try to fix it by resetting the adapter. 974 */ 975 if (status & IM_EPH_INT) { 976 snstop(sc); 977 sninit_locked(sc); 978 } 979 980 out: 981 /* 982 * Handled all interrupt sources. 983 */ 984 985 SMC_SELECT_BANK(sc, 2); 986 987 /* 988 * Reestablish interrupts from mask which have not been deselected 989 * during this interrupt. Note that the hardware mask, which was set 990 * to 0x00 at the start of this service routine, may have been 991 * updated by one or more of the interrupt handers and we must let 992 * those new interrupts stay enabled here. 993 */ 994 mask |= CSR_READ_1(sc, INTR_MASK_REG_B); 995 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 996 sc->intr_mask = mask; 997 } 998 999 static void 1000 snread(struct ifnet *ifp) 1001 { 1002 struct sn_softc *sc = ifp->if_softc; 1003 struct ether_header *eh; 1004 struct mbuf *m; 1005 short status; 1006 int packet_number; 1007 uint16_t packet_length; 1008 uint8_t *data; 1009 1010 SMC_SELECT_BANK(sc, 2); 1011 #if 0 1012 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1013 1014 if (packet_number & FIFO_REMPTY) { 1015 1016 /* 1017 * we got called , but nothing was on the FIFO 1018 */ 1019 printf("sn: Receive interrupt with nothing on FIFO\n"); 1020 return; 1021 } 1022 #endif 1023 read_another: 1024 1025 /* 1026 * Start reading from the start of the packet. Since PTR_RCV is set, 1027 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1028 */ 1029 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 1030 1031 /* 1032 * First two words are status and packet_length 1033 */ 1034 status = CSR_READ_2(sc, DATA_REG_W); 1035 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK; 1036 1037 /* 1038 * The packet length contains 3 extra words: status, length, and a 1039 * extra word with the control byte. 1040 */ 1041 packet_length -= 6; 1042 1043 /* 1044 * Account for receive errors and discard. 1045 */ 1046 if (status & RS_ERRORS) { 1047 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1048 goto out; 1049 } 1050 /* 1051 * A packet is received. 1052 */ 1053 1054 /* 1055 * Adjust for odd-length packet. 1056 */ 1057 if (status & RS_ODDFRAME) 1058 packet_length++; 1059 1060 /* 1061 * Allocate a header mbuf from the kernel. 1062 */ 1063 MGETHDR(m, M_NOWAIT, MT_DATA); 1064 if (m == NULL) 1065 goto out; 1066 1067 m->m_pkthdr.rcvif = ifp; 1068 m->m_pkthdr.len = m->m_len = packet_length; 1069 1070 /* 1071 * Attach an mbuf cluster. 1072 */ 1073 if (!(MCLGET(m, M_NOWAIT))) { 1074 m_freem(m); 1075 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1076 printf("sn: snread() kernel memory allocation problem\n"); 1077 goto out; 1078 } 1079 eh = mtod(m, struct ether_header *); 1080 1081 /* 1082 * Get packet, including link layer address, from interface. 1083 */ 1084 data = (uint8_t *) eh; 1085 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1); 1086 if (packet_length & 1) { 1087 data += packet_length & ~1; 1088 *data = CSR_READ_1(sc, DATA_REG_B); 1089 } 1090 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1091 1092 /* 1093 * Remove link layer addresses and whatnot. 1094 */ 1095 m->m_pkthdr.len = m->m_len = packet_length; 1096 1097 /* 1098 * Drop locks before calling if_input() since it may re-enter 1099 * snstart() in the netisr case. This would result in a 1100 * lock reversal. Better performance might be obtained by 1101 * chaining all packets received, dropping the lock, and then 1102 * calling if_input() on each one. 1103 */ 1104 SN_UNLOCK(sc); 1105 (*ifp->if_input)(ifp, m); 1106 SN_LOCK(sc); 1107 1108 out: 1109 1110 /* 1111 * Error or good, tell the card to get rid of this packet Wait for 1112 * the MMU to be un-busy. 1113 */ 1114 SMC_SELECT_BANK(sc, 2); 1115 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1116 ; 1117 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE); 1118 1119 /* 1120 * Check whether another packet is ready 1121 */ 1122 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1123 if (packet_number & FIFO_REMPTY) { 1124 return; 1125 } 1126 goto read_another; 1127 } 1128 1129 1130 /* 1131 * Handle IOCTLS. This function is completely stolen from if_ep.c 1132 * As with its progenitor, it does not handle hardware address 1133 * changes. 1134 */ 1135 static int 1136 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1137 { 1138 struct sn_softc *sc = ifp->if_softc; 1139 int error = 0; 1140 1141 switch (cmd) { 1142 case SIOCSIFFLAGS: 1143 SN_LOCK(sc); 1144 if ((ifp->if_flags & IFF_UP) == 0 && 1145 ifp->if_drv_flags & IFF_DRV_RUNNING) { 1146 snstop(sc); 1147 } else { 1148 /* reinitialize card on any parameter change */ 1149 sninit_locked(sc); 1150 } 1151 SN_UNLOCK(sc); 1152 break; 1153 1154 case SIOCADDMULTI: 1155 case SIOCDELMULTI: 1156 /* update multicast filter list. */ 1157 SN_LOCK(sc); 1158 sn_setmcast(sc); 1159 error = 0; 1160 SN_UNLOCK(sc); 1161 break; 1162 default: 1163 error = ether_ioctl(ifp, cmd, data); 1164 break; 1165 } 1166 return (error); 1167 } 1168 1169 static void 1170 snwatchdog(void *arg) 1171 { 1172 struct sn_softc *sc; 1173 1174 sc = arg; 1175 SN_ASSERT_LOCKED(sc); 1176 callout_reset(&sc->watchdog, hz, snwatchdog, sc); 1177 if (sc->timer == 0 || --sc->timer > 0) 1178 return; 1179 snintr_locked(sc); 1180 } 1181 1182 1183 /* 1. zero the interrupt mask 1184 * 2. clear the enable receive flag 1185 * 3. clear the enable xmit flags 1186 */ 1187 static void 1188 snstop(struct sn_softc *sc) 1189 { 1190 1191 struct ifnet *ifp = sc->ifp; 1192 1193 /* 1194 * Clear interrupt mask; disable all interrupts. 1195 */ 1196 SMC_SELECT_BANK(sc, 2); 1197 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 1198 1199 /* 1200 * Disable transmitter and Receiver 1201 */ 1202 SMC_SELECT_BANK(sc, 0); 1203 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 1204 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 1205 1206 /* 1207 * Cancel watchdog. 1208 */ 1209 sc->timer = 0; 1210 callout_stop(&sc->watchdog); 1211 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1212 } 1213 1214 1215 int 1216 sn_activate(device_t dev) 1217 { 1218 struct sn_softc *sc = device_get_softc(dev); 1219 1220 sc->port_rid = 0; 1221 sc->port_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 1222 &sc->port_rid, SMC_IO_EXTENT, RF_ACTIVE); 1223 if (!sc->port_res) { 1224 if (bootverbose) 1225 device_printf(dev, "Cannot allocate ioport\n"); 1226 return ENOMEM; 1227 } 1228 1229 sc->irq_rid = 0; 1230 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 1231 RF_ACTIVE); 1232 if (!sc->irq_res) { 1233 if (bootverbose) 1234 device_printf(dev, "Cannot allocate irq\n"); 1235 sn_deactivate(dev); 1236 return ENOMEM; 1237 } 1238 return (0); 1239 } 1240 1241 void 1242 sn_deactivate(device_t dev) 1243 { 1244 struct sn_softc *sc = device_get_softc(dev); 1245 1246 if (sc->intrhand) 1247 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1248 sc->intrhand = 0; 1249 if (sc->port_res) 1250 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1251 sc->port_res); 1252 sc->port_res = 0; 1253 if (sc->modem_res) 1254 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid, 1255 sc->modem_res); 1256 sc->modem_res = 0; 1257 if (sc->irq_res) 1258 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1259 sc->irq_res); 1260 sc->irq_res = 0; 1261 return; 1262 } 1263 1264 /* 1265 * Function: sn_probe(device_t dev) 1266 * 1267 * Purpose: 1268 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1269 * Tries to cause as little damage as possible if it's not a SMC chip. 1270 * Returns a 0 on success 1271 * 1272 * Algorithm: 1273 * (1) see if the high byte of BANK_SELECT is 0x33 1274 * (2) compare the ioaddr with the base register's address 1275 * (3) see if I recognize the chip ID in the appropriate register 1276 * 1277 * 1278 */ 1279 int 1280 sn_probe(device_t dev) 1281 { 1282 struct sn_softc *sc = device_get_softc(dev); 1283 uint16_t bank; 1284 uint16_t revision_register; 1285 uint16_t base_address_register; 1286 int err; 1287 1288 if ((err = sn_activate(dev)) != 0) 1289 return err; 1290 1291 /* 1292 * First, see if the high byte is 0x33 1293 */ 1294 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1295 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1296 #ifdef SN_DEBUG 1297 device_printf(dev, "test1 failed\n"); 1298 #endif 1299 goto error; 1300 } 1301 /* 1302 * The above MIGHT indicate a device, but I need to write to further 1303 * test this. Go to bank 0, then test that the register still 1304 * reports the high byte is 0x33. 1305 */ 1306 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000); 1307 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1308 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1309 #ifdef SN_DEBUG 1310 device_printf(dev, "test2 failed\n"); 1311 #endif 1312 goto error; 1313 } 1314 /* 1315 * well, we've already written once, so hopefully another time won't 1316 * hurt. This time, I need to switch the bank register to bank 1, so 1317 * I can access the base address register. The contents of the 1318 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1319 * to match the I/O port address where the adapter is being probed. 1320 */ 1321 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001); 1322 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0; 1323 1324 if (rman_get_start(sc->port_res) != base_address_register) { 1325 1326 /* 1327 * Well, the base address register didn't match. Must not 1328 * have been a SMC chip after all. 1329 */ 1330 #ifdef SN_DEBUG 1331 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1332 "base_address_register = 0x%x\n", 1333 rman_get_start(sc->port_res), base_address_register); 1334 #endif 1335 goto error; 1336 } 1337 1338 /* 1339 * Check if the revision register is something that I recognize. 1340 * These might need to be added to later, as future revisions could 1341 * be added. 1342 */ 1343 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3); 1344 revision_register = CSR_READ_2(sc, REVISION_REG_W); 1345 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1346 1347 /* 1348 * I don't regonize this chip, so... 1349 */ 1350 #ifdef SN_DEBUG 1351 device_printf(dev, "test4 failed\n"); 1352 #endif 1353 goto error; 1354 } 1355 1356 /* 1357 * at this point I'll assume that the chip is an SMC9xxx. It might be 1358 * prudent to check a listing of MAC addresses against the hardware 1359 * address, or do some other tests. 1360 */ 1361 sn_deactivate(dev); 1362 return 0; 1363 error: 1364 sn_deactivate(dev); 1365 return ENXIO; 1366 } 1367 1368 #define MCFSZ 8 1369 1370 static void 1371 sn_setmcast(struct sn_softc *sc) 1372 { 1373 struct ifnet *ifp = sc->ifp; 1374 int flags; 1375 uint8_t mcf[MCFSZ]; 1376 1377 SN_ASSERT_LOCKED(sc); 1378 1379 /* 1380 * Set the receiver filter. We want receive enabled and auto strip 1381 * of CRC from received packet. If we are promiscuous then set that 1382 * bit too. 1383 */ 1384 flags = RCR_ENABLE | RCR_STRIP_CRC; 1385 1386 if (ifp->if_flags & IFF_PROMISC) { 1387 flags |= RCR_PROMISC | RCR_ALMUL; 1388 } else if (ifp->if_flags & IFF_ALLMULTI) { 1389 flags |= RCR_ALMUL; 1390 } else { 1391 if (sn_getmcf(ifp, mcf)) { 1392 /* set filter */ 1393 SMC_SELECT_BANK(sc, 3); 1394 CSR_WRITE_2(sc, MULTICAST1_REG_W, 1395 ((uint16_t)mcf[1] << 8) | mcf[0]); 1396 CSR_WRITE_2(sc, MULTICAST2_REG_W, 1397 ((uint16_t)mcf[3] << 8) | mcf[2]); 1398 CSR_WRITE_2(sc, MULTICAST3_REG_W, 1399 ((uint16_t)mcf[5] << 8) | mcf[4]); 1400 CSR_WRITE_2(sc, MULTICAST4_REG_W, 1401 ((uint16_t)mcf[7] << 8) | mcf[6]); 1402 } else { 1403 flags |= RCR_ALMUL; 1404 } 1405 } 1406 SMC_SELECT_BANK(sc, 0); 1407 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags); 1408 } 1409 1410 static int 1411 sn_getmcf(struct ifnet *ifp, uint8_t *mcf) 1412 { 1413 int i; 1414 uint32_t index, index2; 1415 uint8_t *af = mcf; 1416 struct ifmultiaddr *ifma; 1417 1418 bzero(mcf, MCFSZ); 1419 1420 if_maddr_rlock(ifp); 1421 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1422 if (ifma->ifma_addr->sa_family != AF_LINK) { 1423 if_maddr_runlock(ifp); 1424 return 0; 1425 } 1426 index = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1427 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f; 1428 index2 = 0; 1429 for (i = 0; i < 6; i++) { 1430 index2 <<= 1; 1431 index2 |= (index & 0x01); 1432 index >>= 1; 1433 } 1434 af[index2 >> 3] |= 1 << (index2 & 7); 1435 } 1436 if_maddr_runlock(ifp); 1437 return 1; /* use multicast filter */ 1438 } 1439