1 /*- 2 * Copyright (c) 2015, Stanislav Galabov 3 * Copyright (c) 2014, Aleksandr A. Mityaev 4 * Copyright (c) 2011, Aleksandr Rybalko 5 * based on hard work 6 * by Alexander Egorenkov <[email protected]> 7 * and by Damien Bergamini <[email protected]> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice unmodified, this list of conditions, and the following 15 * disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "if_rtvar.h" 37 #include "if_rtreg.h" 38 39 #include <net/if.h> 40 #include <net/if_var.h> 41 #include <net/if_arp.h> 42 #include <net/ethernet.h> 43 #include <net/if_dl.h> 44 #include <net/if_media.h> 45 #include <net/if_types.h> 46 #include <net/if_vlan_var.h> 47 48 #include <net/bpf.h> 49 50 #include <machine/bus.h> 51 #include <machine/cache.h> 52 #include <machine/cpufunc.h> 53 #include <machine/resource.h> 54 #include <vm/vm_param.h> 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 #include <machine/pmap.h> 58 #include <sys/bus.h> 59 #include <sys/rman.h> 60 61 #include "opt_platform.h" 62 #include "opt_rt305x.h" 63 64 #ifdef FDT 65 #include <dev/ofw/openfirm.h> 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 #endif 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include <mips/rt305x/rt305x_sysctlvar.h> 74 #include <mips/rt305x/rt305xreg.h> 75 76 #ifdef IF_RT_PHY_SUPPORT 77 #include "miibus_if.h" 78 #endif 79 80 /* 81 * Defines and macros 82 */ 83 #define RT_MAX_AGG_SIZE 3840 84 85 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE 86 87 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S) 88 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f) 89 90 #define RT_TX_WATCHDOG_TIMEOUT 5 91 92 #define RT_CHIPID_RT3050 0x3050 93 #define RT_CHIPID_RT3052 0x3052 94 #define RT_CHIPID_RT5350 0x5350 95 #define RT_CHIPID_RT6855 0x6855 96 #define RT_CHIPID_MT7620 0x7620 97 98 #ifdef FDT 99 /* more specific and new models should go first */ 100 static const struct ofw_compat_data rt_compat_data[] = { 101 { "ralink,rt6855-eth", (uintptr_t)RT_CHIPID_RT6855 }, 102 { "ralink,rt5350-eth", (uintptr_t)RT_CHIPID_RT5350 }, 103 { "ralink,rt3052-eth", (uintptr_t)RT_CHIPID_RT3052 }, 104 { "ralink,rt305x-eth", (uintptr_t)RT_CHIPID_RT3050 }, 105 { NULL, (uintptr_t)NULL } 106 }; 107 #endif 108 109 /* 110 * Static function prototypes 111 */ 112 static int rt_probe(device_t dev); 113 static int rt_attach(device_t dev); 114 static int rt_detach(device_t dev); 115 static int rt_shutdown(device_t dev); 116 static int rt_suspend(device_t dev); 117 static int rt_resume(device_t dev); 118 static void rt_init_locked(void *priv); 119 static void rt_init(void *priv); 120 static void rt_stop_locked(void *priv); 121 static void rt_stop(void *priv); 122 static void rt_start(struct ifnet *ifp); 123 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 124 static void rt_periodic(void *arg); 125 static void rt_tx_watchdog(void *arg); 126 static void rt_intr(void *arg); 127 static void rt_rt5350_intr(void *arg); 128 static void rt_tx_coherent_intr(struct rt_softc *sc); 129 static void rt_rx_coherent_intr(struct rt_softc *sc); 130 static void rt_rx_delay_intr(struct rt_softc *sc); 131 static void rt_tx_delay_intr(struct rt_softc *sc); 132 static void rt_rx_intr(struct rt_softc *sc, int qid); 133 static void rt_tx_intr(struct rt_softc *sc, int qid); 134 static void rt_rx_done_task(void *context, int pending); 135 static void rt_tx_done_task(void *context, int pending); 136 static void rt_periodic_task(void *context, int pending); 137 static int rt_rx_eof(struct rt_softc *sc, 138 struct rt_softc_rx_ring *ring, int limit); 139 static void rt_tx_eof(struct rt_softc *sc, 140 struct rt_softc_tx_ring *ring); 141 static void rt_update_stats(struct rt_softc *sc); 142 static void rt_watchdog(struct rt_softc *sc); 143 static void rt_update_raw_counters(struct rt_softc *sc); 144 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask); 145 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask); 146 static int rt_txrx_enable(struct rt_softc *sc); 147 static int rt_alloc_rx_ring(struct rt_softc *sc, 148 struct rt_softc_rx_ring *ring, int qid); 149 static void rt_reset_rx_ring(struct rt_softc *sc, 150 struct rt_softc_rx_ring *ring); 151 static void rt_free_rx_ring(struct rt_softc *sc, 152 struct rt_softc_rx_ring *ring); 153 static int rt_alloc_tx_ring(struct rt_softc *sc, 154 struct rt_softc_tx_ring *ring, int qid); 155 static void rt_reset_tx_ring(struct rt_softc *sc, 156 struct rt_softc_tx_ring *ring); 157 static void rt_free_tx_ring(struct rt_softc *sc, 158 struct rt_softc_tx_ring *ring); 159 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, 160 int nseg, int error); 161 static void rt_sysctl_attach(struct rt_softc *sc); 162 #ifdef IF_RT_PHY_SUPPORT 163 void rt_miibus_statchg(device_t); 164 static int rt_miibus_readreg(device_t, int, int); 165 static int rt_miibus_writereg(device_t, int, int, int); 166 #endif 167 static int rt_ifmedia_upd(struct ifnet *); 168 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *); 169 170 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD, 0, "RT driver parameters"); 171 #ifdef IF_RT_DEBUG 172 static int rt_debug = 0; 173 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RWTUN, &rt_debug, 0, 174 "RT debug level"); 175 #endif 176 177 static int 178 rt_probe(device_t dev) 179 { 180 struct rt_softc *sc = device_get_softc(dev); 181 char buf[80]; 182 #ifdef FDT 183 const struct ofw_compat_data * cd; 184 185 cd = ofw_bus_search_compatible(dev, rt_compat_data); 186 if (cd->ocd_data == (uintptr_t)NULL) 187 return (ENXIO); 188 189 sc->rt_chipid = (unsigned int)(cd->ocd_data); 190 #else 191 #if defined(MT7620) 192 sc->rt_chipid = RT_CHIPID_MT7620; 193 #elif defined(RT5350) 194 sc->rt_chipid = RT_CHIPID_RT5350; 195 #else 196 sc->rt_chipid = RT_CHIPID_RT3050; 197 #endif 198 #endif 199 snprintf(buf, sizeof(buf), "Ralink RT%x onChip Ethernet driver", 200 sc->rt_chipid); 201 device_set_desc_copy(dev, buf); 202 return (BUS_PROBE_GENERIC); 203 } 204 205 /* 206 * macaddr_atoi - translate string MAC address to uint8_t array 207 */ 208 static int 209 macaddr_atoi(const char *str, uint8_t *mac) 210 { 211 int count, i; 212 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */ 213 214 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x", 215 &amac[0], &amac[1], &amac[2], 216 &amac[3], &amac[4], &amac[5]); 217 if (count < ETHER_ADDR_LEN) { 218 memset(mac, 0, ETHER_ADDR_LEN); 219 return (1); 220 } 221 222 /* Copy aligned to result */ 223 for (i = 0; i < ETHER_ADDR_LEN; i ++) 224 mac[i] = (amac[i] & 0xff); 225 226 return (0); 227 } 228 229 #ifdef USE_GENERATED_MAC_ADDRESS 230 /* 231 * generate_mac(uin8_t *mac) 232 * This is MAC address generator for cases when real device MAC address 233 * unknown or not yet accessible. 234 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv. 235 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0] 236 * 237 * Output - MAC address, that do not change between reboots, if hints or 238 * bootloader info unchange. 239 */ 240 static void 241 generate_mac(uint8_t *mac) 242 { 243 unsigned char *cp; 244 int i = 0; 245 uint32_t crc = 0xffffffff; 246 247 /* Generate CRC32 on kenv */ 248 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) { 249 crc = calculate_crc32c(crc, cp, strlen(cp) + 1); 250 } 251 crc = ~crc; 252 253 mac[0] = 'b'; 254 mac[1] = 's'; 255 mac[2] = 'd'; 256 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff); 257 mac[4] = (crc >> 8) & 0xff; 258 mac[5] = crc & 0xff; 259 } 260 #endif 261 262 /* 263 * ether_request_mac - try to find usable MAC address. 264 */ 265 static int 266 ether_request_mac(device_t dev, uint8_t *mac) 267 { 268 char *var; 269 270 /* 271 * "ethaddr" is passed via envp on RedBoot platforms 272 * "kmac" is passed via argv on RouterBOOT platforms 273 */ 274 #if defined(RT305X_UBOOT) || defined(__REDBOOT__) || defined(__ROUTERBOOT__) 275 if ((var = kern_getenv("ethaddr")) != NULL || 276 (var = kern_getenv("kmac")) != NULL ) { 277 278 if(!macaddr_atoi(var, mac)) { 279 printf("%s: use %s macaddr from KENV\n", 280 device_get_nameunit(dev), var); 281 freeenv(var); 282 return (0); 283 } 284 freeenv(var); 285 } 286 #endif 287 288 /* 289 * Try from hints 290 * hint.[dev].[unit].macaddr 291 */ 292 if (!resource_string_value(device_get_name(dev), 293 device_get_unit(dev), "macaddr", (const char **)&var)) { 294 295 if(!macaddr_atoi(var, mac)) { 296 printf("%s: use %s macaddr from hints\n", 297 device_get_nameunit(dev), var); 298 return (0); 299 } 300 } 301 302 #ifdef USE_GENERATED_MAC_ADDRESS 303 generate_mac(mac); 304 305 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x " 306 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 307 #else 308 /* Hardcoded */ 309 mac[0] = 0x00; 310 mac[1] = 0x18; 311 mac[2] = 0xe7; 312 mac[3] = 0xd5; 313 mac[4] = 0x83; 314 mac[5] = 0x90; 315 316 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n"); 317 #endif 318 319 return (0); 320 } 321 322 /* 323 * Reset hardware 324 */ 325 static void 326 reset_freng(struct rt_softc *sc) 327 { 328 /* XXX hard reset kills everything so skip it ... */ 329 return; 330 } 331 332 static int 333 rt_attach(device_t dev) 334 { 335 struct rt_softc *sc; 336 struct ifnet *ifp; 337 int error, i; 338 339 sc = device_get_softc(dev); 340 sc->dev = dev; 341 342 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK, 343 MTX_DEF | MTX_RECURSE); 344 345 sc->mem_rid = 0; 346 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 347 RF_ACTIVE); 348 if (sc->mem == NULL) { 349 device_printf(dev, "could not allocate memory resource\n"); 350 error = ENXIO; 351 goto fail; 352 } 353 354 sc->bst = rman_get_bustag(sc->mem); 355 sc->bsh = rman_get_bushandle(sc->mem); 356 357 sc->irq_rid = 0; 358 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 359 RF_ACTIVE); 360 if (sc->irq == NULL) { 361 device_printf(dev, 362 "could not allocate interrupt resource\n"); 363 error = ENXIO; 364 goto fail; 365 } 366 367 #ifdef IF_RT_DEBUG 368 sc->debug = rt_debug; 369 370 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 371 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 372 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level"); 373 #endif 374 375 /* Reset hardware */ 376 reset_freng(sc); 377 378 /* Fill in soc-specific registers map */ 379 switch(sc->rt_chipid) { 380 case RT_CHIPID_MT7620: 381 case RT_CHIPID_RT5350: 382 device_printf(dev, "RT%x Ethernet MAC (rev 0x%08x)\n", 383 sc->rt_chipid, sc->mac_rev); 384 /* RT5350: No GDMA, PSE, CDMA, PPE */ 385 RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1 386 RT_READ(sc, GE_PORT_BASE + 0x0C00) | (0x7<<16)); 387 sc->delay_int_cfg=RT5350_PDMA_BASE+RT5350_DELAY_INT_CFG; 388 sc->fe_int_status=RT5350_FE_INT_STATUS; 389 sc->fe_int_enable=RT5350_FE_INT_ENABLE; 390 sc->pdma_glo_cfg=RT5350_PDMA_BASE+RT5350_PDMA_GLO_CFG; 391 sc->pdma_rst_idx=RT5350_PDMA_BASE+RT5350_PDMA_RST_IDX; 392 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 393 sc->tx_base_ptr[i]=RT5350_PDMA_BASE+RT5350_TX_BASE_PTR(i); 394 sc->tx_max_cnt[i]=RT5350_PDMA_BASE+RT5350_TX_MAX_CNT(i); 395 sc->tx_ctx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_CTX_IDX(i); 396 sc->tx_dtx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_DTX_IDX(i); 397 } 398 sc->rx_ring_count=2; 399 sc->rx_base_ptr[0]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR0; 400 sc->rx_max_cnt[0]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT0; 401 sc->rx_calc_idx[0]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX0; 402 sc->rx_drx_idx[0]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX0; 403 sc->rx_base_ptr[1]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR1; 404 sc->rx_max_cnt[1]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT1; 405 sc->rx_calc_idx[1]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX1; 406 sc->rx_drx_idx[1]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX1; 407 sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE; 408 sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE; 409 break; 410 case RT_CHIPID_RT6855: 411 device_printf(dev, "RT6855 Ethernet MAC (rev 0x%08x)\n", 412 sc->mac_rev); 413 break; 414 default: 415 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n", 416 sc->mac_rev); 417 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG, 418 ( 419 GDM_ICS_EN | /* Enable IP Csum */ 420 GDM_TCS_EN | /* Enable TCP Csum */ 421 GDM_UCS_EN | /* Enable UDP Csum */ 422 GDM_STRPCRC | /* Strip CRC from packet */ 423 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */ 424 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */ 425 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */ 426 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */ 427 )); 428 429 sc->delay_int_cfg=PDMA_BASE+DELAY_INT_CFG; 430 sc->fe_int_status=GE_PORT_BASE+FE_INT_STATUS; 431 sc->fe_int_enable=GE_PORT_BASE+FE_INT_ENABLE; 432 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG; 433 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG; 434 sc->pdma_rst_idx=PDMA_BASE+PDMA_RST_IDX; 435 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 436 sc->tx_base_ptr[i]=PDMA_BASE+TX_BASE_PTR(i); 437 sc->tx_max_cnt[i]=PDMA_BASE+TX_MAX_CNT(i); 438 sc->tx_ctx_idx[i]=PDMA_BASE+TX_CTX_IDX(i); 439 sc->tx_dtx_idx[i]=PDMA_BASE+TX_DTX_IDX(i); 440 } 441 sc->rx_ring_count=1; 442 sc->rx_base_ptr[0]=PDMA_BASE+RX_BASE_PTR0; 443 sc->rx_max_cnt[0]=PDMA_BASE+RX_MAX_CNT0; 444 sc->rx_calc_idx[0]=PDMA_BASE+RX_CALC_IDX0; 445 sc->rx_drx_idx[0]=PDMA_BASE+RX_DRX_IDX0; 446 sc->int_rx_done_mask=INT_RX_DONE; 447 sc->int_tx_done_mask=INT_TXQ0_DONE; 448 }; 449 450 /* allocate Tx and Rx rings */ 451 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 452 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i); 453 if (error != 0) { 454 device_printf(dev, "could not allocate Tx ring #%d\n", 455 i); 456 goto fail; 457 } 458 } 459 460 sc->tx_ring_mgtqid = 5; 461 for (i = 0; i < sc->rx_ring_count; i++) { 462 error = rt_alloc_rx_ring(sc, &sc->rx_ring[i], i); 463 if (error != 0) { 464 device_printf(dev, "could not allocate Rx ring\n"); 465 goto fail; 466 } 467 } 468 469 callout_init(&sc->periodic_ch, 0); 470 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0); 471 472 ifp = sc->ifp = if_alloc(IFT_ETHER); 473 if (ifp == NULL) { 474 device_printf(dev, "could not if_alloc()\n"); 475 error = ENOMEM; 476 goto fail; 477 } 478 479 ifp->if_softc = sc; 480 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 481 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 482 ifp->if_init = rt_init; 483 ifp->if_ioctl = rt_ioctl; 484 ifp->if_start = rt_start; 485 #define RT_TX_QLEN 256 486 487 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN); 488 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN; 489 IFQ_SET_READY(&ifp->if_snd); 490 491 #ifdef IF_RT_PHY_SUPPORT 492 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd, 493 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 494 if (error != 0) { 495 device_printf(dev, "attaching PHYs failed\n"); 496 error = ENXIO; 497 goto fail; 498 } 499 #else 500 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts); 501 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 502 NULL); 503 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX); 504 505 #endif /* IF_RT_PHY_SUPPORT */ 506 507 ether_request_mac(dev, sc->mac_addr); 508 ether_ifattach(ifp, sc->mac_addr); 509 510 /* 511 * Tell the upper layer(s) we support long frames. 512 */ 513 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 514 ifp->if_capabilities |= IFCAP_VLAN_MTU; 515 ifp->if_capenable |= IFCAP_VLAN_MTU; 516 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM; 517 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM; 518 519 /* init task queue */ 520 TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc); 521 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc); 522 TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc); 523 524 sc->rx_process_limit = 100; 525 526 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT, 527 taskqueue_thread_enqueue, &sc->taskqueue); 528 529 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq", 530 device_get_nameunit(sc->dev)); 531 532 rt_sysctl_attach(sc); 533 534 /* set up interrupt */ 535 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 536 NULL, (sc->rt_chipid == RT_CHIPID_RT5350 || 537 sc->rt_chipid == RT_CHIPID_MT7620) ? rt_rt5350_intr : rt_intr, 538 sc, &sc->irqh); 539 if (error != 0) { 540 printf("%s: could not set up interrupt\n", 541 device_get_nameunit(dev)); 542 goto fail; 543 } 544 #ifdef IF_RT_DEBUG 545 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug)); 546 #endif 547 548 return (0); 549 550 fail: 551 /* free Tx and Rx rings */ 552 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) 553 rt_free_tx_ring(sc, &sc->tx_ring[i]); 554 555 for (i = 0; i < sc->rx_ring_count; i++) 556 rt_free_rx_ring(sc, &sc->rx_ring[i]); 557 558 mtx_destroy(&sc->lock); 559 560 if (sc->mem != NULL) 561 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, 562 sc->mem); 563 564 if (sc->irq != NULL) 565 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 566 sc->irq); 567 568 return (error); 569 } 570 571 /* 572 * Set media options. 573 */ 574 static int 575 rt_ifmedia_upd(struct ifnet *ifp) 576 { 577 struct rt_softc *sc; 578 #ifdef IF_RT_PHY_SUPPORT 579 struct mii_data *mii; 580 struct mii_softc *miisc; 581 int error = 0; 582 583 sc = ifp->if_softc; 584 RT_SOFTC_LOCK(sc); 585 586 mii = device_get_softc(sc->rt_miibus); 587 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 588 PHY_RESET(miisc); 589 error = mii_mediachg(mii); 590 RT_SOFTC_UNLOCK(sc); 591 592 return (error); 593 594 #else /* !IF_RT_PHY_SUPPORT */ 595 596 struct ifmedia *ifm; 597 struct ifmedia_entry *ife; 598 599 sc = ifp->if_softc; 600 ifm = &sc->rt_ifmedia; 601 ife = ifm->ifm_cur; 602 603 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 604 return (EINVAL); 605 606 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 607 device_printf(sc->dev, 608 "AUTO is not supported for multiphy MAC"); 609 return (EINVAL); 610 } 611 612 /* 613 * Ignore everything 614 */ 615 return (0); 616 #endif /* IF_RT_PHY_SUPPORT */ 617 } 618 619 /* 620 * Report current media status. 621 */ 622 static void 623 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 624 { 625 #ifdef IF_RT_PHY_SUPPORT 626 struct rt_softc *sc; 627 struct mii_data *mii; 628 629 sc = ifp->if_softc; 630 631 RT_SOFTC_LOCK(sc); 632 mii = device_get_softc(sc->rt_miibus); 633 mii_pollstat(mii); 634 ifmr->ifm_active = mii->mii_media_active; 635 ifmr->ifm_status = mii->mii_media_status; 636 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 637 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 638 RT_SOFTC_UNLOCK(sc); 639 #else /* !IF_RT_PHY_SUPPORT */ 640 641 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 642 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 643 #endif /* IF_RT_PHY_SUPPORT */ 644 } 645 646 static int 647 rt_detach(device_t dev) 648 { 649 struct rt_softc *sc; 650 struct ifnet *ifp; 651 int i; 652 653 sc = device_get_softc(dev); 654 ifp = sc->ifp; 655 656 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n"); 657 658 RT_SOFTC_LOCK(sc); 659 660 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 661 662 callout_stop(&sc->periodic_ch); 663 callout_stop(&sc->tx_watchdog_ch); 664 665 taskqueue_drain(sc->taskqueue, &sc->rx_done_task); 666 taskqueue_drain(sc->taskqueue, &sc->tx_done_task); 667 taskqueue_drain(sc->taskqueue, &sc->periodic_task); 668 669 /* free Tx and Rx rings */ 670 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) 671 rt_free_tx_ring(sc, &sc->tx_ring[i]); 672 for (i = 0; i < sc->rx_ring_count; i++) 673 rt_free_rx_ring(sc, &sc->rx_ring[i]); 674 675 RT_SOFTC_UNLOCK(sc); 676 677 #ifdef IF_RT_PHY_SUPPORT 678 if (sc->rt_miibus != NULL) 679 device_delete_child(dev, sc->rt_miibus); 680 #endif 681 682 ether_ifdetach(ifp); 683 if_free(ifp); 684 685 taskqueue_free(sc->taskqueue); 686 687 mtx_destroy(&sc->lock); 688 689 bus_generic_detach(dev); 690 bus_teardown_intr(dev, sc->irq, sc->irqh); 691 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 692 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 693 694 return (0); 695 } 696 697 static int 698 rt_shutdown(device_t dev) 699 { 700 struct rt_softc *sc; 701 702 sc = device_get_softc(dev); 703 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n"); 704 rt_stop(sc); 705 706 return (0); 707 } 708 709 static int 710 rt_suspend(device_t dev) 711 { 712 struct rt_softc *sc; 713 714 sc = device_get_softc(dev); 715 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n"); 716 rt_stop(sc); 717 718 return (0); 719 } 720 721 static int 722 rt_resume(device_t dev) 723 { 724 struct rt_softc *sc; 725 struct ifnet *ifp; 726 727 sc = device_get_softc(dev); 728 ifp = sc->ifp; 729 730 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n"); 731 732 if (ifp->if_flags & IFF_UP) 733 rt_init(sc); 734 735 return (0); 736 } 737 738 /* 739 * rt_init_locked - Run initialization process having locked mtx. 740 */ 741 static void 742 rt_init_locked(void *priv) 743 { 744 struct rt_softc *sc; 745 struct ifnet *ifp; 746 #ifdef IF_RT_PHY_SUPPORT 747 struct mii_data *mii; 748 #endif 749 int i, ntries; 750 uint32_t tmp; 751 752 sc = priv; 753 ifp = sc->ifp; 754 #ifdef IF_RT_PHY_SUPPORT 755 mii = device_get_softc(sc->rt_miibus); 756 #endif 757 758 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n"); 759 760 RT_SOFTC_ASSERT_LOCKED(sc); 761 762 /* hardware reset */ 763 //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET); 764 //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG); 765 766 /* Fwd to CPU (uni|broad|multi)cast and Unknown */ 767 if(sc->rt_chipid == RT_CHIPID_RT3050 || sc->rt_chipid == RT_CHIPID_RT3052) 768 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG, 769 ( 770 GDM_ICS_EN | /* Enable IP Csum */ 771 GDM_TCS_EN | /* Enable TCP Csum */ 772 GDM_UCS_EN | /* Enable UDP Csum */ 773 GDM_STRPCRC | /* Strip CRC from packet */ 774 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */ 775 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */ 776 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */ 777 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */ 778 )); 779 780 /* disable DMA engine */ 781 RT_WRITE(sc, sc->pdma_glo_cfg, 0); 782 RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff); 783 784 /* wait while DMA engine is busy */ 785 for (ntries = 0; ntries < 100; ntries++) { 786 tmp = RT_READ(sc, sc->pdma_glo_cfg); 787 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY))) 788 break; 789 DELAY(1000); 790 } 791 792 if (ntries == 100) { 793 device_printf(sc->dev, "timeout waiting for DMA engine\n"); 794 goto fail; 795 } 796 797 /* reset Rx and Tx rings */ 798 tmp = FE_RST_DRX_IDX0 | 799 FE_RST_DTX_IDX3 | 800 FE_RST_DTX_IDX2 | 801 FE_RST_DTX_IDX1 | 802 FE_RST_DTX_IDX0; 803 804 RT_WRITE(sc, sc->pdma_rst_idx, tmp); 805 806 /* XXX switch set mac address */ 807 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) 808 rt_reset_tx_ring(sc, &sc->tx_ring[i]); 809 810 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 811 /* update TX_BASE_PTRx */ 812 RT_WRITE(sc, sc->tx_base_ptr[i], 813 sc->tx_ring[i].desc_phys_addr); 814 RT_WRITE(sc, sc->tx_max_cnt[i], 815 RT_SOFTC_TX_RING_DESC_COUNT); 816 RT_WRITE(sc, sc->tx_ctx_idx[i], 0); 817 } 818 819 /* init Rx ring */ 820 for (i = 0; i < sc->rx_ring_count; i++) 821 rt_reset_rx_ring(sc, &sc->rx_ring[i]); 822 823 /* update RX_BASE_PTRx */ 824 for (i = 0; i < sc->rx_ring_count; i++) { 825 RT_WRITE(sc, sc->rx_base_ptr[i], 826 sc->rx_ring[i].desc_phys_addr); 827 RT_WRITE(sc, sc->rx_max_cnt[i], 828 RT_SOFTC_RX_RING_DATA_COUNT); 829 RT_WRITE(sc, sc->rx_calc_idx[i], 830 RT_SOFTC_RX_RING_DATA_COUNT - 1); 831 } 832 833 /* write back DDONE, 16byte burst enable RX/TX DMA */ 834 tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN; 835 if (sc->rt_chipid == RT_CHIPID_MT7620) 836 tmp |= (1<<31); 837 RT_WRITE(sc, sc->pdma_glo_cfg, tmp); 838 839 /* disable interrupts mitigation */ 840 RT_WRITE(sc, sc->delay_int_cfg, 0); 841 842 /* clear pending interrupts */ 843 RT_WRITE(sc, sc->fe_int_status, 0xffffffff); 844 845 /* enable interrupts */ 846 if (sc->rt_chipid == RT_CHIPID_RT5350 || 847 sc->rt_chipid == RT_CHIPID_MT7620) 848 tmp = RT5350_INT_TX_COHERENT | 849 RT5350_INT_RX_COHERENT | 850 RT5350_INT_TXQ3_DONE | 851 RT5350_INT_TXQ2_DONE | 852 RT5350_INT_TXQ1_DONE | 853 RT5350_INT_TXQ0_DONE | 854 RT5350_INT_RXQ1_DONE | 855 RT5350_INT_RXQ0_DONE; 856 else 857 tmp = CNT_PPE_AF | 858 CNT_GDM_AF | 859 PSE_P2_FC | 860 GDM_CRC_DROP | 861 PSE_BUF_DROP | 862 GDM_OTHER_DROP | 863 PSE_P1_FC | 864 PSE_P0_FC | 865 PSE_FQ_EMPTY | 866 INT_TX_COHERENT | 867 INT_RX_COHERENT | 868 INT_TXQ3_DONE | 869 INT_TXQ2_DONE | 870 INT_TXQ1_DONE | 871 INT_TXQ0_DONE | 872 INT_RX_DONE; 873 874 sc->intr_enable_mask = tmp; 875 876 RT_WRITE(sc, sc->fe_int_enable, tmp); 877 878 if (rt_txrx_enable(sc) != 0) 879 goto fail; 880 881 #ifdef IF_RT_PHY_SUPPORT 882 if (mii) mii_mediachg(mii); 883 #endif /* IF_RT_PHY_SUPPORT */ 884 885 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 886 ifp->if_drv_flags |= IFF_DRV_RUNNING; 887 888 sc->periodic_round = 0; 889 890 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc); 891 892 return; 893 894 fail: 895 rt_stop_locked(sc); 896 } 897 898 /* 899 * rt_init - lock and initialize device. 900 */ 901 static void 902 rt_init(void *priv) 903 { 904 struct rt_softc *sc; 905 906 sc = priv; 907 RT_SOFTC_LOCK(sc); 908 rt_init_locked(sc); 909 RT_SOFTC_UNLOCK(sc); 910 } 911 912 /* 913 * rt_stop_locked - stop TX/RX w/ lock 914 */ 915 static void 916 rt_stop_locked(void *priv) 917 { 918 struct rt_softc *sc; 919 struct ifnet *ifp; 920 921 sc = priv; 922 ifp = sc->ifp; 923 924 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n"); 925 926 RT_SOFTC_ASSERT_LOCKED(sc); 927 sc->tx_timer = 0; 928 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 929 callout_stop(&sc->periodic_ch); 930 callout_stop(&sc->tx_watchdog_ch); 931 RT_SOFTC_UNLOCK(sc); 932 taskqueue_block(sc->taskqueue); 933 934 /* 935 * Sometime rt_stop_locked called from isr and we get panic 936 * When found, I fix it 937 */ 938 #ifdef notyet 939 taskqueue_drain(sc->taskqueue, &sc->rx_done_task); 940 taskqueue_drain(sc->taskqueue, &sc->tx_done_task); 941 taskqueue_drain(sc->taskqueue, &sc->periodic_task); 942 #endif 943 RT_SOFTC_LOCK(sc); 944 945 /* disable interrupts */ 946 RT_WRITE(sc, sc->fe_int_enable, 0); 947 948 if(sc->rt_chipid == RT_CHIPID_RT5350 || 949 sc->rt_chipid == RT_CHIPID_MT7620) { 950 } else { 951 /* reset adapter */ 952 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET); 953 954 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG, 955 ( 956 GDM_ICS_EN | /* Enable IP Csum */ 957 GDM_TCS_EN | /* Enable TCP Csum */ 958 GDM_UCS_EN | /* Enable UDP Csum */ 959 GDM_STRPCRC | /* Strip CRC from packet */ 960 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */ 961 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */ 962 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */ 963 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */ 964 )); 965 } 966 } 967 968 static void 969 rt_stop(void *priv) 970 { 971 struct rt_softc *sc; 972 973 sc = priv; 974 RT_SOFTC_LOCK(sc); 975 rt_stop_locked(sc); 976 RT_SOFTC_UNLOCK(sc); 977 } 978 979 /* 980 * rt_tx_data - transmit packet. 981 */ 982 static int 983 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid) 984 { 985 struct ifnet *ifp; 986 struct rt_softc_tx_ring *ring; 987 struct rt_softc_tx_data *data; 988 struct rt_txdesc *desc; 989 struct mbuf *m_d; 990 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER]; 991 int error, ndmasegs, ndescs, i; 992 993 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT, 994 ("%s: Tx data: invalid qid=%d\n", 995 device_get_nameunit(sc->dev), qid)); 996 997 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]); 998 999 ifp = sc->ifp; 1000 ring = &sc->tx_ring[qid]; 1001 desc = &ring->desc[ring->desc_cur]; 1002 data = &ring->data[ring->data_cur]; 1003 1004 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m, 1005 dma_seg, &ndmasegs, 0); 1006 if (error != 0) { 1007 /* too many fragments, linearize */ 1008 1009 RT_DPRINTF(sc, RT_DEBUG_TX, 1010 "could not load mbuf DMA map, trying to linearize " 1011 "mbuf: ndmasegs=%d, len=%d, error=%d\n", 1012 ndmasegs, m->m_pkthdr.len, error); 1013 1014 m_d = m_collapse(m, M_NOWAIT, 16); 1015 if (m_d == NULL) { 1016 m_freem(m); 1017 m = NULL; 1018 return (ENOMEM); 1019 } 1020 m = m_d; 1021 1022 sc->tx_defrag_packets++; 1023 1024 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, 1025 data->dma_map, m, dma_seg, &ndmasegs, 0); 1026 if (error != 0) { 1027 device_printf(sc->dev, "could not load mbuf DMA map: " 1028 "ndmasegs=%d, len=%d, error=%d\n", 1029 ndmasegs, m->m_pkthdr.len, error); 1030 m_freem(m); 1031 return (error); 1032 } 1033 } 1034 1035 if (m->m_pkthdr.len == 0) 1036 ndmasegs = 0; 1037 1038 /* determine how many Tx descs are required */ 1039 ndescs = 1 + ndmasegs / 2; 1040 if ((ring->desc_queued + ndescs) > 1041 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) { 1042 RT_DPRINTF(sc, RT_DEBUG_TX, 1043 "there are not enough Tx descs\n"); 1044 1045 sc->no_tx_desc_avail++; 1046 1047 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 1048 m_freem(m); 1049 return (EFBIG); 1050 } 1051 1052 data->m = m; 1053 1054 /* set up Tx descs */ 1055 for (i = 0; i < ndmasegs; i += 2) { 1056 1057 /* TODO: this needs to be refined as MT7620 for example has 1058 * a different word3 layout than RT305x and RT5350 (the last 1059 * one doesn't use word3 at all). 1060 */ 1061 1062 /* Set destination */ 1063 if (sc->rt_chipid != RT_CHIPID_MT7620) 1064 desc->dst = (TXDSCR_DST_PORT_GDMA1); 1065 1066 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1067 desc->dst |= (TXDSCR_IP_CSUM_GEN|TXDSCR_UDP_CSUM_GEN| 1068 TXDSCR_TCP_CSUM_GEN); 1069 /* Set queue id */ 1070 desc->qn = qid; 1071 /* No PPPoE */ 1072 desc->pppoe = 0; 1073 /* No VLAN */ 1074 desc->vid = 0; 1075 1076 desc->sdp0 = htole32(dma_seg[i].ds_addr); 1077 desc->sdl0 = htole16(dma_seg[i].ds_len | 1078 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 )); 1079 1080 if ((i+1) < ndmasegs) { 1081 desc->sdp1 = htole32(dma_seg[i+1].ds_addr); 1082 desc->sdl1 = htole16(dma_seg[i+1].ds_len | 1083 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 )); 1084 } else { 1085 desc->sdp1 = 0; 1086 desc->sdl1 = 0; 1087 } 1088 1089 if ((i+2) < ndmasegs) { 1090 ring->desc_queued++; 1091 ring->desc_cur = (ring->desc_cur + 1) % 1092 RT_SOFTC_TX_RING_DESC_COUNT; 1093 } 1094 desc = &ring->desc[ring->desc_cur]; 1095 } 1096 1097 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, " 1098 "DMA ds_len=%d/%d/%d/%d/%d\n", 1099 m->m_pkthdr.len, ndmasegs, 1100 (int) dma_seg[0].ds_len, 1101 (int) dma_seg[1].ds_len, 1102 (int) dma_seg[2].ds_len, 1103 (int) dma_seg[3].ds_len, 1104 (int) dma_seg[4].ds_len); 1105 1106 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, 1107 BUS_DMASYNC_PREWRITE); 1108 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 1109 BUS_DMASYNC_PREWRITE); 1110 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 1111 BUS_DMASYNC_PREWRITE); 1112 1113 ring->desc_queued++; 1114 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT; 1115 1116 ring->data_queued++; 1117 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT; 1118 1119 /* kick Tx */ 1120 RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur); 1121 1122 return (0); 1123 } 1124 1125 /* 1126 * rt_start - start Transmit/Receive 1127 */ 1128 static void 1129 rt_start(struct ifnet *ifp) 1130 { 1131 struct rt_softc *sc; 1132 struct mbuf *m; 1133 int qid = 0 /* XXX must check QoS priority */; 1134 1135 sc = ifp->if_softc; 1136 1137 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1138 return; 1139 1140 for (;;) { 1141 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1142 if (m == NULL) 1143 break; 1144 1145 m->m_pkthdr.rcvif = NULL; 1146 1147 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]); 1148 1149 if (sc->tx_ring[qid].data_queued >= 1150 RT_SOFTC_TX_RING_DATA_COUNT) { 1151 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); 1152 1153 RT_DPRINTF(sc, RT_DEBUG_TX, 1154 "if_start: Tx ring with qid=%d is full\n", qid); 1155 1156 m_freem(m); 1157 1158 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1159 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1160 1161 sc->tx_data_queue_full[qid]++; 1162 1163 break; 1164 } 1165 1166 if (rt_tx_data(sc, m, qid) != 0) { 1167 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); 1168 1169 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1170 1171 break; 1172 } 1173 1174 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); 1175 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT; 1176 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc); 1177 } 1178 } 1179 1180 /* 1181 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because 1182 * filtering done by attached Ethernet switch. 1183 */ 1184 static void 1185 rt_update_promisc(struct ifnet *ifp) 1186 { 1187 struct rt_softc *sc; 1188 1189 sc = ifp->if_softc; 1190 printf("%s: %s promiscuous mode\n", 1191 device_get_nameunit(sc->dev), 1192 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving"); 1193 } 1194 1195 /* 1196 * rt_ioctl - ioctl handler. 1197 */ 1198 static int 1199 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1200 { 1201 struct rt_softc *sc; 1202 struct ifreq *ifr; 1203 #ifdef IF_RT_PHY_SUPPORT 1204 struct mii_data *mii; 1205 #endif /* IF_RT_PHY_SUPPORT */ 1206 int error, startall; 1207 1208 sc = ifp->if_softc; 1209 ifr = (struct ifreq *) data; 1210 1211 error = 0; 1212 1213 switch (cmd) { 1214 case SIOCSIFFLAGS: 1215 startall = 0; 1216 RT_SOFTC_LOCK(sc); 1217 if (ifp->if_flags & IFF_UP) { 1218 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1219 if ((ifp->if_flags ^ sc->if_flags) & 1220 IFF_PROMISC) 1221 rt_update_promisc(ifp); 1222 } else { 1223 rt_init_locked(sc); 1224 startall = 1; 1225 } 1226 } else { 1227 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1228 rt_stop_locked(sc); 1229 } 1230 sc->if_flags = ifp->if_flags; 1231 RT_SOFTC_UNLOCK(sc); 1232 break; 1233 case SIOCGIFMEDIA: 1234 case SIOCSIFMEDIA: 1235 #ifdef IF_RT_PHY_SUPPORT 1236 mii = device_get_softc(sc->rt_miibus); 1237 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1238 #else 1239 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd); 1240 #endif /* IF_RT_PHY_SUPPORT */ 1241 break; 1242 default: 1243 error = ether_ioctl(ifp, cmd, data); 1244 break; 1245 } 1246 return (error); 1247 } 1248 1249 /* 1250 * rt_periodic - Handler of PERIODIC interrupt 1251 */ 1252 static void 1253 rt_periodic(void *arg) 1254 { 1255 struct rt_softc *sc; 1256 1257 sc = arg; 1258 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n"); 1259 taskqueue_enqueue(sc->taskqueue, &sc->periodic_task); 1260 } 1261 1262 /* 1263 * rt_tx_watchdog - Handler of TX Watchdog 1264 */ 1265 static void 1266 rt_tx_watchdog(void *arg) 1267 { 1268 struct rt_softc *sc; 1269 struct ifnet *ifp; 1270 1271 sc = arg; 1272 ifp = sc->ifp; 1273 1274 if (sc->tx_timer == 0) 1275 return; 1276 1277 if (--sc->tx_timer == 0) { 1278 device_printf(sc->dev, "Tx watchdog timeout: resetting\n"); 1279 #ifdef notyet 1280 /* 1281 * XXX: Commented out, because reset break input. 1282 */ 1283 rt_stop_locked(sc); 1284 rt_init_locked(sc); 1285 #endif 1286 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1287 sc->tx_watchdog_timeouts++; 1288 } 1289 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc); 1290 } 1291 1292 /* 1293 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt 1294 */ 1295 static void 1296 rt_cnt_ppe_af(struct rt_softc *sc) 1297 { 1298 1299 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n"); 1300 } 1301 1302 /* 1303 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt 1304 */ 1305 static void 1306 rt_cnt_gdm_af(struct rt_softc *sc) 1307 { 1308 1309 RT_DPRINTF(sc, RT_DEBUG_INTR, 1310 "GDMA 1 & 2 Counter Table Almost Full\n"); 1311 } 1312 1313 /* 1314 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt 1315 */ 1316 static void 1317 rt_pse_p2_fc(struct rt_softc *sc) 1318 { 1319 1320 RT_DPRINTF(sc, RT_DEBUG_INTR, 1321 "PSE port2 (GDMA 2) flow control asserted.\n"); 1322 } 1323 1324 /* 1325 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error 1326 * interrupt 1327 */ 1328 static void 1329 rt_gdm_crc_drop(struct rt_softc *sc) 1330 { 1331 1332 RT_DPRINTF(sc, RT_DEBUG_INTR, 1333 "GDMA 1 & 2 discard a packet due to CRC error\n"); 1334 } 1335 1336 /* 1337 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt 1338 */ 1339 static void 1340 rt_pse_buf_drop(struct rt_softc *sc) 1341 { 1342 1343 RT_DPRINTF(sc, RT_DEBUG_INTR, 1344 "PSE discards a packet due to buffer sharing limitation\n"); 1345 } 1346 1347 /* 1348 * rt_gdm_other_drop - Handler of discard on other reason interrupt 1349 */ 1350 static void 1351 rt_gdm_other_drop(struct rt_softc *sc) 1352 { 1353 1354 RT_DPRINTF(sc, RT_DEBUG_INTR, 1355 "GDMA 1 & 2 discard a packet due to other reason\n"); 1356 } 1357 1358 /* 1359 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt 1360 */ 1361 static void 1362 rt_pse_p1_fc(struct rt_softc *sc) 1363 { 1364 1365 RT_DPRINTF(sc, RT_DEBUG_INTR, 1366 "PSE port1 (GDMA 1) flow control asserted.\n"); 1367 } 1368 1369 /* 1370 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt 1371 */ 1372 static void 1373 rt_pse_p0_fc(struct rt_softc *sc) 1374 { 1375 1376 RT_DPRINTF(sc, RT_DEBUG_INTR, 1377 "PSE port0 (CDMA) flow control asserted.\n"); 1378 } 1379 1380 /* 1381 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt 1382 */ 1383 static void 1384 rt_pse_fq_empty(struct rt_softc *sc) 1385 { 1386 1387 RT_DPRINTF(sc, RT_DEBUG_INTR, 1388 "PSE free Q empty threshold reached & forced drop " 1389 "condition occurred.\n"); 1390 } 1391 1392 /* 1393 * rt_intr - main ISR 1394 */ 1395 static void 1396 rt_intr(void *arg) 1397 { 1398 struct rt_softc *sc; 1399 struct ifnet *ifp; 1400 uint32_t status; 1401 1402 sc = arg; 1403 ifp = sc->ifp; 1404 1405 /* acknowledge interrupts */ 1406 status = RT_READ(sc, sc->fe_int_status); 1407 RT_WRITE(sc, sc->fe_int_status, status); 1408 1409 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status); 1410 1411 if (status == 0xffffffff || /* device likely went away */ 1412 status == 0) /* not for us */ 1413 return; 1414 1415 sc->interrupts++; 1416 1417 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1418 return; 1419 1420 if (status & CNT_PPE_AF) 1421 rt_cnt_ppe_af(sc); 1422 1423 if (status & CNT_GDM_AF) 1424 rt_cnt_gdm_af(sc); 1425 1426 if (status & PSE_P2_FC) 1427 rt_pse_p2_fc(sc); 1428 1429 if (status & GDM_CRC_DROP) 1430 rt_gdm_crc_drop(sc); 1431 1432 if (status & PSE_BUF_DROP) 1433 rt_pse_buf_drop(sc); 1434 1435 if (status & GDM_OTHER_DROP) 1436 rt_gdm_other_drop(sc); 1437 1438 if (status & PSE_P1_FC) 1439 rt_pse_p1_fc(sc); 1440 1441 if (status & PSE_P0_FC) 1442 rt_pse_p0_fc(sc); 1443 1444 if (status & PSE_FQ_EMPTY) 1445 rt_pse_fq_empty(sc); 1446 1447 if (status & INT_TX_COHERENT) 1448 rt_tx_coherent_intr(sc); 1449 1450 if (status & INT_RX_COHERENT) 1451 rt_rx_coherent_intr(sc); 1452 1453 if (status & RX_DLY_INT) 1454 rt_rx_delay_intr(sc); 1455 1456 if (status & TX_DLY_INT) 1457 rt_tx_delay_intr(sc); 1458 1459 if (status & INT_RX_DONE) 1460 rt_rx_intr(sc, 0); 1461 1462 if (status & INT_TXQ3_DONE) 1463 rt_tx_intr(sc, 3); 1464 1465 if (status & INT_TXQ2_DONE) 1466 rt_tx_intr(sc, 2); 1467 1468 if (status & INT_TXQ1_DONE) 1469 rt_tx_intr(sc, 1); 1470 1471 if (status & INT_TXQ0_DONE) 1472 rt_tx_intr(sc, 0); 1473 } 1474 1475 /* 1476 * rt_rt5350_intr - main ISR for Ralink 5350 SoC 1477 */ 1478 static void 1479 rt_rt5350_intr(void *arg) 1480 { 1481 struct rt_softc *sc; 1482 struct ifnet *ifp; 1483 uint32_t status; 1484 1485 sc = arg; 1486 ifp = sc->ifp; 1487 1488 /* acknowledge interrupts */ 1489 status = RT_READ(sc, sc->fe_int_status); 1490 RT_WRITE(sc, sc->fe_int_status, status); 1491 1492 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status); 1493 1494 if (status == 0xffffffff || /* device likely went away */ 1495 status == 0) /* not for us */ 1496 return; 1497 1498 sc->interrupts++; 1499 1500 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1501 return; 1502 1503 if (status & RT5350_INT_TX_COHERENT) 1504 rt_tx_coherent_intr(sc); 1505 if (status & RT5350_INT_RX_COHERENT) 1506 rt_rx_coherent_intr(sc); 1507 if (status & RT5350_RX_DLY_INT) 1508 rt_rx_delay_intr(sc); 1509 if (status & RT5350_TX_DLY_INT) 1510 rt_tx_delay_intr(sc); 1511 if (status & RT5350_INT_RXQ1_DONE) 1512 rt_rx_intr(sc, 1); 1513 if (status & RT5350_INT_RXQ0_DONE) 1514 rt_rx_intr(sc, 0); 1515 if (status & RT5350_INT_TXQ3_DONE) 1516 rt_tx_intr(sc, 3); 1517 if (status & RT5350_INT_TXQ2_DONE) 1518 rt_tx_intr(sc, 2); 1519 if (status & RT5350_INT_TXQ1_DONE) 1520 rt_tx_intr(sc, 1); 1521 if (status & RT5350_INT_TXQ0_DONE) 1522 rt_tx_intr(sc, 0); 1523 } 1524 1525 static void 1526 rt_tx_coherent_intr(struct rt_softc *sc) 1527 { 1528 uint32_t tmp; 1529 int i; 1530 1531 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n"); 1532 1533 sc->tx_coherent_interrupts++; 1534 1535 /* restart DMA engine */ 1536 tmp = RT_READ(sc, sc->pdma_glo_cfg); 1537 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN); 1538 RT_WRITE(sc, sc->pdma_glo_cfg, tmp); 1539 1540 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) 1541 rt_reset_tx_ring(sc, &sc->tx_ring[i]); 1542 1543 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 1544 RT_WRITE(sc, sc->tx_base_ptr[i], 1545 sc->tx_ring[i].desc_phys_addr); 1546 RT_WRITE(sc, sc->tx_max_cnt[i], 1547 RT_SOFTC_TX_RING_DESC_COUNT); 1548 RT_WRITE(sc, sc->tx_ctx_idx[i], 0); 1549 } 1550 1551 rt_txrx_enable(sc); 1552 } 1553 1554 /* 1555 * rt_rx_coherent_intr 1556 */ 1557 static void 1558 rt_rx_coherent_intr(struct rt_softc *sc) 1559 { 1560 uint32_t tmp; 1561 int i; 1562 1563 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n"); 1564 1565 sc->rx_coherent_interrupts++; 1566 1567 /* restart DMA engine */ 1568 tmp = RT_READ(sc, sc->pdma_glo_cfg); 1569 tmp &= ~(FE_RX_DMA_EN); 1570 RT_WRITE(sc, sc->pdma_glo_cfg, tmp); 1571 1572 /* init Rx ring */ 1573 for (i = 0; i < sc->rx_ring_count; i++) 1574 rt_reset_rx_ring(sc, &sc->rx_ring[i]); 1575 1576 for (i = 0; i < sc->rx_ring_count; i++) { 1577 RT_WRITE(sc, sc->rx_base_ptr[i], 1578 sc->rx_ring[i].desc_phys_addr); 1579 RT_WRITE(sc, sc->rx_max_cnt[i], 1580 RT_SOFTC_RX_RING_DATA_COUNT); 1581 RT_WRITE(sc, sc->rx_calc_idx[i], 1582 RT_SOFTC_RX_RING_DATA_COUNT - 1); 1583 } 1584 1585 rt_txrx_enable(sc); 1586 } 1587 1588 /* 1589 * rt_rx_intr - a packet received 1590 */ 1591 static void 1592 rt_rx_intr(struct rt_softc *sc, int qid) 1593 { 1594 KASSERT(qid >= 0 && qid < sc->rx_ring_count, 1595 ("%s: Rx interrupt: invalid qid=%d\n", 1596 device_get_nameunit(sc->dev), qid)); 1597 1598 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n"); 1599 sc->rx_interrupts[qid]++; 1600 RT_SOFTC_LOCK(sc); 1601 1602 if (!(sc->intr_disable_mask & (sc->int_rx_done_mask << qid))) { 1603 rt_intr_disable(sc, (sc->int_rx_done_mask << qid)); 1604 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task); 1605 } 1606 1607 sc->intr_pending_mask |= (sc->int_rx_done_mask << qid); 1608 RT_SOFTC_UNLOCK(sc); 1609 } 1610 1611 static void 1612 rt_rx_delay_intr(struct rt_softc *sc) 1613 { 1614 1615 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n"); 1616 sc->rx_delay_interrupts++; 1617 } 1618 1619 static void 1620 rt_tx_delay_intr(struct rt_softc *sc) 1621 { 1622 1623 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n"); 1624 sc->tx_delay_interrupts++; 1625 } 1626 1627 /* 1628 * rt_tx_intr - Transsmition of packet done 1629 */ 1630 static void 1631 rt_tx_intr(struct rt_softc *sc, int qid) 1632 { 1633 1634 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT, 1635 ("%s: Tx interrupt: invalid qid=%d\n", 1636 device_get_nameunit(sc->dev), qid)); 1637 1638 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid); 1639 1640 sc->tx_interrupts[qid]++; 1641 RT_SOFTC_LOCK(sc); 1642 1643 if (!(sc->intr_disable_mask & (sc->int_tx_done_mask << qid))) { 1644 rt_intr_disable(sc, (sc->int_tx_done_mask << qid)); 1645 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task); 1646 } 1647 1648 sc->intr_pending_mask |= (sc->int_tx_done_mask << qid); 1649 RT_SOFTC_UNLOCK(sc); 1650 } 1651 1652 /* 1653 * rt_rx_done_task - run RX task 1654 */ 1655 static void 1656 rt_rx_done_task(void *context, int pending) 1657 { 1658 struct rt_softc *sc; 1659 struct ifnet *ifp; 1660 int again; 1661 1662 sc = context; 1663 ifp = sc->ifp; 1664 1665 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n"); 1666 1667 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1668 return; 1669 1670 sc->intr_pending_mask &= ~sc->int_rx_done_mask; 1671 1672 again = rt_rx_eof(sc, &sc->rx_ring[0], sc->rx_process_limit); 1673 1674 RT_SOFTC_LOCK(sc); 1675 1676 if ((sc->intr_pending_mask & sc->int_rx_done_mask) || again) { 1677 RT_DPRINTF(sc, RT_DEBUG_RX, 1678 "Rx done task: scheduling again\n"); 1679 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task); 1680 } else { 1681 rt_intr_enable(sc, sc->int_rx_done_mask); 1682 } 1683 1684 RT_SOFTC_UNLOCK(sc); 1685 } 1686 1687 /* 1688 * rt_tx_done_task - check for pending TX task in all queues 1689 */ 1690 static void 1691 rt_tx_done_task(void *context, int pending) 1692 { 1693 struct rt_softc *sc; 1694 struct ifnet *ifp; 1695 uint32_t intr_mask; 1696 int i; 1697 1698 sc = context; 1699 ifp = sc->ifp; 1700 1701 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n"); 1702 1703 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1704 return; 1705 1706 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) { 1707 if (sc->intr_pending_mask & (sc->int_tx_done_mask << i)) { 1708 sc->intr_pending_mask &= ~(sc->int_tx_done_mask << i); 1709 rt_tx_eof(sc, &sc->tx_ring[i]); 1710 } 1711 } 1712 1713 sc->tx_timer = 0; 1714 1715 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1716 1717 if(sc->rt_chipid == RT_CHIPID_RT5350 || 1718 sc->rt_chipid == RT_CHIPID_MT7620) 1719 intr_mask = ( 1720 RT5350_INT_TXQ3_DONE | 1721 RT5350_INT_TXQ2_DONE | 1722 RT5350_INT_TXQ1_DONE | 1723 RT5350_INT_TXQ0_DONE); 1724 else 1725 intr_mask = ( 1726 INT_TXQ3_DONE | 1727 INT_TXQ2_DONE | 1728 INT_TXQ1_DONE | 1729 INT_TXQ0_DONE); 1730 1731 RT_SOFTC_LOCK(sc); 1732 1733 rt_intr_enable(sc, ~sc->intr_pending_mask & 1734 (sc->intr_disable_mask & intr_mask)); 1735 1736 if (sc->intr_pending_mask & intr_mask) { 1737 RT_DPRINTF(sc, RT_DEBUG_TX, 1738 "Tx done task: scheduling again\n"); 1739 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task); 1740 } 1741 1742 RT_SOFTC_UNLOCK(sc); 1743 1744 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1745 rt_start(ifp); 1746 } 1747 1748 /* 1749 * rt_periodic_task - run periodic task 1750 */ 1751 static void 1752 rt_periodic_task(void *context, int pending) 1753 { 1754 struct rt_softc *sc; 1755 struct ifnet *ifp; 1756 1757 sc = context; 1758 ifp = sc->ifp; 1759 1760 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n", 1761 sc->periodic_round); 1762 1763 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1764 return; 1765 1766 RT_SOFTC_LOCK(sc); 1767 sc->periodic_round++; 1768 rt_update_stats(sc); 1769 1770 if ((sc->periodic_round % 10) == 0) { 1771 rt_update_raw_counters(sc); 1772 rt_watchdog(sc); 1773 } 1774 1775 RT_SOFTC_UNLOCK(sc); 1776 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc); 1777 } 1778 1779 /* 1780 * rt_rx_eof - check for frames that done by DMA engine and pass it into 1781 * network subsystem. 1782 */ 1783 static int 1784 rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit) 1785 { 1786 struct ifnet *ifp; 1787 /* struct rt_softc_rx_ring *ring; */ 1788 struct rt_rxdesc *desc; 1789 struct rt_softc_rx_data *data; 1790 struct mbuf *m, *mnew; 1791 bus_dma_segment_t segs[1]; 1792 bus_dmamap_t dma_map; 1793 uint32_t index, desc_flags; 1794 int error, nsegs, len, nframes; 1795 1796 ifp = sc->ifp; 1797 /* ring = &sc->rx_ring[0]; */ 1798 1799 nframes = 0; 1800 1801 while (limit != 0) { 1802 index = RT_READ(sc, sc->rx_drx_idx[0]); 1803 if (ring->cur == index) 1804 break; 1805 1806 desc = &ring->desc[ring->cur]; 1807 data = &ring->data[ring->cur]; 1808 1809 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 1810 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1811 1812 #ifdef IF_RT_DEBUG 1813 if ( sc->debug & RT_DEBUG_RX ) { 1814 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc); 1815 hexdump(desc, 16, 0, 0); 1816 printf("-----------------------------------\n"); 1817 } 1818 #endif 1819 1820 /* XXX Sometime device don`t set DDONE bit */ 1821 #ifdef DDONE_FIXED 1822 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) { 1823 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n"); 1824 break; 1825 } 1826 #endif 1827 1828 len = le16toh(desc->sdl0) & 0x3fff; 1829 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len); 1830 1831 nframes++; 1832 1833 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1834 MJUMPAGESIZE); 1835 if (mnew == NULL) { 1836 sc->rx_mbuf_alloc_errors++; 1837 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1838 goto skip; 1839 } 1840 1841 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE; 1842 1843 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, 1844 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT); 1845 if (error != 0) { 1846 RT_DPRINTF(sc, RT_DEBUG_RX, 1847 "could not load Rx mbuf DMA map: " 1848 "error=%d, nsegs=%d\n", 1849 error, nsegs); 1850 1851 m_freem(mnew); 1852 1853 sc->rx_mbuf_dmamap_errors++; 1854 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1855 1856 goto skip; 1857 } 1858 1859 KASSERT(nsegs == 1, ("%s: too many DMA segments", 1860 device_get_nameunit(sc->dev))); 1861 1862 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 1863 BUS_DMASYNC_POSTREAD); 1864 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 1865 1866 dma_map = data->dma_map; 1867 data->dma_map = ring->spare_dma_map; 1868 ring->spare_dma_map = dma_map; 1869 1870 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 1871 BUS_DMASYNC_PREREAD); 1872 1873 m = data->m; 1874 desc_flags = desc->src; 1875 1876 data->m = mnew; 1877 /* Add 2 for proper align of RX IP header */ 1878 desc->sdp0 = htole32(segs[0].ds_addr+2); 1879 desc->sdl0 = htole32(segs[0].ds_len-2); 1880 desc->src = 0; 1881 desc->ai = 0; 1882 desc->foe = 0; 1883 1884 RT_DPRINTF(sc, RT_DEBUG_RX, 1885 "Rx frame: rxdesc flags=0x%08x\n", desc_flags); 1886 1887 m->m_pkthdr.rcvif = ifp; 1888 /* Add 2 to fix data align, after sdp0 = addr + 2 */ 1889 m->m_data += 2; 1890 m->m_pkthdr.len = m->m_len = len; 1891 1892 /* check for crc errors */ 1893 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1894 /*check for valid checksum*/ 1895 if (desc_flags & (RXDSXR_SRC_IP_CSUM_FAIL| 1896 RXDSXR_SRC_L4_CSUM_FAIL)) { 1897 RT_DPRINTF(sc, RT_DEBUG_RX, 1898 "rxdesc: crc error\n"); 1899 1900 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1901 1902 if (!(ifp->if_flags & IFF_PROMISC)) { 1903 m_freem(m); 1904 goto skip; 1905 } 1906 } 1907 if ((desc_flags & RXDSXR_SRC_IP_CSUM_FAIL) != 0) { 1908 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1909 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1910 m->m_pkthdr.csum_data = 0xffff; 1911 } 1912 m->m_flags &= ~M_HASFCS; 1913 } 1914 1915 (*ifp->if_input)(ifp, m); 1916 skip: 1917 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE); 1918 1919 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 1920 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1921 1922 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT; 1923 1924 limit--; 1925 } 1926 1927 if (ring->cur == 0) 1928 RT_WRITE(sc, sc->rx_calc_idx[0], 1929 RT_SOFTC_RX_RING_DATA_COUNT - 1); 1930 else 1931 RT_WRITE(sc, sc->rx_calc_idx[0], 1932 ring->cur - 1); 1933 1934 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes); 1935 1936 sc->rx_packets += nframes; 1937 1938 return (limit == 0); 1939 } 1940 1941 /* 1942 * rt_tx_eof - check for successful transmitted frames and mark their 1943 * descriptor as free. 1944 */ 1945 static void 1946 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring) 1947 { 1948 struct ifnet *ifp; 1949 struct rt_txdesc *desc; 1950 struct rt_softc_tx_data *data; 1951 uint32_t index; 1952 int ndescs, nframes; 1953 1954 ifp = sc->ifp; 1955 1956 ndescs = 0; 1957 nframes = 0; 1958 1959 for (;;) { 1960 index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]); 1961 if (ring->desc_next == index) 1962 break; 1963 1964 ndescs++; 1965 1966 desc = &ring->desc[ring->desc_next]; 1967 1968 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 1969 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1970 1971 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) || 1972 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) { 1973 nframes++; 1974 1975 data = &ring->data[ring->data_next]; 1976 1977 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 1978 BUS_DMASYNC_POSTWRITE); 1979 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 1980 1981 m_freem(data->m); 1982 1983 data->m = NULL; 1984 1985 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1986 1987 RT_SOFTC_TX_RING_LOCK(ring); 1988 ring->data_queued--; 1989 ring->data_next = (ring->data_next + 1) % 1990 RT_SOFTC_TX_RING_DATA_COUNT; 1991 RT_SOFTC_TX_RING_UNLOCK(ring); 1992 } 1993 1994 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE); 1995 1996 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 1997 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1998 1999 RT_SOFTC_TX_RING_LOCK(ring); 2000 ring->desc_queued--; 2001 ring->desc_next = (ring->desc_next + 1) % 2002 RT_SOFTC_TX_RING_DESC_COUNT; 2003 RT_SOFTC_TX_RING_UNLOCK(ring); 2004 } 2005 2006 RT_DPRINTF(sc, RT_DEBUG_TX, 2007 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs, 2008 nframes); 2009 } 2010 2011 /* 2012 * rt_update_stats - query statistics counters and update related variables. 2013 */ 2014 static void 2015 rt_update_stats(struct rt_softc *sc) 2016 { 2017 struct ifnet *ifp; 2018 2019 ifp = sc->ifp; 2020 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n"); 2021 /* XXX do update stats here */ 2022 } 2023 2024 /* 2025 * rt_watchdog - reinit device on watchdog event. 2026 */ 2027 static void 2028 rt_watchdog(struct rt_softc *sc) 2029 { 2030 uint32_t tmp; 2031 #ifdef notyet 2032 int ntries; 2033 #endif 2034 if(sc->rt_chipid != RT_CHIPID_RT5350 && 2035 sc->rt_chipid != RT_CHIPID_MT7620) { 2036 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA); 2037 2038 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG, 2039 "watchdog: PSE_IQ_STA=0x%08x\n", tmp); 2040 } 2041 /* XXX: do not reset */ 2042 #ifdef notyet 2043 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) { 2044 sc->tx_queue_not_empty[0]++; 2045 2046 for (ntries = 0; ntries < 10; ntries++) { 2047 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA); 2048 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0) 2049 break; 2050 2051 DELAY(1); 2052 } 2053 } 2054 2055 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) { 2056 sc->tx_queue_not_empty[1]++; 2057 2058 for (ntries = 0; ntries < 10; ntries++) { 2059 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA); 2060 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0) 2061 break; 2062 2063 DELAY(1); 2064 } 2065 } 2066 #endif 2067 } 2068 2069 /* 2070 * rt_update_raw_counters - update counters. 2071 */ 2072 static void 2073 rt_update_raw_counters(struct rt_softc *sc) 2074 { 2075 2076 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0); 2077 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0); 2078 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0); 2079 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0); 2080 2081 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0); 2082 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0); 2083 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0); 2084 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0); 2085 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0); 2086 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0); 2087 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0); 2088 } 2089 2090 static void 2091 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask) 2092 { 2093 uint32_t tmp; 2094 2095 sc->intr_disable_mask &= ~intr_mask; 2096 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask; 2097 RT_WRITE(sc, sc->fe_int_enable, tmp); 2098 } 2099 2100 static void 2101 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask) 2102 { 2103 uint32_t tmp; 2104 2105 sc->intr_disable_mask |= intr_mask; 2106 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask; 2107 RT_WRITE(sc, sc->fe_int_enable, tmp); 2108 } 2109 2110 /* 2111 * rt_txrx_enable - enable TX/RX DMA 2112 */ 2113 static int 2114 rt_txrx_enable(struct rt_softc *sc) 2115 { 2116 struct ifnet *ifp; 2117 uint32_t tmp; 2118 int ntries; 2119 2120 ifp = sc->ifp; 2121 2122 /* enable Tx/Rx DMA engine */ 2123 for (ntries = 0; ntries < 200; ntries++) { 2124 tmp = RT_READ(sc, sc->pdma_glo_cfg); 2125 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY))) 2126 break; 2127 2128 DELAY(1000); 2129 } 2130 2131 if (ntries == 200) { 2132 device_printf(sc->dev, "timeout waiting for DMA engine\n"); 2133 return (-1); 2134 } 2135 2136 DELAY(50); 2137 2138 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN; 2139 RT_WRITE(sc, sc->pdma_glo_cfg, tmp); 2140 2141 /* XXX set Rx filter */ 2142 return (0); 2143 } 2144 2145 /* 2146 * rt_alloc_rx_ring - allocate RX DMA ring buffer 2147 */ 2148 static int 2149 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid) 2150 { 2151 struct rt_rxdesc *desc; 2152 struct rt_softc_rx_data *data; 2153 bus_dma_segment_t segs[1]; 2154 int i, nsegs, error; 2155 2156 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2157 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2158 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1, 2159 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 2160 0, NULL, NULL, &ring->desc_dma_tag); 2161 if (error != 0) { 2162 device_printf(sc->dev, 2163 "could not create Rx desc DMA tag\n"); 2164 goto fail; 2165 } 2166 2167 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc, 2168 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map); 2169 if (error != 0) { 2170 device_printf(sc->dev, 2171 "could not allocate Rx desc DMA memory\n"); 2172 goto fail; 2173 } 2174 2175 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map, 2176 ring->desc, 2177 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 2178 rt_dma_map_addr, &ring->desc_phys_addr, 0); 2179 if (error != 0) { 2180 device_printf(sc->dev, "could not load Rx desc DMA map\n"); 2181 goto fail; 2182 } 2183 2184 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2185 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2186 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL, 2187 &ring->data_dma_tag); 2188 if (error != 0) { 2189 device_printf(sc->dev, 2190 "could not create Rx data DMA tag\n"); 2191 goto fail; 2192 } 2193 2194 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { 2195 desc = &ring->desc[i]; 2196 data = &ring->data[i]; 2197 2198 error = bus_dmamap_create(ring->data_dma_tag, 0, 2199 &data->dma_map); 2200 if (error != 0) { 2201 device_printf(sc->dev, "could not create Rx data DMA " 2202 "map\n"); 2203 goto fail; 2204 } 2205 2206 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 2207 MJUMPAGESIZE); 2208 if (data->m == NULL) { 2209 device_printf(sc->dev, "could not allocate Rx mbuf\n"); 2210 error = ENOMEM; 2211 goto fail; 2212 } 2213 2214 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE; 2215 2216 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, 2217 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT); 2218 if (error != 0) { 2219 device_printf(sc->dev, 2220 "could not load Rx mbuf DMA map\n"); 2221 goto fail; 2222 } 2223 2224 KASSERT(nsegs == 1, ("%s: too many DMA segments", 2225 device_get_nameunit(sc->dev))); 2226 2227 /* Add 2 for proper align of RX IP header */ 2228 desc->sdp0 = htole32(segs[0].ds_addr+2); 2229 desc->sdl0 = htole32(segs[0].ds_len-2); 2230 } 2231 2232 error = bus_dmamap_create(ring->data_dma_tag, 0, 2233 &ring->spare_dma_map); 2234 if (error != 0) { 2235 device_printf(sc->dev, 2236 "could not create Rx spare DMA map\n"); 2237 goto fail; 2238 } 2239 2240 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2241 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2242 ring->qid = qid; 2243 return (0); 2244 2245 fail: 2246 rt_free_rx_ring(sc, ring); 2247 return (error); 2248 } 2249 2250 /* 2251 * rt_reset_rx_ring - reset RX ring buffer 2252 */ 2253 static void 2254 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring) 2255 { 2256 struct rt_rxdesc *desc; 2257 int i; 2258 2259 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { 2260 desc = &ring->desc[i]; 2261 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE); 2262 } 2263 2264 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2265 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2266 ring->cur = 0; 2267 } 2268 2269 /* 2270 * rt_free_rx_ring - free memory used by RX ring buffer 2271 */ 2272 static void 2273 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring) 2274 { 2275 struct rt_softc_rx_data *data; 2276 int i; 2277 2278 if (ring->desc != NULL) { 2279 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2280 BUS_DMASYNC_POSTWRITE); 2281 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map); 2282 bus_dmamem_free(ring->desc_dma_tag, ring->desc, 2283 ring->desc_dma_map); 2284 } 2285 2286 if (ring->desc_dma_tag != NULL) 2287 bus_dma_tag_destroy(ring->desc_dma_tag); 2288 2289 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { 2290 data = &ring->data[i]; 2291 2292 if (data->m != NULL) { 2293 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 2294 BUS_DMASYNC_POSTREAD); 2295 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 2296 m_freem(data->m); 2297 } 2298 2299 if (data->dma_map != NULL) 2300 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map); 2301 } 2302 2303 if (ring->spare_dma_map != NULL) 2304 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map); 2305 2306 if (ring->data_dma_tag != NULL) 2307 bus_dma_tag_destroy(ring->data_dma_tag); 2308 } 2309 2310 /* 2311 * rt_alloc_tx_ring - allocate TX ring buffer 2312 */ 2313 static int 2314 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid) 2315 { 2316 struct rt_softc_tx_data *data; 2317 int error, i; 2318 2319 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF); 2320 2321 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2322 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2323 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1, 2324 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 2325 0, NULL, NULL, &ring->desc_dma_tag); 2326 if (error != 0) { 2327 device_printf(sc->dev, 2328 "could not create Tx desc DMA tag\n"); 2329 goto fail; 2330 } 2331 2332 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc, 2333 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map); 2334 if (error != 0) { 2335 device_printf(sc->dev, 2336 "could not allocate Tx desc DMA memory\n"); 2337 goto fail; 2338 } 2339 2340 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map, 2341 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT * 2342 sizeof(struct rt_txdesc)), rt_dma_map_addr, 2343 &ring->desc_phys_addr, 0); 2344 if (error != 0) { 2345 device_printf(sc->dev, "could not load Tx desc DMA map\n"); 2346 goto fail; 2347 } 2348 2349 ring->desc_queued = 0; 2350 ring->desc_cur = 0; 2351 ring->desc_next = 0; 2352 2353 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2354 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2355 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1, 2356 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 2357 0, NULL, NULL, &ring->seg0_dma_tag); 2358 if (error != 0) { 2359 device_printf(sc->dev, 2360 "could not create Tx seg0 DMA tag\n"); 2361 goto fail; 2362 } 2363 2364 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0, 2365 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map); 2366 if (error != 0) { 2367 device_printf(sc->dev, 2368 "could not allocate Tx seg0 DMA memory\n"); 2369 goto fail; 2370 } 2371 2372 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map, 2373 ring->seg0, 2374 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 2375 rt_dma_map_addr, &ring->seg0_phys_addr, 0); 2376 if (error != 0) { 2377 device_printf(sc->dev, "could not load Tx seg0 DMA map\n"); 2378 goto fail; 2379 } 2380 2381 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2382 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2383 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL, 2384 &ring->data_dma_tag); 2385 if (error != 0) { 2386 device_printf(sc->dev, 2387 "could not create Tx data DMA tag\n"); 2388 goto fail; 2389 } 2390 2391 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { 2392 data = &ring->data[i]; 2393 2394 error = bus_dmamap_create(ring->data_dma_tag, 0, 2395 &data->dma_map); 2396 if (error != 0) { 2397 device_printf(sc->dev, "could not create Tx data DMA " 2398 "map\n"); 2399 goto fail; 2400 } 2401 } 2402 2403 ring->data_queued = 0; 2404 ring->data_cur = 0; 2405 ring->data_next = 0; 2406 2407 ring->qid = qid; 2408 return (0); 2409 2410 fail: 2411 rt_free_tx_ring(sc, ring); 2412 return (error); 2413 } 2414 2415 /* 2416 * rt_reset_tx_ring - reset TX ring buffer to empty state 2417 */ 2418 static void 2419 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring) 2420 { 2421 struct rt_softc_tx_data *data; 2422 struct rt_txdesc *desc; 2423 int i; 2424 2425 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) { 2426 desc = &ring->desc[i]; 2427 2428 desc->sdl0 = 0; 2429 desc->sdl1 = 0; 2430 } 2431 2432 ring->desc_queued = 0; 2433 ring->desc_cur = 0; 2434 ring->desc_next = 0; 2435 2436 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2437 BUS_DMASYNC_PREWRITE); 2438 2439 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, 2440 BUS_DMASYNC_PREWRITE); 2441 2442 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { 2443 data = &ring->data[i]; 2444 2445 if (data->m != NULL) { 2446 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 2447 BUS_DMASYNC_POSTWRITE); 2448 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 2449 m_freem(data->m); 2450 data->m = NULL; 2451 } 2452 } 2453 2454 ring->data_queued = 0; 2455 ring->data_cur = 0; 2456 ring->data_next = 0; 2457 } 2458 2459 /* 2460 * rt_free_tx_ring - free RX ring buffer 2461 */ 2462 static void 2463 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring) 2464 { 2465 struct rt_softc_tx_data *data; 2466 int i; 2467 2468 if (ring->desc != NULL) { 2469 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2470 BUS_DMASYNC_POSTWRITE); 2471 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map); 2472 bus_dmamem_free(ring->desc_dma_tag, ring->desc, 2473 ring->desc_dma_map); 2474 } 2475 2476 if (ring->desc_dma_tag != NULL) 2477 bus_dma_tag_destroy(ring->desc_dma_tag); 2478 2479 if (ring->seg0 != NULL) { 2480 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, 2481 BUS_DMASYNC_POSTWRITE); 2482 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map); 2483 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0, 2484 ring->seg0_dma_map); 2485 } 2486 2487 if (ring->seg0_dma_tag != NULL) 2488 bus_dma_tag_destroy(ring->seg0_dma_tag); 2489 2490 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { 2491 data = &ring->data[i]; 2492 2493 if (data->m != NULL) { 2494 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 2495 BUS_DMASYNC_POSTWRITE); 2496 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 2497 m_freem(data->m); 2498 } 2499 2500 if (data->dma_map != NULL) 2501 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map); 2502 } 2503 2504 if (ring->data_dma_tag != NULL) 2505 bus_dma_tag_destroy(ring->data_dma_tag); 2506 2507 mtx_destroy(&ring->lock); 2508 } 2509 2510 /* 2511 * rt_dma_map_addr - get address of busdma segment 2512 */ 2513 static void 2514 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2515 { 2516 if (error != 0) 2517 return; 2518 2519 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 2520 2521 *(bus_addr_t *) arg = segs[0].ds_addr; 2522 } 2523 2524 /* 2525 * rt_sysctl_attach - attach sysctl nodes for NIC counters. 2526 */ 2527 static void 2528 rt_sysctl_attach(struct rt_softc *sc) 2529 { 2530 struct sysctl_ctx_list *ctx; 2531 struct sysctl_oid *tree; 2532 struct sysctl_oid *stats; 2533 2534 ctx = device_get_sysctl_ctx(sc->dev); 2535 tree = device_get_sysctl_tree(sc->dev); 2536 2537 /* statistic counters */ 2538 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2539 "stats", CTLFLAG_RD, 0, "statistic"); 2540 2541 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2542 "interrupts", CTLFLAG_RD, &sc->interrupts, 2543 "all interrupts"); 2544 2545 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2546 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts, 2547 "Tx coherent interrupts"); 2548 2549 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2550 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts, 2551 "Rx coherent interrupts"); 2552 2553 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2554 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts[0], 2555 "Rx interrupts"); 2556 2557 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2558 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts, 2559 "Rx delay interrupts"); 2560 2561 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2562 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3], 2563 "Tx AC3 interrupts"); 2564 2565 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2566 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2], 2567 "Tx AC2 interrupts"); 2568 2569 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2570 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1], 2571 "Tx AC1 interrupts"); 2572 2573 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2574 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0], 2575 "Tx AC0 interrupts"); 2576 2577 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2578 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts, 2579 "Tx delay interrupts"); 2580 2581 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2582 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued, 2583 0, "Tx AC3 descriptors queued"); 2584 2585 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2586 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued, 2587 0, "Tx AC3 data queued"); 2588 2589 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2590 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued, 2591 0, "Tx AC2 descriptors queued"); 2592 2593 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2594 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued, 2595 0, "Tx AC2 data queued"); 2596 2597 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2598 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued, 2599 0, "Tx AC1 descriptors queued"); 2600 2601 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2602 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued, 2603 0, "Tx AC1 data queued"); 2604 2605 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2606 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued, 2607 0, "Tx AC0 descriptors queued"); 2608 2609 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2610 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued, 2611 0, "Tx AC0 data queued"); 2612 2613 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2614 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3], 2615 "Tx AC3 data queue full"); 2616 2617 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2618 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2], 2619 "Tx AC2 data queue full"); 2620 2621 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2622 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1], 2623 "Tx AC1 data queue full"); 2624 2625 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2626 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0], 2627 "Tx AC0 data queue full"); 2628 2629 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2630 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts, 2631 "Tx watchdog timeouts"); 2632 2633 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2634 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets, 2635 "Tx defragmented packets"); 2636 2637 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2638 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail, 2639 "no Tx descriptors available"); 2640 2641 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2642 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors, 2643 "Rx mbuf allocation errors"); 2644 2645 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2646 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors, 2647 "Rx mbuf DMA mapping errors"); 2648 2649 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2650 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0], 2651 "Tx queue 0 not empty"); 2652 2653 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2654 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1], 2655 "Tx queue 1 not empty"); 2656 2657 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2658 "rx_packets", CTLFLAG_RD, &sc->rx_packets, 2659 "Rx packets"); 2660 2661 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2662 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err, 2663 "Rx CRC errors"); 2664 2665 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2666 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err, 2667 "Rx PHY errors"); 2668 2669 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2670 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets, 2671 "Rx duplicate packets"); 2672 2673 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2674 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows, 2675 "Rx FIFO overflows"); 2676 2677 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2678 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes, 2679 "Rx bytes"); 2680 2681 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2682 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err, 2683 "Rx too long frame errors"); 2684 2685 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2686 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err, 2687 "Rx too short frame errors"); 2688 2689 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2690 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes, 2691 "Tx bytes"); 2692 2693 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2694 "tx_packets", CTLFLAG_RD, &sc->tx_packets, 2695 "Tx packets"); 2696 2697 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2698 "tx_skip", CTLFLAG_RD, &sc->tx_skip, 2699 "Tx skip count for GDMA ports"); 2700 2701 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2702 "tx_collision", CTLFLAG_RD, &sc->tx_collision, 2703 "Tx collision count for GDMA ports"); 2704 } 2705 2706 #ifdef IF_RT_PHY_SUPPORT 2707 static int 2708 rt_miibus_readreg(device_t dev, int phy, int reg) 2709 { 2710 struct rt_softc *sc = device_get_softc(dev); 2711 2712 /* 2713 * PSEUDO_PHYAD is a special value for indicate switch attached. 2714 * No one PHY use PSEUDO_PHYAD (0x1e) address. 2715 */ 2716 if (phy == 31) { 2717 /* Fake PHY ID for bfeswitch attach */ 2718 switch (reg) { 2719 case MII_BMSR: 2720 return (BMSR_EXTSTAT|BMSR_MEDIAMASK); 2721 case MII_PHYIDR1: 2722 return (0x40); /* As result of faking */ 2723 case MII_PHYIDR2: /* PHY will detect as */ 2724 return (0x6250); /* bfeswitch */ 2725 } 2726 } 2727 2728 /* Wait prev command done if any */ 2729 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); 2730 RT_WRITE(sc, MDIO_ACCESS, 2731 MDIO_CMD_ONGO || 2732 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) || 2733 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK)); 2734 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); 2735 2736 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK); 2737 } 2738 2739 static int 2740 rt_miibus_writereg(device_t dev, int phy, int reg, int val) 2741 { 2742 struct rt_softc *sc = device_get_softc(dev); 2743 2744 /* Wait prev command done if any */ 2745 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); 2746 RT_WRITE(sc, MDIO_ACCESS, 2747 MDIO_CMD_ONGO || MDIO_CMD_WR || 2748 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) || 2749 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) || 2750 (val & MDIO_PHY_DATA_MASK)); 2751 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); 2752 2753 return (0); 2754 } 2755 2756 void 2757 rt_miibus_statchg(device_t dev) 2758 { 2759 struct rt_softc *sc = device_get_softc(dev); 2760 struct mii_data *mii; 2761 2762 mii = device_get_softc(sc->rt_miibus); 2763 2764 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2765 (IFM_ACTIVE | IFM_AVALID)) { 2766 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2767 case IFM_10_T: 2768 case IFM_100_TX: 2769 /* XXX check link here */ 2770 sc->flags |= 1; 2771 break; 2772 default: 2773 break; 2774 } 2775 } 2776 } 2777 #endif /* IF_RT_PHY_SUPPORT */ 2778 2779 static device_method_t rt_dev_methods[] = 2780 { 2781 DEVMETHOD(device_probe, rt_probe), 2782 DEVMETHOD(device_attach, rt_attach), 2783 DEVMETHOD(device_detach, rt_detach), 2784 DEVMETHOD(device_shutdown, rt_shutdown), 2785 DEVMETHOD(device_suspend, rt_suspend), 2786 DEVMETHOD(device_resume, rt_resume), 2787 2788 #ifdef IF_RT_PHY_SUPPORT 2789 /* MII interface */ 2790 DEVMETHOD(miibus_readreg, rt_miibus_readreg), 2791 DEVMETHOD(miibus_writereg, rt_miibus_writereg), 2792 DEVMETHOD(miibus_statchg, rt_miibus_statchg), 2793 #endif 2794 2795 DEVMETHOD_END 2796 }; 2797 2798 static driver_t rt_driver = 2799 { 2800 "rt", 2801 rt_dev_methods, 2802 sizeof(struct rt_softc) 2803 }; 2804 2805 static devclass_t rt_dev_class; 2806 2807 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0); 2808 #ifdef FDT 2809 DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0); 2810 #endif 2811 2812 MODULE_DEPEND(rt, ether, 1, 1, 1); 2813 MODULE_DEPEND(rt, miibus, 1, 1, 1); 2814 2815