1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2000 Berkeley Software Design, Inc. 5 * Copyright (c) 1997, 1998, 1999, 2000 6 * Bill Paul <[email protected]>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available 41 * from http://www.amd.com. 42 * 43 * The AMD PCnet/PCI controllers are more advanced and functional 44 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 45 * backwards compatibility with the LANCE and thus can be made 46 * to work with older LANCE drivers. This is in fact how the 47 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 48 * is that the PCnet/PCI devices offer several performance enhancements 49 * which can't be exploited in LANCE compatibility mode. Chief among 50 * these enhancements is the ability to perform PCI DMA operations 51 * using 32-bit addressing (which eliminates the need for ISA 52 * bounce-buffering), and special receive buffer alignment (which 53 * allows the receive handler to pass packets to the upper protocol 54 * layers without copying on both the x86 and alpha platforms). 55 */ 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/sockio.h> 60 #include <sys/mbuf.h> 61 #include <sys/malloc.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/socket.h> 65 66 #include <net/if.h> 67 #include <net/if_var.h> 68 #include <net/if_arp.h> 69 #include <net/ethernet.h> 70 #include <net/if_dl.h> 71 #include <net/if_media.h> 72 #include <net/if_types.h> 73 74 #include <net/bpf.h> 75 76 #include <vm/vm.h> /* for vtophys */ 77 #include <vm/pmap.h> /* for vtophys */ 78 #include <machine/bus.h> 79 #include <machine/resource.h> 80 #include <sys/bus.h> 81 #include <sys/rman.h> 82 83 #include <dev/mii/mii.h> 84 #include <dev/mii/miivar.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 89 #define PCN_USEIOSPACE 90 91 #include <dev/pcn/if_pcnreg.h> 92 93 MODULE_DEPEND(pcn, pci, 1, 1, 1); 94 MODULE_DEPEND(pcn, ether, 1, 1, 1); 95 MODULE_DEPEND(pcn, miibus, 1, 1, 1); 96 97 /* "device miibus" required. See GENERIC if you get errors here. */ 98 #include "miibus_if.h" 99 100 /* 101 * Various supported device vendors/types and their names. 102 */ 103 static const struct pcn_type pcn_devs[] = { 104 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 105 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 106 { 0, 0, NULL } 107 }; 108 109 static const struct pcn_chipid { 110 u_int32_t id; 111 const char *name; 112 } pcn_chipid[] = { 113 { Am79C971, "Am79C971" }, 114 { Am79C972, "Am79C972" }, 115 { Am79C973, "Am79C973" }, 116 { Am79C978, "Am79C978" }, 117 { Am79C975, "Am79C975" }, 118 { Am79C976, "Am79C976" }, 119 { 0, NULL }, 120 }; 121 122 static const char *pcn_chipid_name(u_int32_t); 123 static u_int32_t pcn_chip_id(device_t); 124 static const struct pcn_type *pcn_match(u_int16_t, u_int16_t); 125 126 static u_int32_t pcn_csr_read(struct pcn_softc *, int); 127 static u_int16_t pcn_csr_read16(struct pcn_softc *, int); 128 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int); 129 static void pcn_csr_write(struct pcn_softc *, int, int); 130 static u_int32_t pcn_bcr_read(struct pcn_softc *, int); 131 static void pcn_bcr_write(struct pcn_softc *, int, int); 132 133 static int pcn_probe(device_t); 134 static int pcn_attach(device_t); 135 static int pcn_detach(device_t); 136 137 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *); 138 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *); 139 static void pcn_rxeof(struct pcn_softc *); 140 static void pcn_txeof(struct pcn_softc *); 141 static void pcn_intr(void *); 142 static void pcn_tick(void *); 143 static void pcn_start(struct ifnet *); 144 static void pcn_start_locked(struct ifnet *); 145 static int pcn_ioctl(struct ifnet *, u_long, caddr_t); 146 static void pcn_init(void *); 147 static void pcn_init_locked(struct pcn_softc *); 148 static void pcn_stop(struct pcn_softc *); 149 static void pcn_watchdog(struct pcn_softc *); 150 static int pcn_shutdown(device_t); 151 static int pcn_ifmedia_upd(struct ifnet *); 152 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *); 153 154 static int pcn_miibus_readreg(device_t, int, int); 155 static int pcn_miibus_writereg(device_t, int, int, int); 156 static void pcn_miibus_statchg(device_t); 157 158 static void pcn_setfilt(struct ifnet *); 159 static void pcn_setmulti(struct pcn_softc *); 160 static void pcn_reset(struct pcn_softc *); 161 static int pcn_list_rx_init(struct pcn_softc *); 162 static int pcn_list_tx_init(struct pcn_softc *); 163 164 #ifdef PCN_USEIOSPACE 165 #define PCN_RES SYS_RES_IOPORT 166 #define PCN_RID PCN_PCI_LOIO 167 #else 168 #define PCN_RES SYS_RES_MEMORY 169 #define PCN_RID PCN_PCI_LOMEM 170 #endif 171 172 static device_method_t pcn_methods[] = { 173 /* Device interface */ 174 DEVMETHOD(device_probe, pcn_probe), 175 DEVMETHOD(device_attach, pcn_attach), 176 DEVMETHOD(device_detach, pcn_detach), 177 DEVMETHOD(device_shutdown, pcn_shutdown), 178 179 /* MII interface */ 180 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 181 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 182 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 183 184 DEVMETHOD_END 185 }; 186 187 static driver_t pcn_driver = { 188 "pcn", 189 pcn_methods, 190 sizeof(struct pcn_softc) 191 }; 192 193 static devclass_t pcn_devclass; 194 195 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 196 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 197 198 #define PCN_CSR_SETBIT(sc, reg, x) \ 199 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 200 201 #define PCN_CSR_CLRBIT(sc, reg, x) \ 202 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 203 204 #define PCN_BCR_SETBIT(sc, reg, x) \ 205 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 206 207 #define PCN_BCR_CLRBIT(sc, reg, x) \ 208 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 209 210 static u_int32_t 211 pcn_csr_read(sc, reg) 212 struct pcn_softc *sc; 213 int reg; 214 { 215 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 216 return(CSR_READ_4(sc, PCN_IO32_RDP)); 217 } 218 219 static u_int16_t 220 pcn_csr_read16(sc, reg) 221 struct pcn_softc *sc; 222 int reg; 223 { 224 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 225 return(CSR_READ_2(sc, PCN_IO16_RDP)); 226 } 227 228 static void 229 pcn_csr_write(sc, reg, val) 230 struct pcn_softc *sc; 231 int reg; 232 int val; 233 { 234 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 235 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 236 return; 237 } 238 239 static u_int32_t 240 pcn_bcr_read(sc, reg) 241 struct pcn_softc *sc; 242 int reg; 243 { 244 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 245 return(CSR_READ_4(sc, PCN_IO32_BDP)); 246 } 247 248 static u_int16_t 249 pcn_bcr_read16(sc, reg) 250 struct pcn_softc *sc; 251 int reg; 252 { 253 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 254 return(CSR_READ_2(sc, PCN_IO16_BDP)); 255 } 256 257 static void 258 pcn_bcr_write(sc, reg, val) 259 struct pcn_softc *sc; 260 int reg; 261 int val; 262 { 263 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 264 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 265 return; 266 } 267 268 static int 269 pcn_miibus_readreg(dev, phy, reg) 270 device_t dev; 271 int phy, reg; 272 { 273 struct pcn_softc *sc; 274 int val; 275 276 sc = device_get_softc(dev); 277 278 /* 279 * At least Am79C971 with DP83840A wedge when isolating the 280 * external PHY so we can't allow multiple external PHYs. 281 * There are cards that use Am79C971 with both the internal 282 * and an external PHY though. 283 * For internal PHYs it doesn't really matter whether we can 284 * isolate the remaining internal and the external ones in 285 * the PHY drivers as the internal PHYs have to be enabled 286 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc. 287 * With Am79C97{3,5,8} we don't support switching beetween 288 * the internal and external PHYs, yet, so we can't allow 289 * multiple PHYs with these either. 290 * Am79C97{2,6} actually only support external PHYs (not 291 * connectable internal ones respond at the usual addresses, 292 * which don't hurt if we let them show up on the bus) and 293 * isolating them works. 294 */ 295 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) || 296 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 || 297 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr != -1 && 298 phy != sc->pcn_extphyaddr) 299 return(0); 300 301 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 302 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 303 if (val == 0xFFFF) 304 return(0); 305 306 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) || 307 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 || 308 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr == -1) 309 sc->pcn_extphyaddr = phy; 310 311 return(val); 312 } 313 314 static int 315 pcn_miibus_writereg(dev, phy, reg, data) 316 device_t dev; 317 int phy, reg, data; 318 { 319 struct pcn_softc *sc; 320 321 sc = device_get_softc(dev); 322 323 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 324 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 325 326 return(0); 327 } 328 329 static void 330 pcn_miibus_statchg(dev) 331 device_t dev; 332 { 333 struct pcn_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->pcn_miibus); 338 339 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 340 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 341 } else { 342 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 343 } 344 345 return; 346 } 347 348 static void 349 pcn_setmulti(sc) 350 struct pcn_softc *sc; 351 { 352 struct ifnet *ifp; 353 struct ifmultiaddr *ifma; 354 u_int32_t h, i; 355 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 356 357 ifp = sc->pcn_ifp; 358 359 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 360 361 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 362 for (i = 0; i < 4; i++) 363 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 364 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 365 return; 366 } 367 368 /* first, zot all the existing hash bits */ 369 for (i = 0; i < 4; i++) 370 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 371 372 /* now program new ones */ 373 if_maddr_rlock(ifp); 374 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 375 if (ifma->ifma_addr->sa_family != AF_LINK) 376 continue; 377 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 378 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 379 hashes[h >> 4] |= 1 << (h & 0xF); 380 } 381 if_maddr_runlock(ifp); 382 383 for (i = 0; i < 4; i++) 384 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 385 386 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 387 388 return; 389 } 390 391 static void 392 pcn_reset(sc) 393 struct pcn_softc *sc; 394 { 395 /* 396 * Issue a reset by reading from the RESET register. 397 * Note that we don't know if the chip is operating in 398 * 16-bit or 32-bit mode at this point, so we attempt 399 * to reset the chip both ways. If one fails, the other 400 * will succeed. 401 */ 402 CSR_READ_2(sc, PCN_IO16_RESET); 403 CSR_READ_4(sc, PCN_IO32_RESET); 404 405 /* Wait a little while for the chip to get its brains in order. */ 406 DELAY(1000); 407 408 /* Select 32-bit (DWIO) mode */ 409 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 410 411 /* Select software style 3. */ 412 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 413 414 return; 415 } 416 417 static const char * 418 pcn_chipid_name(u_int32_t id) 419 { 420 const struct pcn_chipid *p; 421 422 p = pcn_chipid; 423 while (p->name) { 424 if (id == p->id) 425 return (p->name); 426 p++; 427 } 428 return ("Unknown"); 429 } 430 431 static u_int32_t 432 pcn_chip_id(device_t dev) 433 { 434 struct pcn_softc *sc; 435 u_int32_t chip_id; 436 437 sc = device_get_softc(dev); 438 /* 439 * Note: we can *NOT* put the chip into 440 * 32-bit mode yet. The le(4) driver will only 441 * work in 16-bit mode, and once the chip 442 * goes into 32-bit mode, the only way to 443 * get it out again is with a hardware reset. 444 * So if pcn_probe() is called before the 445 * le(4) driver's probe routine, the chip will 446 * be locked into 32-bit operation and the 447 * le(4) driver will be unable to attach to it. 448 * Note II: if the chip happens to already 449 * be in 32-bit mode, we still need to check 450 * the chip ID, but first we have to detect 451 * 32-bit mode using only 16-bit operations. 452 * The safest way to do this is to read the 453 * PCI subsystem ID from BCR23/24 and compare 454 * that with the value read from PCI config 455 * space. 456 */ 457 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 458 chip_id <<= 16; 459 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 460 /* 461 * Note III: the test for 0x10001000 is a hack to 462 * pacify VMware, who's pseudo-PCnet interface is 463 * broken. Reading the subsystem register from PCI 464 * config space yields 0x00000000 while reading the 465 * same value from I/O space yields 0x10001000. It's 466 * not supposed to be that way. 467 */ 468 if (chip_id == pci_read_config(dev, 469 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 470 /* We're in 16-bit mode. */ 471 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 472 chip_id <<= 16; 473 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 474 } else { 475 /* We're in 32-bit mode. */ 476 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 477 chip_id <<= 16; 478 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 479 } 480 481 return (chip_id); 482 } 483 484 static const struct pcn_type * 485 pcn_match(u_int16_t vid, u_int16_t did) 486 { 487 const struct pcn_type *t; 488 489 t = pcn_devs; 490 while (t->pcn_name != NULL) { 491 if ((vid == t->pcn_vid) && (did == t->pcn_did)) 492 return (t); 493 t++; 494 } 495 return (NULL); 496 } 497 498 /* 499 * Probe for an AMD chip. Check the PCI vendor and device 500 * IDs against our list and return a device name if we find a match. 501 */ 502 static int 503 pcn_probe(dev) 504 device_t dev; 505 { 506 const struct pcn_type *t; 507 struct pcn_softc *sc; 508 int rid; 509 u_int32_t chip_id; 510 511 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev)); 512 if (t == NULL) 513 return (ENXIO); 514 sc = device_get_softc(dev); 515 516 /* 517 * Temporarily map the I/O space so we can read the chip ID register. 518 */ 519 rid = PCN_RID; 520 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 521 if (sc->pcn_res == NULL) { 522 device_printf(dev, "couldn't map ports/memory\n"); 523 return(ENXIO); 524 } 525 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 526 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 527 528 chip_id = pcn_chip_id(dev); 529 530 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 531 532 switch((chip_id >> 12) & PART_MASK) { 533 case Am79C971: 534 case Am79C972: 535 case Am79C973: 536 case Am79C975: 537 case Am79C976: 538 case Am79C978: 539 break; 540 default: 541 return(ENXIO); 542 } 543 device_set_desc(dev, t->pcn_name); 544 return(BUS_PROBE_DEFAULT); 545 } 546 547 /* 548 * Attach the interface. Allocate softc structures, do ifmedia 549 * setup and ethernet/BPF attach. 550 */ 551 static int 552 pcn_attach(dev) 553 device_t dev; 554 { 555 u_int32_t eaddr[2]; 556 struct pcn_softc *sc; 557 struct mii_data *mii; 558 struct mii_softc *miisc; 559 struct ifnet *ifp; 560 int error = 0, rid; 561 562 sc = device_get_softc(dev); 563 564 /* Initialize our mutex. */ 565 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 566 MTX_DEF); 567 /* 568 * Map control/status registers. 569 */ 570 pci_enable_busmaster(dev); 571 572 /* Retrieve the chip ID */ 573 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK; 574 device_printf(dev, "Chip ID %04x (%s)\n", 575 sc->pcn_type, pcn_chipid_name(sc->pcn_type)); 576 577 rid = PCN_RID; 578 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 579 580 if (sc->pcn_res == NULL) { 581 device_printf(dev, "couldn't map ports/memory\n"); 582 error = ENXIO; 583 goto fail; 584 } 585 586 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 587 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 588 589 /* Allocate interrupt */ 590 rid = 0; 591 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 592 RF_SHAREABLE | RF_ACTIVE); 593 594 if (sc->pcn_irq == NULL) { 595 device_printf(dev, "couldn't map interrupt\n"); 596 error = ENXIO; 597 goto fail; 598 } 599 600 /* Reset the adapter. */ 601 pcn_reset(sc); 602 603 /* 604 * Get station address from the EEPROM. 605 */ 606 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 607 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 608 609 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0); 610 611 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 612 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 613 614 if (sc->pcn_ldata == NULL) { 615 device_printf(dev, "no memory for list buffers!\n"); 616 error = ENXIO; 617 goto fail; 618 } 619 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 620 621 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER); 622 if (ifp == NULL) { 623 device_printf(dev, "can not if_alloc()\n"); 624 error = ENOSPC; 625 goto fail; 626 } 627 ifp->if_softc = sc; 628 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 629 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 630 ifp->if_ioctl = pcn_ioctl; 631 ifp->if_start = pcn_start; 632 ifp->if_init = pcn_init; 633 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 634 635 /* 636 * Do MII setup. 637 * See the comment in pcn_miibus_readreg() for why we can't 638 * universally pass MIIF_NOISOLATE here. 639 */ 640 sc->pcn_extphyaddr = -1; 641 error = mii_attach(dev, &sc->pcn_miibus, ifp, pcn_ifmedia_upd, 642 pcn_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 643 if (error != 0) { 644 device_printf(dev, "attaching PHYs failed\n"); 645 goto fail; 646 } 647 /* 648 * Record the media instances of internal PHYs, which map the 649 * built-in interfaces to the MII, so we can set the active 650 * PHY/port based on the currently selected media. 651 */ 652 sc->pcn_inst_10bt = -1; 653 mii = device_get_softc(sc->pcn_miibus); 654 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 655 switch (miisc->mii_phy) { 656 case PCN_PHYAD_10BT: 657 sc->pcn_inst_10bt = miisc->mii_inst; 658 break; 659 /* 660 * XXX deal with the Am79C97{3,5} internal 100baseT 661 * and the Am79C978 internal HomePNA PHYs. 662 */ 663 } 664 } 665 666 /* 667 * Call MI attach routine. 668 */ 669 ether_ifattach(ifp, (u_int8_t *) eaddr); 670 671 /* Hook interrupt last to avoid having to lock softc */ 672 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE, 673 NULL, pcn_intr, sc, &sc->pcn_intrhand); 674 675 if (error) { 676 device_printf(dev, "couldn't set up irq\n"); 677 ether_ifdetach(ifp); 678 goto fail; 679 } 680 681 fail: 682 if (error) 683 pcn_detach(dev); 684 685 return(error); 686 } 687 688 /* 689 * Shutdown hardware and free up resources. This can be called any 690 * time after the mutex has been initialized. It is called in both 691 * the error case in attach and the normal detach case so it needs 692 * to be careful about only freeing resources that have actually been 693 * allocated. 694 */ 695 static int 696 pcn_detach(dev) 697 device_t dev; 698 { 699 struct pcn_softc *sc; 700 struct ifnet *ifp; 701 702 sc = device_get_softc(dev); 703 ifp = sc->pcn_ifp; 704 705 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 706 707 /* These should only be active if attach succeeded */ 708 if (device_is_attached(dev)) { 709 PCN_LOCK(sc); 710 pcn_reset(sc); 711 pcn_stop(sc); 712 PCN_UNLOCK(sc); 713 callout_drain(&sc->pcn_stat_callout); 714 ether_ifdetach(ifp); 715 } 716 if (sc->pcn_miibus) 717 device_delete_child(dev, sc->pcn_miibus); 718 bus_generic_detach(dev); 719 720 if (sc->pcn_intrhand) 721 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 722 if (sc->pcn_irq) 723 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 724 if (sc->pcn_res) 725 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 726 727 if (ifp) 728 if_free(ifp); 729 730 if (sc->pcn_ldata) { 731 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 732 M_DEVBUF); 733 } 734 735 mtx_destroy(&sc->pcn_mtx); 736 737 return(0); 738 } 739 740 /* 741 * Initialize the transmit descriptors. 742 */ 743 static int 744 pcn_list_tx_init(sc) 745 struct pcn_softc *sc; 746 { 747 struct pcn_list_data *ld; 748 struct pcn_ring_data *cd; 749 int i; 750 751 cd = &sc->pcn_cdata; 752 ld = sc->pcn_ldata; 753 754 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 755 cd->pcn_tx_chain[i] = NULL; 756 ld->pcn_tx_list[i].pcn_tbaddr = 0; 757 ld->pcn_tx_list[i].pcn_txctl = 0; 758 ld->pcn_tx_list[i].pcn_txstat = 0; 759 } 760 761 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 762 763 return(0); 764 } 765 766 767 /* 768 * Initialize the RX descriptors and allocate mbufs for them. 769 */ 770 static int 771 pcn_list_rx_init(sc) 772 struct pcn_softc *sc; 773 { 774 struct pcn_ring_data *cd; 775 int i; 776 777 cd = &sc->pcn_cdata; 778 779 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 780 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 781 return(ENOBUFS); 782 } 783 784 cd->pcn_rx_prod = 0; 785 786 return(0); 787 } 788 789 /* 790 * Initialize an RX descriptor and attach an MBUF cluster. 791 */ 792 static int 793 pcn_newbuf(sc, idx, m) 794 struct pcn_softc *sc; 795 int idx; 796 struct mbuf *m; 797 { 798 struct mbuf *m_new = NULL; 799 struct pcn_rx_desc *c; 800 801 c = &sc->pcn_ldata->pcn_rx_list[idx]; 802 803 if (m == NULL) { 804 MGETHDR(m_new, M_NOWAIT, MT_DATA); 805 if (m_new == NULL) 806 return(ENOBUFS); 807 808 if (!(MCLGET(m_new, M_NOWAIT))) { 809 m_freem(m_new); 810 return(ENOBUFS); 811 } 812 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 813 } else { 814 m_new = m; 815 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 816 m_new->m_data = m_new->m_ext.ext_buf; 817 } 818 819 m_adj(m_new, ETHER_ALIGN); 820 821 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 822 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 823 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 824 c->pcn_bufsz |= PCN_RXLEN_MBO; 825 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 826 827 return(0); 828 } 829 830 /* 831 * A frame has been uploaded: pass the resulting mbuf chain up to 832 * the higher level protocols. 833 */ 834 static void 835 pcn_rxeof(sc) 836 struct pcn_softc *sc; 837 { 838 struct mbuf *m; 839 struct ifnet *ifp; 840 struct pcn_rx_desc *cur_rx; 841 int i; 842 843 PCN_LOCK_ASSERT(sc); 844 845 ifp = sc->pcn_ifp; 846 i = sc->pcn_cdata.pcn_rx_prod; 847 848 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 849 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 850 m = sc->pcn_cdata.pcn_rx_chain[i]; 851 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 852 853 /* 854 * If an error occurs, update stats, clear the 855 * status word and leave the mbuf cluster in place: 856 * it should simply get re-used next time this descriptor 857 * comes up in the ring. 858 */ 859 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 860 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 861 pcn_newbuf(sc, i, m); 862 PCN_INC(i, PCN_RX_LIST_CNT); 863 continue; 864 } 865 866 if (pcn_newbuf(sc, i, NULL)) { 867 /* Ran out of mbufs; recycle this one. */ 868 pcn_newbuf(sc, i, m); 869 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 870 PCN_INC(i, PCN_RX_LIST_CNT); 871 continue; 872 } 873 874 PCN_INC(i, PCN_RX_LIST_CNT); 875 876 /* No errors; receive the packet. */ 877 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 878 m->m_len = m->m_pkthdr.len = 879 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 880 m->m_pkthdr.rcvif = ifp; 881 882 PCN_UNLOCK(sc); 883 (*ifp->if_input)(ifp, m); 884 PCN_LOCK(sc); 885 } 886 887 sc->pcn_cdata.pcn_rx_prod = i; 888 889 return; 890 } 891 892 /* 893 * A frame was downloaded to the chip. It's safe for us to clean up 894 * the list buffers. 895 */ 896 897 static void 898 pcn_txeof(sc) 899 struct pcn_softc *sc; 900 { 901 struct pcn_tx_desc *cur_tx = NULL; 902 struct ifnet *ifp; 903 u_int32_t idx; 904 905 ifp = sc->pcn_ifp; 906 907 /* 908 * Go through our tx list and free mbufs for those 909 * frames that have been transmitted. 910 */ 911 idx = sc->pcn_cdata.pcn_tx_cons; 912 while (idx != sc->pcn_cdata.pcn_tx_prod) { 913 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 914 915 if (!PCN_OWN_TXDESC(cur_tx)) 916 break; 917 918 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 919 sc->pcn_cdata.pcn_tx_cnt--; 920 PCN_INC(idx, PCN_TX_LIST_CNT); 921 continue; 922 } 923 924 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 925 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 926 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 927 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 928 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 929 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 930 } 931 932 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 933 cur_tx->pcn_txstat & PCN_TXSTAT_TRC); 934 935 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 936 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 937 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 938 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 939 } 940 941 sc->pcn_cdata.pcn_tx_cnt--; 942 PCN_INC(idx, PCN_TX_LIST_CNT); 943 } 944 945 if (idx != sc->pcn_cdata.pcn_tx_cons) { 946 /* Some buffers have been freed. */ 947 sc->pcn_cdata.pcn_tx_cons = idx; 948 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 949 } 950 sc->pcn_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 951 952 return; 953 } 954 955 static void 956 pcn_tick(xsc) 957 void *xsc; 958 { 959 struct pcn_softc *sc; 960 struct mii_data *mii; 961 struct ifnet *ifp; 962 963 sc = xsc; 964 ifp = sc->pcn_ifp; 965 PCN_LOCK_ASSERT(sc); 966 967 mii = device_get_softc(sc->pcn_miibus); 968 mii_tick(mii); 969 970 /* link just died */ 971 if (sc->pcn_link && !(mii->mii_media_status & IFM_ACTIVE)) 972 sc->pcn_link = 0; 973 974 /* link just came up, restart */ 975 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 976 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 977 sc->pcn_link++; 978 if (ifp->if_snd.ifq_head != NULL) 979 pcn_start_locked(ifp); 980 } 981 982 if (sc->pcn_timer > 0 && --sc->pcn_timer == 0) 983 pcn_watchdog(sc); 984 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc); 985 986 return; 987 } 988 989 static void 990 pcn_intr(arg) 991 void *arg; 992 { 993 struct pcn_softc *sc; 994 struct ifnet *ifp; 995 u_int32_t status; 996 997 sc = arg; 998 ifp = sc->pcn_ifp; 999 1000 PCN_LOCK(sc); 1001 1002 /* Suppress unwanted interrupts */ 1003 if (!(ifp->if_flags & IFF_UP)) { 1004 pcn_stop(sc); 1005 PCN_UNLOCK(sc); 1006 return; 1007 } 1008 1009 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 1010 1011 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 1012 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 1013 1014 if (status & PCN_CSR_RINT) 1015 pcn_rxeof(sc); 1016 1017 if (status & PCN_CSR_TINT) 1018 pcn_txeof(sc); 1019 1020 if (status & PCN_CSR_ERR) { 1021 pcn_init_locked(sc); 1022 break; 1023 } 1024 } 1025 1026 if (ifp->if_snd.ifq_head != NULL) 1027 pcn_start_locked(ifp); 1028 1029 PCN_UNLOCK(sc); 1030 return; 1031 } 1032 1033 /* 1034 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1035 * pointers to the fragment pointers. 1036 */ 1037 static int 1038 pcn_encap(sc, m_head, txidx) 1039 struct pcn_softc *sc; 1040 struct mbuf *m_head; 1041 u_int32_t *txidx; 1042 { 1043 struct pcn_tx_desc *f = NULL; 1044 struct mbuf *m; 1045 int frag, cur, cnt = 0; 1046 1047 /* 1048 * Start packing the mbufs in this chain into 1049 * the fragment pointers. Stop when we run out 1050 * of fragments or hit the end of the mbuf chain. 1051 */ 1052 m = m_head; 1053 cur = frag = *txidx; 1054 1055 for (m = m_head; m != NULL; m = m->m_next) { 1056 if (m->m_len == 0) 1057 continue; 1058 1059 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1060 return(ENOBUFS); 1061 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1062 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1063 f->pcn_txctl |= PCN_TXCTL_MBO; 1064 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1065 if (cnt == 0) 1066 f->pcn_txctl |= PCN_TXCTL_STP; 1067 else 1068 f->pcn_txctl |= PCN_TXCTL_OWN; 1069 cur = frag; 1070 PCN_INC(frag, PCN_TX_LIST_CNT); 1071 cnt++; 1072 } 1073 1074 if (m != NULL) 1075 return(ENOBUFS); 1076 1077 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1078 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1079 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1080 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1081 sc->pcn_cdata.pcn_tx_cnt += cnt; 1082 *txidx = frag; 1083 1084 return(0); 1085 } 1086 1087 /* 1088 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1089 * to the mbuf data regions directly in the transmit lists. We also save a 1090 * copy of the pointers since the transmit list fragment pointers are 1091 * physical addresses. 1092 */ 1093 static void 1094 pcn_start(ifp) 1095 struct ifnet *ifp; 1096 { 1097 struct pcn_softc *sc; 1098 1099 sc = ifp->if_softc; 1100 PCN_LOCK(sc); 1101 pcn_start_locked(ifp); 1102 PCN_UNLOCK(sc); 1103 } 1104 1105 static void 1106 pcn_start_locked(ifp) 1107 struct ifnet *ifp; 1108 { 1109 struct pcn_softc *sc; 1110 struct mbuf *m_head = NULL; 1111 u_int32_t idx; 1112 1113 sc = ifp->if_softc; 1114 1115 PCN_LOCK_ASSERT(sc); 1116 1117 if (!sc->pcn_link) 1118 return; 1119 1120 idx = sc->pcn_cdata.pcn_tx_prod; 1121 1122 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1123 return; 1124 1125 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1126 IF_DEQUEUE(&ifp->if_snd, m_head); 1127 if (m_head == NULL) 1128 break; 1129 1130 if (pcn_encap(sc, m_head, &idx)) { 1131 IF_PREPEND(&ifp->if_snd, m_head); 1132 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1133 break; 1134 } 1135 1136 /* 1137 * If there's a BPF listener, bounce a copy of this frame 1138 * to him. 1139 */ 1140 BPF_MTAP(ifp, m_head); 1141 1142 } 1143 1144 /* Transmit */ 1145 sc->pcn_cdata.pcn_tx_prod = idx; 1146 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1147 1148 /* 1149 * Set a timeout in case the chip goes out to lunch. 1150 */ 1151 sc->pcn_timer = 5; 1152 1153 return; 1154 } 1155 1156 static void 1157 pcn_setfilt(ifp) 1158 struct ifnet *ifp; 1159 { 1160 struct pcn_softc *sc; 1161 1162 sc = ifp->if_softc; 1163 1164 /* If we want promiscuous mode, set the allframes bit. */ 1165 if (ifp->if_flags & IFF_PROMISC) { 1166 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1167 } else { 1168 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1169 } 1170 1171 /* Set the capture broadcast bit to capture broadcast frames. */ 1172 if (ifp->if_flags & IFF_BROADCAST) { 1173 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1174 } else { 1175 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1176 } 1177 1178 return; 1179 } 1180 1181 static void 1182 pcn_init(xsc) 1183 void *xsc; 1184 { 1185 struct pcn_softc *sc = xsc; 1186 1187 PCN_LOCK(sc); 1188 pcn_init_locked(sc); 1189 PCN_UNLOCK(sc); 1190 } 1191 1192 static void 1193 pcn_init_locked(sc) 1194 struct pcn_softc *sc; 1195 { 1196 struct ifnet *ifp = sc->pcn_ifp; 1197 struct mii_data *mii = NULL; 1198 struct ifmedia_entry *ife; 1199 1200 PCN_LOCK_ASSERT(sc); 1201 1202 /* 1203 * Cancel pending I/O and free all RX/TX buffers. 1204 */ 1205 pcn_stop(sc); 1206 pcn_reset(sc); 1207 1208 mii = device_get_softc(sc->pcn_miibus); 1209 ife = mii->mii_media.ifm_cur; 1210 1211 /* Set MAC address */ 1212 pcn_csr_write(sc, PCN_CSR_PAR0, 1213 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]); 1214 pcn_csr_write(sc, PCN_CSR_PAR1, 1215 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]); 1216 pcn_csr_write(sc, PCN_CSR_PAR2, 1217 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]); 1218 1219 /* Init circular RX list. */ 1220 if (pcn_list_rx_init(sc) == ENOBUFS) { 1221 if_printf(ifp, "initialization failed: no " 1222 "memory for rx buffers\n"); 1223 pcn_stop(sc); 1224 return; 1225 } 1226 1227 /* 1228 * Init tx descriptors. 1229 */ 1230 pcn_list_tx_init(sc); 1231 1232 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */ 1233 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL); 1234 1235 /* 1236 * Set up the port based on the currently selected media. 1237 * For Am79C978 we've to unconditionally set PCN_PORT_MII and 1238 * set the PHY in PCN_BCR_PHYSEL instead. 1239 */ 1240 if (sc->pcn_type != Am79C978 && 1241 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt) 1242 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET); 1243 else 1244 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1245 1246 /* Set up RX filter. */ 1247 pcn_setfilt(ifp); 1248 1249 /* 1250 * Load the multicast filter. 1251 */ 1252 pcn_setmulti(sc); 1253 1254 /* 1255 * Load the addresses of the RX and TX lists. 1256 */ 1257 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1258 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1259 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1260 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1261 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1262 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1263 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1264 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1265 1266 /* Set the RX and TX ring sizes. */ 1267 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1268 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1269 1270 /* We're not using the initialization block. */ 1271 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1272 1273 /* Enable fast suspend mode. */ 1274 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1275 1276 /* 1277 * Enable burst read and write. Also set the no underflow 1278 * bit. This will avoid transmit underruns in certain 1279 * conditions while still providing decent performance. 1280 */ 1281 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1282 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1283 1284 /* Enable graceful recovery from underflow. */ 1285 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1286 1287 /* Enable auto-padding of short TX frames. */ 1288 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1289 1290 /* Disable MII autoneg (we handle this ourselves). */ 1291 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1292 1293 if (sc->pcn_type == Am79C978) 1294 /* XXX support other PHYs? */ 1295 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1296 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1297 1298 /* Enable interrupts and start the controller running. */ 1299 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1300 1301 mii_mediachg(mii); 1302 1303 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1304 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1305 1306 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc); 1307 1308 return; 1309 } 1310 1311 /* 1312 * Set media options. 1313 */ 1314 static int 1315 pcn_ifmedia_upd(ifp) 1316 struct ifnet *ifp; 1317 { 1318 struct pcn_softc *sc; 1319 1320 sc = ifp->if_softc; 1321 1322 PCN_LOCK(sc); 1323 1324 /* 1325 * At least Am79C971 with DP83840A can wedge when switching 1326 * from the internal 10baseT PHY to the external PHY without 1327 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE 1328 * the PCnet chip has to be powered down or stopped anyway 1329 * and although documented otherwise it doesn't take effect 1330 * until the next initialization. 1331 */ 1332 sc->pcn_link = 0; 1333 pcn_stop(sc); 1334 pcn_reset(sc); 1335 pcn_init_locked(sc); 1336 if (ifp->if_snd.ifq_head != NULL) 1337 pcn_start_locked(ifp); 1338 1339 PCN_UNLOCK(sc); 1340 1341 return(0); 1342 } 1343 1344 /* 1345 * Report current media status. 1346 */ 1347 static void 1348 pcn_ifmedia_sts(ifp, ifmr) 1349 struct ifnet *ifp; 1350 struct ifmediareq *ifmr; 1351 { 1352 struct pcn_softc *sc; 1353 struct mii_data *mii; 1354 1355 sc = ifp->if_softc; 1356 1357 mii = device_get_softc(sc->pcn_miibus); 1358 PCN_LOCK(sc); 1359 mii_pollstat(mii); 1360 ifmr->ifm_active = mii->mii_media_active; 1361 ifmr->ifm_status = mii->mii_media_status; 1362 PCN_UNLOCK(sc); 1363 1364 return; 1365 } 1366 1367 static int 1368 pcn_ioctl(ifp, command, data) 1369 struct ifnet *ifp; 1370 u_long command; 1371 caddr_t data; 1372 { 1373 struct pcn_softc *sc = ifp->if_softc; 1374 struct ifreq *ifr = (struct ifreq *) data; 1375 struct mii_data *mii = NULL; 1376 int error = 0; 1377 1378 switch(command) { 1379 case SIOCSIFFLAGS: 1380 PCN_LOCK(sc); 1381 if (ifp->if_flags & IFF_UP) { 1382 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1383 ifp->if_flags & IFF_PROMISC && 1384 !(sc->pcn_if_flags & IFF_PROMISC)) { 1385 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1386 PCN_EXTCTL1_SPND); 1387 pcn_setfilt(ifp); 1388 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1389 PCN_EXTCTL1_SPND); 1390 pcn_csr_write(sc, PCN_CSR_CSR, 1391 PCN_CSR_INTEN|PCN_CSR_START); 1392 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1393 !(ifp->if_flags & IFF_PROMISC) && 1394 sc->pcn_if_flags & IFF_PROMISC) { 1395 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1396 PCN_EXTCTL1_SPND); 1397 pcn_setfilt(ifp); 1398 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1399 PCN_EXTCTL1_SPND); 1400 pcn_csr_write(sc, PCN_CSR_CSR, 1401 PCN_CSR_INTEN|PCN_CSR_START); 1402 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1403 pcn_init_locked(sc); 1404 } else { 1405 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1406 pcn_stop(sc); 1407 } 1408 sc->pcn_if_flags = ifp->if_flags; 1409 PCN_UNLOCK(sc); 1410 error = 0; 1411 break; 1412 case SIOCADDMULTI: 1413 case SIOCDELMULTI: 1414 PCN_LOCK(sc); 1415 pcn_setmulti(sc); 1416 PCN_UNLOCK(sc); 1417 error = 0; 1418 break; 1419 case SIOCGIFMEDIA: 1420 case SIOCSIFMEDIA: 1421 mii = device_get_softc(sc->pcn_miibus); 1422 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1423 break; 1424 default: 1425 error = ether_ioctl(ifp, command, data); 1426 break; 1427 } 1428 1429 return(error); 1430 } 1431 1432 static void 1433 pcn_watchdog(struct pcn_softc *sc) 1434 { 1435 struct ifnet *ifp; 1436 1437 PCN_LOCK_ASSERT(sc); 1438 ifp = sc->pcn_ifp; 1439 1440 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1441 if_printf(ifp, "watchdog timeout\n"); 1442 1443 pcn_stop(sc); 1444 pcn_reset(sc); 1445 pcn_init_locked(sc); 1446 1447 if (ifp->if_snd.ifq_head != NULL) 1448 pcn_start_locked(ifp); 1449 } 1450 1451 /* 1452 * Stop the adapter and free any mbufs allocated to the 1453 * RX and TX lists. 1454 */ 1455 static void 1456 pcn_stop(struct pcn_softc *sc) 1457 { 1458 int i; 1459 struct ifnet *ifp; 1460 1461 PCN_LOCK_ASSERT(sc); 1462 ifp = sc->pcn_ifp; 1463 sc->pcn_timer = 0; 1464 1465 callout_stop(&sc->pcn_stat_callout); 1466 1467 /* Turn off interrupts */ 1468 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1469 /* Stop adapter */ 1470 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1471 sc->pcn_link = 0; 1472 1473 /* 1474 * Free data in the RX lists. 1475 */ 1476 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1477 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1478 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1479 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1480 } 1481 } 1482 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1483 sizeof(sc->pcn_ldata->pcn_rx_list)); 1484 1485 /* 1486 * Free the TX list buffers. 1487 */ 1488 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1489 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1490 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1491 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1492 } 1493 } 1494 1495 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1496 sizeof(sc->pcn_ldata->pcn_tx_list)); 1497 1498 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1499 1500 return; 1501 } 1502 1503 /* 1504 * Stop all chip I/O so that the kernel's probe routines don't 1505 * get confused by errant DMAs when rebooting. 1506 */ 1507 static int 1508 pcn_shutdown(device_t dev) 1509 { 1510 struct pcn_softc *sc; 1511 1512 sc = device_get_softc(dev); 1513 1514 PCN_LOCK(sc); 1515 pcn_reset(sc); 1516 pcn_stop(sc); 1517 PCN_UNLOCK(sc); 1518 1519 return 0; 1520 } 1521