xref: /freebsd-12.1/sys/dev/mlx5/driver.h (revision 85de300e) 
1 /*-
2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30 
31 #include "opt_ratelimit.h"
32 
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
44 
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
48 
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
51 
52 enum {
53 	MLX5_BOARD_ID_LEN = 64,
54 	MLX5_MAX_NAME_LEN = 16,
55 };
56 
57 enum {
58 	MLX5_CMD_TIMEOUT_MSEC	= 8 * 60 * 1000,
59 	MLX5_CMD_WQ_MAX_NAME	= 32,
60 };
61 
62 enum {
63 	CMD_OWNER_SW		= 0x0,
64 	CMD_OWNER_HW		= 0x1,
65 	CMD_STATUS_SUCCESS	= 0,
66 };
67 
68 enum mlx5_sqp_t {
69 	MLX5_SQP_SMI		= 0,
70 	MLX5_SQP_GSI		= 1,
71 	MLX5_SQP_IEEE_1588	= 2,
72 	MLX5_SQP_SNIFFER	= 3,
73 	MLX5_SQP_SYNC_UMR	= 4,
74 };
75 
76 enum {
77 	MLX5_MAX_PORTS	= 2,
78 };
79 
80 enum {
81 	MLX5_EQ_VEC_PAGES	 = 0,
82 	MLX5_EQ_VEC_CMD		 = 1,
83 	MLX5_EQ_VEC_ASYNC	 = 2,
84 	MLX5_EQ_VEC_COMP_BASE,
85 };
86 
87 enum {
88 	MLX5_MAX_IRQ_NAME	= 32
89 };
90 
91 enum {
92 	MLX5_ATOMIC_MODE_OFF		= 16,
93 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
94 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
95 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
96 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
97 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
98 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
99 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
100 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
101 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
102 };
103 
104 enum {
105 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
106 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
107 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
108 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
109 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
110 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
111 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
112 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
113 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
114 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
115 };
116 
117 enum {
118 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
119 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
120 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
121 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
122 };
123 
124 enum {
125 	MLX5_REG_QPTS		 = 0x4002,
126 	MLX5_REG_QETCR		 = 0x4005,
127 	MLX5_REG_QPDP		 = 0x4007,
128 	MLX5_REG_QTCT		 = 0x400A,
129 	MLX5_REG_QPDPM		 = 0x4013,
130 	MLX5_REG_QHLL		 = 0x4016,
131 	MLX5_REG_QCAM		 = 0x4019,
132 	MLX5_REG_DCBX_PARAM	 = 0x4020,
133 	MLX5_REG_DCBX_APP	 = 0x4021,
134 	MLX5_REG_PCAP		 = 0x5001,
135 	MLX5_REG_FPGA_CAP	 = 0x4022,
136 	MLX5_REG_FPGA_CTRL	 = 0x4023,
137 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
138 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
139 	MLX5_REG_PMTU		 = 0x5003,
140 	MLX5_REG_PTYS		 = 0x5004,
141 	MLX5_REG_PAOS		 = 0x5006,
142 	MLX5_REG_PFCC		 = 0x5007,
143 	MLX5_REG_PPCNT		 = 0x5008,
144 	MLX5_REG_PMAOS		 = 0x5012,
145 	MLX5_REG_PUDE		 = 0x5009,
146 	MLX5_REG_PPTB		 = 0x500B,
147 	MLX5_REG_PBMC		 = 0x500C,
148 	MLX5_REG_PMPE		 = 0x5010,
149 	MLX5_REG_PELC		 = 0x500e,
150 	MLX5_REG_PVLC		 = 0x500f,
151 	MLX5_REG_PMLP		 = 0x5002,
152 	MLX5_REG_PCAM		 = 0x507f,
153 	MLX5_REG_NODE_DESC	 = 0x6001,
154 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
155 	MLX5_REG_MTMP		 = 0x900a,
156 	MLX5_REG_MCIA		 = 0x9014,
157 	MLX5_REG_MFRL		 = 0x9028,
158 	MLX5_REG_MPCNT		 = 0x9051,
159 	MLX5_REG_MCQI		 = 0x9061,
160 	MLX5_REG_MCC		 = 0x9062,
161 	MLX5_REG_MCDA		 = 0x9063,
162 	MLX5_REG_MCAM		 = 0x907f,
163 };
164 
165 enum dbg_rsc_type {
166 	MLX5_DBG_RSC_QP,
167 	MLX5_DBG_RSC_EQ,
168 	MLX5_DBG_RSC_CQ,
169 };
170 
171 enum {
172 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
173 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
174 	MLX5_INTERFACE_NUMBER       = 2,
175 };
176 
177 struct mlx5_field_desc {
178 	struct dentry	       *dent;
179 	int			i;
180 };
181 
182 struct mlx5_rsc_debug {
183 	struct mlx5_core_dev   *dev;
184 	void		       *object;
185 	enum dbg_rsc_type	type;
186 	struct dentry	       *root;
187 	struct mlx5_field_desc	fields[0];
188 };
189 
190 enum mlx5_dev_event {
191 	MLX5_DEV_EVENT_SYS_ERROR,
192 	MLX5_DEV_EVENT_PORT_UP,
193 	MLX5_DEV_EVENT_PORT_DOWN,
194 	MLX5_DEV_EVENT_PORT_INITIALIZED,
195 	MLX5_DEV_EVENT_LID_CHANGE,
196 	MLX5_DEV_EVENT_PKEY_CHANGE,
197 	MLX5_DEV_EVENT_GUID_CHANGE,
198 	MLX5_DEV_EVENT_CLIENT_REREG,
199 	MLX5_DEV_EVENT_VPORT_CHANGE,
200 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
201 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
202 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
203 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
204 };
205 
206 enum mlx5_port_status {
207 	MLX5_PORT_UP        = 1 << 0,
208 	MLX5_PORT_DOWN      = 1 << 1,
209 };
210 
211 enum {
212 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
213 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
214 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
215 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
216 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
217 	MLX5_VSC_DATA_OFFSET	 = 0x14,
218 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
219 };
220 
221 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
222 
223 struct mlx5_uuar_info {
224 	struct mlx5_uar	       *uars;
225 	int			num_uars;
226 	int			num_low_latency_uuars;
227 	unsigned long	       *bitmap;
228 	unsigned int	       *count;
229 	struct mlx5_bf	       *bfs;
230 
231 	/*
232 	 * protect uuar allocation data structs
233 	 */
234 	struct mutex		lock;
235 	u32			ver;
236 };
237 
238 struct mlx5_bf {
239 	void __iomem	       *reg;
240 	void __iomem	       *regreg;
241 	int			buf_size;
242 	struct mlx5_uar	       *uar;
243 	unsigned long		offset;
244 	int			need_lock;
245 	/* protect blue flame buffer selection when needed
246 	 */
247 	spinlock_t		lock;
248 
249 	/* serialize 64 bit writes when done as two 32 bit accesses
250 	 */
251 	spinlock_t		lock32;
252 	int			uuarn;
253 };
254 
255 struct mlx5_cmd_first {
256 	__be32		data[4];
257 };
258 
259 struct cache_ent;
260 struct mlx5_fw_page {
261 	union {
262 		struct rb_node rb_node;
263 		struct list_head list;
264 	};
265 	struct mlx5_cmd_first first;
266 	struct mlx5_core_dev *dev;
267 	bus_dmamap_t dma_map;
268 	bus_addr_t dma_addr;
269 	void *virt_addr;
270 	struct cache_ent *cache;
271 	u32 numpages;
272 	u16 load_done;
273 #define	MLX5_LOAD_ST_NONE 0
274 #define	MLX5_LOAD_ST_SUCCESS 1
275 #define	MLX5_LOAD_ST_FAILURE 2
276 	u16 func_id;
277 };
278 #define	mlx5_cmd_msg mlx5_fw_page
279 
280 struct mlx5_cmd_debug {
281 	struct dentry	       *dbg_root;
282 	struct dentry	       *dbg_in;
283 	struct dentry	       *dbg_out;
284 	struct dentry	       *dbg_outlen;
285 	struct dentry	       *dbg_status;
286 	struct dentry	       *dbg_run;
287 	void		       *in_msg;
288 	void		       *out_msg;
289 	u8			status;
290 	u16			inlen;
291 	u16			outlen;
292 };
293 
294 struct cache_ent {
295 	/* protect block chain allocations
296 	 */
297 	spinlock_t		lock;
298 	struct list_head	head;
299 };
300 
301 struct cmd_msg_cache {
302 	struct cache_ent	large;
303 	struct cache_ent	med;
304 
305 };
306 
307 struct mlx5_traffic_counter {
308 	u64         packets;
309 	u64         octets;
310 };
311 
312 enum mlx5_cmd_mode {
313 	MLX5_CMD_MODE_POLLING,
314 	MLX5_CMD_MODE_EVENTS
315 };
316 
317 struct mlx5_cmd_stats {
318 	u64		sum;
319 	u64		n;
320 	struct dentry  *root;
321 	struct dentry  *avg;
322 	struct dentry  *count;
323 	/* protect command average calculations */
324 	spinlock_t	lock;
325 };
326 
327 struct mlx5_cmd {
328 	struct mlx5_fw_page *cmd_page;
329 	bus_dma_tag_t dma_tag;
330 	struct sx dma_sx;
331 	struct mtx dma_mtx;
332 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
333 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
334 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
335 	struct cv dma_cv;
336 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
337 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
338 	void	       *cmd_buf;
339 	dma_addr_t	dma;
340 	u16		cmdif_rev;
341 	u8		log_sz;
342 	u8		log_stride;
343 	int		max_reg_cmds;
344 	int		events;
345 	u32 __iomem    *vector;
346 
347 	/* protect command queue allocations
348 	 */
349 	spinlock_t	alloc_lock;
350 
351 	/* protect token allocations
352 	 */
353 	spinlock_t	token_lock;
354 	u8		token;
355 	unsigned long	bitmask;
356 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
357 	struct workqueue_struct *wq;
358 	struct semaphore sem;
359 	struct semaphore pages_sem;
360 	enum mlx5_cmd_mode mode;
361 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
362 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
363 	struct mlx5_cmd_debug dbg;
364 	struct cmd_msg_cache cache;
365 	int checksum_disabled;
366 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
367 };
368 
369 struct mlx5_port_caps {
370 	int	gid_table_len;
371 	int	pkey_table_len;
372 	u8	ext_port_cap;
373 };
374 
375 struct mlx5_buf {
376 	bus_dma_tag_t		dma_tag;
377 	bus_dmamap_t		dma_map;
378 	struct mlx5_core_dev   *dev;
379 	struct {
380 		void	       *buf;
381 	} direct;
382 	u64		       *page_list;
383 	int			npages;
384 	int			size;
385 	u8			page_shift;
386 	u8			load_done;
387 };
388 
389 struct mlx5_frag_buf {
390 	struct mlx5_buf_list	*frags;
391 	int			npages;
392 	int			size;
393 	u8			page_shift;
394 };
395 
396 struct mlx5_eq {
397 	struct mlx5_core_dev   *dev;
398 	__be32 __iomem	       *doorbell;
399 	u32			cons_index;
400 	struct mlx5_buf		buf;
401 	int			size;
402 	u8			irqn;
403 	u8			eqn;
404 	int			nent;
405 	u64			mask;
406 	struct list_head	list;
407 	int			index;
408 	struct mlx5_rsc_debug	*dbg;
409 };
410 
411 struct mlx5_core_psv {
412 	u32	psv_idx;
413 	struct psv_layout {
414 		u32	pd;
415 		u16	syndrome;
416 		u16	reserved;
417 		u16	bg;
418 		u16	app_tag;
419 		u32	ref_tag;
420 	} psv;
421 };
422 
423 struct mlx5_core_sig_ctx {
424 	struct mlx5_core_psv	psv_memory;
425 	struct mlx5_core_psv	psv_wire;
426 #if (__FreeBSD_version >= 1100000)
427 	struct ib_sig_err       err_item;
428 #endif
429 	bool			sig_status_checked;
430 	bool			sig_err_exists;
431 	u32			sigerr_count;
432 };
433 
434 enum {
435 	MLX5_MKEY_MR = 1,
436 	MLX5_MKEY_MW,
437 	MLX5_MKEY_MR_USER,
438 };
439 
440 struct mlx5_core_mkey {
441 	u64			iova;
442 	u64			size;
443 	u32			key;
444 	u32			pd;
445 	u32			type;
446 };
447 
448 struct mlx5_core_mr {
449 	u64			iova;
450 	u64			size;
451 	u32			key;
452 	u32			pd;
453 };
454 
455 enum mlx5_res_type {
456 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
457 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
458 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
459 	MLX5_RES_SRQ	= 3,
460 	MLX5_RES_XSRQ	= 4,
461 	MLX5_RES_DCT	= 5,
462 };
463 
464 struct mlx5_core_rsc_common {
465 	enum mlx5_res_type	res;
466 	atomic_t		refcount;
467 	struct completion	free;
468 };
469 
470 struct mlx5_core_srq {
471 	struct mlx5_core_rsc_common	common; /* must be first */
472 	u32				srqn;
473 	int				max;
474 	size_t				max_gs;
475 	size_t				max_avail_gather;
476 	int				wqe_shift;
477 	void				(*event)(struct mlx5_core_srq *, int);
478 	atomic_t			refcount;
479 	struct completion		free;
480 };
481 
482 struct mlx5_eq_table {
483 	void __iomem	       *update_ci;
484 	void __iomem	       *update_arm_ci;
485 	struct list_head	comp_eqs_list;
486 	struct mlx5_eq		pages_eq;
487 	struct mlx5_eq		async_eq;
488 	struct mlx5_eq		cmd_eq;
489 	int			num_comp_vectors;
490 	/* protect EQs list
491 	 */
492 	spinlock_t		lock;
493 };
494 
495 struct mlx5_uar {
496 	u32			index;
497 	void __iomem	       *bf_map;
498 	void __iomem	       *map;
499 };
500 
501 
502 struct mlx5_core_health {
503 	struct mlx5_health_buffer __iomem	*health;
504 	__be32 __iomem		       *health_counter;
505 	struct timer_list		timer;
506 	u32				prev;
507 	int				miss_counter;
508 	u32				fatal_error;
509 	struct workqueue_struct	       *wq_watchdog;
510 	struct work_struct		work_watchdog;
511 	/* wq spinlock to synchronize draining */
512 	spinlock_t			wq_lock;
513 	struct workqueue_struct	       *wq;
514 	unsigned long			flags;
515 	struct work_struct		work;
516 	struct delayed_work		recover_work;
517 	unsigned int			last_reset_req;
518 };
519 
520 #ifdef RATELIMIT
521 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	(128 * 1024)
522 #else
523 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
524 #endif
525 
526 struct mlx5_cq_linear_array_entry {
527 	spinlock_t	lock;
528 	struct mlx5_core_cq * volatile cq;
529 };
530 
531 struct mlx5_cq_table {
532 	/* protect radix tree
533 	 */
534 	spinlock_t		lock;
535 	struct radix_tree_root	tree;
536 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
537 };
538 
539 struct mlx5_qp_table {
540 	/* protect radix tree
541 	 */
542 	spinlock_t		lock;
543 	struct radix_tree_root	tree;
544 };
545 
546 struct mlx5_srq_table {
547 	/* protect radix tree
548 	 */
549 	spinlock_t		lock;
550 	struct radix_tree_root	tree;
551 };
552 
553 struct mlx5_mr_table {
554 	/* protect radix tree
555 	 */
556 	spinlock_t		lock;
557 	struct radix_tree_root	tree;
558 };
559 
560 struct mlx5_irq_info {
561 	char name[MLX5_MAX_IRQ_NAME];
562 };
563 
564 #ifdef RATELIMIT
565 struct mlx5_rl_entry {
566 	u32			rate;
567 	u16			burst;
568 	u16			index;
569 	u32			refcount;
570 };
571 
572 struct mlx5_rl_table {
573 	struct mutex		rl_lock;
574 	u16			max_size;
575 	u32			max_rate;
576 	u32			min_rate;
577 	struct mlx5_rl_entry   *rl_entry;
578 };
579 #endif
580 
581 struct mlx5_priv {
582 	char			name[MLX5_MAX_NAME_LEN];
583 	struct mlx5_eq_table	eq_table;
584 	struct msix_entry	*msix_arr;
585 	struct mlx5_irq_info	*irq_info;
586 	struct mlx5_uuar_info	uuari;
587 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
588 	int			disable_irqs;
589 
590 	struct io_mapping	*bf_mapping;
591 
592 	/* pages stuff */
593 	struct workqueue_struct *pg_wq;
594 	struct rb_root		page_root;
595 	s64			fw_pages;
596 	atomic_t		reg_pages;
597 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
598 	struct mlx5_core_health health;
599 
600 	struct mlx5_srq_table	srq_table;
601 
602 	/* start: qp staff */
603 	struct mlx5_qp_table	qp_table;
604 	struct dentry	       *qp_debugfs;
605 	struct dentry	       *eq_debugfs;
606 	struct dentry	       *cq_debugfs;
607 	struct dentry	       *cmdif_debugfs;
608 	/* end: qp staff */
609 
610 	/* start: cq staff */
611 	struct mlx5_cq_table	cq_table;
612 	/* end: cq staff */
613 
614 	/* start: mr staff */
615 	struct mlx5_mr_table	mr_table;
616 	/* end: mr staff */
617 
618 	/* start: alloc staff */
619 	int			numa_node;
620 
621 	struct mutex   pgdir_mutex;
622 	struct list_head        pgdir_list;
623 	/* end: alloc staff */
624 	struct dentry	       *dbg_root;
625 
626 	/* protect mkey key part */
627 	spinlock_t		mkey_lock;
628 	u8			mkey_key;
629 
630 	struct list_head        dev_list;
631 	struct list_head        ctx_list;
632 	spinlock_t              ctx_lock;
633 	unsigned long		pci_dev_data;
634 #ifdef RATELIMIT
635 	struct mlx5_rl_table	rl_table;
636 #endif
637 };
638 
639 enum mlx5_device_state {
640 	MLX5_DEVICE_STATE_UP,
641 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
642 };
643 
644 enum mlx5_interface_state {
645 	MLX5_INTERFACE_STATE_UP,
646 };
647 
648 enum mlx5_pci_status {
649 	MLX5_PCI_STATUS_DISABLED,
650 	MLX5_PCI_STATUS_ENABLED,
651 };
652 
653 #define	MLX5_MAX_RESERVED_GIDS	8
654 
655 struct mlx5_rsvd_gids {
656 	unsigned int start;
657 	unsigned int count;
658 	struct ida ida;
659 };
660 
661 struct mlx5_special_contexts {
662 	int resd_lkey;
663 };
664 
665 struct mlx5_flow_root_namespace;
666 struct mlx5_dump_data;
667 struct mlx5_core_dev {
668 	struct pci_dev	       *pdev;
669 	/* sync pci state */
670 	struct mutex		pci_status_mutex;
671 	enum mlx5_pci_status	pci_status;
672 	char			board_id[MLX5_BOARD_ID_LEN];
673 	struct mlx5_cmd		cmd;
674 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
675 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
676 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
677 	struct {
678 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
679 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
680 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
681 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
682 	} caps;
683 	phys_addr_t		iseg_base;
684 	struct mlx5_init_seg __iomem *iseg;
685 	enum mlx5_device_state	state;
686 	/* sync interface state */
687 	struct mutex		intf_state_mutex;
688 	unsigned long		intf_state;
689 	void			(*event) (struct mlx5_core_dev *dev,
690 					  enum mlx5_dev_event event,
691 					  unsigned long param);
692 	struct mlx5_priv	priv;
693 	struct mlx5_profile	*profile;
694 	atomic_t		num_qps;
695 	u32			vsc_addr;
696 	u32			issi;
697 	struct mlx5_special_contexts special_contexts;
698 	unsigned int module_status[MLX5_MAX_PORTS];
699 	struct mlx5_flow_root_namespace *root_ns;
700 	struct mlx5_flow_root_namespace *fdb_root_ns;
701 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
702 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
703 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
704 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
705 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
706 	struct mlx5_dump_data	*dump_data;
707 
708 	struct sysctl_ctx_list	sysctl_ctx;
709 	int			msix_eqvec;
710 	int			pwr_status;
711 	int			pwr_value;
712 
713 	struct {
714 		struct mlx5_rsvd_gids	reserved_gids;
715 		atomic_t		roce_en;
716 	} roce;
717 #ifdef CONFIG_MLX5_FPGA
718 	struct mlx5_fpga_device	*fpga;
719 #endif
720 };
721 
722 enum {
723 	MLX5_WOL_DISABLE       = 0,
724 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
725 	MLX5_WOL_MAGIC         = 1 << 2,
726 	MLX5_WOL_ARP           = 1 << 3,
727 	MLX5_WOL_BROADCAST     = 1 << 4,
728 	MLX5_WOL_MULTICAST     = 1 << 5,
729 	MLX5_WOL_UNICAST       = 1 << 6,
730 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
731 };
732 
733 struct mlx5_db {
734 	__be32			*db;
735 	union {
736 		struct mlx5_db_pgdir		*pgdir;
737 		struct mlx5_ib_user_db_page	*user_page;
738 	}			u;
739 	dma_addr_t		dma;
740 	int			index;
741 };
742 
743 struct mlx5_net_counters {
744 	u64	packets;
745 	u64	octets;
746 };
747 
748 struct mlx5_ptys_reg {
749 	u8	an_dis_admin;
750 	u8	an_dis_ap;
751 	u8	local_port;
752 	u8	proto_mask;
753 	u32	eth_proto_cap;
754 	u16	ib_link_width_cap;
755 	u16	ib_proto_cap;
756 	u32	eth_proto_admin;
757 	u16	ib_link_width_admin;
758 	u16	ib_proto_admin;
759 	u32	eth_proto_oper;
760 	u16	ib_link_width_oper;
761 	u16	ib_proto_oper;
762 	u32	eth_proto_lp_advertise;
763 };
764 
765 struct mlx5_pvlc_reg {
766 	u8	local_port;
767 	u8	vl_hw_cap;
768 	u8	vl_admin;
769 	u8	vl_operational;
770 };
771 
772 struct mlx5_pmtu_reg {
773 	u8	local_port;
774 	u16	max_mtu;
775 	u16	admin_mtu;
776 	u16	oper_mtu;
777 };
778 
779 struct mlx5_vport_counters {
780 	struct mlx5_net_counters	received_errors;
781 	struct mlx5_net_counters	transmit_errors;
782 	struct mlx5_net_counters	received_ib_unicast;
783 	struct mlx5_net_counters	transmitted_ib_unicast;
784 	struct mlx5_net_counters	received_ib_multicast;
785 	struct mlx5_net_counters	transmitted_ib_multicast;
786 	struct mlx5_net_counters	received_eth_broadcast;
787 	struct mlx5_net_counters	transmitted_eth_broadcast;
788 	struct mlx5_net_counters	received_eth_unicast;
789 	struct mlx5_net_counters	transmitted_eth_unicast;
790 	struct mlx5_net_counters	received_eth_multicast;
791 	struct mlx5_net_counters	transmitted_eth_multicast;
792 };
793 
794 enum {
795 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
796 };
797 
798 struct mlx5_core_dct {
799 	struct mlx5_core_rsc_common	common; /* must be first */
800 	void (*event)(struct mlx5_core_dct *, int);
801 	int			dctn;
802 	struct completion	drained;
803 	struct mlx5_rsc_debug	*dbg;
804 	int			pid;
805 };
806 
807 enum {
808 	MLX5_COMP_EQ_SIZE = 1024,
809 };
810 
811 enum {
812 	MLX5_PTYS_IB = 1 << 0,
813 	MLX5_PTYS_EN = 1 << 2,
814 };
815 
816 struct mlx5_db_pgdir {
817 	struct list_head	list;
818 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
819 	struct mlx5_fw_page    *fw_page;
820 	__be32		       *db_page;
821 	dma_addr_t		db_dma;
822 };
823 
824 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
825 
826 struct mlx5_cmd_work_ent {
827 	struct mlx5_cmd_msg    *in;
828 	struct mlx5_cmd_msg    *out;
829 	int			uin_size;
830 	void		       *uout;
831 	int			uout_size;
832 	mlx5_cmd_cbk_t		callback;
833         struct delayed_work     cb_timeout_work;
834 	void		       *context;
835 	int			idx;
836 	struct completion	done;
837 	struct mlx5_cmd        *cmd;
838 	struct work_struct	work;
839 	struct mlx5_cmd_layout *lay;
840 	int			ret;
841 	int			page_queue;
842 	u8			status;
843 	u8			token;
844 	u64			ts1;
845 	u64			ts2;
846 	u16			op;
847 	u8			busy;
848 	bool			polling;
849 };
850 
851 struct mlx5_pas {
852 	u64	pa;
853 	u8	log_sz;
854 };
855 
856 enum port_state_policy {
857 	MLX5_POLICY_DOWN        = 0,
858 	MLX5_POLICY_UP          = 1,
859 	MLX5_POLICY_FOLLOW      = 2,
860 	MLX5_POLICY_INVALID     = 0xffffffff
861 };
862 
863 static inline void *
864 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
865 {
866 	return ((char *)buf->direct.buf + offset);
867 }
868 
869 
870 extern struct workqueue_struct *mlx5_core_wq;
871 
872 #define STRUCT_FIELD(header, field) \
873 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
874 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
875 
876 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
877 {
878 	return pci_get_drvdata(pdev);
879 }
880 
881 extern struct dentry *mlx5_debugfs_root;
882 
883 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
884 {
885 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
886 }
887 
888 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
889 {
890 	return ioread32be(&dev->iseg->fw_rev) >> 16;
891 }
892 
893 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
894 {
895 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
896 }
897 
898 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
899 {
900 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
901 }
902 
903 static inline int mlx5_get_gid_table_len(u16 param)
904 {
905 	if (param > 4) {
906 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
907 		return 0;
908 	}
909 
910 	return 8 * (1 << param);
911 }
912 
913 static inline void *mlx5_vzalloc(unsigned long size)
914 {
915 	void *rtn;
916 
917 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
918 	return rtn;
919 }
920 
921 static inline void *mlx5_vmalloc(unsigned long size)
922 {
923 	void *rtn;
924 
925 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
926 	if (!rtn)
927 		rtn = vmalloc(size);
928 	return rtn;
929 }
930 
931 static inline u32 mlx5_base_mkey(const u32 key)
932 {
933 	return key & 0xffffff00u;
934 }
935 
936 int mlx5_cmd_init(struct mlx5_core_dev *dev);
937 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
938 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
939 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
940 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
941 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
942 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
943 		  int out_size);
944 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
945 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
946 		     void *context);
947 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
948 			  void *out, int out_size);
949 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
950 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
951 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
952 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
953 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
954 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
955 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
956 int mlx5_health_init(struct mlx5_core_dev *dev);
957 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
958 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
959 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
960 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
961 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
962 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
963 
964 #define	mlx5_buf_alloc_node(dev, size, direct, buf, node) \
965 	mlx5_buf_alloc(dev, size, direct, buf)
966 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
967 		   struct mlx5_buf *buf);
968 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
969 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
970 			 struct mlx5_srq_attr *in);
971 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
972 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
973 			struct mlx5_srq_attr *out);
974 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
975 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
976 		      u16 lwm, int is_srq);
977 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
978 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
979 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
980 			     struct mlx5_core_mr *mkey,
981 			     u32 *in, int inlen,
982 			     u32 *out, int outlen,
983 			     mlx5_cmd_cbk_t callback, void *context);
984 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
985 			  struct mlx5_core_mr *mr,
986 			  u32 *in, int inlen);
987 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
988 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
989 			 u32 *out, int outlen);
990 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
991 			     u32 *mkey);
992 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
993 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
994 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
995 		      u16 opmod, u8 port);
996 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
997 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
998 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
999 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1000 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1001 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1002 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1003 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1004 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1005 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1006 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1007 				 s32 npages);
1008 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1009 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1010 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1011 void mlx5_register_debugfs(void);
1012 void mlx5_unregister_debugfs(void);
1013 int mlx5_eq_init(struct mlx5_core_dev *dev);
1014 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1015 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1016 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1017 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1018 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1019 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1020 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1021 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1022 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1023 		       int nent, u64 mask, const char *name, struct mlx5_uar *uar);
1024 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1025 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1026 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1027 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1028 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1029 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1030 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1031 				u64 addr);
1032 
1033 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1034 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1035 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1036 			 int size_in, void *data_out, int size_out,
1037 			 u16 reg_num, int arg, int write);
1038 
1039 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1040 
1041 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1042 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1043 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1044 		       u32 *out, int outlen);
1045 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1046 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1047 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1048 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1049 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1050 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1051 		       int node);
1052 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1053 
1054 const char *mlx5_command_str(int command);
1055 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1056 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1057 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1058 			 int npsvs, u32 *sig_index);
1059 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1060 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1061 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1062 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1063 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1064 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1065 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1066 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1067 			  struct mlx5_pvlc_reg *pvlc, int write);
1068 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1069 			  struct mlx5_ptys_reg *ptys, int write);
1070 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1071 			  struct mlx5_pmtu_reg *pmtu, int write);
1072 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1073 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1074 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1075 				int priority, int *is_enable);
1076 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1077 				 int priority, int enable);
1078 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1079 				void *out, int out_size);
1080 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1081 				 void *in, int in_size);
1082 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1083 				    void *out, int out_size);
1084 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1085 			       int in_size);
1086 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1087 				   u8 num_of_samples, u16 sample_index,
1088 				   void *out, int out_size);
1089 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1090 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1091 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1092 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1093 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1094 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1095 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1096 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1097 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1098 			       u16 *p_power, u8 *p_status);
1099 
1100 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1101 {
1102 	return mkey >> 8;
1103 }
1104 
1105 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1106 {
1107 	return mkey_idx << 8;
1108 }
1109 
1110 static inline u8 mlx5_mkey_variant(u32 mkey)
1111 {
1112 	return mkey & 0xff;
1113 }
1114 
1115 enum {
1116 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1117 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1118 };
1119 
1120 enum {
1121 	MAX_MR_CACHE_ENTRIES    = 15,
1122 };
1123 
1124 struct mlx5_interface {
1125 	void *			(*add)(struct mlx5_core_dev *dev);
1126 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1127 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1128 					 enum mlx5_dev_event event, unsigned long param);
1129 	void *                  (*get_dev)(void *context);
1130 	int			protocol;
1131 	struct list_head	list;
1132 };
1133 
1134 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1135 int mlx5_register_interface(struct mlx5_interface *intf);
1136 void mlx5_unregister_interface(struct mlx5_interface *intf);
1137 
1138 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1139 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1140     u8 roce_version, u8 roce_l3_type, const u8 *gid,
1141     const u8 *mac, bool vlan, u16 vlan_id);
1142 
1143 struct mlx5_profile {
1144 	u64	mask;
1145 	u8	log_max_qp;
1146 	struct {
1147 		int	size;
1148 		int	limit;
1149 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1150 };
1151 
1152 enum {
1153 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1154 };
1155 
1156 enum {
1157 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1158 };
1159 
1160 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1161 {
1162 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1163 }
1164 #ifdef RATELIMIT
1165 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1166 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1167 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1168 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1169 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1170 
1171 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1172 {
1173 	return !!(dev->priv.rl_table.max_size);
1174 }
1175 #endif
1176 
1177 #endif /* MLX5_DRIVER_H */
1178