1 /*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 * 36 */ 37 38 #ifndef _FIREWIRE_H 39 #define _FIREWIRE_H 1 40 41 #define DEV_DEF 0 42 #define DEV_DV 2 43 44 struct fw_isochreq { 45 unsigned char ch:6, 46 tag:2; 47 }; 48 49 struct fw_isobufreq { 50 struct fw_bufspec { 51 unsigned int nchunk; 52 unsigned int npacket; 53 unsigned int psize; 54 } tx, rx; 55 }; 56 57 struct fw_addr { 58 uint32_t hi; 59 uint32_t lo; 60 }; 61 62 struct fw_asybindreq { 63 struct fw_addr start; 64 unsigned long len; 65 }; 66 67 struct fw_reg_req_t { 68 uint32_t addr; 69 uint32_t data; 70 }; 71 72 #define MAXREC(x) (2 << (x)) 73 #define FWPMAX_S400 (2048 + 20) /* MAXREC plus space for control data */ 74 #define FWMAXQUEUE 128 75 76 #define FWLOCALBUS 0xffc0 77 78 #define FWTCODE_WREQQ 0 79 #define FWTCODE_WREQB 1 80 #define FWTCODE_WRES 2 81 #define FWTCODE_RREQQ 4 82 #define FWTCODE_RREQB 5 83 #define FWTCODE_RRESQ 6 84 #define FWTCODE_RRESB 7 85 #define FWTCODE_CYCS 8 86 #define FWTCODE_LREQ 9 87 #define FWTCODE_STREAM 0xa 88 #define FWTCODE_LRES 0xb 89 #define FWTCODE_PHY 0xe 90 91 #define FWRETRY_1 0 92 #define FWRETRY_X 1 93 #define FWRETRY_A 2 94 #define FWRETRY_B 3 95 96 #define FWRCODE_COMPLETE 0 97 #define FWRCODE_ER_CONFL 4 98 #define FWRCODE_ER_DATA 5 99 #define FWRCODE_ER_TYPE 6 100 #define FWRCODE_ER_ADDR 7 101 102 /* 103 * Defined 1394a-2000 104 * Table 5B-1 105 */ 106 #define FWSPD_S100 0 107 #define FWSPD_S200 1 108 #define FWSPD_S400 2 109 #define FWSPD_S800 3 110 #define FWSPD_S1600 4 111 #define FWSPD_S3200 5 112 113 #define FWP_TL_VALID (1 << 7) 114 115 struct fw_isohdr { 116 uint32_t hdr[1]; 117 }; 118 119 struct fw_asyhdr { 120 uint32_t hdr[4]; 121 }; 122 123 #if BYTE_ORDER == BIG_ENDIAN 124 #define BIT4x2(x,y) uint8_t x:4, y:4 125 #define BIT16x2(x,y) uint32_t x:16, y:16 126 #else 127 #define BIT4x2(x,y) uint8_t y:4, x:4 128 #define BIT16x2(x,y) uint32_t y:16, x:16 129 #endif 130 131 132 #if BYTE_ORDER == BIG_ENDIAN 133 #define COMMON_HDR(a,b,c,d) uint32_t a:16,b:8,c:4,d:4 134 #define COMMON_RES(a,b,c,d) uint32_t a:16,b:4,c:4,d:8 135 #else 136 #define COMMON_HDR(a,b,c,d) uint32_t d:4,c:4,b:8,a:16 137 #define COMMON_RES(a,b,c,d) uint32_t d:8,c:4,b:4,a:16 138 #endif 139 140 struct fw_pkt { 141 union { 142 uint32_t ld[0]; 143 struct { 144 COMMON_HDR(, , tcode, ); 145 } common; 146 struct { 147 COMMON_HDR(len, chtag, tcode, sy); 148 uint32_t payload[0]; 149 } stream; 150 struct { 151 COMMON_HDR(dst, tlrt, tcode, pri); 152 BIT16x2(src, ); 153 } hdr; 154 struct { 155 COMMON_HDR(dst, tlrt, tcode, pri); 156 BIT16x2(src, dest_hi); 157 uint32_t dest_lo; 158 } rreqq; 159 struct { 160 COMMON_HDR(dst, tlrt, tcode, pri); 161 COMMON_RES(src, rtcode, , ); 162 uint32_t :32; 163 } wres; 164 struct { 165 COMMON_HDR(dst, tlrt, tcode, pri); 166 BIT16x2(src, dest_hi); 167 uint32_t dest_lo; 168 BIT16x2(len, extcode); 169 } rreqb; 170 struct { 171 COMMON_HDR(dst, tlrt, tcode, pri); 172 BIT16x2(src, dest_hi); 173 uint32_t dest_lo; 174 uint32_t data; 175 } wreqq; 176 struct { 177 COMMON_HDR(dst, tlrt, tcode, pri); 178 BIT16x2(src, dest_hi); 179 uint32_t dest_lo; 180 uint32_t data; 181 } cyc; 182 struct { 183 COMMON_HDR(dst, tlrt, tcode, pri); 184 COMMON_RES(src, rtcode, , ); 185 uint32_t :32; 186 uint32_t data; 187 } rresq; 188 struct { 189 COMMON_HDR(dst, tlrt, tcode, pri); 190 BIT16x2(src, dest_hi); 191 uint32_t dest_lo; 192 BIT16x2(len, extcode); 193 uint32_t payload[0]; 194 } wreqb; 195 struct { 196 COMMON_HDR(dst, tlrt, tcode, pri); 197 BIT16x2(src, dest_hi); 198 uint32_t dest_lo; 199 BIT16x2(len, extcode); 200 uint32_t payload[0]; 201 } lreq; 202 struct { 203 COMMON_HDR(dst, tlrt, tcode, pri); 204 COMMON_RES(src, rtcode, , ); 205 uint32_t :32; 206 BIT16x2(len, extcode); 207 uint32_t payload[0]; 208 } rresb; 209 struct { 210 COMMON_HDR(dst, tlrt, tcode, pri); 211 COMMON_RES(src, rtcode, , ); 212 uint32_t :32; 213 BIT16x2(len, extcode); 214 uint32_t payload[0]; 215 } lres; 216 } mode; 217 }; 218 219 /* 220 * Response code (rtcode) 221 */ 222 /* The node has successfully completed the command. */ 223 #define RESP_CMP 0 224 /* A resource conflict was detected. The request may be retried. */ 225 #define RESP_CONFLICT_ERROR 4 226 /* Hardware error, data is unavailable. */ 227 #define RESP_DATA_ERROR 5 228 /* A field in the request packet header was set to an unsupported or incorrect 229 * value, or an invalid transaction was attempted (e.g., a write to a read-only 230 * address). */ 231 #define RESP_TYPE_ERROR 6 232 /* The destination offset field in the request was set to an address not 233 * accessible in the destination node. */ 234 #define RESP_ADDRESS_ERROR 7 235 236 /* 237 * Extended transaction code (extcode) 238 */ 239 #define EXTCODE_MASK_SWAP 1 240 #define EXTCODE_CMP_SWAP 2 241 #define EXTCODE_FETCH_ADD 3 242 #define EXTCODE_LITTLE_ADD 4 243 #define EXTCODE_BOUNDED_ADD 5 244 #define EXTCODE_WRAP_ADD 6 245 246 struct fw_eui64 { 247 uint32_t hi, lo; 248 }; 249 #define FW_EUI64_BYTE(eui, x) \ 250 ((((x)<4)? \ 251 ((eui)->hi >> (8*(3-(x)))): \ 252 ((eui)->lo >> (8*(7-(x)))) \ 253 ) & 0xff) 254 #define FW_EUI64_EQUAL(x, y) \ 255 ((x).hi == (y).hi && (x).lo == (y).lo) 256 257 struct fw_asyreq { 258 struct fw_asyreq_t{ 259 unsigned char sped; 260 unsigned int type; 261 #define FWASREQNODE 0 262 #define FWASREQEUI 1 263 #define FWASRESTL 2 264 #define FWASREQSTREAM 3 265 unsigned short len; 266 union { 267 struct fw_eui64 eui; 268 }dst; 269 }req; 270 struct fw_pkt pkt; 271 uint32_t data[512]; 272 }; 273 274 struct fw_devinfo { 275 struct fw_eui64 eui; 276 uint16_t dst; 277 uint16_t status; 278 }; 279 280 #define FW_MAX_DEVLST 70 281 struct fw_devlstreq { 282 uint16_t n; 283 uint16_t info_len; 284 struct fw_devinfo dev[FW_MAX_DEVLST]; 285 }; 286 287 /* 288 * Defined in IEEE 1394a-2000 289 * 4.3.4.1 290 */ 291 #define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3 292 #define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2 293 #define FW_SELF_ID_PORT_NOT_CONNECTED 1 294 #define FW_SELF_ID_PORT_NOT_EXISTS 0 295 #if BYTE_ORDER == BIG_ENDIAN 296 union fw_self_id { 297 struct { 298 uint32_t id:2, 299 phy_id:6, 300 sequel:1, 301 link_active:1, 302 gap_count:6, 303 phy_speed:2, 304 phy_delay:2, 305 contender:1, 306 power_class:3, 307 port0:2, 308 port1:2, 309 port2:2, 310 initiated_reset:1, 311 more_packets:1; 312 } p0; 313 struct { 314 uint32_t 315 id:2, 316 phy_id:6, 317 sequel:1, 318 sequence_num:3, 319 reserved2:2, 320 port3:2, 321 port4:2, 322 port5:2, 323 port6:2, 324 port7:2, 325 port8:2, 326 port9:2, 327 port10:2, 328 reserved1:1, 329 more_packets:1; 330 } p1; 331 struct { 332 uint32_t 333 id:2, 334 phy_id:6, 335 sequel:1, 336 sequence_num:3, 337 :2, 338 port11:2, 339 port12:2, 340 port13:2, 341 port14:2, 342 port15:2, 343 :8; 344 } p2; 345 }; 346 #else 347 union fw_self_id { 348 struct { 349 uint32_t more_packets:1, 350 initiated_reset:1, 351 port2:2, 352 port1:2, 353 port0:2, 354 power_class:3, 355 contender:1, 356 phy_delay:2, 357 phy_speed:2, 358 gap_count:6, 359 link_active:1, 360 sequel:1, 361 phy_id:6, 362 id:2; 363 } p0; 364 struct { 365 uint32_t more_packets:1, 366 reserved1:1, 367 port10:2, 368 port9:2, 369 port8:2, 370 port7:2, 371 port6:2, 372 port5:2, 373 port4:2, 374 port3:2, 375 reserved2:2, 376 sequence_num:3, 377 sequel:1, 378 phy_id:6, 379 id:2; 380 } p1; 381 struct { 382 uint32_t 383 reserved3:8, 384 port15:2, 385 port14:2, 386 port13:2, 387 port12:2, 388 port11:2, 389 reserved4:2, 390 sequence_num:3, 391 sequel:1, 392 phy_id:6, 393 id:2; 394 } p2; 395 }; 396 #endif 397 398 399 struct fw_topology_map { 400 uint32_t crc:16, 401 crc_len:16; 402 uint32_t generation; 403 uint32_t self_id_count:16, 404 node_count:16; 405 union fw_self_id self_id[4*64]; 406 }; 407 408 struct fw_speed_map { 409 uint32_t crc:16, 410 crc_len:16; 411 uint32_t generation; 412 uint8_t speed[64][64]; 413 }; 414 415 struct fw_crom_buf { 416 struct fw_eui64 eui; 417 uint32_t len; 418 void *ptr; 419 }; 420 421 /* 422 * FireWire specific system requests. 423 */ 424 #define FW_SSTBUF _IOWR('S', 86, struct fw_isobufreq) 425 #define FW_GSTBUF _IOWR('S', 87, struct fw_isobufreq) 426 #define FW_SRSTREAM _IOWR('S', 88, struct fw_isochreq) 427 #define FW_GRSTREAM _IOWR('S', 89, struct fw_isochreq) 428 #define FW_STSTREAM _IOWR('S', 90, struct fw_isochreq) 429 #define FW_GTSTREAM _IOWR('S', 91, struct fw_isochreq) 430 431 #define FW_ASYREQ _IOWR('S', 92, struct fw_asyreq) 432 #define FW_IBUSRST _IOR('S', 1, unsigned int) 433 #define FW_GDEVLST _IOWR('S', 2, struct fw_devlstreq) 434 #define FW_SBINDADDR _IOWR('S', 3, struct fw_asybindreq) 435 #define FW_CBINDADDR _IOWR('S', 4, struct fw_asybindreq) 436 #define FW_GTPMAP _IOR('S', 5, struct fw_topology_map) 437 #define FW_GCROM _IOWR('S', 7, struct fw_crom_buf) 438 439 #define FW_SDEUI64 _IOW('S', 20, struct fw_eui64) 440 #define FW_GDEUI64 _IOR('S', 21, struct fw_eui64) 441 442 #define FWOHCI_RDREG _IOWR('S', 80, struct fw_reg_req_t) 443 #define FWOHCI_WRREG _IOWR('S', 81, struct fw_reg_req_t) 444 #define FWOHCI_RDPHYREG _IOWR('S', 82, struct fw_reg_req_t) 445 #define FWOHCI_WRPHYREG _IOWR('S', 83, struct fw_reg_req_t) 446 447 #define DUMPDMA _IOWR('S', 82, uint32_t) 448 449 #ifdef _KERNEL 450 451 #define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */ 452 453 #if defined(__DragonFly__) || __FreeBSD_version < 500000 454 #define dev2unit(x) ((minor(x) & 0xff) | (minor(x) >> 8)) 455 #define unit2minor(x) (((x) & 0xff) | (((x) << 8) & ~0xffff)) 456 #endif 457 458 #define MAKEMINOR(f, u, s) \ 459 ((f) | (((u) & 0xff) << 8) | (s & 0xff)) 460 #define DEV2UNIT(x) ((dev2unit(x) & 0xff00) >> 8) 461 #define DEV2SUB(x) (dev2unit(x) & 0xff) 462 463 #define FWMEM_FLAG 0x10000 464 #define DEV_FWMEM(x) (dev2unit(x) & FWMEM_FLAG) 465 #endif 466 #endif 467