1 /* 2 * Copyright (c) 1996, Javier Mart�n Rueda ([email protected]) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * 28 * MAINTAINER: Matthew N. Dodd <[email protected]> 29 * <[email protected]> 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Intel EtherExpress Pro/10, Pro/10+ Ethernet driver 37 * 38 * Revision history: 39 * 40 * dd-mmm-yyyy: Multicast support ported from NetBSD's if_iy driver. 41 * 30-Oct-1996: first beta version. Inet and BPF supported, but no multicast. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/socket.h> 50 51 #include <sys/module.h> 52 #include <sys/bus.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <sys/rman.h> 57 58 #include <net/if.h> 59 #include <net/if_arp.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/ethernet.h> 63 #include <net/bpf.h> 64 65 #include <netinet/in.h> 66 #include <netinet/if_ether.h> 67 68 69 #include <isa/isavar.h> 70 #include <isa/pnpvar.h> 71 72 #include <dev/ex/if_exreg.h> 73 #include <dev/ex/if_exvar.h> 74 75 #ifdef EXDEBUG 76 # define Start_End 1 77 # define Rcvd_Pkts 2 78 # define Sent_Pkts 4 79 # define Status 8 80 static int debug_mask = 0; 81 # define DODEBUG(level, action) if (level & debug_mask) action 82 #else 83 # define DODEBUG(level, action) 84 #endif 85 86 devclass_t ex_devclass; 87 88 char irq2eemap[] = 89 { -1, -1, 0, 1, -1, 2, -1, -1, -1, 0, 3, 4, -1, -1, -1, -1 }; 90 u_char ee2irqmap[] = 91 { 9, 3, 5, 10, 11, 0, 0, 0 }; 92 93 char plus_irq2eemap[] = 94 { -1, -1, -1, 0, 1, 2, -1, 3, -1, 4, 5, 6, 7, -1, -1, -1 }; 95 u_char plus_ee2irqmap[] = 96 { 3, 4, 5, 7, 9, 10, 11, 12 }; 97 98 /* Network Interface Functions */ 99 static void ex_init(void *); 100 static void ex_start(struct ifnet *); 101 static int ex_ioctl(struct ifnet *, u_long, caddr_t); 102 static void ex_watchdog(struct ifnet *); 103 104 /* ifmedia Functions */ 105 static int ex_ifmedia_upd(struct ifnet *); 106 static void ex_ifmedia_sts(struct ifnet *, struct ifmediareq *); 107 108 static int ex_get_media(struct ex_softc *); 109 110 static void ex_reset(struct ex_softc *); 111 static void ex_setmulti(struct ex_softc *); 112 113 static void ex_tx_intr(struct ex_softc *); 114 static void ex_rx_intr(struct ex_softc *); 115 116 void 117 ex_get_address(struct ex_softc *sc, u_char *enaddr) 118 { 119 uint16_t eaddr_tmp; 120 121 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Lo); 122 enaddr[5] = eaddr_tmp & 0xff; 123 enaddr[4] = eaddr_tmp >> 8; 124 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Mid); 125 enaddr[3] = eaddr_tmp & 0xff; 126 enaddr[2] = eaddr_tmp >> 8; 127 eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Hi); 128 enaddr[1] = eaddr_tmp & 0xff; 129 enaddr[0] = eaddr_tmp >> 8; 130 131 return; 132 } 133 134 int 135 ex_card_type(u_char *enaddr) 136 { 137 if ((enaddr[0] == 0x00) && (enaddr[1] == 0xA0) && (enaddr[2] == 0xC9)) 138 return (CARD_TYPE_EX_10_PLUS); 139 140 return (CARD_TYPE_EX_10); 141 } 142 143 /* 144 * Caller is responsible for eventually calling 145 * ex_release_resources() on failure. 146 */ 147 int 148 ex_alloc_resources(device_t dev) 149 { 150 struct ex_softc * sc = device_get_softc(dev); 151 int error = 0; 152 153 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 154 &sc->ioport_rid, RF_ACTIVE); 155 if (!sc->ioport) { 156 device_printf(dev, "No I/O space?!\n"); 157 error = ENOMEM; 158 goto bad; 159 } 160 sc->bst = rman_get_bustag(sc->ioport); 161 sc->bsh = rman_get_bushandle(sc->ioport); 162 163 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 164 RF_ACTIVE); 165 166 if (!sc->irq) { 167 device_printf(dev, "No IRQ?!\n"); 168 error = ENOMEM; 169 goto bad; 170 } 171 172 bad: 173 return (error); 174 } 175 176 void 177 ex_release_resources(device_t dev) 178 { 179 struct ex_softc * sc = device_get_softc(dev); 180 181 if (sc->ih) { 182 bus_teardown_intr(dev, sc->irq, sc->ih); 183 sc->ih = NULL; 184 } 185 186 if (sc->ioport) { 187 bus_release_resource(dev, SYS_RES_IOPORT, 188 sc->ioport_rid, sc->ioport); 189 sc->ioport = NULL; 190 } 191 192 if (sc->irq) { 193 bus_release_resource(dev, SYS_RES_IRQ, 194 sc->irq_rid, sc->irq); 195 sc->irq = NULL; 196 } 197 198 return; 199 } 200 201 int 202 ex_attach(device_t dev) 203 { 204 struct ex_softc * sc = device_get_softc(dev); 205 struct ifnet * ifp = &sc->arpcom.ac_if; 206 struct ifmedia * ifm; 207 uint16_t temp; 208 209 /* work out which set of irq <-> internal tables to use */ 210 if (ex_card_type(sc->arpcom.ac_enaddr) == CARD_TYPE_EX_10_PLUS) { 211 sc->irq2ee = plus_irq2eemap; 212 sc->ee2irq = plus_ee2irqmap; 213 } else { 214 sc->irq2ee = irq2eemap; 215 sc->ee2irq = ee2irqmap; 216 } 217 218 sc->mem_size = CARD_RAM_SIZE; /* XXX This should be read from the card itself. */ 219 220 /* 221 * Initialize the ifnet structure. 222 */ 223 ifp->if_softc = sc; 224 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 225 ifp->if_mtu = ETHERMTU; 226 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 227 ifp->if_start = ex_start; 228 ifp->if_ioctl = ex_ioctl; 229 ifp->if_watchdog = ex_watchdog; 230 ifp->if_init = ex_init; 231 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 232 233 ifmedia_init(&sc->ifmedia, 0, ex_ifmedia_upd, ex_ifmedia_sts); 234 235 temp = ex_eeprom_read(sc, EE_W5); 236 if (temp & EE_W5_PORT_TPE) 237 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 238 if (temp & EE_W5_PORT_BNC) 239 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 240 if (temp & EE_W5_PORT_AUI) 241 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 242 243 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 244 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_NONE, 0, NULL); 245 ifmedia_set(&sc->ifmedia, ex_get_media(sc)); 246 247 ifm = &sc->ifmedia; 248 ifm->ifm_media = ifm->ifm_cur->ifm_media; 249 ex_ifmedia_upd(ifp); 250 251 /* 252 * Attach the interface. 253 */ 254 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 255 256 return(0); 257 } 258 259 int 260 ex_detach(device_t dev) 261 { 262 struct ex_softc *sc; 263 struct ifnet *ifp; 264 265 sc = device_get_softc(dev); 266 ifp = &sc->arpcom.ac_if; 267 268 ex_stop(sc); 269 270 ifp->if_flags &= ~IFF_RUNNING; 271 ether_ifdetach(ifp); 272 273 ex_release_resources(dev); 274 275 return (0); 276 } 277 278 static void 279 ex_init(void *xsc) 280 { 281 struct ex_softc * sc = (struct ex_softc *) xsc; 282 struct ifnet * ifp = &sc->arpcom.ac_if; 283 int s; 284 int i; 285 unsigned short temp_reg; 286 287 DODEBUG(Start_End, printf("%s: ex_init: start\n", ifp->if_xname);); 288 289 s = splimp(); 290 ifp->if_timer = 0; 291 292 /* 293 * Load the ethernet address into the card. 294 */ 295 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel); 296 temp_reg = CSR_READ_1(sc, EEPROM_REG); 297 if (temp_reg & Trnoff_Enable) { 298 CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable); 299 } 300 for (i = 0; i < ETHER_ADDR_LEN; i++) { 301 CSR_WRITE_1(sc, I_ADDR_REG0 + i, sc->arpcom.ac_enaddr[i]); 302 } 303 /* 304 * - Setup transmit chaining and discard bad received frames. 305 * - Match broadcast. 306 * - Clear test mode. 307 * - Set receiving mode. 308 * - Set IRQ number. 309 */ 310 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr); 311 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem); 312 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ ); 313 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel); 314 CSR_WRITE_1(sc, INT_NO_REG, (CSR_READ_1(sc, INT_NO_REG) & 0xf8) | sc->irq2ee[sc->irq_no]); 315 316 /* 317 * Divide the available memory in the card into rcv and xmt buffers. 318 * By default, I use the first 3/4 of the memory for the rcv buffer, 319 * and the remaining 1/4 of the memory for the xmt buffer. 320 */ 321 sc->rx_mem_size = sc->mem_size * 3 / 4; 322 sc->tx_mem_size = sc->mem_size - sc->rx_mem_size; 323 sc->rx_lower_limit = 0x0000; 324 sc->rx_upper_limit = sc->rx_mem_size - 2; 325 sc->tx_lower_limit = sc->rx_mem_size; 326 sc->tx_upper_limit = sc->mem_size - 2; 327 CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8); 328 CSR_WRITE_1(sc, RCV_UPPER_LIMIT_REG, sc->rx_upper_limit >> 8); 329 CSR_WRITE_1(sc, XMT_LOWER_LIMIT_REG, sc->tx_lower_limit >> 8); 330 CSR_WRITE_1(sc, XMT_UPPER_LIMIT_REG, sc->tx_upper_limit >> 8); 331 332 /* 333 * Enable receive and transmit interrupts, and clear any pending int. 334 */ 335 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT); 336 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel); 337 CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int)); 338 CSR_WRITE_1(sc, STATUS_REG, All_Int); 339 340 /* 341 * Initialize receive and transmit ring buffers. 342 */ 343 CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit); 344 sc->rx_head = sc->rx_lower_limit; 345 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe); 346 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit); 347 sc->tx_head = sc->tx_tail = sc->tx_lower_limit; 348 349 ifp->if_flags |= IFF_RUNNING; 350 ifp->if_flags &= ~IFF_OACTIVE; 351 DODEBUG(Status, printf("OIDLE init\n");); 352 353 ex_setmulti(sc); 354 355 /* 356 * Final reset of the board, and enable operation. 357 */ 358 CSR_WRITE_1(sc, CMD_REG, Sel_Reset_CMD); 359 DELAY(2); 360 CSR_WRITE_1(sc, CMD_REG, Rcv_Enable_CMD); 361 362 ex_start(ifp); 363 splx(s); 364 365 DODEBUG(Start_End, printf("%s: ex_init: finish\n", ifp->if_xname);); 366 } 367 368 369 static void 370 ex_start(struct ifnet *ifp) 371 { 372 struct ex_softc * sc = ifp->if_softc; 373 int i, s, len, data_len, avail, dest, next; 374 unsigned char tmp16[2]; 375 struct mbuf * opkt; 376 struct mbuf * m; 377 378 DODEBUG(Start_End, printf("ex_start%d: start\n", unit);); 379 380 s = splimp(); 381 382 /* 383 * Main loop: send outgoing packets to network card until there are no 384 * more packets left, or the card cannot accept any more yet. 385 */ 386 while (((opkt = ifp->if_snd.ifq_head) != NULL) && 387 !(ifp->if_flags & IFF_OACTIVE)) { 388 389 /* 390 * Ensure there is enough free transmit buffer space for 391 * this packet, including its header. Note: the header 392 * cannot wrap around the end of the transmit buffer and 393 * must be kept together, so we allow space for twice the 394 * length of the header, just in case. 395 */ 396 397 for (len = 0, m = opkt; m != NULL; m = m->m_next) { 398 len += m->m_len; 399 } 400 401 data_len = len; 402 403 DODEBUG(Sent_Pkts, printf("1. Sending packet with %d data bytes. ", data_len);); 404 405 if (len & 1) { 406 len += XMT_HEADER_LEN + 1; 407 } else { 408 len += XMT_HEADER_LEN; 409 } 410 411 if ((i = sc->tx_tail - sc->tx_head) >= 0) { 412 avail = sc->tx_mem_size - i; 413 } else { 414 avail = -i; 415 } 416 417 DODEBUG(Sent_Pkts, printf("i=%d, avail=%d\n", i, avail);); 418 419 if (avail >= len + XMT_HEADER_LEN) { 420 IF_DEQUEUE(&ifp->if_snd, opkt); 421 422 #ifdef EX_PSA_INTR 423 /* 424 * Disable rx and tx interrupts, to avoid corruption 425 * of the host address register by interrupt service 426 * routines. 427 * XXX Is this necessary with splimp() enabled? 428 */ 429 CSR_WRITE_1(sc, MASK_REG, All_Int); 430 #endif 431 432 /* 433 * Compute the start and end addresses of this 434 * frame in the tx buffer. 435 */ 436 dest = sc->tx_tail; 437 next = dest + len; 438 439 if (next > sc->tx_upper_limit) { 440 if ((sc->tx_upper_limit + 2 - sc->tx_tail) <= 441 XMT_HEADER_LEN) { 442 dest = sc->tx_lower_limit; 443 next = dest + len; 444 } else { 445 next = sc->tx_lower_limit + 446 next - sc->tx_upper_limit - 2; 447 } 448 } 449 450 /* 451 * Build the packet frame in the card's ring buffer. 452 */ 453 DODEBUG(Sent_Pkts, printf("2. dest=%d, next=%d. ", dest, next);); 454 455 CSR_WRITE_2(sc, HOST_ADDR_REG, dest); 456 CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD); 457 CSR_WRITE_2(sc, IO_PORT_REG, 0); 458 CSR_WRITE_2(sc, IO_PORT_REG, next); 459 CSR_WRITE_2(sc, IO_PORT_REG, data_len); 460 461 /* 462 * Output the packet data to the card. Ensure all 463 * transfers are 16-bit wide, even if individual 464 * mbufs have odd length. 465 */ 466 for (m = opkt, i = 0; m != NULL; m = m->m_next) { 467 DODEBUG(Sent_Pkts, printf("[%d]", m->m_len);); 468 if (i) { 469 tmp16[1] = *(mtod(m, caddr_t)); 470 CSR_WRITE_MULTI_2(sc, IO_PORT_REG, 471 (uint16_t *) tmp16, 1); 472 } 473 CSR_WRITE_MULTI_2(sc, IO_PORT_REG, 474 (uint16_t *) (mtod(m, caddr_t) + i), 475 (m->m_len - i) / 2); 476 if ((i = (m->m_len - i) & 1) != 0) { 477 tmp16[0] = *(mtod(m, caddr_t) + 478 m->m_len - 1); 479 } 480 } 481 if (i) 482 CSR_WRITE_MULTI_2(sc, IO_PORT_REG, 483 (uint16_t *) tmp16, 1); 484 /* 485 * If there were other frames chained, update the 486 * chain in the last one. 487 */ 488 if (sc->tx_head != sc->tx_tail) { 489 if (sc->tx_tail != dest) { 490 CSR_WRITE_2(sc, HOST_ADDR_REG, 491 sc->tx_last + XMT_Chain_Point); 492 CSR_WRITE_2(sc, IO_PORT_REG, dest); 493 } 494 CSR_WRITE_2(sc, HOST_ADDR_REG, 495 sc->tx_last + XMT_Byte_Count); 496 i = CSR_READ_2(sc, IO_PORT_REG); 497 CSR_WRITE_2(sc, HOST_ADDR_REG, 498 sc->tx_last + XMT_Byte_Count); 499 CSR_WRITE_2(sc, IO_PORT_REG, i | Ch_bit); 500 } 501 502 /* 503 * Resume normal operation of the card: 504 * - Make a dummy read to flush the DRAM write 505 * pipeline. 506 * - Enable receive and transmit interrupts. 507 * - Send Transmit or Resume_XMT command, as 508 * appropriate. 509 */ 510 CSR_READ_2(sc, IO_PORT_REG); 511 #ifdef EX_PSA_INTR 512 CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int)); 513 #endif 514 if (sc->tx_head == sc->tx_tail) { 515 CSR_WRITE_2(sc, XMT_BAR, dest); 516 CSR_WRITE_1(sc, CMD_REG, Transmit_CMD); 517 sc->tx_head = dest; 518 DODEBUG(Sent_Pkts, printf("Transmit\n");); 519 } else { 520 CSR_WRITE_1(sc, CMD_REG, Resume_XMT_List_CMD); 521 DODEBUG(Sent_Pkts, printf("Resume\n");); 522 } 523 524 sc->tx_last = dest; 525 sc->tx_tail = next; 526 527 BPF_MTAP(ifp, opkt); 528 529 ifp->if_timer = 2; 530 ifp->if_opackets++; 531 m_freem(opkt); 532 } else { 533 ifp->if_flags |= IFF_OACTIVE; 534 DODEBUG(Status, printf("OACTIVE start\n");); 535 } 536 } 537 538 splx(s); 539 540 DODEBUG(Start_End, printf("ex_start%d: finish\n", unit);); 541 } 542 543 void 544 ex_stop(struct ex_softc *sc) 545 { 546 547 DODEBUG(Start_End, printf("ex_stop%d: start\n", unit);); 548 549 /* 550 * Disable card operation: 551 * - Disable the interrupt line. 552 * - Flush transmission and disable reception. 553 * - Mask and clear all interrupts. 554 * - Reset the 82595. 555 */ 556 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel); 557 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT); 558 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel); 559 CSR_WRITE_1(sc, CMD_REG, Rcv_Stop); 560 sc->tx_head = sc->tx_tail = sc->tx_lower_limit; 561 sc->tx_last = 0; /* XXX I think these two lines are not necessary, because ex_init will always be called again to reinit the interface. */ 562 CSR_WRITE_1(sc, MASK_REG, All_Int); 563 CSR_WRITE_1(sc, STATUS_REG, All_Int); 564 CSR_WRITE_1(sc, CMD_REG, Reset_CMD); 565 DELAY(200); 566 567 DODEBUG(Start_End, printf("ex_stop%d: finish\n", unit);); 568 569 return; 570 } 571 572 void 573 ex_intr(void *arg) 574 { 575 struct ex_softc *sc = (struct ex_softc *)arg; 576 struct ifnet *ifp = &sc->arpcom.ac_if; 577 int int_status, send_pkts; 578 int loops = 100; 579 580 DODEBUG(Start_End, printf("ex_intr%d: start\n", unit);); 581 582 send_pkts = 0; 583 while (loops-- > 0 && 584 (int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) { 585 /* don't loop forever */ 586 if (int_status == 0xff) 587 break; 588 if (int_status & Rx_Int) { 589 CSR_WRITE_1(sc, STATUS_REG, Rx_Int); 590 ex_rx_intr(sc); 591 } else if (int_status & Tx_Int) { 592 CSR_WRITE_1(sc, STATUS_REG, Tx_Int); 593 ex_tx_intr(sc); 594 send_pkts = 1; 595 } 596 } 597 if (loops == 0) 598 printf("100 loops are not enough\n"); 599 600 /* 601 * If any packet has been transmitted, and there are queued packets to 602 * be sent, attempt to send more packets to the network card. 603 */ 604 if (send_pkts && (ifp->if_snd.ifq_head != NULL)) 605 ex_start(ifp); 606 607 DODEBUG(Start_End, printf("ex_intr%d: finish\n", unit);); 608 609 return; 610 } 611 612 static void 613 ex_tx_intr(struct ex_softc *sc) 614 { 615 struct ifnet * ifp = &sc->arpcom.ac_if; 616 int tx_status; 617 618 DODEBUG(Start_End, printf("ex_tx_intr%d: start\n", unit);); 619 620 /* 621 * - Cancel the watchdog. 622 * For all packets transmitted since last transmit interrupt: 623 * - Advance chain pointer to next queued packet. 624 * - Update statistics. 625 */ 626 627 ifp->if_timer = 0; 628 629 while (sc->tx_head != sc->tx_tail) { 630 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_head); 631 632 if (! CSR_READ_2(sc, IO_PORT_REG) & Done_bit) 633 break; 634 635 tx_status = CSR_READ_2(sc, IO_PORT_REG); 636 sc->tx_head = CSR_READ_2(sc, IO_PORT_REG); 637 638 if (tx_status & TX_OK_bit) { 639 ifp->if_opackets++; 640 } else { 641 ifp->if_oerrors++; 642 } 643 644 ifp->if_collisions += tx_status & No_Collisions_bits; 645 } 646 647 /* 648 * The card should be ready to accept more packets now. 649 */ 650 651 ifp->if_flags &= ~IFF_OACTIVE; 652 653 DODEBUG(Status, printf("OIDLE tx_intr\n");); 654 DODEBUG(Start_End, printf("ex_tx_intr%d: finish\n", unit);); 655 656 return; 657 } 658 659 static void 660 ex_rx_intr(struct ex_softc *sc) 661 { 662 struct ifnet * ifp = &sc->arpcom.ac_if; 663 int rx_status; 664 int pkt_len; 665 int QQQ; 666 struct mbuf * m; 667 struct mbuf * ipkt; 668 struct ether_header * eh; 669 670 DODEBUG(Start_End, printf("ex_rx_intr%d: start\n", unit);); 671 672 /* 673 * For all packets received since last receive interrupt: 674 * - If packet ok, read it into a new mbuf and queue it to interface, 675 * updating statistics. 676 * - If packet bad, just discard it, and update statistics. 677 * Finally, advance receive stop limit in card's memory to new location. 678 */ 679 680 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head); 681 682 while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) { 683 684 rx_status = CSR_READ_2(sc, IO_PORT_REG); 685 sc->rx_head = CSR_READ_2(sc, IO_PORT_REG); 686 QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG); 687 688 if (rx_status & RCV_OK_bit) { 689 MGETHDR(m, M_DONTWAIT, MT_DATA); 690 ipkt = m; 691 if (ipkt == NULL) { 692 ifp->if_iqdrops++; 693 } else { 694 ipkt->m_pkthdr.rcvif = ifp; 695 ipkt->m_pkthdr.len = pkt_len; 696 ipkt->m_len = MHLEN; 697 698 while (pkt_len > 0) { 699 if (pkt_len > MINCLSIZE) { 700 MCLGET(m, M_DONTWAIT); 701 if (m->m_flags & M_EXT) { 702 m->m_len = MCLBYTES; 703 } else { 704 m_freem(ipkt); 705 ifp->if_iqdrops++; 706 goto rx_another; 707 } 708 } 709 m->m_len = min(m->m_len, pkt_len); 710 711 /* 712 * NOTE: I'm assuming that all mbufs allocated are of even length, 713 * except for the last one in an odd-length packet. 714 */ 715 716 CSR_READ_MULTI_2(sc, IO_PORT_REG, 717 mtod(m, uint16_t *), m->m_len / 2); 718 719 if (m->m_len & 1) { 720 *(mtod(m, caddr_t) + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG); 721 } 722 pkt_len -= m->m_len; 723 724 if (pkt_len > 0) { 725 MGET(m->m_next, M_DONTWAIT, MT_DATA); 726 if (m->m_next == NULL) { 727 m_freem(ipkt); 728 ifp->if_iqdrops++; 729 goto rx_another; 730 } 731 m = m->m_next; 732 m->m_len = MLEN; 733 } 734 } 735 eh = mtod(ipkt, struct ether_header *); 736 #ifdef EXDEBUG 737 if (debug_mask & Rcvd_Pkts) { 738 if ((eh->ether_dhost[5] != 0xff) || (eh->ether_dhost[0] != 0xff)) { 739 printf("Receive packet with %d data bytes: %6D -> ", QQQ, eh->ether_shost, ":"); 740 printf("%6D\n", eh->ether_dhost, ":"); 741 } /* QQQ */ 742 } 743 #endif 744 (*ifp->if_input)(ifp, ipkt); 745 ifp->if_ipackets++; 746 } 747 } else { 748 ifp->if_ierrors++; 749 } 750 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head); 751 rx_another: ; 752 } 753 754 if (sc->rx_head < sc->rx_lower_limit + 2) 755 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit); 756 else 757 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_head - 2); 758 759 DODEBUG(Start_End, printf("ex_rx_intr%d: finish\n", unit);); 760 761 return; 762 } 763 764 765 static int 766 ex_ioctl(register struct ifnet *ifp, u_long cmd, caddr_t data) 767 { 768 struct ex_softc * sc = ifp->if_softc; 769 struct ifreq * ifr = (struct ifreq *)data; 770 int s; 771 int error = 0; 772 773 DODEBUG(Start_End, printf("%s: ex_ioctl: start ", ifp->if_xname);); 774 775 s = splimp(); 776 777 switch(cmd) { 778 case SIOCSIFADDR: 779 case SIOCGIFADDR: 780 case SIOCSIFMTU: 781 error = ether_ioctl(ifp, cmd, data); 782 break; 783 784 case SIOCSIFFLAGS: 785 DODEBUG(Start_End, printf("SIOCSIFFLAGS");); 786 if ((ifp->if_flags & IFF_UP) == 0 && 787 (ifp->if_flags & IFF_RUNNING)) { 788 789 ifp->if_flags &= ~IFF_RUNNING; 790 ex_stop(sc); 791 } else { 792 ex_init(sc); 793 } 794 break; 795 #ifdef NODEF 796 case SIOCGHWADDR: 797 DODEBUG(Start_End, printf("SIOCGHWADDR");); 798 bcopy((caddr_t)sc->sc_addr, (caddr_t)&ifr->ifr_data, 799 sizeof(sc->sc_addr)); 800 break; 801 #endif 802 case SIOCADDMULTI: 803 case SIOCDELMULTI: 804 ex_init(sc); 805 error = 0; 806 break; 807 case SIOCSIFMEDIA: 808 case SIOCGIFMEDIA: 809 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, cmd); 810 break; 811 default: 812 DODEBUG(Start_End, printf("unknown");); 813 error = EINVAL; 814 } 815 816 splx(s); 817 818 DODEBUG(Start_End, printf("\n%s: ex_ioctl: finish\n", ifp->if_xname);); 819 820 return(error); 821 } 822 823 static void 824 ex_setmulti(struct ex_softc *sc) 825 { 826 struct ifnet *ifp; 827 struct ifmultiaddr *maddr; 828 uint16_t *addr; 829 int count; 830 int timeout, status; 831 832 ifp = &sc->arpcom.ac_if; 833 834 count = 0; 835 TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) { 836 if (maddr->ifma_addr->sa_family != AF_LINK) 837 continue; 838 count++; 839 } 840 841 if ((ifp->if_flags & IFF_PROMISC) || (ifp->if_flags & IFF_ALLMULTI) 842 || count > 63) { 843 /* Interface is in promiscuous mode or there are too many 844 * multicast addresses for the card to handle */ 845 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel); 846 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode); 847 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3)); 848 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel); 849 } 850 else if ((ifp->if_flags & IFF_MULTICAST) && (count > 0)) { 851 /* Program multicast addresses plus our MAC address 852 * into the filter */ 853 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel); 854 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Multi_IA); 855 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3)); 856 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel); 857 858 /* Borrow space from TX buffer; this should be safe 859 * as this is only called from ex_init */ 860 861 CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_lower_limit); 862 CSR_WRITE_2(sc, IO_PORT_REG, MC_Setup_CMD); 863 CSR_WRITE_2(sc, IO_PORT_REG, 0); 864 CSR_WRITE_2(sc, IO_PORT_REG, 0); 865 CSR_WRITE_2(sc, IO_PORT_REG, (count + 1) * 6); 866 867 TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) { 868 if (maddr->ifma_addr->sa_family != AF_LINK) 869 continue; 870 871 addr = (uint16_t*)LLADDR((struct sockaddr_dl *) 872 maddr->ifma_addr); 873 CSR_WRITE_2(sc, IO_PORT_REG, *addr++); 874 CSR_WRITE_2(sc, IO_PORT_REG, *addr++); 875 CSR_WRITE_2(sc, IO_PORT_REG, *addr++); 876 } 877 878 /* Program our MAC address as well */ 879 /* XXX: Is this necessary? The Linux driver does this 880 * but the NetBSD driver does not */ 881 addr = (uint16_t*)(&sc->arpcom.ac_enaddr); 882 CSR_WRITE_2(sc, IO_PORT_REG, *addr++); 883 CSR_WRITE_2(sc, IO_PORT_REG, *addr++); 884 CSR_WRITE_2(sc, IO_PORT_REG, *addr++); 885 886 CSR_READ_2(sc, IO_PORT_REG); 887 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit); 888 CSR_WRITE_1(sc, CMD_REG, MC_Setup_CMD); 889 890 sc->tx_head = sc->tx_lower_limit; 891 sc->tx_tail = sc->tx_head + XMT_HEADER_LEN + (count + 1) * 6; 892 893 for (timeout=0; timeout<100; timeout++) { 894 DELAY(2); 895 if ((CSR_READ_1(sc, STATUS_REG) & Exec_Int) == 0) 896 continue; 897 898 status = CSR_READ_1(sc, CMD_REG); 899 CSR_WRITE_1(sc, STATUS_REG, Exec_Int); 900 break; 901 } 902 903 sc->tx_head = sc->tx_tail; 904 } 905 else 906 { 907 /* No multicast or promiscuous mode */ 908 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel); 909 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) & 0xDE); 910 /* ~(Multi_IA | Promisc_Mode) */ 911 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3)); 912 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel); 913 } 914 } 915 916 static void 917 ex_reset(struct ex_softc *sc) 918 { 919 int s; 920 921 DODEBUG(Start_End, printf("ex_reset%d: start\n", unit);); 922 923 s = splimp(); 924 925 ex_stop(sc); 926 ex_init(sc); 927 928 splx(s); 929 930 DODEBUG(Start_End, printf("ex_reset%d: finish\n", unit);); 931 932 return; 933 } 934 935 static void 936 ex_watchdog(struct ifnet *ifp) 937 { 938 struct ex_softc * sc = ifp->if_softc; 939 940 DODEBUG(Start_End, printf("%s: ex_watchdog: start\n", ifp->if_xname);); 941 942 ifp->if_flags &= ~IFF_OACTIVE; 943 944 DODEBUG(Status, printf("OIDLE watchdog\n");); 945 946 ifp->if_oerrors++; 947 ex_reset(sc); 948 ex_start(ifp); 949 950 DODEBUG(Start_End, printf("%s: ex_watchdog: finish\n", ifp->if_xname);); 951 952 return; 953 } 954 955 static int 956 ex_get_media(struct ex_softc *sc) 957 { 958 int current; 959 int media; 960 961 media = ex_eeprom_read(sc, EE_W5); 962 963 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel); 964 current = CSR_READ_1(sc, REG3); 965 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel); 966 967 if ((current & TPE_bit) && (media & EE_W5_PORT_TPE)) 968 return(IFM_ETHER|IFM_10_T); 969 if ((current & BNC_bit) && (media & EE_W5_PORT_BNC)) 970 return(IFM_ETHER|IFM_10_2); 971 972 if (media & EE_W5_PORT_AUI) 973 return (IFM_ETHER|IFM_10_5); 974 975 return (IFM_ETHER|IFM_AUTO); 976 } 977 978 static int 979 ex_ifmedia_upd(ifp) 980 struct ifnet * ifp; 981 { 982 struct ex_softc * sc = ifp->if_softc; 983 984 if (IFM_TYPE(sc->ifmedia.ifm_media) != IFM_ETHER) 985 return EINVAL; 986 987 return (0); 988 } 989 990 static void 991 ex_ifmedia_sts(ifp, ifmr) 992 struct ifnet * ifp; 993 struct ifmediareq * ifmr; 994 { 995 struct ex_softc * sc = ifp->if_softc; 996 997 ifmr->ifm_active = ex_get_media(sc); 998 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 999 1000 return; 1001 } 1002 1003 u_short 1004 ex_eeprom_read(struct ex_softc *sc, int location) 1005 { 1006 int i; 1007 u_short data = 0; 1008 int read_cmd = location | EE_READ_CMD; 1009 short ctrl_val = EECS; 1010 1011 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel); 1012 CSR_WRITE_1(sc, EEPROM_REG, EECS); 1013 for (i = 8; i >= 0; i--) { 1014 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val; 1015 CSR_WRITE_1(sc, EEPROM_REG, outval); 1016 CSR_WRITE_1(sc, EEPROM_REG, outval | EESK); 1017 DELAY(3); 1018 CSR_WRITE_1(sc, EEPROM_REG, outval); 1019 DELAY(2); 1020 } 1021 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val); 1022 1023 for (i = 16; i > 0; i--) { 1024 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK); 1025 DELAY(3); 1026 data = (data << 1) | 1027 ((CSR_READ_1(sc, EEPROM_REG) & EEDO) ? 1 : 0); 1028 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val); 1029 DELAY(2); 1030 } 1031 1032 ctrl_val &= ~EECS; 1033 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK); 1034 DELAY(3); 1035 CSR_WRITE_1(sc, EEPROM_REG, ctrl_val); 1036 DELAY(2); 1037 CSR_WRITE_1(sc, CMD_REG, Bank0_Sel); 1038 return(data); 1039 } 1040