1 /*- 2 * Copyright (c) 2004 Scott Long 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 /* $NetBSD: esp_sbus.c,v 1.27 2002/12/10 13:44:47 pk Exp $ */ 29 30 /*- 31 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 36 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 #include <sys/cdefs.h> 68 __FBSDID("$FreeBSD$"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/bus.h> 73 #include <sys/kernel.h> 74 #include <sys/module.h> 75 #include <sys/resource.h> 76 #include <sys/lock.h> 77 #include <sys/mutex.h> 78 79 #include <machine/bus.h> 80 #include <dev/ofw/openfirm.h> 81 #include <machine/ofw_machdep.h> 82 #include <machine/resource.h> 83 #include <sys/rman.h> 84 #include <sparc64/sbus/sbusvar.h> 85 86 #include <cam/cam.h> 87 #include <cam/cam_ccb.h> 88 #include <cam/scsi/scsi_all.h> 89 90 #include <dev/esp/lsi64854reg.h> 91 #include <dev/esp/lsi64854var.h> 92 93 #include <dev/esp/ncr53c9xreg.h> 94 #include <dev/esp/ncr53c9xvar.h> 95 96 /* #define ESP_SBUS_DEBUG */ 97 98 struct esp_softc { 99 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 100 struct device *sc_dev; 101 102 int sc_rid; 103 struct resource *sc_res; 104 bus_space_handle_t sc_regh; 105 bus_space_tag_t sc_regt; 106 107 int sc_irqrid; 108 struct resource *sc_irqres; 109 void *sc_irq; 110 111 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 112 113 int sc_pri; /* SBUS priority */ 114 }; 115 116 static int esp_sbus_probe(device_t); 117 static int esp_sbus_attach(device_t); 118 static int esp_sbus_detach(device_t); 119 static int esp_sbus_suspend(device_t); 120 static int esp_sbus_resume(device_t); 121 122 static device_method_t esp_sbus_methods[] = { 123 DEVMETHOD(device_probe, esp_sbus_probe), 124 DEVMETHOD(device_attach, esp_sbus_attach), 125 DEVMETHOD(device_detach, esp_sbus_detach), 126 DEVMETHOD(device_suspend, esp_sbus_suspend), 127 DEVMETHOD(device_resume, esp_sbus_resume), 128 {0, 0} 129 }; 130 131 static driver_t esp_sbus_driver = { 132 "esp", 133 esp_sbus_methods, 134 sizeof(struct esp_softc) 135 }; 136 137 static devclass_t esp_devclass; 138 DRIVER_MODULE(esp, sbus, esp_sbus_driver, esp_devclass, 0, 0); 139 140 /* 141 * Functions and the switch for the MI code. 142 */ 143 static u_char esp_read_reg(struct ncr53c9x_softc *, int); 144 static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 145 static int esp_dma_isintr(struct ncr53c9x_softc *); 146 static void esp_dma_reset(struct ncr53c9x_softc *); 147 static int esp_dma_intr(struct ncr53c9x_softc *); 148 static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, 149 int, size_t *); 150 static void esp_dma_go(struct ncr53c9x_softc *); 151 static void esp_dma_stop(struct ncr53c9x_softc *); 152 static int esp_dma_isactive(struct ncr53c9x_softc *); 153 static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 154 155 static struct ncr53c9x_glue esp_sbus_glue = { 156 esp_read_reg, 157 esp_write_reg, 158 esp_dma_isintr, 159 esp_dma_reset, 160 esp_dma_intr, 161 esp_dma_setup, 162 esp_dma_go, 163 esp_dma_stop, 164 esp_dma_isactive, 165 NULL, /* gl_clear_latched_intr */ 166 }; 167 168 static int 169 esp_sbus_probe(device_t dev) 170 { 171 char *name; 172 173 name = sbus_get_name(dev); 174 if (strcmp("SUNW,fas", name) == 0) { 175 device_set_desc(dev, "Sun FAS366 Fast-Wide SCSI"); 176 return (-10); 177 } 178 179 return (ENXIO); 180 } 181 182 static int 183 esp_sbus_attach(device_t dev) 184 { 185 struct esp_softc *esc = device_get_softc(dev); 186 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 187 struct lsi64854_softc *lsc; 188 phandle_t node; 189 int burst; 190 191 esc->sc_dev = dev; 192 node = sbus_get_node(dev); 193 if (OF_getprop(node, "initiator-id", &sc->sc_id, 194 sizeof(sc->sc_id)) == -1) 195 sc->sc_id = 7;; 196 sc->sc_freq = sbus_get_clockfreq(dev); 197 198 #ifdef ESP_SBUS_DEBUG 199 device_printf(dev, "espattach_sbus: sc_id %d, freq %d\n", 200 sc->sc_id, sc->sc_freq); 201 #endif 202 203 /* 204 * allocate space for dma, in SUNW,fas there are no separate 205 * dma device 206 */ 207 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 208 209 if (lsc == NULL) { 210 device_printf(dev, "out of memory (lsi64854_softc)\n"); 211 return (ENOMEM); 212 } 213 esc->sc_dma = lsc; 214 215 /* 216 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 217 */ 218 219 /* Map dma registers */ 220 lsc->sc_rid = 0; 221 if ((lsc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 222 &lsc->sc_rid, RF_ACTIVE)) == NULL) { 223 device_printf(dev, "cannot map dma registers\n"); 224 free(lsc, M_DEVBUF); 225 return (ENXIO); 226 } 227 lsc->sc_regt = rman_get_bustag(lsc->sc_res); 228 lsc->sc_regh = rman_get_bushandle(lsc->sc_res); 229 230 /* Create a parent DMA tag based on this bus */ 231 if (bus_dma_tag_create(NULL, /* parent */ 232 PAGE_SIZE, 0, /* algnmnt, boundary */ 233 BUS_SPACE_MAXADDR, /* lowaddr */ 234 BUS_SPACE_MAXADDR, /* highaddr */ 235 NULL, NULL, /* filter, filterarg */ 236 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 237 0, /* nsegments */ 238 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 239 0, /* flags */ 240 NULL, NULL, /* No locking */ 241 &lsc->sc_parent_dmat)) { 242 device_printf(dev, "cannot allocate parent DMA tag\n"); 243 free(lsc, M_DEVBUF); 244 return (ENOMEM); 245 } 246 burst = sbus_get_burstsz(dev); 247 248 #ifdef ESP_SBUS_DEBUG 249 printf("espattach_sbus: burst 0x%x\n", burst); 250 #endif 251 252 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 253 (burst & SBUS_BURST_16) ? 16 : 0; 254 255 lsc->sc_channel = L64854_CHANNEL_SCSI; 256 lsc->sc_client = sc; 257 lsc->sc_dev = dev; 258 259 lsi64854_attach(lsc); 260 261 /* 262 * map SCSI core registers 263 */ 264 esc->sc_rid = 1; 265 if ((esc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 266 &esc->sc_rid, RF_ACTIVE)) == NULL) { 267 device_printf(dev, "cannot map scsi core registers\n"); 268 free(lsc, M_DEVBUF); 269 return (ENXIO); 270 } 271 esc->sc_regt = rman_get_bustag(esc->sc_res); 272 esc->sc_regh = rman_get_bushandle(esc->sc_res); 273 274 #if 0 275 esc->sc_pri = sa->sa_pri; 276 277 /* add me to the sbus structures */ 278 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 279 sbus_establish(&esc->sc_sd, &sc->sc_dev); 280 #endif 281 282 espattach(esc, &esp_sbus_glue); 283 284 return (0); 285 } 286 287 static int 288 esp_sbus_detach(device_t dev) 289 { 290 struct ncr53c9x_softc *sc; 291 struct esp_softc *esc; 292 293 esc = device_get_softc(dev); 294 sc = &esc->sc_ncr53c9x; 295 return (ncr53c9x_detach(sc, 0)); 296 } 297 298 static int 299 esp_sbus_suspend(device_t dev) 300 { 301 return (ENXIO); 302 } 303 304 static int 305 esp_sbus_resume(device_t dev) 306 { 307 return (ENXIO); 308 } 309 310 /* 311 * Attach this instance, and then all the sub-devices 312 */ 313 void 314 espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 315 { 316 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 317 unsigned int uid = 0; 318 319 /* 320 * Set up glue for MI code early; we use some of it here. 321 */ 322 sc->sc_glue = gluep; 323 324 /* gimme MHz */ 325 sc->sc_freq /= 1000000; 326 327 /* 328 * XXX More of this should be in ncr53c9x_attach(), but 329 * XXX should we really poke around the chip that much in 330 * XXX the MI code? Think about this more... 331 */ 332 333 /* 334 * It is necessary to try to load the 2nd config register here, 335 * to find out what rev the esp chip is, else the ncr53c9x_reset 336 * will not set up the defaults correctly. 337 */ 338 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 339 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 340 sc->sc_cfg3 = NCRCFG3_CDB; 341 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 342 343 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 344 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 345 sc->sc_rev = NCR_VARIANT_ESP100; 346 } else { 347 sc->sc_cfg2 = NCRCFG2_SCSI2; 348 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 349 sc->sc_cfg3 = 0; 350 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 351 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 352 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 353 if (NCR_READ_REG(sc, NCR_CFG3) != 354 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 355 sc->sc_rev = NCR_VARIANT_ESP100A; 356 } else { 357 /* NCRCFG2_FE enables > 64K transfers */ 358 sc->sc_cfg2 |= NCRCFG2_FE; 359 sc->sc_cfg3 = 0; 360 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 361 sc->sc_rev = NCR_VARIANT_ESP200; 362 363 /* XXX spec says it's valid after power up or chip reset */ 364 uid = NCR_READ_REG(sc, NCR_UID); 365 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 366 sc->sc_rev = NCR_VARIANT_FAS366; 367 } 368 } 369 370 #ifdef ESP_SBUS_DEBUG 371 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 372 #endif 373 374 /* 375 * XXX minsync and maxxfer _should_ be set up in MI code, 376 * XXX but it appears to have some dependency on what sort 377 * XXX of DMA we're hooked up to, etc. 378 */ 379 380 /* 381 * This is the value used to start sync negotiations 382 * Note that the NCR register "SYNCTP" is programmed 383 * in "clocks per byte", and has a minimum value of 4. 384 * The SCSI period used in negotiation is one-fourth 385 * of the time (in nanoseconds) needed to transfer one byte. 386 * Since the chip's clock is given in MHz, we have the following 387 * formula: 4 * period = (1000 / freq) * 4 388 */ 389 sc->sc_minsync = 1000 / sc->sc_freq; 390 391 /* limit minsync due to unsolved performance issues */ 392 sc->sc_maxsync = sc->sc_minsync; 393 sc->sc_maxoffset = 15; 394 395 sc->sc_extended_geom = 1; 396 397 /* 398 * Alas, we must now modify the value a bit, because it's 399 * only valid when can switch on FASTCLK and FASTSCSI bits 400 * in config register 3... 401 */ 402 switch (sc->sc_rev) { 403 case NCR_VARIANT_ESP100: 404 sc->sc_maxwidth = 0; 405 sc->sc_maxxfer = 64 * 1024; 406 sc->sc_minsync = 0; /* No synch on old chip? */ 407 break; 408 409 case NCR_VARIANT_ESP100A: 410 sc->sc_maxwidth = 1; 411 sc->sc_maxxfer = 64 * 1024; 412 /* Min clocks/byte is 5 */ 413 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 414 break; 415 416 case NCR_VARIANT_ESP200: 417 case NCR_VARIANT_FAS366: 418 sc->sc_maxwidth = 1; 419 sc->sc_maxxfer = 16 * 1024 * 1024; 420 /* XXX - do actually set FAST* bits */ 421 break; 422 } 423 424 /* Establish interrupt channel */ 425 esc->sc_irqrid = 0; 426 if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ, 427 &esc->sc_irqrid, RF_SHAREABLE|RF_ACTIVE)) == NULL) { 428 device_printf(esc->sc_dev, "Cannot allocate interrupt\n"); 429 return; 430 } 431 if (bus_setup_intr(esc->sc_dev, esc->sc_irqres, 432 INTR_TYPE_BIO|INTR_ENTROPY, ncr53c9x_intr, sc, &esc->sc_irq)) { 433 device_printf(esc->sc_dev, "Cannot set up interrupt\n"); 434 return; 435 } 436 437 /* Turn on target selection using the `dma' method */ 438 if (sc->sc_rev != NCR_VARIANT_FAS366) 439 sc->sc_features |= NCR_F_DMASELECT; 440 441 /* Do the common parts of attachment. */ 442 sc->sc_dev = esc->sc_dev; 443 ncr53c9x_attach(sc); 444 } 445 446 /* 447 * Glue functions. 448 */ 449 450 #ifdef ESP_SBUS_DEBUG 451 int esp_sbus_debug = 0; 452 453 static struct { 454 char *r_name; 455 int r_flag; 456 } esp__read_regnames [] = { 457 { "TCL", 0}, /* 0/00 */ 458 { "TCM", 0}, /* 1/04 */ 459 { "FIFO", 0}, /* 2/08 */ 460 { "CMD", 0}, /* 3/0c */ 461 { "STAT", 0}, /* 4/10 */ 462 { "INTR", 0}, /* 5/14 */ 463 { "STEP", 0}, /* 6/18 */ 464 { "FFLAGS", 1}, /* 7/1c */ 465 { "CFG1", 1}, /* 8/20 */ 466 { "STAT2", 0}, /* 9/24 */ 467 { "CFG4", 1}, /* a/28 */ 468 { "CFG2", 1}, /* b/2c */ 469 { "CFG3", 1}, /* c/30 */ 470 { "-none", 1}, /* d/34 */ 471 { "TCH", 1}, /* e/38 */ 472 { "TCX", 1}, /* f/3c */ 473 }; 474 475 static struct { 476 char *r_name; 477 int r_flag; 478 } esp__write_regnames[] = { 479 { "TCL", 1}, /* 0/00 */ 480 { "TCM", 1}, /* 1/04 */ 481 { "FIFO", 0}, /* 2/08 */ 482 { "CMD", 0}, /* 3/0c */ 483 { "SELID", 1}, /* 4/10 */ 484 { "TIMEOUT", 1}, /* 5/14 */ 485 { "SYNCTP", 1}, /* 6/18 */ 486 { "SYNCOFF", 1}, /* 7/1c */ 487 { "CFG1", 1}, /* 8/20 */ 488 { "CCF", 1}, /* 9/24 */ 489 { "TEST", 1}, /* a/28 */ 490 { "CFG2", 1}, /* b/2c */ 491 { "CFG3", 1}, /* c/30 */ 492 { "-none", 1}, /* d/34 */ 493 { "TCH", 1}, /* e/38 */ 494 { "TCX", 1}, /* f/3c */ 495 }; 496 #endif 497 498 u_char 499 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 500 { 501 struct esp_softc *esc = (struct esp_softc *)sc; 502 u_char v; 503 504 v = bus_space_read_1(esc->sc_regt, esc->sc_regh, reg * 4); 505 #ifdef ESP_SBUS_DEBUG 506 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 507 printf("RD:%x <%s> %x\n", reg * 4, 508 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 509 #endif 510 return v; 511 } 512 513 void 514 esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 515 { 516 struct esp_softc *esc = (struct esp_softc *)sc; 517 518 #ifdef ESP_SBUS_DEBUG 519 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 520 printf("WR:%x <%s> %x\n", reg * 4, 521 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 522 #endif 523 bus_space_write_1(esc->sc_regt, esc->sc_regh, reg * 4, v); 524 } 525 526 int 527 esp_dma_isintr(struct ncr53c9x_softc *sc) 528 { 529 struct esp_softc *esc = (struct esp_softc *)sc; 530 531 return (DMA_ISINTR(esc->sc_dma)); 532 } 533 534 void 535 esp_dma_reset(struct ncr53c9x_softc *sc) 536 { 537 struct esp_softc *esc = (struct esp_softc *)sc; 538 539 DMA_RESET(esc->sc_dma); 540 } 541 542 int 543 esp_dma_intr(struct ncr53c9x_softc *sc) 544 { 545 struct esp_softc *esc = (struct esp_softc *)sc; 546 547 return (DMA_INTR(esc->sc_dma)); 548 } 549 550 int 551 esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 552 int datain, size_t *dmasize) 553 { 554 struct esp_softc *esc = (struct esp_softc *)sc; 555 556 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 557 } 558 559 void 560 esp_dma_go(struct ncr53c9x_softc *sc) 561 { 562 struct esp_softc *esc = (struct esp_softc *)sc; 563 564 DMA_GO(esc->sc_dma); 565 } 566 567 void 568 esp_dma_stop(struct ncr53c9x_softc *sc) 569 { 570 struct esp_softc *esc = (struct esp_softc *)sc; 571 u_int32_t csr; 572 573 csr = L64854_GCSR(esc->sc_dma); 574 csr &= ~D_EN_DMA; 575 L64854_SCSR(esc->sc_dma, csr); 576 } 577 578 int 579 esp_dma_isactive(struct ncr53c9x_softc *sc) 580 { 581 struct esp_softc *esc = (struct esp_softc *)sc; 582 583 return (DMA_ISACTIVE(esc->sc_dma)); 584 } 585