1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1997 by Simon Shapiro 5 * All Rights Reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 /* 35 * 36 * dpt.h: Definitions and constants used by the SCSI side of the DPT 37 * 38 * credits: Mike Neuffer; DPT low level code and in other areas as well. 39 * Mark Salyzyn; Many vital bits of info and diagnostics. 40 * Justin Gibbs; FreeBSD API, debugging and style 41 * Ron McDaniels; SCSI Software Interrupts 42 * FreeBSD.ORG; Great O/S to work on and for. 43 */ 44 45 #ifndef _DPT_H 46 #define _DPT_H 47 48 #include <sys/ioccom.h> 49 50 51 #undef DPT_USE_DLM_SWI 52 53 #define DPT_RELEASE 1 54 #define DPT_VERSION 4 55 #define DPT_PATCH 5 56 #define DPT_MONTH 8 57 #define DPT_DAY 3 58 #define DPT_YEAR 18 /* 1998 - 1980 */ 59 60 #define DPT_CTL_RELEASE 1 61 #define DPT_CTL_VERSION 0 62 #define DPT_CTL_PATCH 6 63 64 #ifndef PAGESIZ 65 #define PAGESIZ 4096 66 #endif 67 68 #ifndef physaddr 69 typedef void *physaddr; 70 #endif 71 72 #undef DPT_INQUIRE_DEVICES /* We have no buyers for this function */ 73 #define DPT_SUPPORT_POLLING /* Use polled mode at boot (must be ON!) */ 74 #define DPT_OPENNINGS 8 /* Commands-in-progress per device */ 75 76 #define DPT_RETRIES 5 /* Times to retry failed commands */ 77 #undef DPT_DISABLE_SG 78 #define DPT_HAS_OPEN 79 80 /* Arguments to dpt_run_queue() can be: */ 81 82 #define DPT_MAX_TARGET_MODE_BUFFER_SIZE 8192 83 #define DPT_FREE_LIST_INCREMENT 64 84 #define DPT_CMD_LEN 12 85 86 /* 87 * How many segments do we want in a Scatter/Gather list? 88 * Some HBA's can do 16, Some 8192. Since we pre-allocate 89 * them in fixed increments, we need to put a practical limit on 90 * these. A passed parameter (from kernel boot or lkm) would help 91 */ 92 #define DPT_MAX_SEGS 32 93 94 /* Debug levels */ 95 96 #undef DPT_DEBUG_PCI 97 #undef DPT_DEBUG_INIT 98 #undef DPT_DEBUG_SETUP 99 #undef DPT_DEBUG_STATES 100 #undef DPT_DEBUG_CONFIG 101 #undef DPT_DEBUG_QUEUES 102 #undef DPT_DEBUG_SCSI_CMD 103 #undef DPT_DEBUG_SOFTINTR 104 #undef DPT_DEBUG_HARDINTR 105 #undef DPT_DEBUG_HEX_DUMPS 106 #undef DPT_DEBUG_POLLING 107 #undef DPT_DEBUG_INQUIRE 108 #undef DPT_DEBUG_COMPLETION 109 #undef DPT_DEBUG_COMPLETION_ERRORS 110 #define DPT_DEBUG_MINPHYS 111 #undef DPT_DEBUG_SG 112 #undef DPT_DEBUG_SG_SHOW_DATA 113 #undef DPT_DEBUG_SCSI_CMD_NAME 114 #undef DPT_DEBUG_CONTROL 115 #undef DPT_DEBUG_TIMEOUTS 116 #undef DPT_DEBUG_SHUTDOWN 117 #define DPT_DEBUG_USER_CMD 118 119 /* 120 * Misc. definitions 121 */ 122 #undef TRUE 123 #undef FALSE 124 #define TRUE 1 125 #define FALSE 0 126 127 #define MAX_CHANNELS 3 128 #define MAX_TARGETS 16 129 #define MAX_LUNS 8 130 131 /* Map minor numbers to device identity */ 132 #define TARGET_MASK 0x000f 133 #define BUS_MASK 0x0030 134 #define HBA_MASK 0x01c0 135 #define LUN_MASK 0x0e00 136 137 #define minor2target(minor) ( minor & TARGET_MASK ) 138 #define minor2bus(minor) ( (minor & BUS_MASK) >> 4 ) 139 #define minor2hba(minor) ( (minor & HBA_MASK) >> 6 ) 140 #define minor2lun(minor) ( (minor & LUN_MASK) >> 9 ) 141 142 /* 143 * Valid values for cache_type 144 */ 145 #define DPT_NO_CACHE 0 146 #define DPT_CACHE_WRITETHROUGH 1 147 #define DPT_CACHE_WRITEBACK 2 148 149 #define min(a,b) ((a<b)?(a):(b)) 150 151 #define MAXISA 4 152 #define MAXPCI 16 153 #define MAXIRQ 16 154 #define MAXTARGET 16 155 156 #define IS_ISA 'I' 157 #define IS_PCI 'P' 158 159 #define BUSMASTER 0xff 160 #define PIO 0xfe 161 162 #define EATA_SIGNATURE 0x41544145 /* little ENDIAN "EATA" */ 163 #define DPT_BLINK_INDICATOR 0x42445054 164 165 #define DPT_ID1 0x12 166 #define DPT_ID2 0x1 167 #define ATT_ID1 0x06 168 #define ATT_ID2 0x94 169 #define ATT_ID3 0x0 170 171 #define NEC_ID1 0x38 172 #define NEC_ID2 0xa3 173 #define NEC_ID3 0x82 174 175 #define MAX_PCI_DEVICES 32 /* Maximum # Of Devices Per Bus */ 176 #define MAX_METHOD_2 16 /* Max Devices For Method 2 */ 177 #define MAX_PCI_BUS 16 /* Maximum # Of Busses Allowed */ 178 179 #define DPT_MAX_RETRIES 2 180 181 #define READ 0 182 #define WRITE 1 183 #define OTHER 2 184 185 #define HD(cmd) ((hostdata *)&(cmd->host->hostdata)) 186 #define CD(cmd) ((struct eata_ccb *)(cmd->host_scribble)) 187 #define SD(host) ((hostdata *)&(host->hostdata)) 188 189 /* 190 * EATA Command & Register definitions 191 */ 192 193 #define PCI_REG_DPTconfig 0x40 194 #define PCI_REG_PumpModeAddress 0x44 195 #define PCI_REG_PumpModeData 0x48 196 #define PCI_REG_ConfigParam1 0x50 197 #define PCI_REG_ConfigParam2 0x54 198 199 #define EATA_CMD_RESET 0xf9 200 #define EATA_COLD_BOOT 0x06 /* Last resort only! */ 201 202 #define EATA_CMD_IMMEDIATE 0xfa 203 204 #define EATA_CMD_DMA_READ_CONFIG 0xfd 205 #define EATA_CMD_DMA_SET_CONFIG 0xfe 206 #define EATA_CMD_DMA_SEND_CP 0xff 207 208 #define ECS_EMULATE_SENSE 0xd4 209 210 /* 211 * Immediate Commands 212 * Beware of this enumeration. Not all commands are in sequence! 213 */ 214 215 enum dpt_immediate_cmd { 216 EATA_GENERIC_ABORT, 217 EATA_SPECIFIC_RESET, 218 EATA_BUS_RESET, 219 EATA_SPECIFIC_ABORT, 220 EATA_QUIET_INTR, 221 EATA_SMART_ROM_DL_EN, 222 EATA_COLD_BOOT_HBA, /* Only as a last resort */ 223 EATA_FORCE_IO, 224 EATA_SCSI_BUS_OFFLINE, 225 EATA_RESET_MASKED_BUS, 226 EATA_POWER_OFF_WARN 227 }; 228 229 #define HA_CTRLREG 0x206 /* control register for HBA */ 230 #define HA_CTRL_DISINT 0x02 /* CTRLREG: disable interrupts */ 231 #define HA_CTRL_RESCPU 0x04 /* CTRLREG: reset processo */ 232 #define HA_CTRL_8HEADS 0x08 /* 233 * CTRLREG: set for drives with 234 * >=8 heads 235 * (WD1003 rudimentary :-) 236 */ 237 238 #define HA_WCOMMAND 0x07 /* command register offset */ 239 #define HA_WIFC 0x06 /* immediate command offset */ 240 #define HA_WCODE 0x05 241 #define HA_WCODE2 0x04 242 #define HA_WDMAADDR 0x02 /* DMA address LSB offset */ 243 #define HA_RERROR 0x01 /* Error Register, offset 1 from base */ 244 #define HA_RAUXSTAT 0x08 /* aux status register offset */ 245 #define HA_RSTATUS 0x07 /* status register offset */ 246 #define HA_RDATA 0x00 /* data register (16bit) */ 247 #define HA_WDATA 0x00 /* data register (16bit) */ 248 249 #define HA_ABUSY 0x01 /* aux busy bit */ 250 #define HA_AIRQ 0x02 /* aux IRQ pending bit */ 251 #define HA_SERROR 0x01 /* pr. command ended in error */ 252 #define HA_SMORE 0x02 /* more data soon to come */ 253 #define HA_SCORR 0x04 /* datio_addra corrected */ 254 #define HA_SDRQ 0x08 /* data request active */ 255 #define HA_SSC 0x10 /* seek complete */ 256 #define HA_SFAULT 0x20 /* write fault */ 257 #define HA_SREADY 0x40 /* drive ready */ 258 #define HA_SBUSY 0x80 /* drive busy */ 259 #define HA_SDRDY (HA_SSC|HA_SREADY|HA_SDRQ) 260 261 /* 262 * Message definitions 263 */ 264 265 enum dpt_message { 266 HA_NO_ERROR, /* No Error */ 267 HA_ERR_SEL_TO, /* Selection Timeout */ 268 HA_ERR_CMD_TO, /* Command Timeout */ 269 HA_SCSIBUS_RESET, 270 HA_HBA_POWER_UP, /* Initial Controller Power-up */ 271 HA_UNX_BUSPHASE, /* Unexpected Bus Phase */ 272 HA_UNX_BUS_FREE, /* Unexpected Bus Free */ 273 HA_BUS_PARITY, /* Bus Parity Error */ 274 HA_SCSI_HUNG, /* SCSI Hung */ 275 HA_UNX_MSGRJCT, /* Unexpected Message Rejected */ 276 HA_RESET_STUCK, /* SCSI Bus Reset Stuck */ 277 HA_RSENSE_FAIL, /* Auto Request-Sense Failed */ 278 HA_PARITY_ERR, /* Controller Ram Parity Error */ 279 HA_CP_ABORT_NA, /* Abort Message sent to non-active cmd */ 280 HA_CP_ABORTED, /* Abort Message sent to active cmd */ 281 HA_CP_RESET_NA, /* Reset Message sent to non-active cmd */ 282 HA_CP_RESET, /* Reset Message sent to active cmd */ 283 HA_ECC_ERR, /* Controller Ram ECC Error */ 284 HA_PCI_PARITY, /* PCI Parity Error */ 285 HA_PCI_MABORT, /* PCI Master Abort */ 286 HA_PCI_TABORT, /* PCI Target Abort */ 287 HA_PCI_STABORT /* PCI Signaled Target Abort */ 288 }; 289 290 #define HA_STATUS_MASK 0x7F 291 #define HA_IDENTIFY_MSG 0x80 292 #define HA_DISCO_RECO 0x40 /* Disconnect/Reconnect */ 293 294 #define DPT_RW_BUFF_HEART 0X00 295 #define DPT_RW_BUFF_DLM 0x02 296 #define DPT_RW_BUFF_ACCESS 0x03 297 298 #define HA_INTR_OFF 1 299 #define HA_INTR_ON 0 300 301 /* This is really a one-time shot through some black magic */ 302 #define DPT_EATA_REVA 0x1c 303 #define DPT_EATA_REVB 0x1e 304 #define DPT_EATA_REVC 0x22 305 #define DPT_EATA_REVZ 0x24 306 307 308 /* IOCTL List */ 309 310 #define DPT_RW_CMD_LEN 32 311 #define DPT_RW_CMD_DUMP_SOFTC "dump softc" 312 #define DPT_RW_CMD_DUMP_SYSINFO "dump sysinfo" 313 #define DPT_RW_CMD_DUMP_METRICS "dump metrics" 314 #define DPT_RW_CMD_CLEAR_METRICS "clear metrics" 315 #define DPT_RW_CMD_SHOW_LED "show LED" 316 317 #define DPT_IOCTL_INTERNAL_METRICS _IOR('D', 1, dpt_perf_t) 318 #define DPT_IOCTL_SOFTC _IOR('D', 2, dpt_user_softc_t) 319 #define DPT_IOCTL_SEND _IOWR('D', 3, eata_pt_t) 320 #define SDI_SEND 0x40044444 /* Observed from dptmgr */ 321 322 /* 323 * Other definitions 324 */ 325 326 #define DPT_HCP_LENGTH(page) (ntohs(*(int16_t *)(void *)(&page[2]))+4) 327 #define DPT_HCP_FIRST(page) (&page[4]) 328 #define DPT_HCP_NEXT(param) (¶m[3 + param[3] + 1]) 329 #define DPT_HCP_CODE(param) (ntohs(*(int16_t *)(void *)param)) 330 331 332 /* Possible return values from dpt_register_buffer() */ 333 334 #define SCSI_TM_READ_BUFFER 0x3c 335 #define SCSI_TM_WRITE_BUFFER 0x3b 336 337 #define SCSI_TM_MODE_MASK 0x07 /* Strip off reserved and LUN */ 338 #define SCSI_TM_LUN_MASK 0xe0 /* Strip off reserved and LUN */ 339 340 typedef enum { 341 SUCCESSFULLY_REGISTERED, 342 DRIVER_DOWN, 343 ALREADY_REGISTERED, 344 REGISTERED_TO_ANOTHER, 345 NOT_REGISTERED, 346 INVALID_UNIT, 347 INVALID_SENDER, 348 INVALID_CALLBACK, 349 NO_RESOURCES 350 } dpt_rb_t; 351 352 typedef enum { 353 REGISTER_BUFFER, 354 RELEASE_BUFFER 355 } dpt_rb_op_t; 356 357 /* 358 * New way for completion routines to reliably copmplete processing. 359 * Should take properly typed dpt_softc_t and dpt_ccb_t, 360 * but interdependencies preclude that. 361 */ 362 typedef void (*ccb_callback)(void *dpt, int bus, void *ccb); 363 364 typedef void (*buff_wr_done)(int unit, u_int8_t channel, u_int8_t target, 365 u_int8_t lun, u_int16_t offset, u_int16_t length, 366 int result); 367 368 typedef void (*dpt_rec_buff)(int unit, u_int8_t channel, u_int8_t target, 369 u_int8_t lun, void *buffer, u_int16_t offset, 370 u_int16_t length); 371 372 /* HBA's Status port (register) bitmap */ 373 typedef struct reg_bit { /* reading this one will clear the interrupt */ 374 u_int8_t error :1, /* previous command ended in an error */ 375 more :1, /* More DATA coming soon Poll BSY & DRQ (PIO) */ 376 corr :1, /* data read was successfully corrected with ECC */ 377 drq :1, /* data request active */ 378 sc :1, /* seek complete */ 379 fault :1, /* write fault */ 380 ready :1, /* drive ready */ 381 busy :1; /* controller busy */ 382 } dpt_status_reg_t; 383 384 /* HBA's Auxiliary status port (register) bitmap */ 385 typedef struct reg_abit { /* reading this won't clear the interrupt */ 386 u_int8_t abusy :1, /* auxiliary busy */ 387 irq :1, /* set when drive interrupt is asserted */ 388 :6; 389 } dpt_aux_status_t; 390 391 /* The EATA Register Set as a structure */ 392 typedef struct eata_register { 393 u_int8_t data_reg[2]; /* R, couldn't figure this one out */ 394 u_int8_t cp_addr[4]; /* W, CP address register */ 395 union { 396 u_int8_t command; /* 397 * W, command code: 398 * [read|set] conf, send CP 399 */ 400 struct reg_bit status; /* R, see register_bit1 */ 401 u_int8_t statusbyte; 402 } ovr; 403 struct reg_abit aux_stat; /* R, see register_bit2 */ 404 } eata_reg_t; 405 406 /* 407 * Holds the results of a READ_CONFIGURATION command 408 * Beware of data items which are larger than 1 byte. 409 * these come from the DPT in network order. 410 * On an Intel ``CPU'' they will be upside down and backwards! 411 * The dpt_get_conf function is normally responsible for flipping 412 * Everything back. 413 */ 414 typedef struct get_conf { /* Read Configuration Array */ 415 union { 416 struct { 417 u_int8_t foo_DevType; 418 u_int8_t foo_PageCode; 419 u_int8_t foo_Reserved0; 420 u_int8_t foo_len; 421 } foo; 422 u_int32_t foo_length; /* Should return 0x22, 0x24, etc */ 423 } bar; 424 #define gcs_length bar.foo_length 425 #define gcs_PageCode bar.foo.foo_DevType 426 #define gcs_reserved0 bar.foo.foo_Reserved0 427 #define gcs_len bar.foo.foo_len 428 429 u_int32_t signature; /* Signature MUST be "EATA". ntohl()`ed */ 430 431 u_int8_t version2 :4, 432 version :4; /* EATA Version level */ 433 434 u_int8_t OCS_enabled :1, /* Overlap Command Support enabled */ 435 TAR_support :1, /* SCSI Target Mode supported */ 436 TRNXFR :1, /* Truncate Transfer Cmd Used in PIO Mode */ 437 MORE_support:1, /* MORE supported (PIO Mode Only) */ 438 DMA_support :1, /* DMA supported */ 439 DMA_valid :1, /* DRQ value in Byte 30 is valid */ 440 ATA :1, /* ATA device connected (not supported) */ 441 HAA_valid :1; /* Hostadapter Address is valid */ 442 443 u_int16_t cppadlen; /* 444 * Number of pad bytes send after CD data set 445 * to zero for DMA commands. Ntohl()`ed 446 */ 447 u_int8_t scsi_idS; /* SCSI ID of controller 2-0 Byte 0 res. */ 448 u_int8_t scsi_id2; /* If not, zero is returned */ 449 u_int8_t scsi_id1; 450 u_int8_t scsi_id0; 451 u_int32_t cplen; /* CP length: number of valid cp bytes */ 452 453 u_int32_t splen; /* Returned bytes for a received SP command */ 454 u_int16_t queuesiz; /* max number of queueable CPs */ 455 456 u_int16_t dummy; 457 u_int16_t SGsiz; /* max number of SG table entrie */ 458 459 u_int8_t IRQ :4,/* IRQ used this HBA */ 460 IRQ_TR :1,/* IRQ Trigger: 0=edge, 1=level */ 461 SECOND :1,/* This is a secondary controller */ 462 DMA_channel:2;/* DRQ index, DRQ is 2comp of DRQX */ 463 464 u_int8_t sync; /* 0-7 sync active bitmask (deprecated) */ 465 u_int8_t DSBLE :1, /* ISA i/o addressing is disabled */ 466 FORCADR :1, /* i/o address has been forced */ 467 SG_64K :1, 468 SG_UAE :1, 469 :4; 470 471 u_int8_t MAX_ID :5, /* Max number of SCSI target IDs */ 472 MAX_CHAN :3; /* Number of SCSI busses on HBA */ 473 474 u_int8_t MAX_LUN; /* Max number of LUNs */ 475 u_int8_t :3, 476 AUTOTRM :1, 477 M1_inst :1, 478 ID_qest :1, /* Raidnum ID is questionable */ 479 is_PCI :1, /* HBA is PCI */ 480 is_EISA :1; /* HBA is EISA */ 481 482 u_int8_t RAIDNUM; /* unique HBA identifier */ 483 u_int8_t unused[4]; /* When doing PIO, you GET 512 bytes */ 484 485 /* >>------>> End of The DPT structure <<------<< */ 486 487 u_int32_t length; /* True length, after ntohl conversion */ 488 } dpt_conf_t; 489 490 /* Scatter-Gather list entry */ 491 typedef struct dpt_sg_segment { 492 u_int32_t seg_addr; /* All fields in network byte order */ 493 u_int32_t seg_len; 494 } dpt_sg_t; 495 496 497 /* Status Packet */ 498 typedef struct eata_sp { 499 u_int8_t hba_stat :7, /* HBA status */ 500 EOC :1; /* True if command finished */ 501 502 u_int8_t scsi_stat; /* Target SCSI status */ 503 504 u_int8_t reserved[2]; 505 506 u_int32_t residue_len; /* Number of bytes not transferred */ 507 508 u_int32_t ccb_busaddr; 509 510 u_int8_t sp_ID_Message; 511 u_int8_t sp_Que_Message; 512 u_int8_t sp_Tag_Message; 513 u_int8_t msg[9]; 514 } dpt_sp_t; 515 516 /* 517 * A strange collection of O/S-Hardware releated bits and pieces. 518 * Used by the dpt_ioctl() entry point to return DPT_SYSINFO command. 519 */ 520 typedef struct dpt_drive_parameters { 521 u_int16_t cylinders; /* Up to 1024 */ 522 u_int8_t heads; /* Up to 255 */ 523 u_int8_t sectors; /* Up to 63 */ 524 } dpt_drive_t; 525 526 typedef struct driveParam_S driveParam_T; 527 528 #define SI_CMOS_Valid 0x0001 529 #define SI_NumDrivesValid 0x0002 530 #define SI_ProcessorValid 0x0004 531 #define SI_MemorySizeValid 0x0008 532 #define SI_DriveParamsValid 0x0010 533 #define SI_SmartROMverValid 0x0020 534 #define SI_OSversionValid 0x0040 535 #define SI_OSspecificValid 0x0080 536 #define SI_BusTypeValid 0x0100 537 538 #define SI_ALL_VALID 0x0FFF 539 #define SI_NO_SmartROM 0x8000 540 541 #define SI_ISA_BUS 0x00 542 #define SI_PCI_BUS 0x04 543 544 #define HBA_BUS_ISA 0x00 545 #define HBA_BUS_PCI 0x02 546 547 typedef struct dpt_sysinfo { 548 u_int8_t drive0CMOS; /* CMOS Drive 0 Type */ 549 u_int8_t drive1CMOS; /* CMOS Drive 1 Type */ 550 u_int8_t numDrives; /* 0040:0075 contents */ 551 u_int8_t processorFamily; /* Same as DPTSIG definition */ 552 u_int8_t processorType; /* Same as DPTSIG definition */ 553 u_int8_t smartROMMajorVersion; 554 u_int8_t smartROMMinorVersion; /* SmartROM version */ 555 u_int8_t smartROMRevision; 556 u_int16_t flags; /* See bit definitions above */ 557 u_int16_t conventionalMemSize; /* in KB */ 558 u_int32_t extendedMemSize; /* in KB */ 559 u_int32_t osType; /* Same as DPTSIG definition */ 560 u_int8_t osMajorVersion; 561 u_int8_t osMinorVersion; /* The OS version */ 562 u_int8_t osRevision; 563 u_int8_t osSubRevision; 564 u_int8_t busType; /* See defininitions above */ 565 u_int8_t pad[3]; /* For alignment */ 566 dpt_drive_t drives[16]; /* SmartROM Logical Drives */ 567 } dpt_sysinfo_t; 568 569 /* SEND_COMMAND packet structure */ 570 typedef struct eata_ccb { 571 u_int8_t SCSI_Reset :1, /* Cause a SCSI Bus reset on the cmd */ 572 HBA_Init :1, /* Cause Controller to reinitialize */ 573 Auto_Req_Sen :1, /* Do Auto Request Sense on errors */ 574 scatter :1, /* Data Ptr points to a SG Packet */ 575 Quick :1, /* Set this one for NO Status PAcket */ 576 Interpret :1, /* Interpret the SCSI cdb for own use */ 577 DataOut :1, /* Data Out phase with command */ 578 DataIn :1; /* Data In phase with command */ 579 580 u_int8_t reqlen; /* Request Sense Length, if Auto_Req_Sen=1 */ 581 u_int8_t unused[3]; 582 u_int8_t FWNEST :1, /* send cmd to phys RAID component */ 583 unused2 :7; 584 585 u_int8_t Phsunit :1, /* physical unit on mirrored pair */ 586 I_AT :1, /* inhibit address translation */ 587 Disable_Cache :1, /* HBA inhibit caching */ 588 :5; 589 590 u_int8_t cp_id :5, /* SCSI Device ID of target */ 591 cp_channel :3; /* SCSI Channel # of HBA */ 592 593 u_int8_t cp_LUN :5, 594 cp_luntar :1, /* CP is for target ROUTINE */ 595 cp_dispri :1, /* Grant disconnect privilege */ 596 cp_identify :1; /* Always TRUE */ 597 598 u_int8_t cp_msg[3]; /* Message bytes 0-3 */ 599 600 union { 601 struct { 602 u_int8_t x_scsi_cmd; /* Partial SCSI CDB def */ 603 604 u_int8_t x_extent :1, 605 x_bytchk :1, 606 x_reladr :1, 607 x_cmplst :1, 608 x_fmtdata :1, 609 x_lun :3; 610 611 u_int8_t x_page; 612 u_int8_t reserved4; 613 u_int8_t x_len; 614 u_int8_t x_link :1; 615 u_int8_t x_flag :1; 616 u_int8_t reserved5 :4; 617 u_int8_t x_vendor :2; 618 } x; 619 u_int8_t z[12]; /* Command Descriptor Block (= 12) */ 620 } cp_w; 621 622 #define cp_cdb cp_w.z 623 #define cp_scsi_cmd cp_w.x.x_scsi_cmd 624 #define cp_extent cp_w.x.x_extent 625 #define cp_lun cp_w.x.x_lun 626 #define cp_page cp_w.x.x_page 627 #define cp_len cp_w.x.x_len 628 629 #define MULTIFUNCTION_CMD 0x0e /* SCSI Multi Function Cmd */ 630 #define BUS_QUIET 0x04 /* Quite Scsi Bus Code */ 631 #define BUS_UNQUIET 0x05 /* Un Quiet Scsi Bus Code */ 632 633 u_int32_t cp_datalen; /* 634 * Data Transfer Length. If scatter=1 len (IN 635 * BYTES!) of the S/G array 636 */ 637 638 u_int32_t cp_busaddr; /* Unique identifier. Busaddr works well */ 639 u_int32_t cp_dataDMA; /* 640 * Data Address, if scatter=1 then it is the 641 * address of scatter packet 642 */ 643 u_int32_t cp_statDMA; /* address for Status Packet */ 644 u_int32_t cp_reqDMA; /* 645 * Request Sense Address, used if CP command 646 * ends with error 647 */ 648 u_int8_t CP_OpCode; 649 650 } eata_ccb_t; 651 652 /* 653 * DPT Signature Structure. 654 * Used by /dev/dpt to directly pass commands to the HBA 655 * We have more information here than we care for... 656 */ 657 658 /* Current Signature Version - sigBYTE dsSigVersion; */ 659 #define SIG_VERSION 1 660 661 /* 662 * Processor Family - sigBYTE dsProcessorFamily; DISTINCT VALUE 663 * 664 * What type of processor the file is meant to run on. 665 * This will let us know whether to read sigWORDs as high/low or low/high. 666 */ 667 #define PROC_INTEL 0x00 /* Intel 80x86 */ 668 #define PROC_MOTOROLA 0x01 /* Motorola 68K */ 669 #define PROC_MIPS4000 0x02 /* MIPS RISC 4000 */ 670 #define PROC_ALPHA 0x03 /* DEC Alpha */ 671 672 /* 673 * Specific Minimim Processor - sigBYTE dsProcessor; FLAG BITS 674 * 675 * Different bit definitions dependent on processor_family 676 */ 677 678 /* PROC_INTEL: */ 679 #define PROC_8086 0x01 /* Intel 8086 */ 680 #define PROC_286 0x02 /* Intel 80286 */ 681 #define PROC_386 0x04 /* Intel 80386 */ 682 #define PROC_486 0x08 /* Intel 80486 */ 683 #define PROC_PENTIUM 0x10 /* Intel 586 aka P5 aka Pentium */ 684 #define PROC_P6 0x20 /* Intel 686 aka P6 */ 685 686 /* PROC_MOTOROLA: */ 687 #define PROC_68000 0x01 /* Motorola 68000 */ 688 #define PROC_68020 0x02 /* Motorola 68020 */ 689 #define PROC_68030 0x04 /* Motorola 68030 */ 690 #define PROC_68040 0x08 /* Motorola 68040 */ 691 692 /* Filetype - sigBYTE dsFiletype; DISTINCT VALUES */ 693 #define FT_EXECUTABLE 0 /* Executable Program */ 694 #define FT_SCRIPT 1 /* Script/Batch File??? */ 695 #define FT_HBADRVR 2 /* HBA Driver */ 696 #define FT_OTHERDRVR 3 /* Other Driver */ 697 #define FT_IFS 4 /* Installable Filesystem Driver */ 698 #define FT_ENGINE 5 /* DPT Engine */ 699 #define FT_COMPDRVR 6 /* Compressed Driver Disk */ 700 #define FT_LANGUAGE 7 /* Foreign Language file */ 701 #define FT_FIRMWARE 8 /* Downloadable or actual Firmware */ 702 #define FT_COMMMODL 9 /* Communications Module */ 703 #define FT_INT13 10 /* INT 13 style HBA Driver */ 704 #define FT_HELPFILE 11 /* Help file */ 705 #define FT_LOGGER 12 /* Event Logger */ 706 #define FT_INSTALL 13 /* An Install Program */ 707 #define FT_LIBRARY 14 /* Storage Manager Real-Mode Calls */ 708 #define FT_RESOURCE 15 /* Storage Manager Resource File */ 709 #define FT_MODEM_DB 16 /* Storage Manager Modem Database */ 710 711 /* Filetype flags - sigBYTE dsFiletypeFlags; FLAG BITS */ 712 #define FTF_DLL 0x01 /* Dynamic Link Library */ 713 #define FTF_NLM 0x02 /* Netware Loadable Module */ 714 #define FTF_OVERLAYS 0x04 /* Uses overlays */ 715 #define FTF_DEBUG 0x08 /* Debug version */ 716 #define FTF_TSR 0x10 /* TSR */ 717 #define FTF_SYS 0x20 /* DOS Lodable driver */ 718 #define FTF_PROTECTED 0x40 /* Runs in protected mode */ 719 #define FTF_APP_SPEC 0x80 /* Application Specific */ 720 721 /* OEM - sigBYTE dsOEM; DISTINCT VALUES */ 722 #define OEM_DPT 0 /* DPT */ 723 #define OEM_ATT 1 /* ATT */ 724 #define OEM_NEC 2 /* NEC */ 725 #define OEM_ALPHA 3 /* Alphatronix */ 726 #define OEM_AST 4 /* AST */ 727 #define OEM_OLIVETTI 5 /* Olivetti */ 728 #define OEM_SNI 6 /* Siemens/Nixdorf */ 729 730 /* Operating System - sigLONG dsOS; FLAG BITS */ 731 #define OS_DOS 0x00000001 /* PC/MS-DOS */ 732 #define OS_WINDOWS 0x00000002 /* Microsoft Windows 3.x */ 733 #define OS_WINDOWS_NT 0x00000004 /* Microsoft Windows NT */ 734 #define OS_OS2M 0x00000008 /* OS/2 1.2.x,MS 1.3.0,IBM 1.3.x */ 735 #define OS_OS2L 0x00000010 /* Microsoft OS/2 1.301 - LADDR */ 736 #define OS_OS22x 0x00000020 /* IBM OS/2 2.x */ 737 #define OS_NW286 0x00000040 /* Novell NetWare 286 */ 738 #define OS_NW386 0x00000080 /* Novell NetWare 386 */ 739 #define OS_GEN_UNIX 0x00000100 /* Generic Unix */ 740 #define OS_SCO_UNIX 0x00000200 /* SCO Unix */ 741 #define OS_ATT_UNIX 0x00000400 /* ATT Unix */ 742 #define OS_UNIXWARE 0x00000800 /* UnixWare Unix */ 743 #define OS_INT_UNIX 0x00001000 /* Interactive Unix */ 744 #define OS_SOLARIS 0x00002000 /* SunSoft Solaris */ 745 #define OS_QN 0x00004000 /* QNX for Tom Moch */ 746 #define OS_NEXTSTEP 0x00008000 /* NeXTSTEP */ 747 #define OS_BANYAN 0x00010000 /* Banyan Vines */ 748 #define OS_OLIVETTI_UNIX 0x00020000 /* Olivetti Unix */ 749 #define OS_FREEBSD 0x00040000 /* FreeBSD 2.2 and later */ 750 #define OS_OTHER 0x80000000 /* Other */ 751 752 /* Capabilities - sigWORD dsCapabilities; FLAG BITS */ 753 #define CAP_RAID0 0x0001 /* RAID-0 */ 754 #define CAP_RAID1 0x0002 /* RAID-1 */ 755 #define CAP_RAID3 0x0004 /* RAID-3 */ 756 #define CAP_RAID5 0x0008 /* RAID-5 */ 757 #define CAP_SPAN 0x0010 /* Spanning */ 758 #define CAP_PASS 0x0020 /* Provides passthrough */ 759 #define CAP_OVERLAP 0x0040 /* Passthrough supports overlapped commands */ 760 #define CAP_ASPI 0x0080 /* Supports ASPI Command Requests */ 761 #define CAP_ABOVE16MB 0x0100 /* ISA Driver supports greater than 16MB */ 762 #define CAP_EXTEND 0x8000 /* Extended info appears after description */ 763 764 /* Devices Supported - sigWORD dsDeviceSupp; FLAG BITS */ 765 #define DEV_DASD 0x0001 /* DASD (hard drives) */ 766 #define DEV_TAPE 0x0002 /* Tape drives */ 767 #define DEV_PRINTER 0x0004 /* Printers */ 768 #define DEV_PROC 0x0008 /* Processors */ 769 #define DEV_WORM 0x0010 /* WORM drives */ 770 #define DEV_CDROM 0x0020 /* CD-ROM drives */ 771 #define DEV_SCANNER 0x0040 /* Scanners */ 772 #define DEV_OPTICAL 0x0080 /* Optical Drives */ 773 #define DEV_JUKEBOX 0x0100 /* Jukebox */ 774 #define DEV_COMM 0x0200 /* Communications Devices */ 775 #define DEV_OTHER 0x0400 /* Other Devices */ 776 #define DEV_ALL 0xFFFF /* All SCSI Devices */ 777 778 /* Adapters Families Supported - sigWORD dsAdapterSupp; FLAG BITS */ 779 #define ADF_2001 0x0001 /* PM2001 */ 780 #define ADF_2012A 0x0002 /* PM2012A */ 781 #define ADF_PLUS_ISA 0x0004 /* PM2011,PM2021 */ 782 #define ADF_SC3_ISA 0x0010 /* PM2021 */ 783 #define ADF_SC3_PCI 0x0040 /* SmartCache III PCI */ 784 #define ADF_SC4_ISA 0x0080 /* SmartCache IV ISA */ 785 #define ADF_SC4_PCI 0x0200 /* SmartCache IV PCI */ 786 #define ADF_ALL_MASTER 0xFFFE /* All bus mastering */ 787 #define ADF_ALL_CACHE 0xFFFC /* All caching */ 788 #define ADF_ALL 0xFFFF /* ALL DPT adapters */ 789 790 /* Application - sigWORD dsApplication; FLAG BITS */ 791 #define APP_DPTMGR 0x0001 /* DPT Storage Manager */ 792 #define APP_ENGINE 0x0002 /* DPT Engine */ 793 #define APP_SYTOS 0x0004 /* Sytron Sytos Plus */ 794 #define APP_CHEYENNE 0x0008 /* Cheyenne ARCServe + ARCSolo */ 795 #define APP_MSCDEX 0x0010 /* Microsoft CD-ROM extensions */ 796 #define APP_NOVABACK 0x0020 /* NovaStor Novaback */ 797 #define APP_AIM 0x0040 /* Archive Information Manager */ 798 799 /* Requirements - sigBYTE dsRequirements; FLAG BITS */ 800 #define REQ_SMARTROM 0x01 /* Requires SmartROM to be present */ 801 #define REQ_DPTDDL 0x02 /* Requires DPTDDL.SYS to be loaded */ 802 #define REQ_HBA_DRIVER 0x04 /* Requires an HBA driver to be loaded */ 803 #define REQ_ASPI_TRAN 0x08 /* Requires an ASPI Transport Modules */ 804 #define REQ_ENGINE 0x10 /* Requires a DPT Engine to be loaded */ 805 #define REQ_COMM_ENG 0x20 /* Requires a DPT Communications Engine */ 806 807 typedef struct dpt_sig { 808 char dsSignature[6]; /* ALWAYS "dPtSiG" */ 809 u_int8_t SigVersion; /* signature version (currently 1) */ 810 u_int8_t ProcessorFamily; /* what type of processor */ 811 u_int8_t Processor; /* precise processor */ 812 u_int8_t Filetype; /* type of file */ 813 u_int8_t FiletypeFlags; /* flags to specify load type, etc. */ 814 u_int8_t OEM; /* OEM file was created for */ 815 u_int32_t OS; /* which Operating systems */ 816 u_int16_t Capabilities; /* RAID levels, etc. */ 817 u_int16_t DeviceSupp; /* Types of SCSI devices supported */ 818 u_int16_t AdapterSupp; /* DPT adapter families supported */ 819 u_int16_t Application; /* applications file is for */ 820 u_int8_t Requirements; /* Other driver dependencies */ 821 u_int8_t Version; /* 1 */ 822 u_int8_t Revision; /* 'J' */ 823 u_int8_t SubRevision; /* '9', ' ' if N/A */ 824 u_int8_t Month; /* creation month */ 825 u_int8_t Day; /* creation day */ 826 u_int8_t Year; /* creation year since 1980 */ 827 char *Description; /* description (NULL terminated) */ 828 } dpt_sig_t; 829 830 /* 32 bytes minimum - with no description. Put NULL at description[0] */ 831 /* 81 bytes maximum - with 49 character description plus NULL. */ 832 833 /* This line added at Roycroft's request */ 834 /* Microsoft's NT compiler gets confused if you do a pack and don't */ 835 /* restore it. */ 836 typedef struct eata_pass_through { 837 u_int8_t eataID[4]; 838 u_int32_t command; 839 840 #define EATAUSRCMD (('D'<<8)|65) /* EATA PassThrough Command */ 841 #define DPT_SIGNATURE (('D'<<8)|67) /* Get Signature Structure */ 842 #define DPT_NUMCTRLS (('D'<<8)|68) /* Get Number Of DPT Adapters */ 843 #define DPT_CTRLINFO (('D'<<8)|69) /* Get Adapter Info Structure */ 844 #define DPT_SYSINFO (('D'<<8)|72) /* Get System Info Structure */ 845 #define DPT_BLINKLED (('D'<<8)|75) /* Get The BlinkLED Status */ 846 847 u_int8_t *command_buffer; 848 eata_ccb_t command_packet; 849 u_int32_t timeout; 850 u_int8_t host_status; 851 u_int8_t target_status; 852 u_int8_t retries; 853 } eata_pt_t; 854 855 typedef enum { 856 DCCB_FREE = 0x00, 857 DCCB_ACTIVE = 0x01, 858 DCCB_RELEASE_SIMQ = 0x02 859 } dccb_state; 860 861 typedef struct dpt_ccb { 862 eata_ccb_t eata_ccb; 863 bus_dmamap_t dmamap; 864 struct callout timer; 865 dpt_sg_t *sg_list; 866 u_int32_t sg_busaddr; 867 dccb_state state; 868 union ccb *ccb; 869 struct scsi_sense_data sense_data; 870 u_int8_t tag; 871 u_int8_t retries; 872 u_int8_t status; /* status of this queueslot */ 873 u_int8_t *cmd; /* address of cmd */ 874 875 u_int32_t transaction_id; 876 u_int32_t result; 877 caddr_t data; 878 SLIST_ENTRY(dpt_ccb) links; 879 880 #ifdef DPT_MEASURE_PERFORMANCE 881 u_int32_t submitted_time; 882 struct timeval command_started; 883 struct timeval command_ended; 884 #endif 885 } dpt_ccb_t; 886 887 /* 888 * This is provided for compatibility with UnixWare only. 889 * Some of the fields may be bogus. 890 * Others may have a totally different meaning. 891 */ 892 typedef struct dpt_scsi_ha { 893 u_int32_t ha_state; /* Operational state */ 894 u_int8_t ha_id[MAX_CHANNELS]; /* Host adapter SCSI ids */ 895 int32_t ha_base; /* Base I/O address */ 896 int ha_max_jobs; /* Max number of Active Jobs */ 897 int ha_cache:2; /* Cache parameters */ 898 int ha_cachesize:30; /* In meg, only if cache present*/ 899 int ha_nbus; /* Number Of Busses on HBA */ 900 int ha_ntargets; /* Number Of Targets Supported */ 901 int ha_nluns; /* Number Of LUNs Supported */ 902 int ha_tshift; /* Shift value for target */ 903 int ha_bshift; /* Shift value for bus */ 904 int ha_npend; /* # of jobs sent to HBA */ 905 int ha_active_jobs; /* Number Of Active Jobs */ 906 char ha_fw_version[4]; /* Firmware Revision Level */ 907 void *ha_ccb; /* Controller command blocks */ 908 void *ha_cblist; /* Command block free list */ 909 void *ha_dev; /* Logical unit queues */ 910 void *ha_StPkt_lock; /* Status Packet Lock */ 911 void *ha_ccb_lock; /* CCB Lock */ 912 void *ha_LuQWaiting; /* Lu Queue Waiting List */ 913 void *ha_QWait_lock; /* Device Que Waiting Lock */ 914 int ha_QWait_opri; /* Saved Priority Level */ 915 #ifdef DPT_TARGET_MODE 916 dpt_ccb_t *target_ccb[MAX_CHANNELS]; /* Command block waiting writebuf */ 917 #endif 918 } dpt_compat_ha_t; 919 920 /* 921 * Describe the Inquiry Data returned on Page 0 from the Adapter. The 922 * Page C1 Inquiry Data is described in the DptConfig_t structure above. 923 */ 924 typedef struct { 925 u_int8_t deviceType; 926 u_int8_t rm_dtq; 927 u_int8_t otherData[6]; 928 u_int8_t vendor[8]; 929 u_int8_t modelNum[16]; 930 u_int8_t firmware[4]; 931 u_int8_t protocol[4]; 932 } dpt_inq_t; 933 934 /* 935 * sp_EOC is not `safe', so I will check sp_Messages[0] instead! 936 */ 937 #define DptStat_BUSY(x) ((x)->sp_ID_Message) 938 #define DptStat_Reset_BUSY(x) \ 939 ((x)->msg[0] = 0xA5, (x)->EOC = 0, \ 940 (x)->ccb_busaddr = ~0) 941 942 #ifdef DPT_MEASURE_PERFORMANCE 943 #define BIG_ENOUGH 0x8fffffff 944 typedef struct dpt_metrics { 945 u_int32_t command_count[256]; /* We assume MAX 256 SCSI commands */ 946 u_int32_t max_command_time[256]; 947 u_int32_t min_command_time[256]; 948 949 u_int32_t min_intr_time; 950 u_int32_t max_intr_time; 951 u_int32_t aborted_interrupts; 952 u_int32_t spurious_interrupts; 953 954 u_int32_t max_waiting_count; 955 u_int32_t max_submit_count; 956 u_int32_t max_complete_count; 957 958 u_int32_t min_waiting_time; 959 u_int32_t min_submit_time; 960 u_int32_t min_complete_time; 961 962 u_int32_t max_waiting_time; 963 u_int32_t max_submit_time; 964 u_int32_t max_complete_time; 965 966 u_int32_t command_collisions; 967 u_int32_t command_too_busy; 968 u_int32_t max_eata_tries; 969 u_int32_t min_eata_tries; 970 971 u_int32_t read_by_size_count[10]; 972 u_int32_t write_by_size_count[10]; 973 u_int32_t read_by_size_min_time[10]; 974 u_int32_t read_by_size_max_time[10]; 975 u_int32_t write_by_size_min_time[10]; 976 u_int32_t write_by_size_max_time[10]; 977 978 #define SIZE_512 0 979 #define SIZE_1K 1 980 #define SIZE_2K 2 981 #define SIZE_4K 3 982 #define SIZE_8K 4 983 #define SIZE_16K 5 984 #define SIZE_32K 6 985 #define SIZE_64K 7 986 #define SIZE_BIGGER 8 987 #define SIZE_OTHER 9 988 989 struct timeval intr_started; 990 991 u_int32_t warm_starts; 992 u_int32_t cold_boots; 993 } dpt_perf_t; 994 #endif 995 996 struct sg_map_node { 997 bus_dmamap_t sg_dmamap; 998 bus_addr_t sg_physaddr; 999 dpt_sg_t* sg_vaddr; 1000 SLIST_ENTRY(sg_map_node) links; 1001 }; 1002 1003 /* Main state machine and interface structure */ 1004 typedef struct dpt_softc { 1005 device_t dev; 1006 struct mtx lock; 1007 1008 struct resource * io_res; 1009 int io_rid; 1010 int io_type; 1011 int io_offset; 1012 1013 struct resource * irq_res; 1014 int irq_rid; 1015 void * ih; 1016 1017 struct resource * drq_res; 1018 int drq_rid; 1019 1020 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1021 dpt_ccb_t *dpt_dccbs; /* Array of dpt ccbs */ 1022 bus_addr_t dpt_ccb_busbase; /* phys base address of array */ 1023 bus_addr_t dpt_ccb_busend; /* phys end address of array */ 1024 1025 u_int32_t handle_interrupts :1, /* Are we ready for real work? */ 1026 target_mode_enabled :1, 1027 resource_shortage :1, 1028 cache_type :2, 1029 spare :28; 1030 1031 int total_dccbs; 1032 int free_dccbs; 1033 int pending_ccbs; 1034 int completed_ccbs; 1035 1036 SLIST_HEAD(, dpt_ccb) free_dccb_list; 1037 LIST_HEAD(, ccb_hdr) pending_ccb_list; 1038 1039 bus_dma_tag_t parent_dmat; 1040 bus_dma_tag_t dccb_dmat; /* dmat for our ccb array */ 1041 bus_dmamap_t dccb_dmamap; 1042 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 1043 SLIST_HEAD(, sg_map_node) sg_maps; 1044 1045 struct cam_sim *sims[MAX_CHANNELS]; 1046 struct cam_path *paths[MAX_CHANNELS]; 1047 u_int32_t commands_processed; 1048 u_int32_t lost_interrupts; 1049 1050 /* 1051 * These three parameters can be used to allow for wide scsi, and 1052 * for host adapters that support multiple busses. The first two 1053 * should be set to 1 more than the actual max id or lun (i.e. 8 for 1054 * normal systems). 1055 * 1056 * There is a FAT assumption here; We assume that these will never 1057 * exceed MAX_CHANNELS, MAX_TARGETS, MAX_LUNS 1058 */ 1059 u_int channels; /* # of avail scsi chan. */ 1060 u_int32_t max_id; 1061 u_int32_t max_lun; 1062 1063 u_int8_t irq; 1064 u_int8_t dma_channel; 1065 1066 TAILQ_ENTRY(dpt_softc) links; 1067 int init_level; 1068 1069 /* 1070 * Every object on a unit can have a receiver, if it treats 1071 * us as a target. We do that so that separate and independent 1072 * clients can consume received buffers. 1073 */ 1074 1075 #define DPT_RW_BUFFER_SIZE (8 * 1024) 1076 dpt_ccb_t *target_ccb[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 1077 u_int8_t *rw_buffer[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 1078 dpt_rec_buff buffer_receiver[MAX_CHANNELS][MAX_TARGETS][MAX_LUNS]; 1079 1080 dpt_inq_t board_data; 1081 u_int8_t EATA_revision; 1082 u_int8_t bustype; /* bustype of HBA */ 1083 u_int32_t state; /* state of HBA */ 1084 1085 #define DPT_HA_FREE 0x00000000 1086 #define DPT_HA_OK 0x00000000 1087 #define DPT_HA_NO_TIMEOUT 0x00000000 1088 #define DPT_HA_BUSY 0x00000001 1089 #define DPT_HA_TIMEOUT 0x00000002 1090 #define DPT_HA_RESET 0x00000004 1091 #define DPT_HA_LOCKED 0x00000008 1092 #define DPT_HA_ABORTED 0x00000010 1093 #define DPT_HA_CONTROL_ACTIVE 0x00000020 1094 #define DPT_HA_SHUTDOWN_ACTIVE 0x00000040 1095 #define DPT_HA_COMMAND_ACTIVE 0x00000080 1096 #define DPT_HA_QUIET 0x00000100 1097 1098 u_int8_t primary; /* true if primary */ 1099 1100 u_int8_t more_support :1, /* HBA supports MORE flag */ 1101 immediate_support :1, /* HBA supports IMMEDIATE */ 1102 spare2 :6; 1103 1104 u_int8_t resetlevel[MAX_CHANNELS]; 1105 u_int32_t last_ccb; /* Last used ccb */ 1106 u_int32_t cplen; /* size of CP in words */ 1107 u_int16_t cppadlen; /* pad length of cp */ 1108 u_int16_t max_dccbs; 1109 u_int16_t sgsize; /* Entries in the SG list */ 1110 u_int8_t hostid[MAX_CHANNELS]; /* SCSI ID of HBA */ 1111 u_int32_t cache_size; 1112 1113 volatile dpt_sp_t *sp; /* status packet */ 1114 /* Copied from the status packet during interrupt handler */ 1115 u_int8_t hba_stat; 1116 u_int8_t scsi_stat; /* Target SCSI status */ 1117 u_int32_t residue_len; /* Number of bytes not transferred */ 1118 bus_addr_t sp_physaddr; /* phys address of status packet */ 1119 1120 /* 1121 * We put ALL conditional elements at the tail for the structure. 1122 * If we do not, then userland code will crash or trash based on which 1123 * kernel it is running with. 1124 * This isi most visible with usr/sbin/dpt_softc(8) 1125 */ 1126 1127 #ifdef DPT_MEASURE_PERFORMANCE 1128 dpt_perf_t performance; 1129 #endif 1130 1131 #ifdef DPT_RESET_HBA 1132 struct timeval last_contact; 1133 #endif 1134 } dpt_softc_t; 1135 1136 /* 1137 * This structure is used to pass dpt_softc contents to userland via the 1138 * ioctl DPT_IOCTL_SOFTC. The reason for this maddness, is that FreeBSD 1139 * (all BSDs ?) chose to actually assign a nasty meaning to the IOCTL word, 1140 * encoding 13 bits of it as size. As dpt_softc_t is somewhere between 1141 * 8,594 and 8,600 (depends on options), we have to copy the data to 1142 * something less than 4KB long. This siliness also solves the problem of 1143 * varying definition of dpt_softc_t, As the variants are exluded from 1144 * dpt_user_softc. 1145 * 1146 * See dpt_softc_t above for enumerations, comments and such. 1147 */ 1148 typedef struct dpt_user_softc { 1149 int unit; 1150 u_int32_t handle_interrupts :1, /* Are we ready for real work? */ 1151 target_mode_enabled :1, 1152 spare :30; 1153 1154 int total_ccbs_count; 1155 int free_ccbs_count; 1156 int waiting_ccbs_count; 1157 int submitted_ccbs_count; 1158 int completed_ccbs_count; 1159 1160 u_int32_t queue_status; 1161 u_int32_t free_lock; 1162 u_int32_t waiting_lock; 1163 u_int32_t submitted_lock; 1164 u_int32_t completed_lock; 1165 1166 u_int32_t commands_processed; 1167 u_int32_t lost_interrupts; 1168 1169 u_int8_t channels; 1170 u_int32_t max_id; 1171 u_int32_t max_lun; 1172 1173 u_int16_t io_base; 1174 u_int8_t *v_membase; 1175 u_int8_t *p_membase; 1176 1177 u_int8_t irq; 1178 u_int8_t dma_channel; 1179 1180 dpt_inq_t board_data; 1181 u_int8_t EATA_revision; 1182 u_int8_t bustype; 1183 u_int32_t state; 1184 1185 u_int8_t primary; 1186 u_int8_t more_support :1, 1187 immediate_support :1, 1188 spare2 :6; 1189 1190 u_int8_t resetlevel[MAX_CHANNELS]; 1191 u_int32_t last_ccb; 1192 u_int32_t cplen; 1193 u_int16_t cppadlen; 1194 u_int16_t queuesize; 1195 u_int16_t sgsize; 1196 u_int8_t hostid[MAX_CHANNELS]; 1197 u_int32_t cache_type :2, 1198 cache_size :30; 1199 } dpt_user_softc_t; 1200 1201 /* 1202 * Externals: 1203 * These all come from dpt_scsi.c 1204 * 1205 */ 1206 #ifdef _KERNEL 1207 /* This function gets the current hi-res time and returns it to the caller */ 1208 static __inline struct timeval 1209 dpt_time_now(void) 1210 { 1211 struct timeval now; 1212 1213 microtime(&now); 1214 return(now); 1215 } 1216 1217 /* 1218 * Given a minor device number, get its SCSI Unit. 1219 */ 1220 static __inline int 1221 dpt_minor2unit(int minor) 1222 { 1223 return(minor2hba(minor)); 1224 } 1225 1226 dpt_softc_t *dpt_minor2softc(int minor_no); 1227 1228 #endif /* _KERNEL */ 1229 1230 /* 1231 * This function subtracts one timval structure from another, 1232 * Returning the result in usec. 1233 * It assumes that less than 4 billion usecs passed form start to end. 1234 * If times are sensless, ~0 is returned. 1235 */ 1236 static __inline u_int32_t 1237 dpt_time_delta(struct timeval start, 1238 struct timeval end) 1239 { 1240 if (start.tv_sec > end.tv_sec) 1241 return(~0); 1242 1243 if ( (start.tv_sec == end.tv_sec) && (start.tv_usec > end.tv_usec) ) 1244 return(~0); 1245 1246 return ( (end.tv_sec - start.tv_sec) * 1000000 + 1247 (end.tv_usec - start.tv_usec) ); 1248 } 1249 1250 extern devclass_t dpt_devclass; 1251 1252 #ifdef _KERNEL 1253 void dpt_alloc(device_t); 1254 int dpt_detach(device_t); 1255 int dpt_alloc_resources(device_t); 1256 void dpt_release_resources(device_t); 1257 #endif 1258 void dpt_free(struct dpt_softc *dpt); 1259 int dpt_init(struct dpt_softc *dpt); 1260 int dpt_attach(dpt_softc_t * dpt); 1261 void dpt_intr(void *arg); 1262 1263 #if 0 1264 extern void hex_dump(u_char * data, int length, 1265 char *name, int no); 1266 extern char *i2bin(unsigned int no, int length); 1267 extern char *scsi_cmd_name(u_int8_t cmd); 1268 1269 extern dpt_conf_t *dpt_get_conf(dpt_softc_t *dpt, u_int8_t page, 1270 u_int8_t target, u_int8_t size, 1271 int extent); 1272 1273 extern int dpt_setup(dpt_softc_t * dpt, dpt_conf_t * conf); 1274 extern int dpt_attach(dpt_softc_t * dpt); 1275 extern void dpt_shutdown(int howto, dpt_softc_t *dpt); 1276 extern void dpt_detect_cache(dpt_softc_t *dpt); 1277 1278 extern int dpt_user_cmd(dpt_softc_t *dpt, eata_pt_t *user_cmd, 1279 caddr_t cmdarg, int minor_no); 1280 1281 extern u_int8_t dpt_blinking_led(dpt_softc_t *dpt); 1282 1283 extern dpt_rb_t dpt_register_buffer(int unit, u_int8_t channel, u_int8_t target, 1284 u_int8_t lun, u_int8_t mode, 1285 u_int16_t length, u_int16_t offset, 1286 dpt_rec_buff callback, dpt_rb_op_t op); 1287 1288 extern int dpt_send_buffer(int unit, u_int8_t channel, u_int8_t target, 1289 u_int8_t lun, u_int8_t mode, u_int16_t length, 1290 u_int16_t offset, void *data, 1291 buff_wr_done callback); 1292 1293 1294 1295 void dpt_reset_performance(dpt_softc_t *dpt); 1296 #endif 1297 1298 #endif /* _DPT_H */ 1299