1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <[email protected]> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_ratelimit.h" 37 #include "opt_rss.h" 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/priv.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #if defined(__i386__) || defined(__amd64__) 69 #include <machine/md_var.h> 70 #include <machine/cputypes.h> 71 #include <vm/vm.h> 72 #include <vm/pmap.h> 73 #endif 74 #include <crypto/rijndael/rijndael.h> 75 #ifdef DDB 76 #include <ddb/ddb.h> 77 #include <ddb/db_lex.h> 78 #endif 79 80 #include "common/common.h" 81 #include "common/t4_msg.h" 82 #include "common/t4_regs.h" 83 #include "common/t4_regs_values.h" 84 #include "cudbg/cudbg.h" 85 #include "t4_clip.h" 86 #include "t4_ioctl.h" 87 #include "t4_l2t.h" 88 #include "t4_mp_ring.h" 89 #include "t4_if.h" 90 #include "t4_smt.h" 91 92 /* T4 bus driver interface */ 93 static int t4_probe(device_t); 94 static int t4_attach(device_t); 95 static int t4_detach(device_t); 96 static int t4_child_location_str(device_t, device_t, char *, size_t); 97 static int t4_ready(device_t); 98 static int t4_read_port_device(device_t, int, device_t *); 99 static device_method_t t4_methods[] = { 100 DEVMETHOD(device_probe, t4_probe), 101 DEVMETHOD(device_attach, t4_attach), 102 DEVMETHOD(device_detach, t4_detach), 103 104 DEVMETHOD(bus_child_location_str, t4_child_location_str), 105 106 DEVMETHOD(t4_is_main_ready, t4_ready), 107 DEVMETHOD(t4_read_port_device, t4_read_port_device), 108 109 DEVMETHOD_END 110 }; 111 static driver_t t4_driver = { 112 "t4nex", 113 t4_methods, 114 sizeof(struct adapter) 115 }; 116 117 118 /* T4 port (cxgbe) interface */ 119 static int cxgbe_probe(device_t); 120 static int cxgbe_attach(device_t); 121 static int cxgbe_detach(device_t); 122 device_method_t cxgbe_methods[] = { 123 DEVMETHOD(device_probe, cxgbe_probe), 124 DEVMETHOD(device_attach, cxgbe_attach), 125 DEVMETHOD(device_detach, cxgbe_detach), 126 { 0, 0 } 127 }; 128 static driver_t cxgbe_driver = { 129 "cxgbe", 130 cxgbe_methods, 131 sizeof(struct port_info) 132 }; 133 134 /* T4 VI (vcxgbe) interface */ 135 static int vcxgbe_probe(device_t); 136 static int vcxgbe_attach(device_t); 137 static int vcxgbe_detach(device_t); 138 static device_method_t vcxgbe_methods[] = { 139 DEVMETHOD(device_probe, vcxgbe_probe), 140 DEVMETHOD(device_attach, vcxgbe_attach), 141 DEVMETHOD(device_detach, vcxgbe_detach), 142 { 0, 0 } 143 }; 144 static driver_t vcxgbe_driver = { 145 "vcxgbe", 146 vcxgbe_methods, 147 sizeof(struct vi_info) 148 }; 149 150 static d_ioctl_t t4_ioctl; 151 152 static struct cdevsw t4_cdevsw = { 153 .d_version = D_VERSION, 154 .d_ioctl = t4_ioctl, 155 .d_name = "t4nex", 156 }; 157 158 /* T5 bus driver interface */ 159 static int t5_probe(device_t); 160 static device_method_t t5_methods[] = { 161 DEVMETHOD(device_probe, t5_probe), 162 DEVMETHOD(device_attach, t4_attach), 163 DEVMETHOD(device_detach, t4_detach), 164 165 DEVMETHOD(bus_child_location_str, t4_child_location_str), 166 167 DEVMETHOD(t4_is_main_ready, t4_ready), 168 DEVMETHOD(t4_read_port_device, t4_read_port_device), 169 170 DEVMETHOD_END 171 }; 172 static driver_t t5_driver = { 173 "t5nex", 174 t5_methods, 175 sizeof(struct adapter) 176 }; 177 178 179 /* T5 port (cxl) interface */ 180 static driver_t cxl_driver = { 181 "cxl", 182 cxgbe_methods, 183 sizeof(struct port_info) 184 }; 185 186 /* T5 VI (vcxl) interface */ 187 static driver_t vcxl_driver = { 188 "vcxl", 189 vcxgbe_methods, 190 sizeof(struct vi_info) 191 }; 192 193 /* T6 bus driver interface */ 194 static int t6_probe(device_t); 195 static device_method_t t6_methods[] = { 196 DEVMETHOD(device_probe, t6_probe), 197 DEVMETHOD(device_attach, t4_attach), 198 DEVMETHOD(device_detach, t4_detach), 199 200 DEVMETHOD(bus_child_location_str, t4_child_location_str), 201 202 DEVMETHOD(t4_is_main_ready, t4_ready), 203 DEVMETHOD(t4_read_port_device, t4_read_port_device), 204 205 DEVMETHOD_END 206 }; 207 static driver_t t6_driver = { 208 "t6nex", 209 t6_methods, 210 sizeof(struct adapter) 211 }; 212 213 214 /* T6 port (cc) interface */ 215 static driver_t cc_driver = { 216 "cc", 217 cxgbe_methods, 218 sizeof(struct port_info) 219 }; 220 221 /* T6 VI (vcc) interface */ 222 static driver_t vcc_driver = { 223 "vcc", 224 vcxgbe_methods, 225 sizeof(struct vi_info) 226 }; 227 228 /* ifnet interface */ 229 static void cxgbe_init(void *); 230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 231 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 232 static void cxgbe_qflush(struct ifnet *); 233 234 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 235 236 /* 237 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 238 * then ADAPTER_LOCK, then t4_uld_list_lock. 239 */ 240 static struct sx t4_list_lock; 241 SLIST_HEAD(, adapter) t4_list; 242 #ifdef TCP_OFFLOAD 243 static struct sx t4_uld_list_lock; 244 SLIST_HEAD(, uld_info) t4_uld_list; 245 #endif 246 247 /* 248 * Tunables. See tweak_tunables() too. 249 * 250 * Each tunable is set to a default value here if it's known at compile-time. 251 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 252 * provide a reasonable default (upto n) when the driver is loaded. 253 * 254 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 255 * T5 are under hw.cxl. 256 */ 257 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters"); 258 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters"); 259 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters"); 260 261 /* 262 * Number of queues for tx and rx, NIC and offload. 263 */ 264 #define NTXQ 16 265 int t4_ntxq = -NTXQ; 266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 267 "Number of TX queues per port"); 268 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 269 270 #define NRXQ 8 271 int t4_nrxq = -NRXQ; 272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 273 "Number of RX queues per port"); 274 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 275 276 #define NTXQ_VI 1 277 static int t4_ntxq_vi = -NTXQ_VI; 278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 279 "Number of TX queues per VI"); 280 281 #define NRXQ_VI 1 282 static int t4_nrxq_vi = -NRXQ_VI; 283 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 284 "Number of RX queues per VI"); 285 286 static int t4_rsrv_noflowq = 0; 287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 288 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 289 290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 291 #define NOFLDTXQ 8 292 static int t4_nofldtxq = -NOFLDTXQ; 293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 294 "Number of offload TX queues per port"); 295 296 #define NOFLDRXQ 2 297 static int t4_nofldrxq = -NOFLDRXQ; 298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 299 "Number of offload RX queues per port"); 300 301 #define NOFLDTXQ_VI 1 302 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 304 "Number of offload TX queues per VI"); 305 306 #define NOFLDRXQ_VI 1 307 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 309 "Number of offload RX queues per VI"); 310 311 #define TMR_IDX_OFLD 1 312 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 314 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 315 316 #define PKTC_IDX_OFLD (-1) 317 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 319 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 320 321 /* 0 means chip/fw default, non-zero number is value in microseconds */ 322 static u_long t4_toe_keepalive_idle = 0; 323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 324 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 325 326 /* 0 means chip/fw default, non-zero number is value in microseconds */ 327 static u_long t4_toe_keepalive_interval = 0; 328 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 329 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 330 331 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 332 static int t4_toe_keepalive_count = 0; 333 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 334 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 335 336 /* 0 means chip/fw default, non-zero number is value in microseconds */ 337 static u_long t4_toe_rexmt_min = 0; 338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 339 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 340 341 /* 0 means chip/fw default, non-zero number is value in microseconds */ 342 static u_long t4_toe_rexmt_max = 0; 343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 344 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 345 346 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 347 static int t4_toe_rexmt_count = 0; 348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 349 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 350 351 /* -1 means chip/fw default, other values are raw backoff values to use */ 352 static int t4_toe_rexmt_backoff[16] = { 353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 354 }; 355 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0, 356 "cxgbe(4) TOE retransmit backoff values"); 357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 358 &t4_toe_rexmt_backoff[0], 0, ""); 359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_backoff[1], 0, ""); 361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 362 &t4_toe_rexmt_backoff[2], 0, ""); 363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_backoff[3], 0, ""); 365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_backoff[4], 0, ""); 367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 368 &t4_toe_rexmt_backoff[5], 0, ""); 369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 370 &t4_toe_rexmt_backoff[6], 0, ""); 371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 372 &t4_toe_rexmt_backoff[7], 0, ""); 373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_backoff[8], 0, ""); 375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_backoff[9], 0, ""); 377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 378 &t4_toe_rexmt_backoff[10], 0, ""); 379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 380 &t4_toe_rexmt_backoff[11], 0, ""); 381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 382 &t4_toe_rexmt_backoff[12], 0, ""); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[13], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[14], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[15], 0, ""); 389 #endif 390 391 #ifdef DEV_NETMAP 392 #define NNMTXQ_VI 2 393 static int t4_nnmtxq_vi = -NNMTXQ_VI; 394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 395 "Number of netmap TX queues per VI"); 396 397 #define NNMRXQ_VI 2 398 static int t4_nnmrxq_vi = -NNMRXQ_VI; 399 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 400 "Number of netmap RX queues per VI"); 401 #endif 402 403 /* 404 * Holdoff parameters for ports. 405 */ 406 #define TMR_IDX 1 407 int t4_tmr_idx = TMR_IDX; 408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 409 0, "Holdoff timer index"); 410 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 411 412 #define PKTC_IDX (-1) 413 int t4_pktc_idx = PKTC_IDX; 414 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 415 0, "Holdoff packet counter index"); 416 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 417 418 /* 419 * Size (# of entries) of each tx and rx queue. 420 */ 421 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 423 "Number of descriptors in each TX queue"); 424 425 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 427 "Number of descriptors in each RX queue"); 428 429 /* 430 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 431 */ 432 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 434 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 435 436 /* 437 * Configuration file. All the _CF names here are special. 438 */ 439 #define DEFAULT_CF "default" 440 #define BUILTIN_CF "built-in" 441 #define FLASH_CF "flash" 442 #define UWIRE_CF "uwire" 443 #define FPGA_CF "fpga" 444 static char t4_cfg_file[32] = DEFAULT_CF; 445 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 446 sizeof(t4_cfg_file), "Firmware configuration file"); 447 448 /* 449 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 450 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 451 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 452 * mark or when signalled to do so, 0 to never emit PAUSE. 453 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 454 * negotiated settings will override rx_pause/tx_pause. 455 * Otherwise rx_pause/tx_pause are applied forcibly. 456 */ 457 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 459 &t4_pause_settings, 0, 460 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 461 462 /* 463 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 464 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 465 * 0 to disable FEC. 466 */ 467 static int t4_fec = -1; 468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 469 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 470 471 /* 472 * Link autonegotiation. 473 * -1 to run with the firmware default. 474 * 0 to disable. 475 * 1 to enable. 476 */ 477 static int t4_autoneg = -1; 478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 479 "Link autonegotiation"); 480 481 /* 482 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 483 * encouraged respectively). '-n' is the same as 'n' except the firmware 484 * version used in the checks is read from the firmware bundled with the driver. 485 */ 486 static int t4_fw_install = 1; 487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 488 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 489 490 /* 491 * ASIC features that will be used. Disable the ones you don't want so that the 492 * chip resources aren't wasted on features that will not be used. 493 */ 494 static int t4_nbmcaps_allowed = 0; 495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 496 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 497 498 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 499 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 500 &t4_linkcaps_allowed, 0, "Default link capabilities"); 501 502 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 503 FW_CAPS_CONFIG_SWITCH_EGRESS; 504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 505 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 506 507 #ifdef RATELIMIT 508 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 509 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 510 #else 511 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 512 FW_CAPS_CONFIG_NIC_HASHFILTER; 513 #endif 514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 515 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 516 517 static int t4_toecaps_allowed = -1; 518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 519 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 520 521 static int t4_rdmacaps_allowed = -1; 522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 523 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 524 525 static int t4_cryptocaps_allowed = -1; 526 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 527 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 528 529 static int t4_iscsicaps_allowed = -1; 530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 531 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 532 533 static int t4_fcoecaps_allowed = 0; 534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 535 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 536 537 static int t5_write_combine = 0; 538 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 539 0, "Use WC instead of UC for BAR2"); 540 541 static int t4_num_vis = 1; 542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 543 "Number of VIs per port"); 544 545 /* 546 * PCIe Relaxed Ordering. 547 * -1: driver should figure out a good value. 548 * 0: disable RO. 549 * 1: enable RO. 550 * 2: leave RO alone. 551 */ 552 static int pcie_relaxed_ordering = -1; 553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 554 &pcie_relaxed_ordering, 0, 555 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 556 557 static int t4_panic_on_fatal_err = 0; 558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN, 559 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 560 561 #ifdef TCP_OFFLOAD 562 /* 563 * TOE tunables. 564 */ 565 static int t4_cop_managed_offloading = 0; 566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 567 &t4_cop_managed_offloading, 0, 568 "COP (Connection Offload Policy) controls all TOE offload"); 569 #endif 570 571 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 572 static int vi_mac_funcs[] = { 573 FW_VI_FUNC_ETH, 574 FW_VI_FUNC_OFLD, 575 FW_VI_FUNC_IWARP, 576 FW_VI_FUNC_OPENISCSI, 577 FW_VI_FUNC_OPENFCOE, 578 FW_VI_FUNC_FOISCSI, 579 FW_VI_FUNC_FOFCOE, 580 }; 581 582 struct intrs_and_queues { 583 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 584 uint16_t num_vis; /* number of VIs for each port */ 585 uint16_t nirq; /* Total # of vectors */ 586 uint16_t ntxq; /* # of NIC txq's for each port */ 587 uint16_t nrxq; /* # of NIC rxq's for each port */ 588 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 589 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 590 591 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 592 uint16_t ntxq_vi; /* # of NIC txq's */ 593 uint16_t nrxq_vi; /* # of NIC rxq's */ 594 uint16_t nofldtxq_vi; /* # of TOE txq's */ 595 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 596 uint16_t nnmtxq_vi; /* # of netmap txq's */ 597 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 598 }; 599 600 static void setup_memwin(struct adapter *); 601 static void position_memwin(struct adapter *, int, uint32_t); 602 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 603 static int fwmtype_to_hwmtype(int); 604 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 605 uint32_t *); 606 static int fixup_devlog_params(struct adapter *); 607 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 608 static int contact_firmware(struct adapter *); 609 static int partition_resources(struct adapter *); 610 static int get_params__pre_init(struct adapter *); 611 static int set_params__pre_init(struct adapter *); 612 static int get_params__post_init(struct adapter *); 613 static int set_params__post_init(struct adapter *); 614 static void t4_set_desc(struct adapter *); 615 static bool fixed_ifmedia(struct port_info *); 616 static void build_medialist(struct port_info *); 617 static void init_link_config(struct port_info *); 618 static int fixup_link_config(struct port_info *); 619 static int apply_link_config(struct port_info *); 620 static int cxgbe_init_synchronized(struct vi_info *); 621 static int cxgbe_uninit_synchronized(struct vi_info *); 622 static void quiesce_txq(struct adapter *, struct sge_txq *); 623 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 624 static void quiesce_iq(struct adapter *, struct sge_iq *); 625 static void quiesce_fl(struct adapter *, struct sge_fl *); 626 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 627 driver_intr_t *, void *, char *); 628 static int t4_free_irq(struct adapter *, struct irq *); 629 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 630 static void vi_refresh_stats(struct adapter *, struct vi_info *); 631 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 632 static void cxgbe_tick(void *); 633 static void cxgbe_sysctls(struct port_info *); 634 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 635 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 636 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 637 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 638 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 639 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 640 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 641 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 642 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 643 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 644 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 645 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 646 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 647 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 648 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 649 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 650 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 651 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 652 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 653 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 654 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 655 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 656 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 657 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 658 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 659 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 660 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 661 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 662 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 663 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 664 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 665 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 666 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 667 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 668 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 669 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 670 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 671 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 672 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 673 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 674 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 675 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 676 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 677 #ifdef TCP_OFFLOAD 678 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 679 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 680 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 681 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 682 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 683 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 684 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 685 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 686 #endif 687 static int get_sge_context(struct adapter *, struct t4_sge_context *); 688 static int load_fw(struct adapter *, struct t4_data *); 689 static int load_cfg(struct adapter *, struct t4_data *); 690 static int load_boot(struct adapter *, struct t4_bootrom *); 691 static int load_bootcfg(struct adapter *, struct t4_data *); 692 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 693 static void free_offload_policy(struct t4_offload_policy *); 694 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 695 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 696 static int read_i2c(struct adapter *, struct t4_i2c_data *); 697 static int clear_stats(struct adapter *, u_int); 698 #ifdef TCP_OFFLOAD 699 static int toe_capability(struct vi_info *, int); 700 #endif 701 static int mod_event(module_t, int, void *); 702 static int notify_siblings(device_t, int); 703 704 struct { 705 uint16_t device; 706 char *desc; 707 } t4_pciids[] = { 708 {0xa000, "Chelsio Terminator 4 FPGA"}, 709 {0x4400, "Chelsio T440-dbg"}, 710 {0x4401, "Chelsio T420-CR"}, 711 {0x4402, "Chelsio T422-CR"}, 712 {0x4403, "Chelsio T440-CR"}, 713 {0x4404, "Chelsio T420-BCH"}, 714 {0x4405, "Chelsio T440-BCH"}, 715 {0x4406, "Chelsio T440-CH"}, 716 {0x4407, "Chelsio T420-SO"}, 717 {0x4408, "Chelsio T420-CX"}, 718 {0x4409, "Chelsio T420-BT"}, 719 {0x440a, "Chelsio T404-BT"}, 720 {0x440e, "Chelsio T440-LP-CR"}, 721 }, t5_pciids[] = { 722 {0xb000, "Chelsio Terminator 5 FPGA"}, 723 {0x5400, "Chelsio T580-dbg"}, 724 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 725 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 726 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 727 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 728 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 729 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 730 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 731 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 732 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 733 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 734 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 735 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 736 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 737 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 738 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 739 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 740 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 741 742 /* Custom */ 743 {0x5483, "Custom T540-CR"}, 744 {0x5484, "Custom T540-BT"}, 745 }, t6_pciids[] = { 746 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 747 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 748 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 749 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 750 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 751 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 752 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 753 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 754 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 755 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 756 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 757 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 758 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 759 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 760 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 761 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 762 763 /* Custom */ 764 {0x6480, "Custom T6225-CR"}, 765 {0x6481, "Custom T62100-CR"}, 766 {0x6482, "Custom T6225-CR"}, 767 {0x6483, "Custom T62100-CR"}, 768 {0x6484, "Custom T64100-CR"}, 769 {0x6485, "Custom T6240-SO"}, 770 {0x6486, "Custom T6225-SO-CR"}, 771 {0x6487, "Custom T6225-CR"}, 772 }; 773 774 #ifdef TCP_OFFLOAD 775 /* 776 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 777 * be exactly the same for both rxq and ofld_rxq. 778 */ 779 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 780 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 781 #endif 782 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 783 784 static int 785 t4_probe(device_t dev) 786 { 787 int i; 788 uint16_t v = pci_get_vendor(dev); 789 uint16_t d = pci_get_device(dev); 790 uint8_t f = pci_get_function(dev); 791 792 if (v != PCI_VENDOR_ID_CHELSIO) 793 return (ENXIO); 794 795 /* Attach only to PF0 of the FPGA */ 796 if (d == 0xa000 && f != 0) 797 return (ENXIO); 798 799 for (i = 0; i < nitems(t4_pciids); i++) { 800 if (d == t4_pciids[i].device) { 801 device_set_desc(dev, t4_pciids[i].desc); 802 return (BUS_PROBE_DEFAULT); 803 } 804 } 805 806 return (ENXIO); 807 } 808 809 static int 810 t5_probe(device_t dev) 811 { 812 int i; 813 uint16_t v = pci_get_vendor(dev); 814 uint16_t d = pci_get_device(dev); 815 uint8_t f = pci_get_function(dev); 816 817 if (v != PCI_VENDOR_ID_CHELSIO) 818 return (ENXIO); 819 820 /* Attach only to PF0 of the FPGA */ 821 if (d == 0xb000 && f != 0) 822 return (ENXIO); 823 824 for (i = 0; i < nitems(t5_pciids); i++) { 825 if (d == t5_pciids[i].device) { 826 device_set_desc(dev, t5_pciids[i].desc); 827 return (BUS_PROBE_DEFAULT); 828 } 829 } 830 831 return (ENXIO); 832 } 833 834 static int 835 t6_probe(device_t dev) 836 { 837 int i; 838 uint16_t v = pci_get_vendor(dev); 839 uint16_t d = pci_get_device(dev); 840 841 if (v != PCI_VENDOR_ID_CHELSIO) 842 return (ENXIO); 843 844 for (i = 0; i < nitems(t6_pciids); i++) { 845 if (d == t6_pciids[i].device) { 846 device_set_desc(dev, t6_pciids[i].desc); 847 return (BUS_PROBE_DEFAULT); 848 } 849 } 850 851 return (ENXIO); 852 } 853 854 static void 855 t5_attribute_workaround(device_t dev) 856 { 857 device_t root_port; 858 uint32_t v; 859 860 /* 861 * The T5 chips do not properly echo the No Snoop and Relaxed 862 * Ordering attributes when replying to a TLP from a Root 863 * Port. As a workaround, find the parent Root Port and 864 * disable No Snoop and Relaxed Ordering. Note that this 865 * affects all devices under this root port. 866 */ 867 root_port = pci_find_pcie_root_port(dev); 868 if (root_port == NULL) { 869 device_printf(dev, "Unable to find parent root port\n"); 870 return; 871 } 872 873 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 874 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 875 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 876 0) 877 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 878 device_get_nameunit(root_port)); 879 } 880 881 static const struct devnames devnames[] = { 882 { 883 .nexus_name = "t4nex", 884 .ifnet_name = "cxgbe", 885 .vi_ifnet_name = "vcxgbe", 886 .pf03_drv_name = "t4iov", 887 .vf_nexus_name = "t4vf", 888 .vf_ifnet_name = "cxgbev" 889 }, { 890 .nexus_name = "t5nex", 891 .ifnet_name = "cxl", 892 .vi_ifnet_name = "vcxl", 893 .pf03_drv_name = "t5iov", 894 .vf_nexus_name = "t5vf", 895 .vf_ifnet_name = "cxlv" 896 }, { 897 .nexus_name = "t6nex", 898 .ifnet_name = "cc", 899 .vi_ifnet_name = "vcc", 900 .pf03_drv_name = "t6iov", 901 .vf_nexus_name = "t6vf", 902 .vf_ifnet_name = "ccv" 903 } 904 }; 905 906 void 907 t4_init_devnames(struct adapter *sc) 908 { 909 int id; 910 911 id = chip_id(sc); 912 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 913 sc->names = &devnames[id - CHELSIO_T4]; 914 else { 915 device_printf(sc->dev, "chip id %d is not supported.\n", id); 916 sc->names = NULL; 917 } 918 } 919 920 static int 921 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 922 { 923 const char *parent, *name; 924 long value; 925 int line, unit; 926 927 line = 0; 928 parent = device_get_nameunit(sc->dev); 929 name = sc->names->ifnet_name; 930 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 931 if (resource_long_value(name, unit, "port", &value) == 0 && 932 value == pi->port_id) 933 return (unit); 934 } 935 return (-1); 936 } 937 938 static int 939 t4_attach(device_t dev) 940 { 941 struct adapter *sc; 942 int rc = 0, i, j, rqidx, tqidx, nports; 943 struct make_dev_args mda; 944 struct intrs_and_queues iaq; 945 struct sge *s; 946 uint32_t *buf; 947 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 948 int ofld_tqidx; 949 #endif 950 #ifdef TCP_OFFLOAD 951 int ofld_rqidx; 952 #endif 953 #ifdef DEV_NETMAP 954 int nm_rqidx, nm_tqidx; 955 #endif 956 int num_vis; 957 958 sc = device_get_softc(dev); 959 sc->dev = dev; 960 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 961 962 if ((pci_get_device(dev) & 0xff00) == 0x5400) 963 t5_attribute_workaround(dev); 964 pci_enable_busmaster(dev); 965 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 966 uint32_t v; 967 968 pci_set_max_read_req(dev, 4096); 969 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 970 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 971 if (pcie_relaxed_ordering == 0 && 972 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 973 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 974 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 975 } else if (pcie_relaxed_ordering == 1 && 976 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 977 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 978 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 979 } 980 } 981 982 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 983 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 984 sc->traceq = -1; 985 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 986 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 987 device_get_nameunit(dev)); 988 989 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 990 device_get_nameunit(dev)); 991 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 992 t4_add_adapter(sc); 993 994 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 995 TAILQ_INIT(&sc->sfl); 996 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 997 998 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 999 1000 sc->policy = NULL; 1001 rw_init(&sc->policy_lock, "connection offload policy"); 1002 1003 rc = t4_map_bars_0_and_4(sc); 1004 if (rc != 0) 1005 goto done; /* error message displayed already */ 1006 1007 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1008 1009 /* Prepare the adapter for operation. */ 1010 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1011 rc = -t4_prep_adapter(sc, buf); 1012 free(buf, M_CXGBE); 1013 if (rc != 0) { 1014 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1015 goto done; 1016 } 1017 1018 /* 1019 * This is the real PF# to which we're attaching. Works from within PCI 1020 * passthrough environments too, where pci_get_function() could return a 1021 * different PF# depending on the passthrough configuration. We need to 1022 * use the real PF# in all our communication with the firmware. 1023 */ 1024 j = t4_read_reg(sc, A_PL_WHOAMI); 1025 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1026 sc->mbox = sc->pf; 1027 1028 t4_init_devnames(sc); 1029 if (sc->names == NULL) { 1030 rc = ENOTSUP; 1031 goto done; /* error message displayed already */ 1032 } 1033 1034 /* 1035 * Do this really early, with the memory windows set up even before the 1036 * character device. The userland tool's register i/o and mem read 1037 * will work even in "recovery mode". 1038 */ 1039 setup_memwin(sc); 1040 if (t4_init_devlog_params(sc, 0) == 0) 1041 fixup_devlog_params(sc); 1042 make_dev_args_init(&mda); 1043 mda.mda_devsw = &t4_cdevsw; 1044 mda.mda_uid = UID_ROOT; 1045 mda.mda_gid = GID_WHEEL; 1046 mda.mda_mode = 0600; 1047 mda.mda_si_drv1 = sc; 1048 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1049 if (rc != 0) 1050 device_printf(dev, "failed to create nexus char device: %d.\n", 1051 rc); 1052 1053 /* Go no further if recovery mode has been requested. */ 1054 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1055 device_printf(dev, "recovery mode.\n"); 1056 goto done; 1057 } 1058 1059 #if defined(__i386__) 1060 if ((cpu_feature & CPUID_CX8) == 0) { 1061 device_printf(dev, "64 bit atomics not available.\n"); 1062 rc = ENOTSUP; 1063 goto done; 1064 } 1065 #endif 1066 1067 /* Contact the firmware and try to become the master driver. */ 1068 rc = contact_firmware(sc); 1069 if (rc != 0) 1070 goto done; /* error message displayed already */ 1071 MPASS(sc->flags & FW_OK); 1072 1073 rc = get_params__pre_init(sc); 1074 if (rc != 0) 1075 goto done; /* error message displayed already */ 1076 1077 if (sc->flags & MASTER_PF) { 1078 rc = partition_resources(sc); 1079 if (rc != 0) 1080 goto done; /* error message displayed already */ 1081 t4_intr_clear(sc); 1082 } 1083 1084 rc = get_params__post_init(sc); 1085 if (rc != 0) 1086 goto done; /* error message displayed already */ 1087 1088 rc = set_params__post_init(sc); 1089 if (rc != 0) 1090 goto done; /* error message displayed already */ 1091 1092 rc = t4_map_bar_2(sc); 1093 if (rc != 0) 1094 goto done; /* error message displayed already */ 1095 1096 rc = t4_create_dma_tag(sc); 1097 if (rc != 0) 1098 goto done; /* error message displayed already */ 1099 1100 /* 1101 * First pass over all the ports - allocate VIs and initialize some 1102 * basic parameters like mac address, port type, etc. 1103 */ 1104 for_each_port(sc, i) { 1105 struct port_info *pi; 1106 1107 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1108 sc->port[i] = pi; 1109 1110 /* These must be set before t4_port_init */ 1111 pi->adapter = sc; 1112 pi->port_id = i; 1113 /* 1114 * XXX: vi[0] is special so we can't delay this allocation until 1115 * pi->nvi's final value is known. 1116 */ 1117 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1118 M_ZERO | M_WAITOK); 1119 1120 /* 1121 * Allocate the "main" VI and initialize parameters 1122 * like mac addr. 1123 */ 1124 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1125 if (rc != 0) { 1126 device_printf(dev, "unable to initialize port %d: %d\n", 1127 i, rc); 1128 free(pi->vi, M_CXGBE); 1129 free(pi, M_CXGBE); 1130 sc->port[i] = NULL; 1131 goto done; 1132 } 1133 1134 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1135 device_get_nameunit(dev), i); 1136 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1137 sc->chan_map[pi->tx_chan] = i; 1138 1139 /* All VIs on this port share this media. */ 1140 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1141 cxgbe_media_status); 1142 1143 PORT_LOCK(pi); 1144 init_link_config(pi); 1145 fixup_link_config(pi); 1146 build_medialist(pi); 1147 if (fixed_ifmedia(pi)) 1148 pi->flags |= FIXED_IFMEDIA; 1149 PORT_UNLOCK(pi); 1150 1151 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1152 t4_ifnet_unit(sc, pi)); 1153 if (pi->dev == NULL) { 1154 device_printf(dev, 1155 "failed to add device for port %d.\n", i); 1156 rc = ENXIO; 1157 goto done; 1158 } 1159 pi->vi[0].dev = pi->dev; 1160 device_set_softc(pi->dev, pi); 1161 } 1162 1163 /* 1164 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1165 */ 1166 nports = sc->params.nports; 1167 rc = cfg_itype_and_nqueues(sc, &iaq); 1168 if (rc != 0) 1169 goto done; /* error message displayed already */ 1170 1171 num_vis = iaq.num_vis; 1172 sc->intr_type = iaq.intr_type; 1173 sc->intr_count = iaq.nirq; 1174 1175 s = &sc->sge; 1176 s->nrxq = nports * iaq.nrxq; 1177 s->ntxq = nports * iaq.ntxq; 1178 if (num_vis > 1) { 1179 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1180 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1181 } 1182 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1183 s->neq += nports; /* ctrl queues: 1 per port */ 1184 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1185 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1186 if (is_offload(sc) || is_ethoffload(sc)) { 1187 s->nofldtxq = nports * iaq.nofldtxq; 1188 if (num_vis > 1) 1189 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1190 s->neq += s->nofldtxq; 1191 1192 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1193 M_CXGBE, M_ZERO | M_WAITOK); 1194 } 1195 #endif 1196 #ifdef TCP_OFFLOAD 1197 if (is_offload(sc)) { 1198 s->nofldrxq = nports * iaq.nofldrxq; 1199 if (num_vis > 1) 1200 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1201 s->neq += s->nofldrxq; /* free list */ 1202 s->niq += s->nofldrxq; 1203 1204 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1205 M_CXGBE, M_ZERO | M_WAITOK); 1206 } 1207 #endif 1208 #ifdef DEV_NETMAP 1209 if (num_vis > 1) { 1210 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1211 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1212 } 1213 s->neq += s->nnmtxq + s->nnmrxq; 1214 s->niq += s->nnmrxq; 1215 1216 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1217 M_CXGBE, M_ZERO | M_WAITOK); 1218 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1219 M_CXGBE, M_ZERO | M_WAITOK); 1220 #endif 1221 1222 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1223 M_ZERO | M_WAITOK); 1224 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1225 M_ZERO | M_WAITOK); 1226 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1227 M_ZERO | M_WAITOK); 1228 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1229 M_ZERO | M_WAITOK); 1230 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1231 M_ZERO | M_WAITOK); 1232 1233 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1234 M_ZERO | M_WAITOK); 1235 1236 t4_init_l2t(sc, M_WAITOK); 1237 t4_init_smt(sc, M_WAITOK); 1238 t4_init_tx_sched(sc); 1239 #ifdef RATELIMIT 1240 t4_init_etid_table(sc); 1241 #endif 1242 #ifdef INET6 1243 t4_init_clip_table(sc); 1244 #endif 1245 if (sc->vres.key.size != 0) 1246 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1247 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1248 1249 /* 1250 * Second pass over the ports. This time we know the number of rx and 1251 * tx queues that each port should get. 1252 */ 1253 rqidx = tqidx = 0; 1254 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1255 ofld_tqidx = 0; 1256 #endif 1257 #ifdef TCP_OFFLOAD 1258 ofld_rqidx = 0; 1259 #endif 1260 #ifdef DEV_NETMAP 1261 nm_rqidx = nm_tqidx = 0; 1262 #endif 1263 for_each_port(sc, i) { 1264 struct port_info *pi = sc->port[i]; 1265 struct vi_info *vi; 1266 1267 if (pi == NULL) 1268 continue; 1269 1270 pi->nvi = num_vis; 1271 for_each_vi(pi, j, vi) { 1272 vi->pi = pi; 1273 vi->qsize_rxq = t4_qsize_rxq; 1274 vi->qsize_txq = t4_qsize_txq; 1275 1276 vi->first_rxq = rqidx; 1277 vi->first_txq = tqidx; 1278 vi->tmr_idx = t4_tmr_idx; 1279 vi->pktc_idx = t4_pktc_idx; 1280 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1281 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1282 1283 rqidx += vi->nrxq; 1284 tqidx += vi->ntxq; 1285 1286 if (j == 0 && vi->ntxq > 1) 1287 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1288 else 1289 vi->rsrv_noflowq = 0; 1290 1291 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1292 vi->first_ofld_txq = ofld_tqidx; 1293 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1294 ofld_tqidx += vi->nofldtxq; 1295 #endif 1296 #ifdef TCP_OFFLOAD 1297 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1298 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1299 vi->first_ofld_rxq = ofld_rqidx; 1300 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1301 1302 ofld_rqidx += vi->nofldrxq; 1303 #endif 1304 #ifdef DEV_NETMAP 1305 if (j > 0) { 1306 vi->first_nm_rxq = nm_rqidx; 1307 vi->first_nm_txq = nm_tqidx; 1308 vi->nnmrxq = iaq.nnmrxq_vi; 1309 vi->nnmtxq = iaq.nnmtxq_vi; 1310 nm_rqidx += vi->nnmrxq; 1311 nm_tqidx += vi->nnmtxq; 1312 } 1313 #endif 1314 } 1315 } 1316 1317 rc = t4_setup_intr_handlers(sc); 1318 if (rc != 0) { 1319 device_printf(dev, 1320 "failed to setup interrupt handlers: %d\n", rc); 1321 goto done; 1322 } 1323 1324 rc = bus_generic_probe(dev); 1325 if (rc != 0) { 1326 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1327 goto done; 1328 } 1329 1330 /* 1331 * Ensure thread-safe mailbox access (in debug builds). 1332 * 1333 * So far this was the only thread accessing the mailbox but various 1334 * ifnets and sysctls are about to be created and their handlers/ioctls 1335 * will access the mailbox from different threads. 1336 */ 1337 sc->flags |= CHK_MBOX_ACCESS; 1338 1339 rc = bus_generic_attach(dev); 1340 if (rc != 0) { 1341 device_printf(dev, 1342 "failed to attach all child ports: %d\n", rc); 1343 goto done; 1344 } 1345 1346 device_printf(dev, 1347 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1348 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1349 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1350 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1351 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1352 1353 t4_set_desc(sc); 1354 1355 notify_siblings(dev, 0); 1356 1357 done: 1358 if (rc != 0 && sc->cdev) { 1359 /* cdev was created and so cxgbetool works; recover that way. */ 1360 device_printf(dev, 1361 "error during attach, adapter is now in recovery mode.\n"); 1362 rc = 0; 1363 } 1364 1365 if (rc != 0) 1366 t4_detach_common(dev); 1367 else 1368 t4_sysctls(sc); 1369 1370 return (rc); 1371 } 1372 1373 static int 1374 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1375 { 1376 struct adapter *sc; 1377 struct port_info *pi; 1378 int i; 1379 1380 sc = device_get_softc(bus); 1381 buf[0] = '\0'; 1382 for_each_port(sc, i) { 1383 pi = sc->port[i]; 1384 if (pi != NULL && pi->dev == dev) { 1385 snprintf(buf, buflen, "port=%d", pi->port_id); 1386 break; 1387 } 1388 } 1389 return (0); 1390 } 1391 1392 static int 1393 t4_ready(device_t dev) 1394 { 1395 struct adapter *sc; 1396 1397 sc = device_get_softc(dev); 1398 if (sc->flags & FW_OK) 1399 return (0); 1400 return (ENXIO); 1401 } 1402 1403 static int 1404 t4_read_port_device(device_t dev, int port, device_t *child) 1405 { 1406 struct adapter *sc; 1407 struct port_info *pi; 1408 1409 sc = device_get_softc(dev); 1410 if (port < 0 || port >= MAX_NPORTS) 1411 return (EINVAL); 1412 pi = sc->port[port]; 1413 if (pi == NULL || pi->dev == NULL) 1414 return (ENXIO); 1415 *child = pi->dev; 1416 return (0); 1417 } 1418 1419 static int 1420 notify_siblings(device_t dev, int detaching) 1421 { 1422 device_t sibling; 1423 int error, i; 1424 1425 error = 0; 1426 for (i = 0; i < PCI_FUNCMAX; i++) { 1427 if (i == pci_get_function(dev)) 1428 continue; 1429 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1430 pci_get_slot(dev), i); 1431 if (sibling == NULL || !device_is_attached(sibling)) 1432 continue; 1433 if (detaching) 1434 error = T4_DETACH_CHILD(sibling); 1435 else 1436 (void)T4_ATTACH_CHILD(sibling); 1437 if (error) 1438 break; 1439 } 1440 return (error); 1441 } 1442 1443 /* 1444 * Idempotent 1445 */ 1446 static int 1447 t4_detach(device_t dev) 1448 { 1449 struct adapter *sc; 1450 int rc; 1451 1452 sc = device_get_softc(dev); 1453 1454 rc = notify_siblings(dev, 1); 1455 if (rc) { 1456 device_printf(dev, 1457 "failed to detach sibling devices: %d\n", rc); 1458 return (rc); 1459 } 1460 1461 return (t4_detach_common(dev)); 1462 } 1463 1464 int 1465 t4_detach_common(device_t dev) 1466 { 1467 struct adapter *sc; 1468 struct port_info *pi; 1469 int i, rc; 1470 1471 sc = device_get_softc(dev); 1472 1473 if (sc->cdev) { 1474 destroy_dev(sc->cdev); 1475 sc->cdev = NULL; 1476 } 1477 1478 sc->flags &= ~CHK_MBOX_ACCESS; 1479 if (sc->flags & FULL_INIT_DONE) { 1480 if (!(sc->flags & IS_VF)) 1481 t4_intr_disable(sc); 1482 } 1483 1484 if (device_is_attached(dev)) { 1485 rc = bus_generic_detach(dev); 1486 if (rc) { 1487 device_printf(dev, 1488 "failed to detach child devices: %d\n", rc); 1489 return (rc); 1490 } 1491 } 1492 1493 for (i = 0; i < sc->intr_count; i++) 1494 t4_free_irq(sc, &sc->irq[i]); 1495 1496 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1497 t4_free_tx_sched(sc); 1498 1499 for (i = 0; i < MAX_NPORTS; i++) { 1500 pi = sc->port[i]; 1501 if (pi) { 1502 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1503 if (pi->dev) 1504 device_delete_child(dev, pi->dev); 1505 1506 mtx_destroy(&pi->pi_lock); 1507 free(pi->vi, M_CXGBE); 1508 free(pi, M_CXGBE); 1509 } 1510 } 1511 1512 device_delete_children(dev); 1513 1514 if (sc->flags & FULL_INIT_DONE) 1515 adapter_full_uninit(sc); 1516 1517 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1518 t4_fw_bye(sc, sc->mbox); 1519 1520 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1521 pci_release_msi(dev); 1522 1523 if (sc->regs_res) 1524 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1525 sc->regs_res); 1526 1527 if (sc->udbs_res) 1528 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1529 sc->udbs_res); 1530 1531 if (sc->msix_res) 1532 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1533 sc->msix_res); 1534 1535 if (sc->l2t) 1536 t4_free_l2t(sc->l2t); 1537 if (sc->smt) 1538 t4_free_smt(sc->smt); 1539 #ifdef RATELIMIT 1540 t4_free_etid_table(sc); 1541 #endif 1542 if (sc->key_map) 1543 vmem_destroy(sc->key_map); 1544 #ifdef INET6 1545 t4_destroy_clip_table(sc); 1546 #endif 1547 1548 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1549 free(sc->sge.ofld_txq, M_CXGBE); 1550 #endif 1551 #ifdef TCP_OFFLOAD 1552 free(sc->sge.ofld_rxq, M_CXGBE); 1553 #endif 1554 #ifdef DEV_NETMAP 1555 free(sc->sge.nm_rxq, M_CXGBE); 1556 free(sc->sge.nm_txq, M_CXGBE); 1557 #endif 1558 free(sc->irq, M_CXGBE); 1559 free(sc->sge.rxq, M_CXGBE); 1560 free(sc->sge.txq, M_CXGBE); 1561 free(sc->sge.ctrlq, M_CXGBE); 1562 free(sc->sge.iqmap, M_CXGBE); 1563 free(sc->sge.eqmap, M_CXGBE); 1564 free(sc->tids.ftid_tab, M_CXGBE); 1565 free(sc->tids.hpftid_tab, M_CXGBE); 1566 free_hftid_hash(&sc->tids); 1567 free(sc->tids.atid_tab, M_CXGBE); 1568 free(sc->tids.tid_tab, M_CXGBE); 1569 free(sc->tt.tls_rx_ports, M_CXGBE); 1570 t4_destroy_dma_tag(sc); 1571 if (mtx_initialized(&sc->sc_lock)) { 1572 sx_xlock(&t4_list_lock); 1573 SLIST_REMOVE(&t4_list, sc, adapter, link); 1574 sx_xunlock(&t4_list_lock); 1575 mtx_destroy(&sc->sc_lock); 1576 } 1577 1578 callout_drain(&sc->sfl_callout); 1579 if (mtx_initialized(&sc->tids.ftid_lock)) { 1580 mtx_destroy(&sc->tids.ftid_lock); 1581 cv_destroy(&sc->tids.ftid_cv); 1582 } 1583 if (mtx_initialized(&sc->tids.atid_lock)) 1584 mtx_destroy(&sc->tids.atid_lock); 1585 if (mtx_initialized(&sc->sfl_lock)) 1586 mtx_destroy(&sc->sfl_lock); 1587 if (mtx_initialized(&sc->ifp_lock)) 1588 mtx_destroy(&sc->ifp_lock); 1589 if (mtx_initialized(&sc->reg_lock)) 1590 mtx_destroy(&sc->reg_lock); 1591 1592 if (rw_initialized(&sc->policy_lock)) { 1593 rw_destroy(&sc->policy_lock); 1594 #ifdef TCP_OFFLOAD 1595 if (sc->policy != NULL) 1596 free_offload_policy(sc->policy); 1597 #endif 1598 } 1599 1600 for (i = 0; i < NUM_MEMWIN; i++) { 1601 struct memwin *mw = &sc->memwin[i]; 1602 1603 if (rw_initialized(&mw->mw_lock)) 1604 rw_destroy(&mw->mw_lock); 1605 } 1606 1607 bzero(sc, sizeof(*sc)); 1608 1609 return (0); 1610 } 1611 1612 static int 1613 cxgbe_probe(device_t dev) 1614 { 1615 char buf[128]; 1616 struct port_info *pi = device_get_softc(dev); 1617 1618 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1619 device_set_desc_copy(dev, buf); 1620 1621 return (BUS_PROBE_DEFAULT); 1622 } 1623 1624 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1625 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1626 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 1627 IFCAP_HWRXTSTMP) 1628 #define T4_CAP_ENABLE (T4_CAP) 1629 1630 static int 1631 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1632 { 1633 struct ifnet *ifp; 1634 struct sbuf *sb; 1635 1636 vi->xact_addr_filt = -1; 1637 callout_init(&vi->tick, 1); 1638 1639 /* Allocate an ifnet and set it up */ 1640 ifp = if_alloc(IFT_ETHER); 1641 if (ifp == NULL) { 1642 device_printf(dev, "Cannot allocate ifnet\n"); 1643 return (ENOMEM); 1644 } 1645 vi->ifp = ifp; 1646 ifp->if_softc = vi; 1647 1648 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1649 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1650 1651 ifp->if_init = cxgbe_init; 1652 ifp->if_ioctl = cxgbe_ioctl; 1653 ifp->if_transmit = cxgbe_transmit; 1654 ifp->if_qflush = cxgbe_qflush; 1655 ifp->if_get_counter = cxgbe_get_counter; 1656 #ifdef RATELIMIT 1657 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1658 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1659 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1660 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1661 #endif 1662 1663 ifp->if_capabilities = T4_CAP; 1664 ifp->if_capenable = T4_CAP_ENABLE; 1665 #ifdef TCP_OFFLOAD 1666 if (vi->nofldrxq != 0) 1667 ifp->if_capabilities |= IFCAP_TOE; 1668 #endif 1669 #ifdef RATELIMIT 1670 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) { 1671 ifp->if_capabilities |= IFCAP_TXRTLMT; 1672 ifp->if_capenable |= IFCAP_TXRTLMT; 1673 } 1674 #endif 1675 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1676 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1677 1678 ifp->if_hw_tsomax = IP_MAXPACKET; 1679 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 1680 #ifdef RATELIMIT 1681 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) 1682 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 1683 #endif 1684 ifp->if_hw_tsomaxsegsize = 65536; 1685 1686 ether_ifattach(ifp, vi->hw_addr); 1687 #ifdef DEV_NETMAP 1688 if (vi->nnmrxq != 0) 1689 cxgbe_nm_attach(vi); 1690 #endif 1691 sb = sbuf_new_auto(); 1692 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1693 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1694 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1695 case IFCAP_TOE: 1696 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1697 break; 1698 case IFCAP_TOE | IFCAP_TXRTLMT: 1699 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1700 break; 1701 case IFCAP_TXRTLMT: 1702 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1703 break; 1704 } 1705 #endif 1706 #ifdef TCP_OFFLOAD 1707 if (ifp->if_capabilities & IFCAP_TOE) 1708 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1709 #endif 1710 #ifdef DEV_NETMAP 1711 if (ifp->if_capabilities & IFCAP_NETMAP) 1712 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1713 vi->nnmtxq, vi->nnmrxq); 1714 #endif 1715 sbuf_finish(sb); 1716 device_printf(dev, "%s\n", sbuf_data(sb)); 1717 sbuf_delete(sb); 1718 1719 vi_sysctls(vi); 1720 1721 return (0); 1722 } 1723 1724 static int 1725 cxgbe_attach(device_t dev) 1726 { 1727 struct port_info *pi = device_get_softc(dev); 1728 struct adapter *sc = pi->adapter; 1729 struct vi_info *vi; 1730 int i, rc; 1731 1732 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1733 1734 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1735 if (rc) 1736 return (rc); 1737 1738 for_each_vi(pi, i, vi) { 1739 if (i == 0) 1740 continue; 1741 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1742 if (vi->dev == NULL) { 1743 device_printf(dev, "failed to add VI %d\n", i); 1744 continue; 1745 } 1746 device_set_softc(vi->dev, vi); 1747 } 1748 1749 cxgbe_sysctls(pi); 1750 1751 bus_generic_attach(dev); 1752 1753 return (0); 1754 } 1755 1756 static void 1757 cxgbe_vi_detach(struct vi_info *vi) 1758 { 1759 struct ifnet *ifp = vi->ifp; 1760 1761 ether_ifdetach(ifp); 1762 1763 /* Let detach proceed even if these fail. */ 1764 #ifdef DEV_NETMAP 1765 if (ifp->if_capabilities & IFCAP_NETMAP) 1766 cxgbe_nm_detach(vi); 1767 #endif 1768 cxgbe_uninit_synchronized(vi); 1769 callout_drain(&vi->tick); 1770 vi_full_uninit(vi); 1771 1772 if_free(vi->ifp); 1773 vi->ifp = NULL; 1774 } 1775 1776 static int 1777 cxgbe_detach(device_t dev) 1778 { 1779 struct port_info *pi = device_get_softc(dev); 1780 struct adapter *sc = pi->adapter; 1781 int rc; 1782 1783 /* Detach the extra VIs first. */ 1784 rc = bus_generic_detach(dev); 1785 if (rc) 1786 return (rc); 1787 device_delete_children(dev); 1788 1789 doom_vi(sc, &pi->vi[0]); 1790 1791 if (pi->flags & HAS_TRACEQ) { 1792 sc->traceq = -1; /* cloner should not create ifnet */ 1793 t4_tracer_port_detach(sc); 1794 } 1795 1796 cxgbe_vi_detach(&pi->vi[0]); 1797 callout_drain(&pi->tick); 1798 ifmedia_removeall(&pi->media); 1799 1800 end_synchronized_op(sc, 0); 1801 1802 return (0); 1803 } 1804 1805 static void 1806 cxgbe_init(void *arg) 1807 { 1808 struct vi_info *vi = arg; 1809 struct adapter *sc = vi->pi->adapter; 1810 1811 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1812 return; 1813 cxgbe_init_synchronized(vi); 1814 end_synchronized_op(sc, 0); 1815 } 1816 1817 static int 1818 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1819 { 1820 int rc = 0, mtu, flags; 1821 struct vi_info *vi = ifp->if_softc; 1822 struct port_info *pi = vi->pi; 1823 struct adapter *sc = pi->adapter; 1824 struct ifreq *ifr = (struct ifreq *)data; 1825 uint32_t mask; 1826 1827 switch (cmd) { 1828 case SIOCSIFMTU: 1829 mtu = ifr->ifr_mtu; 1830 if (mtu < ETHERMIN || mtu > MAX_MTU) 1831 return (EINVAL); 1832 1833 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1834 if (rc) 1835 return (rc); 1836 ifp->if_mtu = mtu; 1837 if (vi->flags & VI_INIT_DONE) { 1838 t4_update_fl_bufsize(ifp); 1839 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1840 rc = update_mac_settings(ifp, XGMAC_MTU); 1841 } 1842 end_synchronized_op(sc, 0); 1843 break; 1844 1845 case SIOCSIFFLAGS: 1846 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 1847 if (rc) 1848 return (rc); 1849 1850 if (ifp->if_flags & IFF_UP) { 1851 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1852 flags = vi->if_flags; 1853 if ((ifp->if_flags ^ flags) & 1854 (IFF_PROMISC | IFF_ALLMULTI)) { 1855 rc = update_mac_settings(ifp, 1856 XGMAC_PROMISC | XGMAC_ALLMULTI); 1857 } 1858 } else { 1859 rc = cxgbe_init_synchronized(vi); 1860 } 1861 vi->if_flags = ifp->if_flags; 1862 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1863 rc = cxgbe_uninit_synchronized(vi); 1864 } 1865 end_synchronized_op(sc, 0); 1866 break; 1867 1868 case SIOCADDMULTI: 1869 case SIOCDELMULTI: 1870 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 1871 if (rc) 1872 return (rc); 1873 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1874 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1875 end_synchronized_op(sc, 0); 1876 break; 1877 1878 case SIOCSIFCAP: 1879 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1880 if (rc) 1881 return (rc); 1882 1883 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1884 if (mask & IFCAP_TXCSUM) { 1885 ifp->if_capenable ^= IFCAP_TXCSUM; 1886 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1887 1888 if (IFCAP_TSO4 & ifp->if_capenable && 1889 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1890 ifp->if_capenable &= ~IFCAP_TSO4; 1891 if_printf(ifp, 1892 "tso4 disabled due to -txcsum.\n"); 1893 } 1894 } 1895 if (mask & IFCAP_TXCSUM_IPV6) { 1896 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1897 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1898 1899 if (IFCAP_TSO6 & ifp->if_capenable && 1900 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1901 ifp->if_capenable &= ~IFCAP_TSO6; 1902 if_printf(ifp, 1903 "tso6 disabled due to -txcsum6.\n"); 1904 } 1905 } 1906 if (mask & IFCAP_RXCSUM) 1907 ifp->if_capenable ^= IFCAP_RXCSUM; 1908 if (mask & IFCAP_RXCSUM_IPV6) 1909 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1910 1911 /* 1912 * Note that we leave CSUM_TSO alone (it is always set). The 1913 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1914 * sending a TSO request our way, so it's sufficient to toggle 1915 * IFCAP_TSOx only. 1916 */ 1917 if (mask & IFCAP_TSO4) { 1918 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1919 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1920 if_printf(ifp, "enable txcsum first.\n"); 1921 rc = EAGAIN; 1922 goto fail; 1923 } 1924 ifp->if_capenable ^= IFCAP_TSO4; 1925 } 1926 if (mask & IFCAP_TSO6) { 1927 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1928 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1929 if_printf(ifp, "enable txcsum6 first.\n"); 1930 rc = EAGAIN; 1931 goto fail; 1932 } 1933 ifp->if_capenable ^= IFCAP_TSO6; 1934 } 1935 if (mask & IFCAP_LRO) { 1936 #if defined(INET) || defined(INET6) 1937 int i; 1938 struct sge_rxq *rxq; 1939 1940 ifp->if_capenable ^= IFCAP_LRO; 1941 for_each_rxq(vi, i, rxq) { 1942 if (ifp->if_capenable & IFCAP_LRO) 1943 rxq->iq.flags |= IQ_LRO_ENABLED; 1944 else 1945 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1946 } 1947 #endif 1948 } 1949 #ifdef TCP_OFFLOAD 1950 if (mask & IFCAP_TOE) { 1951 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1952 1953 rc = toe_capability(vi, enable); 1954 if (rc != 0) 1955 goto fail; 1956 1957 ifp->if_capenable ^= mask; 1958 } 1959 #endif 1960 if (mask & IFCAP_VLAN_HWTAGGING) { 1961 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1962 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1963 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1964 } 1965 if (mask & IFCAP_VLAN_MTU) { 1966 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1967 1968 /* Need to find out how to disable auto-mtu-inflation */ 1969 } 1970 if (mask & IFCAP_VLAN_HWTSO) 1971 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1972 if (mask & IFCAP_VLAN_HWCSUM) 1973 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1974 #ifdef RATELIMIT 1975 if (mask & IFCAP_TXRTLMT) 1976 ifp->if_capenable ^= IFCAP_TXRTLMT; 1977 #endif 1978 if (mask & IFCAP_HWRXTSTMP) { 1979 int i; 1980 struct sge_rxq *rxq; 1981 1982 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 1983 for_each_rxq(vi, i, rxq) { 1984 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 1985 rxq->iq.flags |= IQ_RX_TIMESTAMP; 1986 else 1987 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 1988 } 1989 } 1990 1991 #ifdef VLAN_CAPABILITIES 1992 VLAN_CAPABILITIES(ifp); 1993 #endif 1994 fail: 1995 end_synchronized_op(sc, 0); 1996 break; 1997 1998 case SIOCSIFMEDIA: 1999 case SIOCGIFMEDIA: 2000 case SIOCGIFXMEDIA: 2001 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 2002 break; 2003 2004 case SIOCGI2C: { 2005 struct ifi2creq i2c; 2006 2007 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 2008 if (rc != 0) 2009 break; 2010 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 2011 rc = EPERM; 2012 break; 2013 } 2014 if (i2c.len > sizeof(i2c.data)) { 2015 rc = EINVAL; 2016 break; 2017 } 2018 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 2019 if (rc) 2020 return (rc); 2021 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 2022 i2c.offset, i2c.len, &i2c.data[0]); 2023 end_synchronized_op(sc, 0); 2024 if (rc == 0) 2025 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 2026 break; 2027 } 2028 2029 default: 2030 rc = ether_ioctl(ifp, cmd, data); 2031 } 2032 2033 return (rc); 2034 } 2035 2036 static int 2037 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 2038 { 2039 struct vi_info *vi = ifp->if_softc; 2040 struct port_info *pi = vi->pi; 2041 struct adapter *sc = pi->adapter; 2042 struct sge_txq *txq; 2043 void *items[1]; 2044 int rc; 2045 2046 M_ASSERTPKTHDR(m); 2047 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 2048 2049 if (__predict_false(pi->link_cfg.link_ok == false)) { 2050 m_freem(m); 2051 return (ENETDOWN); 2052 } 2053 2054 rc = parse_pkt(sc, &m); 2055 if (__predict_false(rc != 0)) { 2056 MPASS(m == NULL); /* was freed already */ 2057 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 2058 return (rc); 2059 } 2060 #ifdef RATELIMIT 2061 if (m->m_pkthdr.snd_tag != NULL) { 2062 /* EAGAIN tells the stack we are not the correct interface. */ 2063 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) { 2064 m_freem(m); 2065 return (EAGAIN); 2066 } 2067 2068 return (ethofld_transmit(ifp, m)); 2069 } 2070 #endif 2071 2072 /* Select a txq. */ 2073 txq = &sc->sge.txq[vi->first_txq]; 2074 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2075 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 2076 vi->rsrv_noflowq); 2077 2078 items[0] = m; 2079 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 2080 if (__predict_false(rc != 0)) 2081 m_freem(m); 2082 2083 return (rc); 2084 } 2085 2086 static void 2087 cxgbe_qflush(struct ifnet *ifp) 2088 { 2089 struct vi_info *vi = ifp->if_softc; 2090 struct sge_txq *txq; 2091 int i; 2092 2093 /* queues do not exist if !VI_INIT_DONE. */ 2094 if (vi->flags & VI_INIT_DONE) { 2095 for_each_txq(vi, i, txq) { 2096 TXQ_LOCK(txq); 2097 txq->eq.flags |= EQ_QFLUSH; 2098 TXQ_UNLOCK(txq); 2099 while (!mp_ring_is_idle(txq->r)) { 2100 mp_ring_check_drainage(txq->r, 0); 2101 pause("qflush", 1); 2102 } 2103 TXQ_LOCK(txq); 2104 txq->eq.flags &= ~EQ_QFLUSH; 2105 TXQ_UNLOCK(txq); 2106 } 2107 } 2108 if_qflush(ifp); 2109 } 2110 2111 static uint64_t 2112 vi_get_counter(struct ifnet *ifp, ift_counter c) 2113 { 2114 struct vi_info *vi = ifp->if_softc; 2115 struct fw_vi_stats_vf *s = &vi->stats; 2116 2117 vi_refresh_stats(vi->pi->adapter, vi); 2118 2119 switch (c) { 2120 case IFCOUNTER_IPACKETS: 2121 return (s->rx_bcast_frames + s->rx_mcast_frames + 2122 s->rx_ucast_frames); 2123 case IFCOUNTER_IERRORS: 2124 return (s->rx_err_frames); 2125 case IFCOUNTER_OPACKETS: 2126 return (s->tx_bcast_frames + s->tx_mcast_frames + 2127 s->tx_ucast_frames + s->tx_offload_frames); 2128 case IFCOUNTER_OERRORS: 2129 return (s->tx_drop_frames); 2130 case IFCOUNTER_IBYTES: 2131 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2132 s->rx_ucast_bytes); 2133 case IFCOUNTER_OBYTES: 2134 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2135 s->tx_ucast_bytes + s->tx_offload_bytes); 2136 case IFCOUNTER_IMCASTS: 2137 return (s->rx_mcast_frames); 2138 case IFCOUNTER_OMCASTS: 2139 return (s->tx_mcast_frames); 2140 case IFCOUNTER_OQDROPS: { 2141 uint64_t drops; 2142 2143 drops = 0; 2144 if (vi->flags & VI_INIT_DONE) { 2145 int i; 2146 struct sge_txq *txq; 2147 2148 for_each_txq(vi, i, txq) 2149 drops += counter_u64_fetch(txq->r->drops); 2150 } 2151 2152 return (drops); 2153 2154 } 2155 2156 default: 2157 return (if_get_counter_default(ifp, c)); 2158 } 2159 } 2160 2161 uint64_t 2162 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2163 { 2164 struct vi_info *vi = ifp->if_softc; 2165 struct port_info *pi = vi->pi; 2166 struct adapter *sc = pi->adapter; 2167 struct port_stats *s = &pi->stats; 2168 2169 if (pi->nvi > 1 || sc->flags & IS_VF) 2170 return (vi_get_counter(ifp, c)); 2171 2172 cxgbe_refresh_stats(sc, pi); 2173 2174 switch (c) { 2175 case IFCOUNTER_IPACKETS: 2176 return (s->rx_frames); 2177 2178 case IFCOUNTER_IERRORS: 2179 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2180 s->rx_fcs_err + s->rx_len_err); 2181 2182 case IFCOUNTER_OPACKETS: 2183 return (s->tx_frames); 2184 2185 case IFCOUNTER_OERRORS: 2186 return (s->tx_error_frames); 2187 2188 case IFCOUNTER_IBYTES: 2189 return (s->rx_octets); 2190 2191 case IFCOUNTER_OBYTES: 2192 return (s->tx_octets); 2193 2194 case IFCOUNTER_IMCASTS: 2195 return (s->rx_mcast_frames); 2196 2197 case IFCOUNTER_OMCASTS: 2198 return (s->tx_mcast_frames); 2199 2200 case IFCOUNTER_IQDROPS: 2201 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2202 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2203 s->rx_trunc3 + pi->tnl_cong_drops); 2204 2205 case IFCOUNTER_OQDROPS: { 2206 uint64_t drops; 2207 2208 drops = s->tx_drop; 2209 if (vi->flags & VI_INIT_DONE) { 2210 int i; 2211 struct sge_txq *txq; 2212 2213 for_each_txq(vi, i, txq) 2214 drops += counter_u64_fetch(txq->r->drops); 2215 } 2216 2217 return (drops); 2218 2219 } 2220 2221 default: 2222 return (if_get_counter_default(ifp, c)); 2223 } 2224 } 2225 2226 /* 2227 * The kernel picks a media from the list we had provided but we still validate 2228 * the requeste. 2229 */ 2230 int 2231 cxgbe_media_change(struct ifnet *ifp) 2232 { 2233 struct vi_info *vi = ifp->if_softc; 2234 struct port_info *pi = vi->pi; 2235 struct ifmedia *ifm = &pi->media; 2236 struct link_config *lc = &pi->link_cfg; 2237 struct adapter *sc = pi->adapter; 2238 int rc; 2239 2240 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2241 if (rc != 0) 2242 return (rc); 2243 PORT_LOCK(pi); 2244 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2245 /* ifconfig .. media autoselect */ 2246 if (!(lc->supported & FW_PORT_CAP32_ANEG)) { 2247 rc = ENOTSUP; /* AN not supported by transceiver */ 2248 goto done; 2249 } 2250 lc->requested_aneg = AUTONEG_ENABLE; 2251 lc->requested_speed = 0; 2252 lc->requested_fc |= PAUSE_AUTONEG; 2253 } else { 2254 lc->requested_aneg = AUTONEG_DISABLE; 2255 lc->requested_speed = 2256 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2257 lc->requested_fc = 0; 2258 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2259 lc->requested_fc |= PAUSE_RX; 2260 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2261 lc->requested_fc |= PAUSE_TX; 2262 } 2263 if (pi->up_vis > 0) { 2264 fixup_link_config(pi); 2265 rc = apply_link_config(pi); 2266 } 2267 done: 2268 PORT_UNLOCK(pi); 2269 end_synchronized_op(sc, 0); 2270 return (rc); 2271 } 2272 2273 /* 2274 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2275 * given speed. 2276 */ 2277 static int 2278 port_mword(struct port_info *pi, uint32_t speed) 2279 { 2280 2281 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2282 MPASS(powerof2(speed)); 2283 2284 switch(pi->port_type) { 2285 case FW_PORT_TYPE_BT_SGMII: 2286 case FW_PORT_TYPE_BT_XFI: 2287 case FW_PORT_TYPE_BT_XAUI: 2288 /* BaseT */ 2289 switch (speed) { 2290 case FW_PORT_CAP32_SPEED_100M: 2291 return (IFM_100_T); 2292 case FW_PORT_CAP32_SPEED_1G: 2293 return (IFM_1000_T); 2294 case FW_PORT_CAP32_SPEED_10G: 2295 return (IFM_10G_T); 2296 } 2297 break; 2298 case FW_PORT_TYPE_KX4: 2299 if (speed == FW_PORT_CAP32_SPEED_10G) 2300 return (IFM_10G_KX4); 2301 break; 2302 case FW_PORT_TYPE_CX4: 2303 if (speed == FW_PORT_CAP32_SPEED_10G) 2304 return (IFM_10G_CX4); 2305 break; 2306 case FW_PORT_TYPE_KX: 2307 if (speed == FW_PORT_CAP32_SPEED_1G) 2308 return (IFM_1000_KX); 2309 break; 2310 case FW_PORT_TYPE_KR: 2311 case FW_PORT_TYPE_BP_AP: 2312 case FW_PORT_TYPE_BP4_AP: 2313 case FW_PORT_TYPE_BP40_BA: 2314 case FW_PORT_TYPE_KR4_100G: 2315 case FW_PORT_TYPE_KR_SFP28: 2316 case FW_PORT_TYPE_KR_XLAUI: 2317 switch (speed) { 2318 case FW_PORT_CAP32_SPEED_1G: 2319 return (IFM_1000_KX); 2320 case FW_PORT_CAP32_SPEED_10G: 2321 return (IFM_10G_KR); 2322 case FW_PORT_CAP32_SPEED_25G: 2323 return (IFM_25G_KR); 2324 case FW_PORT_CAP32_SPEED_40G: 2325 return (IFM_40G_KR4); 2326 case FW_PORT_CAP32_SPEED_50G: 2327 return (IFM_50G_KR2); 2328 case FW_PORT_CAP32_SPEED_100G: 2329 return (IFM_100G_KR4); 2330 } 2331 break; 2332 case FW_PORT_TYPE_FIBER_XFI: 2333 case FW_PORT_TYPE_FIBER_XAUI: 2334 case FW_PORT_TYPE_SFP: 2335 case FW_PORT_TYPE_QSFP_10G: 2336 case FW_PORT_TYPE_QSA: 2337 case FW_PORT_TYPE_QSFP: 2338 case FW_PORT_TYPE_CR4_QSFP: 2339 case FW_PORT_TYPE_CR_QSFP: 2340 case FW_PORT_TYPE_CR2_QSFP: 2341 case FW_PORT_TYPE_SFP28: 2342 /* Pluggable transceiver */ 2343 switch (pi->mod_type) { 2344 case FW_PORT_MOD_TYPE_LR: 2345 switch (speed) { 2346 case FW_PORT_CAP32_SPEED_1G: 2347 return (IFM_1000_LX); 2348 case FW_PORT_CAP32_SPEED_10G: 2349 return (IFM_10G_LR); 2350 case FW_PORT_CAP32_SPEED_25G: 2351 return (IFM_25G_LR); 2352 case FW_PORT_CAP32_SPEED_40G: 2353 return (IFM_40G_LR4); 2354 case FW_PORT_CAP32_SPEED_50G: 2355 return (IFM_50G_LR2); 2356 case FW_PORT_CAP32_SPEED_100G: 2357 return (IFM_100G_LR4); 2358 } 2359 break; 2360 case FW_PORT_MOD_TYPE_SR: 2361 switch (speed) { 2362 case FW_PORT_CAP32_SPEED_1G: 2363 return (IFM_1000_SX); 2364 case FW_PORT_CAP32_SPEED_10G: 2365 return (IFM_10G_SR); 2366 case FW_PORT_CAP32_SPEED_25G: 2367 return (IFM_25G_SR); 2368 case FW_PORT_CAP32_SPEED_40G: 2369 return (IFM_40G_SR4); 2370 case FW_PORT_CAP32_SPEED_50G: 2371 return (IFM_50G_SR2); 2372 case FW_PORT_CAP32_SPEED_100G: 2373 return (IFM_100G_SR4); 2374 } 2375 break; 2376 case FW_PORT_MOD_TYPE_ER: 2377 if (speed == FW_PORT_CAP32_SPEED_10G) 2378 return (IFM_10G_ER); 2379 break; 2380 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2381 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2382 switch (speed) { 2383 case FW_PORT_CAP32_SPEED_1G: 2384 return (IFM_1000_CX); 2385 case FW_PORT_CAP32_SPEED_10G: 2386 return (IFM_10G_TWINAX); 2387 case FW_PORT_CAP32_SPEED_25G: 2388 return (IFM_25G_CR); 2389 case FW_PORT_CAP32_SPEED_40G: 2390 return (IFM_40G_CR4); 2391 case FW_PORT_CAP32_SPEED_50G: 2392 return (IFM_50G_CR2); 2393 case FW_PORT_CAP32_SPEED_100G: 2394 return (IFM_100G_CR4); 2395 } 2396 break; 2397 case FW_PORT_MOD_TYPE_LRM: 2398 if (speed == FW_PORT_CAP32_SPEED_10G) 2399 return (IFM_10G_LRM); 2400 break; 2401 case FW_PORT_MOD_TYPE_NA: 2402 MPASS(0); /* Not pluggable? */ 2403 /* fall throough */ 2404 case FW_PORT_MOD_TYPE_ERROR: 2405 case FW_PORT_MOD_TYPE_UNKNOWN: 2406 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2407 break; 2408 case FW_PORT_MOD_TYPE_NONE: 2409 return (IFM_NONE); 2410 } 2411 break; 2412 case FW_PORT_TYPE_NONE: 2413 return (IFM_NONE); 2414 } 2415 2416 return (IFM_UNKNOWN); 2417 } 2418 2419 void 2420 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2421 { 2422 struct vi_info *vi = ifp->if_softc; 2423 struct port_info *pi = vi->pi; 2424 struct adapter *sc = pi->adapter; 2425 struct link_config *lc = &pi->link_cfg; 2426 2427 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2428 return; 2429 PORT_LOCK(pi); 2430 2431 if (pi->up_vis == 0) { 2432 /* 2433 * If all the interfaces are administratively down the firmware 2434 * does not report transceiver changes. Refresh port info here 2435 * so that ifconfig displays accurate ifmedia at all times. 2436 * This is the only reason we have a synchronized op in this 2437 * function. Just PORT_LOCK would have been enough otherwise. 2438 */ 2439 t4_update_port_info(pi); 2440 build_medialist(pi); 2441 } 2442 2443 /* ifm_status */ 2444 ifmr->ifm_status = IFM_AVALID; 2445 if (lc->link_ok == false) 2446 goto done; 2447 ifmr->ifm_status |= IFM_ACTIVE; 2448 2449 /* ifm_active */ 2450 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2451 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2452 if (lc->fc & PAUSE_RX) 2453 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2454 if (lc->fc & PAUSE_TX) 2455 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2456 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2457 done: 2458 PORT_UNLOCK(pi); 2459 end_synchronized_op(sc, 0); 2460 } 2461 2462 static int 2463 vcxgbe_probe(device_t dev) 2464 { 2465 char buf[128]; 2466 struct vi_info *vi = device_get_softc(dev); 2467 2468 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2469 vi - vi->pi->vi); 2470 device_set_desc_copy(dev, buf); 2471 2472 return (BUS_PROBE_DEFAULT); 2473 } 2474 2475 static int 2476 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2477 { 2478 int func, index, rc; 2479 uint32_t param, val; 2480 2481 ASSERT_SYNCHRONIZED_OP(sc); 2482 2483 index = vi - pi->vi; 2484 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2485 KASSERT(index < nitems(vi_mac_funcs), 2486 ("%s: VI %s doesn't have a MAC func", __func__, 2487 device_get_nameunit(vi->dev))); 2488 func = vi_mac_funcs[index]; 2489 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2490 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 2491 if (rc < 0) { 2492 device_printf(vi->dev, "failed to allocate virtual interface %d" 2493 "for port %d: %d\n", index, pi->port_id, -rc); 2494 return (-rc); 2495 } 2496 vi->viid = rc; 2497 2498 if (vi->rss_size == 1) { 2499 /* 2500 * This VI didn't get a slice of the RSS table. Reduce the 2501 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2502 * configuration file (nvi, rssnvi for this PF) if this is a 2503 * problem. 2504 */ 2505 device_printf(vi->dev, "RSS table not available.\n"); 2506 vi->rss_base = 0xffff; 2507 2508 return (0); 2509 } 2510 2511 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2512 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2513 V_FW_PARAMS_PARAM_YZ(vi->viid); 2514 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2515 if (rc) 2516 vi->rss_base = 0xffff; 2517 else { 2518 MPASS((val >> 16) == vi->rss_size); 2519 vi->rss_base = val & 0xffff; 2520 } 2521 2522 return (0); 2523 } 2524 2525 static int 2526 vcxgbe_attach(device_t dev) 2527 { 2528 struct vi_info *vi; 2529 struct port_info *pi; 2530 struct adapter *sc; 2531 int rc; 2532 2533 vi = device_get_softc(dev); 2534 pi = vi->pi; 2535 sc = pi->adapter; 2536 2537 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2538 if (rc) 2539 return (rc); 2540 rc = alloc_extra_vi(sc, pi, vi); 2541 end_synchronized_op(sc, 0); 2542 if (rc) 2543 return (rc); 2544 2545 rc = cxgbe_vi_attach(dev, vi); 2546 if (rc) { 2547 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2548 return (rc); 2549 } 2550 return (0); 2551 } 2552 2553 static int 2554 vcxgbe_detach(device_t dev) 2555 { 2556 struct vi_info *vi; 2557 struct adapter *sc; 2558 2559 vi = device_get_softc(dev); 2560 sc = vi->pi->adapter; 2561 2562 doom_vi(sc, vi); 2563 2564 cxgbe_vi_detach(vi); 2565 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2566 2567 end_synchronized_op(sc, 0); 2568 2569 return (0); 2570 } 2571 2572 static struct callout fatal_callout; 2573 2574 static void 2575 delayed_panic(void *arg) 2576 { 2577 struct adapter *sc = arg; 2578 2579 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 2580 } 2581 2582 void 2583 t4_fatal_err(struct adapter *sc, bool fw_error) 2584 { 2585 2586 t4_shutdown_adapter(sc); 2587 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n", 2588 device_get_nameunit(sc->dev)); 2589 if (fw_error) { 2590 ASSERT_SYNCHRONIZED_OP(sc); 2591 sc->flags |= ADAP_ERR; 2592 } else { 2593 ADAPTER_LOCK(sc); 2594 sc->flags |= ADAP_ERR; 2595 ADAPTER_UNLOCK(sc); 2596 } 2597 2598 if (t4_panic_on_fatal_err) { 2599 log(LOG_ALERT, "%s: panic on fatal error after 30s", 2600 device_get_nameunit(sc->dev)); 2601 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 2602 } 2603 } 2604 2605 void 2606 t4_add_adapter(struct adapter *sc) 2607 { 2608 sx_xlock(&t4_list_lock); 2609 SLIST_INSERT_HEAD(&t4_list, sc, link); 2610 sx_xunlock(&t4_list_lock); 2611 } 2612 2613 int 2614 t4_map_bars_0_and_4(struct adapter *sc) 2615 { 2616 sc->regs_rid = PCIR_BAR(0); 2617 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2618 &sc->regs_rid, RF_ACTIVE); 2619 if (sc->regs_res == NULL) { 2620 device_printf(sc->dev, "cannot map registers.\n"); 2621 return (ENXIO); 2622 } 2623 sc->bt = rman_get_bustag(sc->regs_res); 2624 sc->bh = rman_get_bushandle(sc->regs_res); 2625 sc->mmio_len = rman_get_size(sc->regs_res); 2626 setbit(&sc->doorbells, DOORBELL_KDB); 2627 2628 sc->msix_rid = PCIR_BAR(4); 2629 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2630 &sc->msix_rid, RF_ACTIVE); 2631 if (sc->msix_res == NULL) { 2632 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2633 return (ENXIO); 2634 } 2635 2636 return (0); 2637 } 2638 2639 int 2640 t4_map_bar_2(struct adapter *sc) 2641 { 2642 2643 /* 2644 * T4: only iWARP driver uses the userspace doorbells. There is no need 2645 * to map it if RDMA is disabled. 2646 */ 2647 if (is_t4(sc) && sc->rdmacaps == 0) 2648 return (0); 2649 2650 sc->udbs_rid = PCIR_BAR(2); 2651 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2652 &sc->udbs_rid, RF_ACTIVE); 2653 if (sc->udbs_res == NULL) { 2654 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2655 return (ENXIO); 2656 } 2657 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2658 2659 if (chip_id(sc) >= CHELSIO_T5) { 2660 setbit(&sc->doorbells, DOORBELL_UDB); 2661 #if defined(__i386__) || defined(__amd64__) 2662 if (t5_write_combine) { 2663 int rc, mode; 2664 2665 /* 2666 * Enable write combining on BAR2. This is the 2667 * userspace doorbell BAR and is split into 128B 2668 * (UDBS_SEG_SIZE) doorbell regions, each associated 2669 * with an egress queue. The first 64B has the doorbell 2670 * and the second 64B can be used to submit a tx work 2671 * request with an implicit doorbell. 2672 */ 2673 2674 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2675 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2676 if (rc == 0) { 2677 clrbit(&sc->doorbells, DOORBELL_UDB); 2678 setbit(&sc->doorbells, DOORBELL_WCWR); 2679 setbit(&sc->doorbells, DOORBELL_UDBWC); 2680 } else { 2681 device_printf(sc->dev, 2682 "couldn't enable write combining: %d\n", 2683 rc); 2684 } 2685 2686 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2687 t4_write_reg(sc, A_SGE_STAT_CFG, 2688 V_STATSOURCE_T5(7) | mode); 2689 } 2690 #endif 2691 } 2692 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2693 2694 return (0); 2695 } 2696 2697 struct memwin_init { 2698 uint32_t base; 2699 uint32_t aperture; 2700 }; 2701 2702 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2703 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2704 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2705 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2706 }; 2707 2708 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2709 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2710 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2711 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2712 }; 2713 2714 static void 2715 setup_memwin(struct adapter *sc) 2716 { 2717 const struct memwin_init *mw_init; 2718 struct memwin *mw; 2719 int i; 2720 uint32_t bar0; 2721 2722 if (is_t4(sc)) { 2723 /* 2724 * Read low 32b of bar0 indirectly via the hardware backdoor 2725 * mechanism. Works from within PCI passthrough environments 2726 * too, where rman_get_start() can return a different value. We 2727 * need to program the T4 memory window decoders with the actual 2728 * addresses that will be coming across the PCIe link. 2729 */ 2730 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2731 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2732 2733 mw_init = &t4_memwin[0]; 2734 } else { 2735 /* T5+ use the relative offset inside the PCIe BAR */ 2736 bar0 = 0; 2737 2738 mw_init = &t5_memwin[0]; 2739 } 2740 2741 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2742 rw_init(&mw->mw_lock, "memory window access"); 2743 mw->mw_base = mw_init->base; 2744 mw->mw_aperture = mw_init->aperture; 2745 mw->mw_curpos = 0; 2746 t4_write_reg(sc, 2747 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2748 (mw->mw_base + bar0) | V_BIR(0) | 2749 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2750 rw_wlock(&mw->mw_lock); 2751 position_memwin(sc, i, 0); 2752 rw_wunlock(&mw->mw_lock); 2753 } 2754 2755 /* flush */ 2756 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2757 } 2758 2759 /* 2760 * Positions the memory window at the given address in the card's address space. 2761 * There are some alignment requirements and the actual position may be at an 2762 * address prior to the requested address. mw->mw_curpos always has the actual 2763 * position of the window. 2764 */ 2765 static void 2766 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2767 { 2768 struct memwin *mw; 2769 uint32_t pf; 2770 uint32_t reg; 2771 2772 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2773 mw = &sc->memwin[idx]; 2774 rw_assert(&mw->mw_lock, RA_WLOCKED); 2775 2776 if (is_t4(sc)) { 2777 pf = 0; 2778 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2779 } else { 2780 pf = V_PFNUM(sc->pf); 2781 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2782 } 2783 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2784 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2785 t4_read_reg(sc, reg); /* flush */ 2786 } 2787 2788 int 2789 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2790 int len, int rw) 2791 { 2792 struct memwin *mw; 2793 uint32_t mw_end, v; 2794 2795 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2796 2797 /* Memory can only be accessed in naturally aligned 4 byte units */ 2798 if (addr & 3 || len & 3 || len <= 0) 2799 return (EINVAL); 2800 2801 mw = &sc->memwin[idx]; 2802 while (len > 0) { 2803 rw_rlock(&mw->mw_lock); 2804 mw_end = mw->mw_curpos + mw->mw_aperture; 2805 if (addr >= mw_end || addr < mw->mw_curpos) { 2806 /* Will need to reposition the window */ 2807 if (!rw_try_upgrade(&mw->mw_lock)) { 2808 rw_runlock(&mw->mw_lock); 2809 rw_wlock(&mw->mw_lock); 2810 } 2811 rw_assert(&mw->mw_lock, RA_WLOCKED); 2812 position_memwin(sc, idx, addr); 2813 rw_downgrade(&mw->mw_lock); 2814 mw_end = mw->mw_curpos + mw->mw_aperture; 2815 } 2816 rw_assert(&mw->mw_lock, RA_RLOCKED); 2817 while (addr < mw_end && len > 0) { 2818 if (rw == 0) { 2819 v = t4_read_reg(sc, mw->mw_base + addr - 2820 mw->mw_curpos); 2821 *val++ = le32toh(v); 2822 } else { 2823 v = *val++; 2824 t4_write_reg(sc, mw->mw_base + addr - 2825 mw->mw_curpos, htole32(v)); 2826 } 2827 addr += 4; 2828 len -= 4; 2829 } 2830 rw_runlock(&mw->mw_lock); 2831 } 2832 2833 return (0); 2834 } 2835 2836 int 2837 alloc_atid_tab(struct tid_info *t, int flags) 2838 { 2839 int i; 2840 2841 MPASS(t->natids > 0); 2842 MPASS(t->atid_tab == NULL); 2843 2844 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2845 M_ZERO | flags); 2846 if (t->atid_tab == NULL) 2847 return (ENOMEM); 2848 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2849 t->afree = t->atid_tab; 2850 t->atids_in_use = 0; 2851 for (i = 1; i < t->natids; i++) 2852 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2853 t->atid_tab[t->natids - 1].next = NULL; 2854 2855 return (0); 2856 } 2857 2858 void 2859 free_atid_tab(struct tid_info *t) 2860 { 2861 2862 KASSERT(t->atids_in_use == 0, 2863 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2864 2865 if (mtx_initialized(&t->atid_lock)) 2866 mtx_destroy(&t->atid_lock); 2867 free(t->atid_tab, M_CXGBE); 2868 t->atid_tab = NULL; 2869 } 2870 2871 int 2872 alloc_atid(struct adapter *sc, void *ctx) 2873 { 2874 struct tid_info *t = &sc->tids; 2875 int atid = -1; 2876 2877 mtx_lock(&t->atid_lock); 2878 if (t->afree) { 2879 union aopen_entry *p = t->afree; 2880 2881 atid = p - t->atid_tab; 2882 MPASS(atid <= M_TID_TID); 2883 t->afree = p->next; 2884 p->data = ctx; 2885 t->atids_in_use++; 2886 } 2887 mtx_unlock(&t->atid_lock); 2888 return (atid); 2889 } 2890 2891 void * 2892 lookup_atid(struct adapter *sc, int atid) 2893 { 2894 struct tid_info *t = &sc->tids; 2895 2896 return (t->atid_tab[atid].data); 2897 } 2898 2899 void 2900 free_atid(struct adapter *sc, int atid) 2901 { 2902 struct tid_info *t = &sc->tids; 2903 union aopen_entry *p = &t->atid_tab[atid]; 2904 2905 mtx_lock(&t->atid_lock); 2906 p->next = t->afree; 2907 t->afree = p; 2908 t->atids_in_use--; 2909 mtx_unlock(&t->atid_lock); 2910 } 2911 2912 static void 2913 queue_tid_release(struct adapter *sc, int tid) 2914 { 2915 2916 CXGBE_UNIMPLEMENTED("deferred tid release"); 2917 } 2918 2919 void 2920 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2921 { 2922 struct wrqe *wr; 2923 struct cpl_tid_release *req; 2924 2925 wr = alloc_wrqe(sizeof(*req), ctrlq); 2926 if (wr == NULL) { 2927 queue_tid_release(sc, tid); /* defer */ 2928 return; 2929 } 2930 req = wrtod(wr); 2931 2932 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2933 2934 t4_wrq_tx(sc, wr); 2935 } 2936 2937 static int 2938 t4_range_cmp(const void *a, const void *b) 2939 { 2940 return ((const struct t4_range *)a)->start - 2941 ((const struct t4_range *)b)->start; 2942 } 2943 2944 /* 2945 * Verify that the memory range specified by the addr/len pair is valid within 2946 * the card's address space. 2947 */ 2948 static int 2949 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 2950 { 2951 struct t4_range mem_ranges[4], *r, *next; 2952 uint32_t em, addr_len; 2953 int i, n, remaining; 2954 2955 /* Memory can only be accessed in naturally aligned 4 byte units */ 2956 if (addr & 3 || len & 3 || len == 0) 2957 return (EINVAL); 2958 2959 /* Enabled memories */ 2960 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2961 2962 r = &mem_ranges[0]; 2963 n = 0; 2964 bzero(r, sizeof(mem_ranges)); 2965 if (em & F_EDRAM0_ENABLE) { 2966 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2967 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2968 if (r->size > 0) { 2969 r->start = G_EDRAM0_BASE(addr_len) << 20; 2970 if (addr >= r->start && 2971 addr + len <= r->start + r->size) 2972 return (0); 2973 r++; 2974 n++; 2975 } 2976 } 2977 if (em & F_EDRAM1_ENABLE) { 2978 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2979 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2980 if (r->size > 0) { 2981 r->start = G_EDRAM1_BASE(addr_len) << 20; 2982 if (addr >= r->start && 2983 addr + len <= r->start + r->size) 2984 return (0); 2985 r++; 2986 n++; 2987 } 2988 } 2989 if (em & F_EXT_MEM_ENABLE) { 2990 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2991 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2992 if (r->size > 0) { 2993 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2994 if (addr >= r->start && 2995 addr + len <= r->start + r->size) 2996 return (0); 2997 r++; 2998 n++; 2999 } 3000 } 3001 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 3002 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3003 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 3004 if (r->size > 0) { 3005 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 3006 if (addr >= r->start && 3007 addr + len <= r->start + r->size) 3008 return (0); 3009 r++; 3010 n++; 3011 } 3012 } 3013 MPASS(n <= nitems(mem_ranges)); 3014 3015 if (n > 1) { 3016 /* Sort and merge the ranges. */ 3017 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 3018 3019 /* Start from index 0 and examine the next n - 1 entries. */ 3020 r = &mem_ranges[0]; 3021 for (remaining = n - 1; remaining > 0; remaining--, r++) { 3022 3023 MPASS(r->size > 0); /* r is a valid entry. */ 3024 next = r + 1; 3025 MPASS(next->size > 0); /* and so is the next one. */ 3026 3027 while (r->start + r->size >= next->start) { 3028 /* Merge the next one into the current entry. */ 3029 r->size = max(r->start + r->size, 3030 next->start + next->size) - r->start; 3031 n--; /* One fewer entry in total. */ 3032 if (--remaining == 0) 3033 goto done; /* short circuit */ 3034 next++; 3035 } 3036 if (next != r + 1) { 3037 /* 3038 * Some entries were merged into r and next 3039 * points to the first valid entry that couldn't 3040 * be merged. 3041 */ 3042 MPASS(next->size > 0); /* must be valid */ 3043 memcpy(r + 1, next, remaining * sizeof(*r)); 3044 #ifdef INVARIANTS 3045 /* 3046 * This so that the foo->size assertion in the 3047 * next iteration of the loop do the right 3048 * thing for entries that were pulled up and are 3049 * no longer valid. 3050 */ 3051 MPASS(n < nitems(mem_ranges)); 3052 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 3053 sizeof(struct t4_range)); 3054 #endif 3055 } 3056 } 3057 done: 3058 /* Done merging the ranges. */ 3059 MPASS(n > 0); 3060 r = &mem_ranges[0]; 3061 for (i = 0; i < n; i++, r++) { 3062 if (addr >= r->start && 3063 addr + len <= r->start + r->size) 3064 return (0); 3065 } 3066 } 3067 3068 return (EFAULT); 3069 } 3070 3071 static int 3072 fwmtype_to_hwmtype(int mtype) 3073 { 3074 3075 switch (mtype) { 3076 case FW_MEMTYPE_EDC0: 3077 return (MEM_EDC0); 3078 case FW_MEMTYPE_EDC1: 3079 return (MEM_EDC1); 3080 case FW_MEMTYPE_EXTMEM: 3081 return (MEM_MC0); 3082 case FW_MEMTYPE_EXTMEM1: 3083 return (MEM_MC1); 3084 default: 3085 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 3086 } 3087 } 3088 3089 /* 3090 * Verify that the memory range specified by the memtype/offset/len pair is 3091 * valid and lies entirely within the memtype specified. The global address of 3092 * the start of the range is returned in addr. 3093 */ 3094 static int 3095 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3096 uint32_t *addr) 3097 { 3098 uint32_t em, addr_len, maddr; 3099 3100 /* Memory can only be accessed in naturally aligned 4 byte units */ 3101 if (off & 3 || len & 3 || len == 0) 3102 return (EINVAL); 3103 3104 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3105 switch (fwmtype_to_hwmtype(mtype)) { 3106 case MEM_EDC0: 3107 if (!(em & F_EDRAM0_ENABLE)) 3108 return (EINVAL); 3109 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3110 maddr = G_EDRAM0_BASE(addr_len) << 20; 3111 break; 3112 case MEM_EDC1: 3113 if (!(em & F_EDRAM1_ENABLE)) 3114 return (EINVAL); 3115 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3116 maddr = G_EDRAM1_BASE(addr_len) << 20; 3117 break; 3118 case MEM_MC: 3119 if (!(em & F_EXT_MEM_ENABLE)) 3120 return (EINVAL); 3121 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3122 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3123 break; 3124 case MEM_MC1: 3125 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3126 return (EINVAL); 3127 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3128 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3129 break; 3130 default: 3131 return (EINVAL); 3132 } 3133 3134 *addr = maddr + off; /* global address */ 3135 return (validate_mem_range(sc, *addr, len)); 3136 } 3137 3138 static int 3139 fixup_devlog_params(struct adapter *sc) 3140 { 3141 struct devlog_params *dparams = &sc->params.devlog; 3142 int rc; 3143 3144 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3145 dparams->size, &dparams->addr); 3146 3147 return (rc); 3148 } 3149 3150 static void 3151 update_nirq(struct intrs_and_queues *iaq, int nports) 3152 { 3153 int extra = T4_EXTRA_INTR; 3154 3155 iaq->nirq = extra; 3156 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 3157 iaq->nirq += nports * (iaq->num_vis - 1) * 3158 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3159 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3160 } 3161 3162 /* 3163 * Adjust requirements to fit the number of interrupts available. 3164 */ 3165 static void 3166 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3167 int navail) 3168 { 3169 int old_nirq; 3170 const int nports = sc->params.nports; 3171 3172 MPASS(nports > 0); 3173 MPASS(navail > 0); 3174 3175 bzero(iaq, sizeof(*iaq)); 3176 iaq->intr_type = itype; 3177 iaq->num_vis = t4_num_vis; 3178 iaq->ntxq = t4_ntxq; 3179 iaq->ntxq_vi = t4_ntxq_vi; 3180 iaq->nrxq = t4_nrxq; 3181 iaq->nrxq_vi = t4_nrxq_vi; 3182 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3183 if (is_offload(sc) || is_ethoffload(sc)) { 3184 iaq->nofldtxq = t4_nofldtxq; 3185 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3186 } 3187 #endif 3188 #ifdef TCP_OFFLOAD 3189 if (is_offload(sc)) { 3190 iaq->nofldrxq = t4_nofldrxq; 3191 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3192 } 3193 #endif 3194 #ifdef DEV_NETMAP 3195 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3196 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3197 #endif 3198 3199 update_nirq(iaq, nports); 3200 if (iaq->nirq <= navail && 3201 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3202 /* 3203 * This is the normal case -- there are enough interrupts for 3204 * everything. 3205 */ 3206 goto done; 3207 } 3208 3209 /* 3210 * If extra VIs have been configured try reducing their count and see if 3211 * that works. 3212 */ 3213 while (iaq->num_vis > 1) { 3214 iaq->num_vis--; 3215 update_nirq(iaq, nports); 3216 if (iaq->nirq <= navail && 3217 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3218 device_printf(sc->dev, "virtual interfaces per port " 3219 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3220 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3221 "itype %d, navail %u, nirq %d.\n", 3222 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3223 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3224 itype, navail, iaq->nirq); 3225 goto done; 3226 } 3227 } 3228 3229 /* 3230 * Extra VIs will not be created. Log a message if they were requested. 3231 */ 3232 MPASS(iaq->num_vis == 1); 3233 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3234 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3235 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3236 if (iaq->num_vis != t4_num_vis) { 3237 device_printf(sc->dev, "extra virtual interfaces disabled. " 3238 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3239 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3240 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3241 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3242 } 3243 3244 /* 3245 * Keep reducing the number of NIC rx queues to the next lower power of 3246 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3247 * if that works. 3248 */ 3249 do { 3250 if (iaq->nrxq > 1) { 3251 do { 3252 iaq->nrxq--; 3253 } while (!powerof2(iaq->nrxq)); 3254 } 3255 if (iaq->nofldrxq > 1) 3256 iaq->nofldrxq >>= 1; 3257 3258 old_nirq = iaq->nirq; 3259 update_nirq(iaq, nports); 3260 if (iaq->nirq <= navail && 3261 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3262 device_printf(sc->dev, "running with reduced number of " 3263 "rx queues because of shortage of interrupts. " 3264 "nrxq=%u, nofldrxq=%u. " 3265 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3266 iaq->nofldrxq, itype, navail, iaq->nirq); 3267 goto done; 3268 } 3269 } while (old_nirq != iaq->nirq); 3270 3271 /* One interrupt for everything. Ugh. */ 3272 device_printf(sc->dev, "running with minimal number of queues. " 3273 "itype %d, navail %u.\n", itype, navail); 3274 iaq->nirq = 1; 3275 MPASS(iaq->nrxq == 1); 3276 iaq->ntxq = 1; 3277 if (iaq->nofldrxq > 1) 3278 iaq->nofldtxq = 1; 3279 done: 3280 MPASS(iaq->num_vis > 0); 3281 if (iaq->num_vis > 1) { 3282 MPASS(iaq->nrxq_vi > 0); 3283 MPASS(iaq->ntxq_vi > 0); 3284 } 3285 MPASS(iaq->nirq > 0); 3286 MPASS(iaq->nrxq > 0); 3287 MPASS(iaq->ntxq > 0); 3288 if (itype == INTR_MSI) { 3289 MPASS(powerof2(iaq->nirq)); 3290 } 3291 } 3292 3293 static int 3294 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3295 { 3296 int rc, itype, navail, nalloc; 3297 3298 for (itype = INTR_MSIX; itype; itype >>= 1) { 3299 3300 if ((itype & t4_intr_types) == 0) 3301 continue; /* not allowed */ 3302 3303 if (itype == INTR_MSIX) 3304 navail = pci_msix_count(sc->dev); 3305 else if (itype == INTR_MSI) 3306 navail = pci_msi_count(sc->dev); 3307 else 3308 navail = 1; 3309 restart: 3310 if (navail == 0) 3311 continue; 3312 3313 calculate_iaq(sc, iaq, itype, navail); 3314 nalloc = iaq->nirq; 3315 rc = 0; 3316 if (itype == INTR_MSIX) 3317 rc = pci_alloc_msix(sc->dev, &nalloc); 3318 else if (itype == INTR_MSI) 3319 rc = pci_alloc_msi(sc->dev, &nalloc); 3320 3321 if (rc == 0 && nalloc > 0) { 3322 if (nalloc == iaq->nirq) 3323 return (0); 3324 3325 /* 3326 * Didn't get the number requested. Use whatever number 3327 * the kernel is willing to allocate. 3328 */ 3329 device_printf(sc->dev, "fewer vectors than requested, " 3330 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3331 itype, iaq->nirq, nalloc); 3332 pci_release_msi(sc->dev); 3333 navail = nalloc; 3334 goto restart; 3335 } 3336 3337 device_printf(sc->dev, 3338 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3339 itype, rc, iaq->nirq, nalloc); 3340 } 3341 3342 device_printf(sc->dev, 3343 "failed to find a usable interrupt type. " 3344 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3345 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3346 3347 return (ENXIO); 3348 } 3349 3350 #define FW_VERSION(chip) ( \ 3351 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3352 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3353 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3354 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3355 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3356 3357 /* Just enough of fw_hdr to cover all version info. */ 3358 struct fw_h { 3359 __u8 ver; 3360 __u8 chip; 3361 __be16 len512; 3362 __be32 fw_ver; 3363 __be32 tp_microcode_ver; 3364 __u8 intfver_nic; 3365 __u8 intfver_vnic; 3366 __u8 intfver_ofld; 3367 __u8 intfver_ri; 3368 __u8 intfver_iscsipdu; 3369 __u8 intfver_iscsi; 3370 __u8 intfver_fcoepdu; 3371 __u8 intfver_fcoe; 3372 }; 3373 /* Spot check a couple of fields. */ 3374 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 3375 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 3376 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 3377 3378 struct fw_info { 3379 uint8_t chip; 3380 char *kld_name; 3381 char *fw_mod_name; 3382 struct fw_h fw_h; 3383 } fw_info[] = { 3384 { 3385 .chip = CHELSIO_T4, 3386 .kld_name = "t4fw_cfg", 3387 .fw_mod_name = "t4fw", 3388 .fw_h = { 3389 .chip = FW_HDR_CHIP_T4, 3390 .fw_ver = htobe32(FW_VERSION(T4)), 3391 .intfver_nic = FW_INTFVER(T4, NIC), 3392 .intfver_vnic = FW_INTFVER(T4, VNIC), 3393 .intfver_ofld = FW_INTFVER(T4, OFLD), 3394 .intfver_ri = FW_INTFVER(T4, RI), 3395 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3396 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3397 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3398 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3399 }, 3400 }, { 3401 .chip = CHELSIO_T5, 3402 .kld_name = "t5fw_cfg", 3403 .fw_mod_name = "t5fw", 3404 .fw_h = { 3405 .chip = FW_HDR_CHIP_T5, 3406 .fw_ver = htobe32(FW_VERSION(T5)), 3407 .intfver_nic = FW_INTFVER(T5, NIC), 3408 .intfver_vnic = FW_INTFVER(T5, VNIC), 3409 .intfver_ofld = FW_INTFVER(T5, OFLD), 3410 .intfver_ri = FW_INTFVER(T5, RI), 3411 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3412 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3413 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3414 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3415 }, 3416 }, { 3417 .chip = CHELSIO_T6, 3418 .kld_name = "t6fw_cfg", 3419 .fw_mod_name = "t6fw", 3420 .fw_h = { 3421 .chip = FW_HDR_CHIP_T6, 3422 .fw_ver = htobe32(FW_VERSION(T6)), 3423 .intfver_nic = FW_INTFVER(T6, NIC), 3424 .intfver_vnic = FW_INTFVER(T6, VNIC), 3425 .intfver_ofld = FW_INTFVER(T6, OFLD), 3426 .intfver_ri = FW_INTFVER(T6, RI), 3427 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3428 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3429 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3430 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3431 }, 3432 } 3433 }; 3434 3435 static struct fw_info * 3436 find_fw_info(int chip) 3437 { 3438 int i; 3439 3440 for (i = 0; i < nitems(fw_info); i++) { 3441 if (fw_info[i].chip == chip) 3442 return (&fw_info[i]); 3443 } 3444 return (NULL); 3445 } 3446 3447 /* 3448 * Is the given firmware API compatible with the one the driver was compiled 3449 * with? 3450 */ 3451 static int 3452 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 3453 { 3454 3455 /* short circuit if it's the exact same firmware version */ 3456 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3457 return (1); 3458 3459 /* 3460 * XXX: Is this too conservative? Perhaps I should limit this to the 3461 * features that are supported in the driver. 3462 */ 3463 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3464 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3465 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3466 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3467 return (1); 3468 #undef SAME_INTF 3469 3470 return (0); 3471 } 3472 3473 static int 3474 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 3475 const struct firmware **fw) 3476 { 3477 struct fw_info *fw_info; 3478 3479 *dcfg = NULL; 3480 if (fw != NULL) 3481 *fw = NULL; 3482 3483 fw_info = find_fw_info(chip_id(sc)); 3484 if (fw_info == NULL) { 3485 device_printf(sc->dev, 3486 "unable to look up firmware information for chip %d.\n", 3487 chip_id(sc)); 3488 return (EINVAL); 3489 } 3490 3491 *dcfg = firmware_get(fw_info->kld_name); 3492 if (*dcfg != NULL) { 3493 if (fw != NULL) 3494 *fw = firmware_get(fw_info->fw_mod_name); 3495 return (0); 3496 } 3497 3498 return (ENOENT); 3499 } 3500 3501 static void 3502 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 3503 const struct firmware *fw) 3504 { 3505 3506 if (fw != NULL) 3507 firmware_put(fw, FIRMWARE_UNLOAD); 3508 if (dcfg != NULL) 3509 firmware_put(dcfg, FIRMWARE_UNLOAD); 3510 } 3511 3512 /* 3513 * Return values: 3514 * 0 means no firmware install attempted. 3515 * ERESTART means a firmware install was attempted and was successful. 3516 * +ve errno means a firmware install was attempted but failed. 3517 */ 3518 static int 3519 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 3520 const struct fw_h *drv_fw, const char *reason, int *already) 3521 { 3522 const struct firmware *cfg, *fw; 3523 const uint32_t c = be32toh(card_fw->fw_ver); 3524 uint32_t d, k; 3525 int rc, fw_install; 3526 struct fw_h bundled_fw; 3527 bool load_attempted; 3528 3529 cfg = fw = NULL; 3530 load_attempted = false; 3531 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 3532 3533 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 3534 if (t4_fw_install < 0) { 3535 rc = load_fw_module(sc, &cfg, &fw); 3536 if (rc != 0 || fw == NULL) { 3537 device_printf(sc->dev, 3538 "failed to load firmware module: %d. cfg %p, fw %p;" 3539 " will use compiled-in firmware version for" 3540 "hw.cxgbe.fw_install checks.\n", 3541 rc, cfg, fw); 3542 } else { 3543 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 3544 } 3545 load_attempted = true; 3546 } 3547 d = be32toh(bundled_fw.fw_ver); 3548 3549 if (reason != NULL) 3550 goto install; 3551 3552 if ((sc->flags & FW_OK) == 0) { 3553 3554 if (c == 0xffffffff) { 3555 reason = "missing"; 3556 goto install; 3557 } 3558 3559 rc = 0; 3560 goto done; 3561 } 3562 3563 if (!fw_compatible(card_fw, &bundled_fw)) { 3564 reason = "incompatible or unusable"; 3565 goto install; 3566 } 3567 3568 if (d > c) { 3569 reason = "older than the version bundled with this driver"; 3570 goto install; 3571 } 3572 3573 if (fw_install == 2 && d != c) { 3574 reason = "different than the version bundled with this driver"; 3575 goto install; 3576 } 3577 3578 /* No reason to do anything to the firmware already on the card. */ 3579 rc = 0; 3580 goto done; 3581 3582 install: 3583 rc = 0; 3584 if ((*already)++) 3585 goto done; 3586 3587 if (fw_install == 0) { 3588 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3589 "but the driver is prohibited from installing a firmware " 3590 "on the card.\n", 3591 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3592 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3593 3594 goto done; 3595 } 3596 3597 /* 3598 * We'll attempt to install a firmware. Load the module first (if it 3599 * hasn't been loaded already). 3600 */ 3601 if (!load_attempted) { 3602 rc = load_fw_module(sc, &cfg, &fw); 3603 if (rc != 0 || fw == NULL) { 3604 device_printf(sc->dev, 3605 "failed to load firmware module: %d. cfg %p, fw %p\n", 3606 rc, cfg, fw); 3607 /* carry on */ 3608 } 3609 } 3610 if (fw == NULL) { 3611 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3612 "but the driver cannot take corrective action because it " 3613 "is unable to load the firmware module.\n", 3614 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3615 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3616 rc = sc->flags & FW_OK ? 0 : ENOENT; 3617 goto done; 3618 } 3619 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 3620 if (k != d) { 3621 MPASS(t4_fw_install > 0); 3622 device_printf(sc->dev, 3623 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 3624 "expecting (%u.%u.%u.%u) and will not be used.\n", 3625 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3626 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 3627 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3628 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3629 rc = sc->flags & FW_OK ? 0 : EINVAL; 3630 goto done; 3631 } 3632 3633 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3634 "installing firmware %u.%u.%u.%u on card.\n", 3635 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3636 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3637 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3638 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3639 3640 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3641 if (rc != 0) { 3642 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 3643 } else { 3644 /* Installed successfully, update the cached header too. */ 3645 rc = ERESTART; 3646 memcpy(card_fw, fw->data, sizeof(*card_fw)); 3647 } 3648 done: 3649 unload_fw_module(sc, cfg, fw); 3650 3651 return (rc); 3652 } 3653 3654 /* 3655 * Establish contact with the firmware and attempt to become the master driver. 3656 * 3657 * A firmware will be installed to the card if needed (if the driver is allowed 3658 * to do so). 3659 */ 3660 static int 3661 contact_firmware(struct adapter *sc) 3662 { 3663 int rc, already = 0; 3664 enum dev_state state; 3665 struct fw_info *fw_info; 3666 struct fw_hdr *card_fw; /* fw on the card */ 3667 const struct fw_h *drv_fw; 3668 3669 fw_info = find_fw_info(chip_id(sc)); 3670 if (fw_info == NULL) { 3671 device_printf(sc->dev, 3672 "unable to look up firmware information for chip %d.\n", 3673 chip_id(sc)); 3674 return (EINVAL); 3675 } 3676 drv_fw = &fw_info->fw_h; 3677 3678 /* Read the header of the firmware on the card */ 3679 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3680 restart: 3681 rc = -t4_get_fw_hdr(sc, card_fw); 3682 if (rc != 0) { 3683 device_printf(sc->dev, 3684 "unable to read firmware header from card's flash: %d\n", 3685 rc); 3686 goto done; 3687 } 3688 3689 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 3690 &already); 3691 if (rc == ERESTART) 3692 goto restart; 3693 if (rc != 0) 3694 goto done; 3695 3696 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3697 if (rc < 0 || state == DEV_STATE_ERR) { 3698 rc = -rc; 3699 device_printf(sc->dev, 3700 "failed to connect to the firmware: %d, %d. " 3701 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3702 #if 0 3703 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3704 "not responding properly to HELLO", &already) == ERESTART) 3705 goto restart; 3706 #endif 3707 goto done; 3708 } 3709 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 3710 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 3711 3712 if (rc == sc->pf) { 3713 sc->flags |= MASTER_PF; 3714 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3715 NULL, &already); 3716 if (rc == ERESTART) 3717 rc = 0; 3718 else if (rc != 0) 3719 goto done; 3720 } else if (state == DEV_STATE_UNINIT) { 3721 /* 3722 * We didn't get to be the master so we definitely won't be 3723 * configuring the chip. It's a bug if someone else hasn't 3724 * configured it already. 3725 */ 3726 device_printf(sc->dev, "couldn't be master(%d), " 3727 "device not already initialized either(%d). " 3728 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3729 rc = EPROTO; 3730 goto done; 3731 } else { 3732 /* 3733 * Some other PF is the master and has configured the chip. 3734 * This is allowed but untested. 3735 */ 3736 device_printf(sc->dev, "PF%d is master, device state %d. " 3737 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3738 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 3739 sc->cfcsum = 0; 3740 rc = 0; 3741 } 3742 done: 3743 if (rc != 0 && sc->flags & FW_OK) { 3744 t4_fw_bye(sc, sc->mbox); 3745 sc->flags &= ~FW_OK; 3746 } 3747 free(card_fw, M_CXGBE); 3748 return (rc); 3749 } 3750 3751 static int 3752 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 3753 uint32_t mtype, uint32_t moff) 3754 { 3755 struct fw_info *fw_info; 3756 const struct firmware *dcfg, *rcfg = NULL; 3757 const uint32_t *cfdata; 3758 uint32_t cflen, addr; 3759 int rc; 3760 3761 load_fw_module(sc, &dcfg, NULL); 3762 3763 /* Card specific interpretation of "default". */ 3764 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3765 if (pci_get_device(sc->dev) == 0x440a) 3766 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 3767 if (is_fpga(sc)) 3768 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 3769 } 3770 3771 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3772 if (dcfg == NULL) { 3773 device_printf(sc->dev, 3774 "KLD with default config is not available.\n"); 3775 rc = ENOENT; 3776 goto done; 3777 } 3778 cfdata = dcfg->data; 3779 cflen = dcfg->datasize & ~3; 3780 } else { 3781 char s[32]; 3782 3783 fw_info = find_fw_info(chip_id(sc)); 3784 if (fw_info == NULL) { 3785 device_printf(sc->dev, 3786 "unable to look up firmware information for chip %d.\n", 3787 chip_id(sc)); 3788 rc = EINVAL; 3789 goto done; 3790 } 3791 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 3792 3793 rcfg = firmware_get(s); 3794 if (rcfg == NULL) { 3795 device_printf(sc->dev, 3796 "unable to load module \"%s\" for configuration " 3797 "profile \"%s\".\n", s, cfg_file); 3798 rc = ENOENT; 3799 goto done; 3800 } 3801 cfdata = rcfg->data; 3802 cflen = rcfg->datasize & ~3; 3803 } 3804 3805 if (cflen > FLASH_CFG_MAX_SIZE) { 3806 device_printf(sc->dev, 3807 "config file too long (%d, max allowed is %d).\n", 3808 cflen, FLASH_CFG_MAX_SIZE); 3809 rc = EINVAL; 3810 goto done; 3811 } 3812 3813 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3814 if (rc != 0) { 3815 device_printf(sc->dev, 3816 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 3817 __func__, mtype, moff, cflen, rc); 3818 rc = EINVAL; 3819 goto done; 3820 } 3821 write_via_memwin(sc, 2, addr, cfdata, cflen); 3822 done: 3823 if (rcfg != NULL) 3824 firmware_put(rcfg, FIRMWARE_UNLOAD); 3825 unload_fw_module(sc, dcfg, NULL); 3826 return (rc); 3827 } 3828 3829 struct caps_allowed { 3830 uint16_t nbmcaps; 3831 uint16_t linkcaps; 3832 uint16_t switchcaps; 3833 uint16_t niccaps; 3834 uint16_t toecaps; 3835 uint16_t rdmacaps; 3836 uint16_t cryptocaps; 3837 uint16_t iscsicaps; 3838 uint16_t fcoecaps; 3839 }; 3840 3841 #define FW_PARAM_DEV(param) \ 3842 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3843 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3844 #define FW_PARAM_PFVF(param) \ 3845 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3846 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3847 3848 /* 3849 * Provide a configuration profile to the firmware and have it initialize the 3850 * chip accordingly. This may involve uploading a configuration file to the 3851 * card. 3852 */ 3853 static int 3854 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 3855 const struct caps_allowed *caps_allowed) 3856 { 3857 int rc; 3858 struct fw_caps_config_cmd caps; 3859 uint32_t mtype, moff, finicsum, cfcsum, param, val; 3860 3861 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3862 if (rc != 0) { 3863 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3864 return (rc); 3865 } 3866 3867 bzero(&caps, sizeof(caps)); 3868 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3869 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3870 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 3871 mtype = 0; 3872 moff = 0; 3873 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3874 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 3875 mtype = FW_MEMTYPE_FLASH; 3876 moff = t4_flash_cfg_addr(sc); 3877 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3878 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3879 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3880 FW_LEN16(caps)); 3881 } else { 3882 /* 3883 * Ask the firmware where it wants us to upload the config file. 3884 */ 3885 param = FW_PARAM_DEV(CF); 3886 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3887 if (rc != 0) { 3888 /* No support for config file? Shouldn't happen. */ 3889 device_printf(sc->dev, 3890 "failed to query config file location: %d.\n", rc); 3891 goto done; 3892 } 3893 mtype = G_FW_PARAMS_PARAM_Y(val); 3894 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3895 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3896 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3897 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3898 FW_LEN16(caps)); 3899 3900 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 3901 if (rc != 0) { 3902 device_printf(sc->dev, 3903 "failed to upload config file to card: %d.\n", rc); 3904 goto done; 3905 } 3906 } 3907 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3908 if (rc != 0) { 3909 device_printf(sc->dev, "failed to pre-process config file: %d " 3910 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3911 goto done; 3912 } 3913 3914 finicsum = be32toh(caps.finicsum); 3915 cfcsum = be32toh(caps.cfcsum); /* actual */ 3916 if (finicsum != cfcsum) { 3917 device_printf(sc->dev, 3918 "WARNING: config file checksum mismatch: %08x %08x\n", 3919 finicsum, cfcsum); 3920 } 3921 sc->cfcsum = cfcsum; 3922 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 3923 3924 /* 3925 * Let the firmware know what features will (not) be used so it can tune 3926 * things accordingly. 3927 */ 3928 #define LIMIT_CAPS(x) do { \ 3929 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 3930 } while (0) 3931 LIMIT_CAPS(nbm); 3932 LIMIT_CAPS(link); 3933 LIMIT_CAPS(switch); 3934 LIMIT_CAPS(nic); 3935 LIMIT_CAPS(toe); 3936 LIMIT_CAPS(rdma); 3937 LIMIT_CAPS(crypto); 3938 LIMIT_CAPS(iscsi); 3939 LIMIT_CAPS(fcoe); 3940 #undef LIMIT_CAPS 3941 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3942 /* 3943 * TOE and hashfilters are mutually exclusive. It is a config 3944 * file or firmware bug if both are reported as available. Try 3945 * to cope with the situation in non-debug builds by disabling 3946 * TOE. 3947 */ 3948 MPASS(caps.toecaps == 0); 3949 3950 caps.toecaps = 0; 3951 caps.rdmacaps = 0; 3952 caps.iscsicaps = 0; 3953 } 3954 3955 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3956 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3957 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3958 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3959 if (rc != 0) { 3960 device_printf(sc->dev, 3961 "failed to process config file: %d.\n", rc); 3962 goto done; 3963 } 3964 3965 t4_tweak_chip_settings(sc); 3966 set_params__pre_init(sc); 3967 3968 /* get basic stuff going */ 3969 rc = -t4_fw_initialize(sc, sc->mbox); 3970 if (rc != 0) { 3971 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 3972 goto done; 3973 } 3974 done: 3975 return (rc); 3976 } 3977 3978 /* 3979 * Partition chip resources for use between various PFs, VFs, etc. 3980 */ 3981 static int 3982 partition_resources(struct adapter *sc) 3983 { 3984 char cfg_file[sizeof(t4_cfg_file)]; 3985 struct caps_allowed caps_allowed; 3986 int rc; 3987 bool fallback; 3988 3989 /* Only the master driver gets to configure the chip resources. */ 3990 MPASS(sc->flags & MASTER_PF); 3991 3992 #define COPY_CAPS(x) do { \ 3993 caps_allowed.x##caps = t4_##x##caps_allowed; \ 3994 } while (0) 3995 bzero(&caps_allowed, sizeof(caps_allowed)); 3996 COPY_CAPS(nbm); 3997 COPY_CAPS(link); 3998 COPY_CAPS(switch); 3999 COPY_CAPS(nic); 4000 COPY_CAPS(toe); 4001 COPY_CAPS(rdma); 4002 COPY_CAPS(crypto); 4003 COPY_CAPS(iscsi); 4004 COPY_CAPS(fcoe); 4005 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 4006 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 4007 retry: 4008 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 4009 if (rc != 0 && fallback) { 4010 device_printf(sc->dev, 4011 "failed (%d) to configure card with \"%s\" profile, " 4012 "will fall back to a basic configuration and retry.\n", 4013 rc, cfg_file); 4014 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 4015 bzero(&caps_allowed, sizeof(caps_allowed)); 4016 COPY_CAPS(switch); 4017 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC; 4018 fallback = false; 4019 goto retry; 4020 } 4021 #undef COPY_CAPS 4022 return (rc); 4023 } 4024 4025 /* 4026 * Retrieve parameters that are needed (or nice to have) very early. 4027 */ 4028 static int 4029 get_params__pre_init(struct adapter *sc) 4030 { 4031 int rc; 4032 uint32_t param[2], val[2]; 4033 4034 t4_get_version_info(sc); 4035 4036 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 4037 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 4038 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 4039 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 4040 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 4041 4042 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 4043 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 4044 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 4045 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 4046 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 4047 4048 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 4049 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 4050 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 4051 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 4052 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 4053 4054 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 4055 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 4056 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 4057 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 4058 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 4059 4060 param[0] = FW_PARAM_DEV(PORTVEC); 4061 param[1] = FW_PARAM_DEV(CCLK); 4062 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4063 if (rc != 0) { 4064 device_printf(sc->dev, 4065 "failed to query parameters (pre_init): %d.\n", rc); 4066 return (rc); 4067 } 4068 4069 sc->params.portvec = val[0]; 4070 sc->params.nports = bitcount32(val[0]); 4071 sc->params.vpd.cclk = val[1]; 4072 4073 /* Read device log parameters. */ 4074 rc = -t4_init_devlog_params(sc, 1); 4075 if (rc == 0) 4076 fixup_devlog_params(sc); 4077 else { 4078 device_printf(sc->dev, 4079 "failed to get devlog parameters: %d.\n", rc); 4080 rc = 0; /* devlog isn't critical for device operation */ 4081 } 4082 4083 return (rc); 4084 } 4085 4086 /* 4087 * Any params that need to be set before FW_INITIALIZE. 4088 */ 4089 static int 4090 set_params__pre_init(struct adapter *sc) 4091 { 4092 int rc = 0; 4093 uint32_t param, val; 4094 4095 if (chip_id(sc) >= CHELSIO_T6) { 4096 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 4097 val = 1; 4098 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4099 /* firmwares < 1.20.1.0 do not have this param. */ 4100 if (rc == FW_EINVAL && sc->params.fw_vers < 4101 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4102 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) { 4103 rc = 0; 4104 } 4105 if (rc != 0) { 4106 device_printf(sc->dev, 4107 "failed to enable high priority filters :%d.\n", 4108 rc); 4109 } 4110 } 4111 4112 /* Enable opaque VIIDs with firmwares that support it. */ 4113 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4114 val = 1; 4115 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4116 if (rc == 0 && val == 1) 4117 sc->params.viid_smt_extn_support = true; 4118 else 4119 sc->params.viid_smt_extn_support = false; 4120 4121 return (rc); 4122 } 4123 4124 /* 4125 * Retrieve various parameters that are of interest to the driver. The device 4126 * has been initialized by the firmware at this point. 4127 */ 4128 static int 4129 get_params__post_init(struct adapter *sc) 4130 { 4131 int rc; 4132 uint32_t param[7], val[7]; 4133 struct fw_caps_config_cmd caps; 4134 4135 param[0] = FW_PARAM_PFVF(IQFLINT_START); 4136 param[1] = FW_PARAM_PFVF(EQ_START); 4137 param[2] = FW_PARAM_PFVF(FILTER_START); 4138 param[3] = FW_PARAM_PFVF(FILTER_END); 4139 param[4] = FW_PARAM_PFVF(L2T_START); 4140 param[5] = FW_PARAM_PFVF(L2T_END); 4141 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 4142 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 4143 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 4144 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 4145 if (rc != 0) { 4146 device_printf(sc->dev, 4147 "failed to query parameters (post_init): %d.\n", rc); 4148 return (rc); 4149 } 4150 4151 sc->sge.iq_start = val[0]; 4152 sc->sge.eq_start = val[1]; 4153 if ((int)val[3] > (int)val[2]) { 4154 sc->tids.ftid_base = val[2]; 4155 sc->tids.ftid_end = val[3]; 4156 sc->tids.nftids = val[3] - val[2] + 1; 4157 } 4158 sc->vres.l2t.start = val[4]; 4159 sc->vres.l2t.size = val[5] - val[4] + 1; 4160 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 4161 ("%s: L2 table size (%u) larger than expected (%u)", 4162 __func__, sc->vres.l2t.size, L2T_SIZE)); 4163 sc->params.core_vdd = val[6]; 4164 4165 if (chip_id(sc) >= CHELSIO_T6) { 4166 4167 sc->tids.tid_base = t4_read_reg(sc, 4168 A_LE_DB_ACTIVE_TABLE_START_INDEX); 4169 4170 param[0] = FW_PARAM_PFVF(HPFILTER_START); 4171 param[1] = FW_PARAM_PFVF(HPFILTER_END); 4172 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4173 if (rc != 0) { 4174 device_printf(sc->dev, 4175 "failed to query hpfilter parameters: %d.\n", rc); 4176 return (rc); 4177 } 4178 if ((int)val[1] > (int)val[0]) { 4179 sc->tids.hpftid_base = val[0]; 4180 sc->tids.hpftid_end = val[1]; 4181 sc->tids.nhpftids = val[1] - val[0] + 1; 4182 4183 /* 4184 * These should go off if the layout changes and the 4185 * driver needs to catch up. 4186 */ 4187 MPASS(sc->tids.hpftid_base == 0); 4188 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 4189 } 4190 } 4191 4192 /* 4193 * MPSBGMAP is queried separately because only recent firmwares support 4194 * it as a parameter and we don't want the compound query above to fail 4195 * on older firmwares. 4196 */ 4197 param[0] = FW_PARAM_DEV(MPSBGMAP); 4198 val[0] = 0; 4199 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4200 if (rc == 0) 4201 sc->params.mps_bg_map = val[0]; 4202 else 4203 sc->params.mps_bg_map = 0; 4204 4205 /* 4206 * Determine whether the firmware supports the filter2 work request. 4207 * This is queried separately for the same reason as MPSBGMAP above. 4208 */ 4209 param[0] = FW_PARAM_DEV(FILTER2_WR); 4210 val[0] = 0; 4211 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4212 if (rc == 0) 4213 sc->params.filter2_wr_support = val[0] != 0; 4214 else 4215 sc->params.filter2_wr_support = 0; 4216 4217 /* 4218 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 4219 * This is queried separately for the same reason as other params above. 4220 */ 4221 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4222 val[0] = 0; 4223 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4224 if (rc == 0) 4225 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 4226 else 4227 sc->params.ulptx_memwrite_dsgl = false; 4228 4229 /* get capabilites */ 4230 bzero(&caps, sizeof(caps)); 4231 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4232 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4233 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4234 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4235 if (rc != 0) { 4236 device_printf(sc->dev, 4237 "failed to get card capabilities: %d.\n", rc); 4238 return (rc); 4239 } 4240 4241 #define READ_CAPS(x) do { \ 4242 sc->x = htobe16(caps.x); \ 4243 } while (0) 4244 READ_CAPS(nbmcaps); 4245 READ_CAPS(linkcaps); 4246 READ_CAPS(switchcaps); 4247 READ_CAPS(niccaps); 4248 READ_CAPS(toecaps); 4249 READ_CAPS(rdmacaps); 4250 READ_CAPS(cryptocaps); 4251 READ_CAPS(iscsicaps); 4252 READ_CAPS(fcoecaps); 4253 4254 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4255 MPASS(chip_id(sc) > CHELSIO_T4); 4256 MPASS(sc->toecaps == 0); 4257 sc->toecaps = 0; 4258 4259 param[0] = FW_PARAM_DEV(NTID); 4260 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4261 if (rc != 0) { 4262 device_printf(sc->dev, 4263 "failed to query HASHFILTER parameters: %d.\n", rc); 4264 return (rc); 4265 } 4266 sc->tids.ntids = val[0]; 4267 if (sc->params.fw_vers < 4268 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4269 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4270 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4271 sc->tids.ntids -= sc->tids.nhpftids; 4272 } 4273 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4274 sc->params.hash_filter = 1; 4275 } 4276 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4277 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4278 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4279 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4280 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4281 if (rc != 0) { 4282 device_printf(sc->dev, 4283 "failed to query NIC parameters: %d.\n", rc); 4284 return (rc); 4285 } 4286 if ((int)val[1] > (int)val[0]) { 4287 sc->tids.etid_base = val[0]; 4288 sc->tids.etid_end = val[1]; 4289 sc->tids.netids = val[1] - val[0] + 1; 4290 sc->params.eo_wr_cred = val[2]; 4291 sc->params.ethoffload = 1; 4292 } 4293 } 4294 if (sc->toecaps) { 4295 /* query offload-related parameters */ 4296 param[0] = FW_PARAM_DEV(NTID); 4297 param[1] = FW_PARAM_PFVF(SERVER_START); 4298 param[2] = FW_PARAM_PFVF(SERVER_END); 4299 param[3] = FW_PARAM_PFVF(TDDP_START); 4300 param[4] = FW_PARAM_PFVF(TDDP_END); 4301 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4302 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4303 if (rc != 0) { 4304 device_printf(sc->dev, 4305 "failed to query TOE parameters: %d.\n", rc); 4306 return (rc); 4307 } 4308 sc->tids.ntids = val[0]; 4309 if (sc->params.fw_vers < 4310 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4311 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4312 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4313 sc->tids.ntids -= sc->tids.nhpftids; 4314 } 4315 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4316 if ((int)val[2] > (int)val[1]) { 4317 sc->tids.stid_base = val[1]; 4318 sc->tids.nstids = val[2] - val[1] + 1; 4319 } 4320 sc->vres.ddp.start = val[3]; 4321 sc->vres.ddp.size = val[4] - val[3] + 1; 4322 sc->params.ofldq_wr_cred = val[5]; 4323 sc->params.offload = 1; 4324 } else { 4325 /* 4326 * The firmware attempts memfree TOE configuration for -SO cards 4327 * and will report toecaps=0 if it runs out of resources (this 4328 * depends on the config file). It may not report 0 for other 4329 * capabilities dependent on the TOE in this case. Set them to 4330 * 0 here so that the driver doesn't bother tracking resources 4331 * that will never be used. 4332 */ 4333 sc->iscsicaps = 0; 4334 sc->rdmacaps = 0; 4335 } 4336 if (sc->rdmacaps) { 4337 param[0] = FW_PARAM_PFVF(STAG_START); 4338 param[1] = FW_PARAM_PFVF(STAG_END); 4339 param[2] = FW_PARAM_PFVF(RQ_START); 4340 param[3] = FW_PARAM_PFVF(RQ_END); 4341 param[4] = FW_PARAM_PFVF(PBL_START); 4342 param[5] = FW_PARAM_PFVF(PBL_END); 4343 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4344 if (rc != 0) { 4345 device_printf(sc->dev, 4346 "failed to query RDMA parameters(1): %d.\n", rc); 4347 return (rc); 4348 } 4349 sc->vres.stag.start = val[0]; 4350 sc->vres.stag.size = val[1] - val[0] + 1; 4351 sc->vres.rq.start = val[2]; 4352 sc->vres.rq.size = val[3] - val[2] + 1; 4353 sc->vres.pbl.start = val[4]; 4354 sc->vres.pbl.size = val[5] - val[4] + 1; 4355 4356 param[0] = FW_PARAM_PFVF(SQRQ_START); 4357 param[1] = FW_PARAM_PFVF(SQRQ_END); 4358 param[2] = FW_PARAM_PFVF(CQ_START); 4359 param[3] = FW_PARAM_PFVF(CQ_END); 4360 param[4] = FW_PARAM_PFVF(OCQ_START); 4361 param[5] = FW_PARAM_PFVF(OCQ_END); 4362 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4363 if (rc != 0) { 4364 device_printf(sc->dev, 4365 "failed to query RDMA parameters(2): %d.\n", rc); 4366 return (rc); 4367 } 4368 sc->vres.qp.start = val[0]; 4369 sc->vres.qp.size = val[1] - val[0] + 1; 4370 sc->vres.cq.start = val[2]; 4371 sc->vres.cq.size = val[3] - val[2] + 1; 4372 sc->vres.ocq.start = val[4]; 4373 sc->vres.ocq.size = val[5] - val[4] + 1; 4374 4375 param[0] = FW_PARAM_PFVF(SRQ_START); 4376 param[1] = FW_PARAM_PFVF(SRQ_END); 4377 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4378 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4379 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4380 if (rc != 0) { 4381 device_printf(sc->dev, 4382 "failed to query RDMA parameters(3): %d.\n", rc); 4383 return (rc); 4384 } 4385 sc->vres.srq.start = val[0]; 4386 sc->vres.srq.size = val[1] - val[0] + 1; 4387 sc->params.max_ordird_qp = val[2]; 4388 sc->params.max_ird_adapter = val[3]; 4389 } 4390 if (sc->iscsicaps) { 4391 param[0] = FW_PARAM_PFVF(ISCSI_START); 4392 param[1] = FW_PARAM_PFVF(ISCSI_END); 4393 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4394 if (rc != 0) { 4395 device_printf(sc->dev, 4396 "failed to query iSCSI parameters: %d.\n", rc); 4397 return (rc); 4398 } 4399 sc->vres.iscsi.start = val[0]; 4400 sc->vres.iscsi.size = val[1] - val[0] + 1; 4401 } 4402 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4403 param[0] = FW_PARAM_PFVF(TLS_START); 4404 param[1] = FW_PARAM_PFVF(TLS_END); 4405 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4406 if (rc != 0) { 4407 device_printf(sc->dev, 4408 "failed to query TLS parameters: %d.\n", rc); 4409 return (rc); 4410 } 4411 sc->vres.key.start = val[0]; 4412 sc->vres.key.size = val[1] - val[0] + 1; 4413 } 4414 4415 t4_init_sge_params(sc); 4416 4417 /* 4418 * We've got the params we wanted to query via the firmware. Now grab 4419 * some others directly from the chip. 4420 */ 4421 rc = t4_read_chip_settings(sc); 4422 4423 return (rc); 4424 } 4425 4426 static int 4427 set_params__post_init(struct adapter *sc) 4428 { 4429 uint32_t param, val; 4430 #ifdef TCP_OFFLOAD 4431 int i, v, shift; 4432 #endif 4433 4434 /* ask for encapsulated CPLs */ 4435 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4436 val = 1; 4437 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4438 4439 /* Enable 32b port caps if the firmware supports it. */ 4440 param = FW_PARAM_PFVF(PORT_CAPS32); 4441 val = 1; 4442 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4443 sc->params.port_caps32 = 1; 4444 4445 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 4446 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 4447 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 4448 V_MASKFILTER(val - 1)); 4449 4450 #ifdef TCP_OFFLOAD 4451 /* 4452 * Override the TOE timers with user provided tunables. This is not the 4453 * recommended way to change the timers (the firmware config file is) so 4454 * these tunables are not documented. 4455 * 4456 * All the timer tunables are in microseconds. 4457 */ 4458 if (t4_toe_keepalive_idle != 0) { 4459 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4460 v &= M_KEEPALIVEIDLE; 4461 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4462 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4463 } 4464 if (t4_toe_keepalive_interval != 0) { 4465 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4466 v &= M_KEEPALIVEINTVL; 4467 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4468 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4469 } 4470 if (t4_toe_keepalive_count != 0) { 4471 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4472 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4473 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4474 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4475 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4476 } 4477 if (t4_toe_rexmt_min != 0) { 4478 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4479 v &= M_RXTMIN; 4480 t4_set_reg_field(sc, A_TP_RXT_MIN, 4481 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4482 } 4483 if (t4_toe_rexmt_max != 0) { 4484 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4485 v &= M_RXTMAX; 4486 t4_set_reg_field(sc, A_TP_RXT_MAX, 4487 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4488 } 4489 if (t4_toe_rexmt_count != 0) { 4490 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4491 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4492 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4493 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4494 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4495 } 4496 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4497 if (t4_toe_rexmt_backoff[i] != -1) { 4498 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4499 shift = (i & 3) << 3; 4500 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4501 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4502 } 4503 } 4504 #endif 4505 return (0); 4506 } 4507 4508 #undef FW_PARAM_PFVF 4509 #undef FW_PARAM_DEV 4510 4511 static void 4512 t4_set_desc(struct adapter *sc) 4513 { 4514 char buf[128]; 4515 struct adapter_params *p = &sc->params; 4516 4517 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4518 4519 device_set_desc_copy(sc->dev, buf); 4520 } 4521 4522 static inline void 4523 ifmedia_add4(struct ifmedia *ifm, int m) 4524 { 4525 4526 ifmedia_add(ifm, m, 0, NULL); 4527 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4528 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4529 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4530 } 4531 4532 /* 4533 * This is the selected media, which is not quite the same as the active media. 4534 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4535 * and active are not the same, and "media: Ethernet selected" otherwise. 4536 */ 4537 static void 4538 set_current_media(struct port_info *pi) 4539 { 4540 struct link_config *lc; 4541 struct ifmedia *ifm; 4542 int mword; 4543 u_int speed; 4544 4545 PORT_LOCK_ASSERT_OWNED(pi); 4546 4547 /* Leave current media alone if it's already set to IFM_NONE. */ 4548 ifm = &pi->media; 4549 if (ifm->ifm_cur != NULL && 4550 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4551 return; 4552 4553 lc = &pi->link_cfg; 4554 if (lc->requested_aneg != AUTONEG_DISABLE && 4555 lc->supported & FW_PORT_CAP32_ANEG) { 4556 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4557 return; 4558 } 4559 mword = IFM_ETHER | IFM_FDX; 4560 if (lc->requested_fc & PAUSE_TX) 4561 mword |= IFM_ETH_TXPAUSE; 4562 if (lc->requested_fc & PAUSE_RX) 4563 mword |= IFM_ETH_RXPAUSE; 4564 if (lc->requested_speed == 0) 4565 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4566 else 4567 speed = lc->requested_speed; 4568 mword |= port_mword(pi, speed_to_fwcap(speed)); 4569 ifmedia_set(ifm, mword); 4570 } 4571 4572 /* 4573 * Returns true if the ifmedia list for the port cannot change. 4574 */ 4575 static bool 4576 fixed_ifmedia(struct port_info *pi) 4577 { 4578 4579 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4580 pi->port_type == FW_PORT_TYPE_BT_XFI || 4581 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4582 pi->port_type == FW_PORT_TYPE_KX4 || 4583 pi->port_type == FW_PORT_TYPE_KX || 4584 pi->port_type == FW_PORT_TYPE_KR || 4585 pi->port_type == FW_PORT_TYPE_BP_AP || 4586 pi->port_type == FW_PORT_TYPE_BP4_AP || 4587 pi->port_type == FW_PORT_TYPE_BP40_BA || 4588 pi->port_type == FW_PORT_TYPE_KR4_100G || 4589 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4590 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4591 } 4592 4593 static void 4594 build_medialist(struct port_info *pi) 4595 { 4596 uint32_t ss, speed; 4597 int unknown, mword, bit; 4598 struct link_config *lc; 4599 struct ifmedia *ifm; 4600 4601 PORT_LOCK_ASSERT_OWNED(pi); 4602 4603 if (pi->flags & FIXED_IFMEDIA) 4604 return; 4605 4606 /* 4607 * Rebuild the ifmedia list. 4608 */ 4609 ifm = &pi->media; 4610 ifmedia_removeall(ifm); 4611 lc = &pi->link_cfg; 4612 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */ 4613 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4614 MPASS(ss != 0); 4615 no_media: 4616 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4617 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4618 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4619 return; 4620 } 4621 4622 unknown = 0; 4623 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 4624 speed = 1 << bit; 4625 MPASS(speed & M_FW_PORT_CAP32_SPEED); 4626 if (ss & speed) { 4627 mword = port_mword(pi, speed); 4628 if (mword == IFM_NONE) { 4629 goto no_media; 4630 } else if (mword == IFM_UNKNOWN) 4631 unknown++; 4632 else 4633 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4634 } 4635 } 4636 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4637 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4638 if (lc->supported & FW_PORT_CAP32_ANEG) 4639 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4640 4641 set_current_media(pi); 4642 } 4643 4644 /* 4645 * Initialize the requested fields in the link config based on driver tunables. 4646 */ 4647 static void 4648 init_link_config(struct port_info *pi) 4649 { 4650 struct link_config *lc = &pi->link_cfg; 4651 4652 PORT_LOCK_ASSERT_OWNED(pi); 4653 4654 lc->requested_speed = 0; 4655 4656 if (t4_autoneg == 0) 4657 lc->requested_aneg = AUTONEG_DISABLE; 4658 else if (t4_autoneg == 1) 4659 lc->requested_aneg = AUTONEG_ENABLE; 4660 else 4661 lc->requested_aneg = AUTONEG_AUTO; 4662 4663 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 4664 PAUSE_AUTONEG); 4665 4666 if (t4_fec == -1 || t4_fec & FEC_AUTO) 4667 lc->requested_fec = FEC_AUTO; 4668 else { 4669 lc->requested_fec = FEC_NONE; 4670 if (t4_fec & FEC_RS) 4671 lc->requested_fec |= FEC_RS; 4672 if (t4_fec & FEC_BASER_RS) 4673 lc->requested_fec |= FEC_BASER_RS; 4674 } 4675 } 4676 4677 /* 4678 * Makes sure that all requested settings comply with what's supported by the 4679 * port. Returns the number of settings that were invalid and had to be fixed. 4680 */ 4681 static int 4682 fixup_link_config(struct port_info *pi) 4683 { 4684 int n = 0; 4685 struct link_config *lc = &pi->link_cfg; 4686 uint32_t fwspeed; 4687 4688 PORT_LOCK_ASSERT_OWNED(pi); 4689 4690 /* Speed (when not autonegotiating) */ 4691 if (lc->requested_speed != 0) { 4692 fwspeed = speed_to_fwcap(lc->requested_speed); 4693 if ((fwspeed & lc->supported) == 0) { 4694 n++; 4695 lc->requested_speed = 0; 4696 } 4697 } 4698 4699 /* Link autonegotiation */ 4700 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 4701 lc->requested_aneg == AUTONEG_DISABLE || 4702 lc->requested_aneg == AUTONEG_AUTO); 4703 if (lc->requested_aneg == AUTONEG_ENABLE && 4704 !(lc->supported & FW_PORT_CAP32_ANEG)) { 4705 n++; 4706 lc->requested_aneg = AUTONEG_AUTO; 4707 } 4708 4709 /* Flow control */ 4710 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 4711 if (lc->requested_fc & PAUSE_TX && 4712 !(lc->supported & FW_PORT_CAP32_FC_TX)) { 4713 n++; 4714 lc->requested_fc &= ~PAUSE_TX; 4715 } 4716 if (lc->requested_fc & PAUSE_RX && 4717 !(lc->supported & FW_PORT_CAP32_FC_RX)) { 4718 n++; 4719 lc->requested_fc &= ~PAUSE_RX; 4720 } 4721 if (!(lc->requested_fc & PAUSE_AUTONEG) && 4722 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) { 4723 n++; 4724 lc->requested_fc |= PAUSE_AUTONEG; 4725 } 4726 4727 /* FEC */ 4728 if ((lc->requested_fec & FEC_RS && 4729 !(lc->supported & FW_PORT_CAP32_FEC_RS)) || 4730 (lc->requested_fec & FEC_BASER_RS && 4731 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) { 4732 n++; 4733 lc->requested_fec = FEC_AUTO; 4734 } 4735 4736 return (n); 4737 } 4738 4739 /* 4740 * Apply the requested L1 settings, which are expected to be valid, to the 4741 * hardware. 4742 */ 4743 static int 4744 apply_link_config(struct port_info *pi) 4745 { 4746 struct adapter *sc = pi->adapter; 4747 struct link_config *lc = &pi->link_cfg; 4748 int rc; 4749 4750 #ifdef INVARIANTS 4751 ASSERT_SYNCHRONIZED_OP(sc); 4752 PORT_LOCK_ASSERT_OWNED(pi); 4753 4754 if (lc->requested_aneg == AUTONEG_ENABLE) 4755 MPASS(lc->supported & FW_PORT_CAP32_ANEG); 4756 if (!(lc->requested_fc & PAUSE_AUTONEG)) 4757 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE); 4758 if (lc->requested_fc & PAUSE_TX) 4759 MPASS(lc->supported & FW_PORT_CAP32_FC_TX); 4760 if (lc->requested_fc & PAUSE_RX) 4761 MPASS(lc->supported & FW_PORT_CAP32_FC_RX); 4762 if (lc->requested_fec & FEC_RS) 4763 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS); 4764 if (lc->requested_fec & FEC_BASER_RS) 4765 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS); 4766 #endif 4767 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4768 if (rc != 0) { 4769 /* Don't complain if the VF driver gets back an EPERM. */ 4770 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 4771 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4772 } else { 4773 /* 4774 * An L1_CFG will almost always result in a link-change event if 4775 * the link is up, and the driver will refresh the actual 4776 * fec/fc/etc. when the notification is processed. If the link 4777 * is down then the actual settings are meaningless. 4778 * 4779 * This takes care of the case where a change in the L1 settings 4780 * may not result in a notification. 4781 */ 4782 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 4783 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 4784 } 4785 return (rc); 4786 } 4787 4788 #define FW_MAC_EXACT_CHUNK 7 4789 4790 /* 4791 * Program the port's XGMAC based on parameters in ifnet. The caller also 4792 * indicates which parameters should be programmed (the rest are left alone). 4793 */ 4794 int 4795 update_mac_settings(struct ifnet *ifp, int flags) 4796 { 4797 int rc = 0; 4798 struct vi_info *vi = ifp->if_softc; 4799 struct port_info *pi = vi->pi; 4800 struct adapter *sc = pi->adapter; 4801 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4802 4803 ASSERT_SYNCHRONIZED_OP(sc); 4804 KASSERT(flags, ("%s: not told what to update.", __func__)); 4805 4806 if (flags & XGMAC_MTU) 4807 mtu = ifp->if_mtu; 4808 4809 if (flags & XGMAC_PROMISC) 4810 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4811 4812 if (flags & XGMAC_ALLMULTI) 4813 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4814 4815 if (flags & XGMAC_VLANEX) 4816 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4817 4818 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4819 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4820 allmulti, 1, vlanex, false); 4821 if (rc) { 4822 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4823 rc); 4824 return (rc); 4825 } 4826 } 4827 4828 if (flags & XGMAC_UCADDR) { 4829 uint8_t ucaddr[ETHER_ADDR_LEN]; 4830 4831 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4832 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4833 ucaddr, true, &vi->smt_idx); 4834 if (rc < 0) { 4835 rc = -rc; 4836 if_printf(ifp, "change_mac failed: %d\n", rc); 4837 return (rc); 4838 } else { 4839 vi->xact_addr_filt = rc; 4840 rc = 0; 4841 } 4842 } 4843 4844 if (flags & XGMAC_MCADDRS) { 4845 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4846 int del = 1; 4847 uint64_t hash = 0; 4848 struct ifmultiaddr *ifma; 4849 int i = 0, j; 4850 4851 if_maddr_rlock(ifp); 4852 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4853 if (ifma->ifma_addr->sa_family != AF_LINK) 4854 continue; 4855 mcaddr[i] = 4856 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4857 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4858 i++; 4859 4860 if (i == FW_MAC_EXACT_CHUNK) { 4861 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4862 del, i, mcaddr, NULL, &hash, 0); 4863 if (rc < 0) { 4864 rc = -rc; 4865 for (j = 0; j < i; j++) { 4866 if_printf(ifp, 4867 "failed to add mc address" 4868 " %02x:%02x:%02x:" 4869 "%02x:%02x:%02x rc=%d\n", 4870 mcaddr[j][0], mcaddr[j][1], 4871 mcaddr[j][2], mcaddr[j][3], 4872 mcaddr[j][4], mcaddr[j][5], 4873 rc); 4874 } 4875 goto mcfail; 4876 } 4877 del = 0; 4878 i = 0; 4879 } 4880 } 4881 if (i > 0) { 4882 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4883 mcaddr, NULL, &hash, 0); 4884 if (rc < 0) { 4885 rc = -rc; 4886 for (j = 0; j < i; j++) { 4887 if_printf(ifp, 4888 "failed to add mc address" 4889 " %02x:%02x:%02x:" 4890 "%02x:%02x:%02x rc=%d\n", 4891 mcaddr[j][0], mcaddr[j][1], 4892 mcaddr[j][2], mcaddr[j][3], 4893 mcaddr[j][4], mcaddr[j][5], 4894 rc); 4895 } 4896 goto mcfail; 4897 } 4898 } 4899 4900 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4901 if (rc != 0) 4902 if_printf(ifp, "failed to set mc address hash: %d", rc); 4903 mcfail: 4904 if_maddr_runlock(ifp); 4905 } 4906 4907 return (rc); 4908 } 4909 4910 /* 4911 * {begin|end}_synchronized_op must be called from the same thread. 4912 */ 4913 int 4914 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4915 char *wmesg) 4916 { 4917 int rc, pri; 4918 4919 #ifdef WITNESS 4920 /* the caller thinks it's ok to sleep, but is it really? */ 4921 if (flags & SLEEP_OK) 4922 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4923 "begin_synchronized_op"); 4924 #endif 4925 4926 if (INTR_OK) 4927 pri = PCATCH; 4928 else 4929 pri = 0; 4930 4931 ADAPTER_LOCK(sc); 4932 for (;;) { 4933 4934 if (vi && IS_DOOMED(vi)) { 4935 rc = ENXIO; 4936 goto done; 4937 } 4938 4939 if (!IS_BUSY(sc)) { 4940 rc = 0; 4941 break; 4942 } 4943 4944 if (!(flags & SLEEP_OK)) { 4945 rc = EBUSY; 4946 goto done; 4947 } 4948 4949 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4950 rc = EINTR; 4951 goto done; 4952 } 4953 } 4954 4955 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4956 SET_BUSY(sc); 4957 #ifdef INVARIANTS 4958 sc->last_op = wmesg; 4959 sc->last_op_thr = curthread; 4960 sc->last_op_flags = flags; 4961 #endif 4962 4963 done: 4964 if (!(flags & HOLD_LOCK) || rc) 4965 ADAPTER_UNLOCK(sc); 4966 4967 return (rc); 4968 } 4969 4970 /* 4971 * Tell if_ioctl and if_init that the VI is going away. This is 4972 * special variant of begin_synchronized_op and must be paired with a 4973 * call to end_synchronized_op. 4974 */ 4975 void 4976 doom_vi(struct adapter *sc, struct vi_info *vi) 4977 { 4978 4979 ADAPTER_LOCK(sc); 4980 SET_DOOMED(vi); 4981 wakeup(&sc->flags); 4982 while (IS_BUSY(sc)) 4983 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4984 SET_BUSY(sc); 4985 #ifdef INVARIANTS 4986 sc->last_op = "t4detach"; 4987 sc->last_op_thr = curthread; 4988 sc->last_op_flags = 0; 4989 #endif 4990 ADAPTER_UNLOCK(sc); 4991 } 4992 4993 /* 4994 * {begin|end}_synchronized_op must be called from the same thread. 4995 */ 4996 void 4997 end_synchronized_op(struct adapter *sc, int flags) 4998 { 4999 5000 if (flags & LOCK_HELD) 5001 ADAPTER_LOCK_ASSERT_OWNED(sc); 5002 else 5003 ADAPTER_LOCK(sc); 5004 5005 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 5006 CLR_BUSY(sc); 5007 wakeup(&sc->flags); 5008 ADAPTER_UNLOCK(sc); 5009 } 5010 5011 static int 5012 cxgbe_init_synchronized(struct vi_info *vi) 5013 { 5014 struct port_info *pi = vi->pi; 5015 struct adapter *sc = pi->adapter; 5016 struct ifnet *ifp = vi->ifp; 5017 int rc = 0, i; 5018 struct sge_txq *txq; 5019 5020 ASSERT_SYNCHRONIZED_OP(sc); 5021 5022 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5023 return (0); /* already running */ 5024 5025 if (!(sc->flags & FULL_INIT_DONE) && 5026 ((rc = adapter_full_init(sc)) != 0)) 5027 return (rc); /* error message displayed already */ 5028 5029 if (!(vi->flags & VI_INIT_DONE) && 5030 ((rc = vi_full_init(vi)) != 0)) 5031 return (rc); /* error message displayed already */ 5032 5033 rc = update_mac_settings(ifp, XGMAC_ALL); 5034 if (rc) 5035 goto done; /* error message displayed already */ 5036 5037 PORT_LOCK(pi); 5038 if (pi->up_vis == 0) { 5039 t4_update_port_info(pi); 5040 fixup_link_config(pi); 5041 build_medialist(pi); 5042 apply_link_config(pi); 5043 } 5044 5045 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 5046 if (rc != 0) { 5047 if_printf(ifp, "enable_vi failed: %d\n", rc); 5048 PORT_UNLOCK(pi); 5049 goto done; 5050 } 5051 5052 /* 5053 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 5054 * if this changes. 5055 */ 5056 5057 for_each_txq(vi, i, txq) { 5058 TXQ_LOCK(txq); 5059 txq->eq.flags |= EQ_ENABLED; 5060 TXQ_UNLOCK(txq); 5061 } 5062 5063 /* 5064 * The first iq of the first port to come up is used for tracing. 5065 */ 5066 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 5067 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 5068 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 5069 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 5070 V_QUEUENUMBER(sc->traceq)); 5071 pi->flags |= HAS_TRACEQ; 5072 } 5073 5074 /* all ok */ 5075 pi->up_vis++; 5076 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5077 5078 if (pi->nvi > 1 || sc->flags & IS_VF) 5079 callout_reset(&vi->tick, hz, vi_tick, vi); 5080 else 5081 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 5082 if (pi->link_cfg.link_ok) 5083 t4_os_link_changed(pi); 5084 PORT_UNLOCK(pi); 5085 done: 5086 if (rc != 0) 5087 cxgbe_uninit_synchronized(vi); 5088 5089 return (rc); 5090 } 5091 5092 /* 5093 * Idempotent. 5094 */ 5095 static int 5096 cxgbe_uninit_synchronized(struct vi_info *vi) 5097 { 5098 struct port_info *pi = vi->pi; 5099 struct adapter *sc = pi->adapter; 5100 struct ifnet *ifp = vi->ifp; 5101 int rc, i; 5102 struct sge_txq *txq; 5103 5104 ASSERT_SYNCHRONIZED_OP(sc); 5105 5106 if (!(vi->flags & VI_INIT_DONE)) { 5107 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5108 KASSERT(0, ("uninited VI is running")); 5109 if_printf(ifp, "uninited VI with running ifnet. " 5110 "vi->flags 0x%016lx, if_flags 0x%08x, " 5111 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 5112 ifp->if_drv_flags); 5113 } 5114 return (0); 5115 } 5116 5117 /* 5118 * Disable the VI so that all its data in either direction is discarded 5119 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 5120 * tick) intact as the TP can deliver negative advice or data that it's 5121 * holding in its RAM (for an offloaded connection) even after the VI is 5122 * disabled. 5123 */ 5124 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 5125 if (rc) { 5126 if_printf(ifp, "disable_vi failed: %d\n", rc); 5127 return (rc); 5128 } 5129 5130 for_each_txq(vi, i, txq) { 5131 TXQ_LOCK(txq); 5132 txq->eq.flags &= ~EQ_ENABLED; 5133 TXQ_UNLOCK(txq); 5134 } 5135 5136 PORT_LOCK(pi); 5137 if (pi->nvi > 1 || sc->flags & IS_VF) 5138 callout_stop(&vi->tick); 5139 else 5140 callout_stop(&pi->tick); 5141 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5142 PORT_UNLOCK(pi); 5143 return (0); 5144 } 5145 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5146 pi->up_vis--; 5147 if (pi->up_vis > 0) { 5148 PORT_UNLOCK(pi); 5149 return (0); 5150 } 5151 5152 pi->link_cfg.link_ok = false; 5153 pi->link_cfg.speed = 0; 5154 pi->link_cfg.link_down_rc = 255; 5155 t4_os_link_changed(pi); 5156 PORT_UNLOCK(pi); 5157 5158 return (0); 5159 } 5160 5161 /* 5162 * It is ok for this function to fail midway and return right away. t4_detach 5163 * will walk the entire sc->irq list and clean up whatever is valid. 5164 */ 5165 int 5166 t4_setup_intr_handlers(struct adapter *sc) 5167 { 5168 int rc, rid, p, q, v; 5169 char s[8]; 5170 struct irq *irq; 5171 struct port_info *pi; 5172 struct vi_info *vi; 5173 struct sge *sge = &sc->sge; 5174 struct sge_rxq *rxq; 5175 #ifdef TCP_OFFLOAD 5176 struct sge_ofld_rxq *ofld_rxq; 5177 #endif 5178 #ifdef DEV_NETMAP 5179 struct sge_nm_rxq *nm_rxq; 5180 #endif 5181 #ifdef RSS 5182 int nbuckets = rss_getnumbuckets(); 5183 #endif 5184 5185 /* 5186 * Setup interrupts. 5187 */ 5188 irq = &sc->irq[0]; 5189 rid = sc->intr_type == INTR_INTX ? 0 : 1; 5190 if (forwarding_intr_to_fwq(sc)) 5191 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 5192 5193 /* Multiple interrupts. */ 5194 if (sc->flags & IS_VF) 5195 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 5196 ("%s: too few intr.", __func__)); 5197 else 5198 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 5199 ("%s: too few intr.", __func__)); 5200 5201 /* The first one is always error intr on PFs */ 5202 if (!(sc->flags & IS_VF)) { 5203 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 5204 if (rc != 0) 5205 return (rc); 5206 irq++; 5207 rid++; 5208 } 5209 5210 /* The second one is always the firmware event queue (first on VFs) */ 5211 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 5212 if (rc != 0) 5213 return (rc); 5214 irq++; 5215 rid++; 5216 5217 for_each_port(sc, p) { 5218 pi = sc->port[p]; 5219 for_each_vi(pi, v, vi) { 5220 vi->first_intr = rid - 1; 5221 5222 if (vi->nnmrxq > 0) { 5223 int n = max(vi->nrxq, vi->nnmrxq); 5224 5225 rxq = &sge->rxq[vi->first_rxq]; 5226 #ifdef DEV_NETMAP 5227 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 5228 #endif 5229 for (q = 0; q < n; q++) { 5230 snprintf(s, sizeof(s), "%x%c%x", p, 5231 'a' + v, q); 5232 if (q < vi->nrxq) 5233 irq->rxq = rxq++; 5234 #ifdef DEV_NETMAP 5235 if (q < vi->nnmrxq) 5236 irq->nm_rxq = nm_rxq++; 5237 5238 if (irq->nm_rxq != NULL && 5239 irq->rxq == NULL) { 5240 /* Netmap rx only */ 5241 rc = t4_alloc_irq(sc, irq, rid, 5242 t4_nm_intr, irq->nm_rxq, s); 5243 } 5244 if (irq->nm_rxq != NULL && 5245 irq->rxq != NULL) { 5246 /* NIC and Netmap rx */ 5247 rc = t4_alloc_irq(sc, irq, rid, 5248 t4_vi_intr, irq, s); 5249 } 5250 #endif 5251 if (irq->rxq != NULL && 5252 irq->nm_rxq == NULL) { 5253 /* NIC rx only */ 5254 rc = t4_alloc_irq(sc, irq, rid, 5255 t4_intr, irq->rxq, s); 5256 } 5257 if (rc != 0) 5258 return (rc); 5259 #ifdef RSS 5260 if (q < vi->nrxq) { 5261 bus_bind_intr(sc->dev, irq->res, 5262 rss_getcpu(q % nbuckets)); 5263 } 5264 #endif 5265 irq++; 5266 rid++; 5267 vi->nintr++; 5268 } 5269 } else { 5270 for_each_rxq(vi, q, rxq) { 5271 snprintf(s, sizeof(s), "%x%c%x", p, 5272 'a' + v, q); 5273 rc = t4_alloc_irq(sc, irq, rid, 5274 t4_intr, rxq, s); 5275 if (rc != 0) 5276 return (rc); 5277 #ifdef RSS 5278 bus_bind_intr(sc->dev, irq->res, 5279 rss_getcpu(q % nbuckets)); 5280 #endif 5281 irq++; 5282 rid++; 5283 vi->nintr++; 5284 } 5285 } 5286 #ifdef TCP_OFFLOAD 5287 for_each_ofld_rxq(vi, q, ofld_rxq) { 5288 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5289 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5290 ofld_rxq, s); 5291 if (rc != 0) 5292 return (rc); 5293 irq++; 5294 rid++; 5295 vi->nintr++; 5296 } 5297 #endif 5298 } 5299 } 5300 MPASS(irq == &sc->irq[sc->intr_count]); 5301 5302 return (0); 5303 } 5304 5305 int 5306 adapter_full_init(struct adapter *sc) 5307 { 5308 int rc, i; 5309 #ifdef RSS 5310 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5311 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5312 #endif 5313 5314 ASSERT_SYNCHRONIZED_OP(sc); 5315 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5316 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5317 ("%s: FULL_INIT_DONE already", __func__)); 5318 5319 /* 5320 * queues that belong to the adapter (not any particular port). 5321 */ 5322 rc = t4_setup_adapter_queues(sc); 5323 if (rc != 0) 5324 goto done; 5325 5326 for (i = 0; i < nitems(sc->tq); i++) { 5327 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5328 taskqueue_thread_enqueue, &sc->tq[i]); 5329 if (sc->tq[i] == NULL) { 5330 device_printf(sc->dev, 5331 "failed to allocate task queue %d\n", i); 5332 rc = ENOMEM; 5333 goto done; 5334 } 5335 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5336 device_get_nameunit(sc->dev), i); 5337 } 5338 #ifdef RSS 5339 MPASS(RSS_KEYSIZE == 40); 5340 rss_getkey((void *)&raw_rss_key[0]); 5341 for (i = 0; i < nitems(rss_key); i++) { 5342 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5343 } 5344 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5345 #endif 5346 5347 if (!(sc->flags & IS_VF)) 5348 t4_intr_enable(sc); 5349 sc->flags |= FULL_INIT_DONE; 5350 done: 5351 if (rc != 0) 5352 adapter_full_uninit(sc); 5353 5354 return (rc); 5355 } 5356 5357 int 5358 adapter_full_uninit(struct adapter *sc) 5359 { 5360 int i; 5361 5362 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5363 5364 t4_teardown_adapter_queues(sc); 5365 5366 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5367 taskqueue_free(sc->tq[i]); 5368 sc->tq[i] = NULL; 5369 } 5370 5371 sc->flags &= ~FULL_INIT_DONE; 5372 5373 return (0); 5374 } 5375 5376 #ifdef RSS 5377 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5378 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5379 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5380 RSS_HASHTYPE_RSS_UDP_IPV6) 5381 5382 /* Translates kernel hash types to hardware. */ 5383 static int 5384 hashconfig_to_hashen(int hashconfig) 5385 { 5386 int hashen = 0; 5387 5388 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5389 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5390 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5391 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5392 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5393 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5394 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5395 } 5396 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5397 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5398 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5399 } 5400 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5401 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5402 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5403 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5404 5405 return (hashen); 5406 } 5407 5408 /* Translates hardware hash types to kernel. */ 5409 static int 5410 hashen_to_hashconfig(int hashen) 5411 { 5412 int hashconfig = 0; 5413 5414 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5415 /* 5416 * If UDP hashing was enabled it must have been enabled for 5417 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5418 * enabling any 4-tuple hash is nonsense configuration. 5419 */ 5420 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5421 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5422 5423 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5424 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5425 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5426 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5427 } 5428 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5429 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5430 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5431 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5432 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5433 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5434 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5435 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5436 5437 return (hashconfig); 5438 } 5439 #endif 5440 5441 int 5442 vi_full_init(struct vi_info *vi) 5443 { 5444 struct adapter *sc = vi->pi->adapter; 5445 struct ifnet *ifp = vi->ifp; 5446 uint16_t *rss; 5447 struct sge_rxq *rxq; 5448 int rc, i, j; 5449 #ifdef RSS 5450 int nbuckets = rss_getnumbuckets(); 5451 int hashconfig = rss_gethashconfig(); 5452 int extra; 5453 #endif 5454 5455 ASSERT_SYNCHRONIZED_OP(sc); 5456 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5457 ("%s: VI_INIT_DONE already", __func__)); 5458 5459 sysctl_ctx_init(&vi->ctx); 5460 vi->flags |= VI_SYSCTL_CTX; 5461 5462 /* 5463 * Allocate tx/rx/fl queues for this VI. 5464 */ 5465 rc = t4_setup_vi_queues(vi); 5466 if (rc != 0) 5467 goto done; /* error message displayed already */ 5468 5469 /* 5470 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5471 */ 5472 if (vi->nrxq > vi->rss_size) { 5473 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5474 "some queues will never receive traffic.\n", vi->nrxq, 5475 vi->rss_size); 5476 } else if (vi->rss_size % vi->nrxq) { 5477 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5478 "expect uneven traffic distribution.\n", vi->nrxq, 5479 vi->rss_size); 5480 } 5481 #ifdef RSS 5482 if (vi->nrxq != nbuckets) { 5483 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5484 "performance will be impacted.\n", vi->nrxq, nbuckets); 5485 } 5486 #endif 5487 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5488 for (i = 0; i < vi->rss_size;) { 5489 #ifdef RSS 5490 j = rss_get_indirection_to_bucket(i); 5491 j %= vi->nrxq; 5492 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5493 rss[i++] = rxq->iq.abs_id; 5494 #else 5495 for_each_rxq(vi, j, rxq) { 5496 rss[i++] = rxq->iq.abs_id; 5497 if (i == vi->rss_size) 5498 break; 5499 } 5500 #endif 5501 } 5502 5503 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5504 vi->rss_size); 5505 if (rc != 0) { 5506 free(rss, M_CXGBE); 5507 if_printf(ifp, "rss_config failed: %d\n", rc); 5508 goto done; 5509 } 5510 5511 #ifdef RSS 5512 vi->hashen = hashconfig_to_hashen(hashconfig); 5513 5514 /* 5515 * We may have had to enable some hashes even though the global config 5516 * wants them disabled. This is a potential problem that must be 5517 * reported to the user. 5518 */ 5519 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 5520 5521 /* 5522 * If we consider only the supported hash types, then the enabled hashes 5523 * are a superset of the requested hashes. In other words, there cannot 5524 * be any supported hash that was requested but not enabled, but there 5525 * can be hashes that were not requested but had to be enabled. 5526 */ 5527 extra &= SUPPORTED_RSS_HASHTYPES; 5528 MPASS((extra & hashconfig) == 0); 5529 5530 if (extra) { 5531 if_printf(ifp, 5532 "global RSS config (0x%x) cannot be accommodated.\n", 5533 hashconfig); 5534 } 5535 if (extra & RSS_HASHTYPE_RSS_IPV4) 5536 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5537 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5538 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5539 if (extra & RSS_HASHTYPE_RSS_IPV6) 5540 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5541 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5542 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5543 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5544 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5545 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5546 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5547 #else 5548 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5549 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5550 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5551 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5552 #endif 5553 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0); 5554 if (rc != 0) { 5555 free(rss, M_CXGBE); 5556 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5557 goto done; 5558 } 5559 5560 vi->rss = rss; 5561 vi->flags |= VI_INIT_DONE; 5562 done: 5563 if (rc != 0) 5564 vi_full_uninit(vi); 5565 5566 return (rc); 5567 } 5568 5569 /* 5570 * Idempotent. 5571 */ 5572 int 5573 vi_full_uninit(struct vi_info *vi) 5574 { 5575 struct port_info *pi = vi->pi; 5576 struct adapter *sc = pi->adapter; 5577 int i; 5578 struct sge_rxq *rxq; 5579 struct sge_txq *txq; 5580 #ifdef TCP_OFFLOAD 5581 struct sge_ofld_rxq *ofld_rxq; 5582 #endif 5583 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5584 struct sge_wrq *ofld_txq; 5585 #endif 5586 5587 if (vi->flags & VI_INIT_DONE) { 5588 5589 /* Need to quiesce queues. */ 5590 5591 /* XXX: Only for the first VI? */ 5592 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5593 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5594 5595 for_each_txq(vi, i, txq) { 5596 quiesce_txq(sc, txq); 5597 } 5598 5599 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5600 for_each_ofld_txq(vi, i, ofld_txq) { 5601 quiesce_wrq(sc, ofld_txq); 5602 } 5603 #endif 5604 5605 for_each_rxq(vi, i, rxq) { 5606 quiesce_iq(sc, &rxq->iq); 5607 quiesce_fl(sc, &rxq->fl); 5608 } 5609 5610 #ifdef TCP_OFFLOAD 5611 for_each_ofld_rxq(vi, i, ofld_rxq) { 5612 quiesce_iq(sc, &ofld_rxq->iq); 5613 quiesce_fl(sc, &ofld_rxq->fl); 5614 } 5615 #endif 5616 free(vi->rss, M_CXGBE); 5617 free(vi->nm_rss, M_CXGBE); 5618 } 5619 5620 t4_teardown_vi_queues(vi); 5621 vi->flags &= ~VI_INIT_DONE; 5622 5623 return (0); 5624 } 5625 5626 static void 5627 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5628 { 5629 struct sge_eq *eq = &txq->eq; 5630 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5631 5632 (void) sc; /* unused */ 5633 5634 #ifdef INVARIANTS 5635 TXQ_LOCK(txq); 5636 MPASS((eq->flags & EQ_ENABLED) == 0); 5637 TXQ_UNLOCK(txq); 5638 #endif 5639 5640 /* Wait for the mp_ring to empty. */ 5641 while (!mp_ring_is_idle(txq->r)) { 5642 mp_ring_check_drainage(txq->r, 0); 5643 pause("rquiesce", 1); 5644 } 5645 5646 /* Then wait for the hardware to finish. */ 5647 while (spg->cidx != htobe16(eq->pidx)) 5648 pause("equiesce", 1); 5649 5650 /* Finally, wait for the driver to reclaim all descriptors. */ 5651 while (eq->cidx != eq->pidx) 5652 pause("dquiesce", 1); 5653 } 5654 5655 static void 5656 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5657 { 5658 5659 /* XXXTX */ 5660 } 5661 5662 static void 5663 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5664 { 5665 (void) sc; /* unused */ 5666 5667 /* Synchronize with the interrupt handler */ 5668 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5669 pause("iqfree", 1); 5670 } 5671 5672 static void 5673 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5674 { 5675 mtx_lock(&sc->sfl_lock); 5676 FL_LOCK(fl); 5677 fl->flags |= FL_DOOMED; 5678 FL_UNLOCK(fl); 5679 callout_stop(&sc->sfl_callout); 5680 mtx_unlock(&sc->sfl_lock); 5681 5682 KASSERT((fl->flags & FL_STARVING) == 0, 5683 ("%s: still starving", __func__)); 5684 } 5685 5686 static int 5687 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5688 driver_intr_t *handler, void *arg, char *name) 5689 { 5690 int rc; 5691 5692 irq->rid = rid; 5693 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5694 RF_SHAREABLE | RF_ACTIVE); 5695 if (irq->res == NULL) { 5696 device_printf(sc->dev, 5697 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5698 return (ENOMEM); 5699 } 5700 5701 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5702 NULL, handler, arg, &irq->tag); 5703 if (rc != 0) { 5704 device_printf(sc->dev, 5705 "failed to setup interrupt for rid %d, name %s: %d\n", 5706 rid, name, rc); 5707 } else if (name) 5708 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5709 5710 return (rc); 5711 } 5712 5713 static int 5714 t4_free_irq(struct adapter *sc, struct irq *irq) 5715 { 5716 if (irq->tag) 5717 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5718 if (irq->res) 5719 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5720 5721 bzero(irq, sizeof(*irq)); 5722 5723 return (0); 5724 } 5725 5726 static void 5727 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5728 { 5729 5730 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5731 t4_get_regs(sc, buf, regs->len); 5732 } 5733 5734 #define A_PL_INDIR_CMD 0x1f8 5735 5736 #define S_PL_AUTOINC 31 5737 #define M_PL_AUTOINC 0x1U 5738 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5739 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5740 5741 #define S_PL_VFID 20 5742 #define M_PL_VFID 0xffU 5743 #define V_PL_VFID(x) ((x) << S_PL_VFID) 5744 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5745 5746 #define S_PL_ADDR 0 5747 #define M_PL_ADDR 0xfffffU 5748 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5749 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5750 5751 #define A_PL_INDIR_DATA 0x1fc 5752 5753 static uint64_t 5754 read_vf_stat(struct adapter *sc, u_int vin, int reg) 5755 { 5756 u32 stats[2]; 5757 5758 mtx_assert(&sc->reg_lock, MA_OWNED); 5759 if (sc->flags & IS_VF) { 5760 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5761 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5762 } else { 5763 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5764 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 5765 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5766 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5767 } 5768 return (((uint64_t)stats[1]) << 32 | stats[0]); 5769 } 5770 5771 static void 5772 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 5773 { 5774 5775 #define GET_STAT(name) \ 5776 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 5777 5778 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5779 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5780 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5781 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5782 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5783 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5784 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5785 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5786 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5787 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5788 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5789 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5790 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5791 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5792 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5793 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5794 5795 #undef GET_STAT 5796 } 5797 5798 static void 5799 t4_clr_vi_stats(struct adapter *sc, u_int vin) 5800 { 5801 int reg; 5802 5803 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 5804 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5805 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5806 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5807 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5808 } 5809 5810 static void 5811 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5812 { 5813 struct timeval tv; 5814 const struct timeval interval = {0, 250000}; /* 250ms */ 5815 5816 if (!(vi->flags & VI_INIT_DONE)) 5817 return; 5818 5819 getmicrotime(&tv); 5820 timevalsub(&tv, &interval); 5821 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5822 return; 5823 5824 mtx_lock(&sc->reg_lock); 5825 t4_get_vi_stats(sc, vi->vin, &vi->stats); 5826 getmicrotime(&vi->last_refreshed); 5827 mtx_unlock(&sc->reg_lock); 5828 } 5829 5830 static void 5831 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5832 { 5833 u_int i, v, tnl_cong_drops, bg_map; 5834 struct timeval tv; 5835 const struct timeval interval = {0, 250000}; /* 250ms */ 5836 5837 getmicrotime(&tv); 5838 timevalsub(&tv, &interval); 5839 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5840 return; 5841 5842 tnl_cong_drops = 0; 5843 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5844 bg_map = pi->mps_bg_map; 5845 while (bg_map) { 5846 i = ffs(bg_map) - 1; 5847 mtx_lock(&sc->reg_lock); 5848 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5849 A_TP_MIB_TNL_CNG_DROP_0 + i); 5850 mtx_unlock(&sc->reg_lock); 5851 tnl_cong_drops += v; 5852 bg_map &= ~(1 << i); 5853 } 5854 pi->tnl_cong_drops = tnl_cong_drops; 5855 getmicrotime(&pi->last_refreshed); 5856 } 5857 5858 static void 5859 cxgbe_tick(void *arg) 5860 { 5861 struct port_info *pi = arg; 5862 struct adapter *sc = pi->adapter; 5863 5864 PORT_LOCK_ASSERT_OWNED(pi); 5865 cxgbe_refresh_stats(sc, pi); 5866 5867 callout_schedule(&pi->tick, hz); 5868 } 5869 5870 void 5871 vi_tick(void *arg) 5872 { 5873 struct vi_info *vi = arg; 5874 struct adapter *sc = vi->pi->adapter; 5875 5876 vi_refresh_stats(sc, vi); 5877 5878 callout_schedule(&vi->tick, hz); 5879 } 5880 5881 /* 5882 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5883 */ 5884 static char *caps_decoder[] = { 5885 "\20\001IPMI\002NCSI", /* 0: NBM */ 5886 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5887 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5888 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5889 "\006HASHFILTER\007ETHOFLD", 5890 "\20\001TOE", /* 4: TOE */ 5891 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5892 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5893 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5894 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5895 "\007T10DIF" 5896 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5897 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5898 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5899 "\004PO_INITIATOR\005PO_TARGET", 5900 }; 5901 5902 void 5903 t4_sysctls(struct adapter *sc) 5904 { 5905 struct sysctl_ctx_list *ctx; 5906 struct sysctl_oid *oid; 5907 struct sysctl_oid_list *children, *c0; 5908 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5909 5910 ctx = device_get_sysctl_ctx(sc->dev); 5911 5912 /* 5913 * dev.t4nex.X. 5914 */ 5915 oid = device_get_sysctl_tree(sc->dev); 5916 c0 = children = SYSCTL_CHILDREN(oid); 5917 5918 sc->sc_do_rxcopy = 1; 5919 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5920 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5921 5922 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5923 sc->params.nports, "# of ports"); 5924 5925 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5926 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells, 5927 sysctl_bitfield_8b, "A", "available doorbells"); 5928 5929 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5930 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5931 5932 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5933 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5934 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5935 "interrupt holdoff timer values (us)"); 5936 5937 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5938 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5939 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5940 "interrupt holdoff packet counter values"); 5941 5942 t4_sge_sysctls(sc, ctx, children); 5943 5944 sc->lro_timeout = 100; 5945 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5946 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5947 5948 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5949 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5950 5951 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5952 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5953 5954 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5955 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5956 5957 if (sc->flags & IS_VF) 5958 return; 5959 5960 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5961 NULL, chip_rev(sc), "chip hardware revision"); 5962 5963 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5964 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5965 5966 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5967 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5968 5969 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5970 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5971 5972 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5973 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5974 5975 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5976 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5977 5978 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5979 sc->er_version, 0, "expansion ROM version"); 5980 5981 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5982 sc->bs_version, 0, "bootstrap firmware version"); 5983 5984 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5985 NULL, sc->params.scfg_vers, "serial config version"); 5986 5987 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5988 NULL, sc->params.vpd_vers, "VPD version"); 5989 5990 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5991 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5992 5993 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5994 sc->cfcsum, "config file checksum"); 5995 5996 #define SYSCTL_CAP(name, n, text) \ 5997 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5998 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \ 5999 sysctl_bitfield_16b, "A", "available " text " capabilities") 6000 6001 SYSCTL_CAP(nbmcaps, 0, "NBM"); 6002 SYSCTL_CAP(linkcaps, 1, "link"); 6003 SYSCTL_CAP(switchcaps, 2, "switch"); 6004 SYSCTL_CAP(niccaps, 3, "NIC"); 6005 SYSCTL_CAP(toecaps, 4, "TCP offload"); 6006 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 6007 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 6008 SYSCTL_CAP(cryptocaps, 7, "crypto"); 6009 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 6010 #undef SYSCTL_CAP 6011 6012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 6013 NULL, sc->tids.nftids, "number of filters"); 6014 6015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 6016 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 6017 "chip temperature (in Celsius)"); 6018 6019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING | 6020 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A", 6021 "microprocessor load averages (debug firmwares only)"); 6022 6023 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 6024 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 6025 6026 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 6027 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS, 6028 sysctl_cpus, "A", "local CPUs"); 6029 6030 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 6031 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS, 6032 sysctl_cpus, "A", "preferred CPUs for interrupts"); 6033 6034 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 6035 &sc->swintr, 0, "software triggered interrupts"); 6036 6037 /* 6038 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 6039 */ 6040 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 6041 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 6042 "logs and miscellaneous information"); 6043 children = SYSCTL_CHILDREN(oid); 6044 6045 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 6046 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6047 sysctl_cctrl, "A", "congestion control"); 6048 6049 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 6050 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6051 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 6052 6053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 6054 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 6055 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 6056 6057 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 6058 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 6059 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 6060 6061 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 6062 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 6063 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 6064 6065 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 6066 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 6067 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 6068 6069 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 6070 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 6071 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 6072 6073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 6074 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la, 6075 "A", "CIM logic analyzer"); 6076 6077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 6078 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6079 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 6080 6081 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 6082 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 6083 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 6084 6085 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 6086 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 6087 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 6088 6089 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 6090 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 6091 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 6092 6093 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 6094 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 6095 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 6096 6097 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 6098 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 6099 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 6100 6101 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 6102 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 6103 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 6104 6105 if (chip_id(sc) > CHELSIO_T4) { 6106 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 6107 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 6108 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 6109 6110 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 6111 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 6112 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 6113 } 6114 6115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 6116 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6117 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 6118 6119 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 6120 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6121 sysctl_cim_qcfg, "A", "CIM queue configuration"); 6122 6123 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 6124 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6125 sysctl_cpl_stats, "A", "CPL statistics"); 6126 6127 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 6128 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6129 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 6130 6131 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 6132 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6133 sysctl_devlog, "A", "firmware's device log"); 6134 6135 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 6136 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6137 sysctl_fcoe_stats, "A", "FCoE statistics"); 6138 6139 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 6140 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6141 sysctl_hw_sched, "A", "hardware scheduler "); 6142 6143 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 6144 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6145 sysctl_l2t, "A", "hardware L2 table"); 6146 6147 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 6148 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6149 sysctl_smt, "A", "hardware source MAC table"); 6150 6151 #ifdef INET6 6152 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 6153 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6154 sysctl_clip, "A", "active CLIP table entries"); 6155 #endif 6156 6157 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 6158 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6159 sysctl_lb_stats, "A", "loopback statistics"); 6160 6161 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 6162 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6163 sysctl_meminfo, "A", "memory regions"); 6164 6165 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 6166 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6167 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 6168 "A", "MPS TCAM entries"); 6169 6170 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 6171 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6172 sysctl_path_mtus, "A", "path MTUs"); 6173 6174 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 6175 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6176 sysctl_pm_stats, "A", "PM statistics"); 6177 6178 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 6179 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6180 sysctl_rdma_stats, "A", "RDMA statistics"); 6181 6182 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 6183 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6184 sysctl_tcp_stats, "A", "TCP statistics"); 6185 6186 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 6187 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6188 sysctl_tids, "A", "TID information"); 6189 6190 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 6191 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6192 sysctl_tp_err_stats, "A", "TP error statistics"); 6193 6194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 6195 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 6196 "TP logic analyzer event capture mask"); 6197 6198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 6199 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6200 sysctl_tp_la, "A", "TP logic analyzer"); 6201 6202 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 6203 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6204 sysctl_tx_rate, "A", "Tx rate"); 6205 6206 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 6207 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6208 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 6209 6210 if (chip_id(sc) >= CHELSIO_T5) { 6211 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 6212 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6213 sysctl_wcwr_stats, "A", "write combined work requests"); 6214 } 6215 6216 #ifdef TCP_OFFLOAD 6217 if (is_offload(sc)) { 6218 int i; 6219 char s[4]; 6220 6221 /* 6222 * dev.t4nex.X.toe. 6223 */ 6224 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 6225 NULL, "TOE parameters"); 6226 children = SYSCTL_CHILDREN(oid); 6227 6228 sc->tt.cong_algorithm = -1; 6229 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 6230 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 6231 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 6232 "3 = highspeed)"); 6233 6234 sc->tt.sndbuf = -1; 6235 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 6236 &sc->tt.sndbuf, 0, "hardware send buffer"); 6237 6238 sc->tt.ddp = 0; 6239 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 6240 &sc->tt.ddp, 0, "DDP allowed"); 6241 6242 sc->tt.rx_coalesce = -1; 6243 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 6244 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 6245 6246 sc->tt.tls = 0; 6247 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 6248 &sc->tt.tls, 0, "Inline TLS allowed"); 6249 6250 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6251 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 6252 "I", "TCP ports that use inline TLS+TOE RX"); 6253 6254 sc->tt.tx_align = -1; 6255 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6256 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6257 6258 sc->tt.tx_zcopy = 0; 6259 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6260 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6261 "Enable zero-copy aio_write(2)"); 6262 6263 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6264 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6265 "cop_managed_offloading", CTLFLAG_RW, 6266 &sc->tt.cop_managed_offloading, 0, 6267 "COP (Connection Offload Policy) controls all TOE offload"); 6268 6269 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6270 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 6271 "TP timer tick (us)"); 6272 6273 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6274 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 6275 "TCP timestamp tick (us)"); 6276 6277 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6278 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 6279 "DACK tick (us)"); 6280 6281 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6282 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 6283 "IU", "DACK timer (us)"); 6284 6285 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6286 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 6287 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 6288 6289 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6290 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 6291 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 6292 6293 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6294 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 6295 sysctl_tp_timer, "LU", "Persist timer min (us)"); 6296 6297 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6298 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 6299 sysctl_tp_timer, "LU", "Persist timer max (us)"); 6300 6301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6302 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 6303 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 6304 6305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6306 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 6307 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 6308 6309 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6310 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 6311 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6312 6313 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6314 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 6315 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 6316 6317 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6318 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 6319 sysctl_tp_shift_cnt, "IU", 6320 "Number of SYN retransmissions before abort"); 6321 6322 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6323 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 6324 sysctl_tp_shift_cnt, "IU", 6325 "Number of retransmissions before abort"); 6326 6327 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6328 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 6329 sysctl_tp_shift_cnt, "IU", 6330 "Number of keepalive probes before abort"); 6331 6332 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6333 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 6334 children = SYSCTL_CHILDREN(oid); 6335 for (i = 0; i < 16; i++) { 6336 snprintf(s, sizeof(s), "%u", i); 6337 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6338 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 6339 "IU", "TOE retransmit backoff"); 6340 } 6341 } 6342 #endif 6343 } 6344 6345 void 6346 vi_sysctls(struct vi_info *vi) 6347 { 6348 struct sysctl_ctx_list *ctx; 6349 struct sysctl_oid *oid; 6350 struct sysctl_oid_list *children; 6351 6352 ctx = device_get_sysctl_ctx(vi->dev); 6353 6354 /* 6355 * dev.v?(cxgbe|cxl).X. 6356 */ 6357 oid = device_get_sysctl_tree(vi->dev); 6358 children = SYSCTL_CHILDREN(oid); 6359 6360 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6361 vi->viid, "VI identifer"); 6362 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6363 &vi->nrxq, 0, "# of rx queues"); 6364 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6365 &vi->ntxq, 0, "# of tx queues"); 6366 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6367 &vi->first_rxq, 0, "index of first rx queue"); 6368 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6369 &vi->first_txq, 0, "index of first tx queue"); 6370 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 6371 vi->rss_base, "start of RSS indirection table"); 6372 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6373 vi->rss_size, "size of RSS indirection table"); 6374 6375 if (IS_MAIN_VI(vi)) { 6376 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6377 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 6378 "Reserve queue 0 for non-flowid packets"); 6379 } 6380 6381 #ifdef TCP_OFFLOAD 6382 if (vi->nofldrxq != 0) { 6383 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6384 &vi->nofldrxq, 0, 6385 "# of rx queues for offloaded TCP connections"); 6386 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6387 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6388 "index of first TOE rx queue"); 6389 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6390 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6391 sysctl_holdoff_tmr_idx_ofld, "I", 6392 "holdoff timer index for TOE queues"); 6393 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6394 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6395 sysctl_holdoff_pktc_idx_ofld, "I", 6396 "holdoff packet counter index for TOE queues"); 6397 } 6398 #endif 6399 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6400 if (vi->nofldtxq != 0) { 6401 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6402 &vi->nofldtxq, 0, 6403 "# of tx queues for TOE/ETHOFLD"); 6404 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6405 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6406 "index of first TOE/ETHOFLD tx queue"); 6407 } 6408 #endif 6409 #ifdef DEV_NETMAP 6410 if (vi->nnmrxq != 0) { 6411 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6412 &vi->nnmrxq, 0, "# of netmap rx queues"); 6413 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6414 &vi->nnmtxq, 0, "# of netmap tx queues"); 6415 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6416 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6417 "index of first netmap rx queue"); 6418 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6419 CTLFLAG_RD, &vi->first_nm_txq, 0, 6420 "index of first netmap tx queue"); 6421 } 6422 #endif 6423 6424 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6425 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 6426 "holdoff timer index"); 6427 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6428 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 6429 "holdoff packet counter index"); 6430 6431 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6432 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 6433 "rx queue size"); 6434 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6435 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 6436 "tx queue size"); 6437 } 6438 6439 static void 6440 cxgbe_sysctls(struct port_info *pi) 6441 { 6442 struct sysctl_ctx_list *ctx; 6443 struct sysctl_oid *oid; 6444 struct sysctl_oid_list *children, *children2; 6445 struct adapter *sc = pi->adapter; 6446 int i; 6447 char name[16]; 6448 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6449 6450 ctx = device_get_sysctl_ctx(pi->dev); 6451 6452 /* 6453 * dev.cxgbe.X. 6454 */ 6455 oid = device_get_sysctl_tree(pi->dev); 6456 children = SYSCTL_CHILDREN(oid); 6457 6458 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 6459 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 6460 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6461 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6462 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 6463 "PHY temperature (in Celsius)"); 6464 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6465 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 6466 "PHY firmware version"); 6467 } 6468 6469 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6470 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 6471 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6472 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 6473 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 6474 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 6475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 6476 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 6477 "autonegotiation (-1 = not supported)"); 6478 6479 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 6480 port_top_speed(pi), "max speed (in Gbps)"); 6481 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 6482 pi->mps_bg_map, "MPS buffer group map"); 6483 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 6484 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 6485 6486 if (sc->flags & IS_VF) 6487 return; 6488 6489 /* 6490 * dev.(cxgbe|cxl).X.tc. 6491 */ 6492 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 6493 "Tx scheduler traffic classes (cl_rl)"); 6494 children2 = SYSCTL_CHILDREN(oid); 6495 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 6496 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 6497 "pktsize for per-flow cl-rl (0 means up to the driver )"); 6498 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 6499 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 6500 "burstsize for per-flow cl-rl (0 means up to the driver)"); 6501 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6502 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6503 6504 snprintf(name, sizeof(name), "%d", i); 6505 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6506 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 6507 "traffic class")); 6508 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 6509 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags, 6510 sysctl_bitfield_8b, "A", "flags"); 6511 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6512 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6513 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6514 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 6515 sysctl_tc_params, "A", "traffic class parameters"); 6516 } 6517 6518 /* 6519 * dev.cxgbe.X.stats. 6520 */ 6521 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 6522 NULL, "port statistics"); 6523 children = SYSCTL_CHILDREN(oid); 6524 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6525 &pi->tx_parse_error, 0, 6526 "# of tx packets with invalid length or # of segments"); 6527 6528 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6529 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6530 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 6531 sysctl_handle_t4_reg64, "QU", desc) 6532 6533 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6534 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6535 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6536 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6537 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6538 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6539 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6540 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6541 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6542 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6543 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 6544 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 6545 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 6546 "# of tx frames in this range", 6547 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 6548 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 6549 "# of tx frames in this range", 6550 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 6551 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 6552 "# of tx frames in this range", 6553 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 6554 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 6555 "# of tx frames in this range", 6556 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 6557 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 6558 "# of tx frames in this range", 6559 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 6560 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 6561 "# of tx frames in this range", 6562 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 6563 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 6564 "# of tx frames in this range", 6565 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 6566 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 6567 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 6568 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 6569 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 6570 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 6571 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 6572 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 6573 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 6574 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 6575 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 6576 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 6577 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 6578 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 6579 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 6580 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 6581 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 6582 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 6583 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 6584 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 6585 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 6586 6587 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 6588 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 6589 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 6590 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 6591 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 6592 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 6593 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 6594 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 6595 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 6596 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 6597 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6598 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6599 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6600 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6601 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6602 "# of frames received with bad FCS", 6603 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6604 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6605 "# of frames received with length error", 6606 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6607 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6608 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6609 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6610 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6611 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6612 "# of rx frames in this range", 6613 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6614 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6615 "# of rx frames in this range", 6616 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6617 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6618 "# of rx frames in this range", 6619 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6620 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6621 "# of rx frames in this range", 6622 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6623 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6624 "# of rx frames in this range", 6625 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6626 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6627 "# of rx frames in this range", 6628 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6629 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6630 "# of rx frames in this range", 6631 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6632 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6633 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6634 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6635 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6636 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6637 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6638 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6639 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6640 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6641 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6642 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6643 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6644 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6645 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6646 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6647 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6648 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6649 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6650 6651 #undef SYSCTL_ADD_T4_REG64 6652 6653 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6654 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6655 &pi->stats.name, desc) 6656 6657 /* We get these from port_stats and they may be stale by up to 1s */ 6658 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6659 "# drops due to buffer-group 0 overflows"); 6660 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6661 "# drops due to buffer-group 1 overflows"); 6662 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6663 "# drops due to buffer-group 2 overflows"); 6664 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6665 "# drops due to buffer-group 3 overflows"); 6666 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6667 "# of buffer-group 0 truncated packets"); 6668 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6669 "# of buffer-group 1 truncated packets"); 6670 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6671 "# of buffer-group 2 truncated packets"); 6672 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6673 "# of buffer-group 3 truncated packets"); 6674 6675 #undef SYSCTL_ADD_T4_PORTSTAT 6676 6677 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6678 CTLFLAG_RD, &pi->tx_tls_records, 6679 "# of TLS records transmitted"); 6680 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6681 CTLFLAG_RD, &pi->tx_tls_octets, 6682 "# of payload octets in transmitted TLS records"); 6683 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6684 CTLFLAG_RD, &pi->rx_tls_records, 6685 "# of TLS records received"); 6686 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6687 CTLFLAG_RD, &pi->rx_tls_octets, 6688 "# of payload octets in received TLS records"); 6689 } 6690 6691 static int 6692 sysctl_int_array(SYSCTL_HANDLER_ARGS) 6693 { 6694 int rc, *i, space = 0; 6695 struct sbuf sb; 6696 6697 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6698 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6699 if (space) 6700 sbuf_printf(&sb, " "); 6701 sbuf_printf(&sb, "%d", *i); 6702 space = 1; 6703 } 6704 rc = sbuf_finish(&sb); 6705 sbuf_delete(&sb); 6706 return (rc); 6707 } 6708 6709 static int 6710 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 6711 { 6712 int rc; 6713 struct sbuf *sb; 6714 6715 rc = sysctl_wire_old_buffer(req, 0); 6716 if (rc != 0) 6717 return(rc); 6718 6719 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6720 if (sb == NULL) 6721 return (ENOMEM); 6722 6723 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 6724 rc = sbuf_finish(sb); 6725 sbuf_delete(sb); 6726 6727 return (rc); 6728 } 6729 6730 static int 6731 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 6732 { 6733 int rc; 6734 struct sbuf *sb; 6735 6736 rc = sysctl_wire_old_buffer(req, 0); 6737 if (rc != 0) 6738 return(rc); 6739 6740 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6741 if (sb == NULL) 6742 return (ENOMEM); 6743 6744 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 6745 rc = sbuf_finish(sb); 6746 sbuf_delete(sb); 6747 6748 return (rc); 6749 } 6750 6751 static int 6752 sysctl_btphy(SYSCTL_HANDLER_ARGS) 6753 { 6754 struct port_info *pi = arg1; 6755 int op = arg2; 6756 struct adapter *sc = pi->adapter; 6757 u_int v; 6758 int rc; 6759 6760 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6761 if (rc) 6762 return (rc); 6763 /* XXX: magic numbers */ 6764 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6765 &v); 6766 end_synchronized_op(sc, 0); 6767 if (rc) 6768 return (rc); 6769 if (op == 0) 6770 v /= 256; 6771 6772 rc = sysctl_handle_int(oidp, &v, 0, req); 6773 return (rc); 6774 } 6775 6776 static int 6777 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6778 { 6779 struct vi_info *vi = arg1; 6780 int rc, val; 6781 6782 val = vi->rsrv_noflowq; 6783 rc = sysctl_handle_int(oidp, &val, 0, req); 6784 if (rc != 0 || req->newptr == NULL) 6785 return (rc); 6786 6787 if ((val >= 1) && (vi->ntxq > 1)) 6788 vi->rsrv_noflowq = 1; 6789 else 6790 vi->rsrv_noflowq = 0; 6791 6792 return (rc); 6793 } 6794 6795 static int 6796 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6797 { 6798 struct vi_info *vi = arg1; 6799 struct adapter *sc = vi->pi->adapter; 6800 int idx, rc, i; 6801 struct sge_rxq *rxq; 6802 uint8_t v; 6803 6804 idx = vi->tmr_idx; 6805 6806 rc = sysctl_handle_int(oidp, &idx, 0, req); 6807 if (rc != 0 || req->newptr == NULL) 6808 return (rc); 6809 6810 if (idx < 0 || idx >= SGE_NTIMERS) 6811 return (EINVAL); 6812 6813 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6814 "t4tmr"); 6815 if (rc) 6816 return (rc); 6817 6818 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6819 for_each_rxq(vi, i, rxq) { 6820 #ifdef atomic_store_rel_8 6821 atomic_store_rel_8(&rxq->iq.intr_params, v); 6822 #else 6823 rxq->iq.intr_params = v; 6824 #endif 6825 } 6826 vi->tmr_idx = idx; 6827 6828 end_synchronized_op(sc, LOCK_HELD); 6829 return (0); 6830 } 6831 6832 static int 6833 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6834 { 6835 struct vi_info *vi = arg1; 6836 struct adapter *sc = vi->pi->adapter; 6837 int idx, rc; 6838 6839 idx = vi->pktc_idx; 6840 6841 rc = sysctl_handle_int(oidp, &idx, 0, req); 6842 if (rc != 0 || req->newptr == NULL) 6843 return (rc); 6844 6845 if (idx < -1 || idx >= SGE_NCOUNTERS) 6846 return (EINVAL); 6847 6848 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6849 "t4pktc"); 6850 if (rc) 6851 return (rc); 6852 6853 if (vi->flags & VI_INIT_DONE) 6854 rc = EBUSY; /* cannot be changed once the queues are created */ 6855 else 6856 vi->pktc_idx = idx; 6857 6858 end_synchronized_op(sc, LOCK_HELD); 6859 return (rc); 6860 } 6861 6862 static int 6863 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6864 { 6865 struct vi_info *vi = arg1; 6866 struct adapter *sc = vi->pi->adapter; 6867 int qsize, rc; 6868 6869 qsize = vi->qsize_rxq; 6870 6871 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6872 if (rc != 0 || req->newptr == NULL) 6873 return (rc); 6874 6875 if (qsize < 128 || (qsize & 7)) 6876 return (EINVAL); 6877 6878 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6879 "t4rxqs"); 6880 if (rc) 6881 return (rc); 6882 6883 if (vi->flags & VI_INIT_DONE) 6884 rc = EBUSY; /* cannot be changed once the queues are created */ 6885 else 6886 vi->qsize_rxq = qsize; 6887 6888 end_synchronized_op(sc, LOCK_HELD); 6889 return (rc); 6890 } 6891 6892 static int 6893 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6894 { 6895 struct vi_info *vi = arg1; 6896 struct adapter *sc = vi->pi->adapter; 6897 int qsize, rc; 6898 6899 qsize = vi->qsize_txq; 6900 6901 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6902 if (rc != 0 || req->newptr == NULL) 6903 return (rc); 6904 6905 if (qsize < 128 || qsize > 65536) 6906 return (EINVAL); 6907 6908 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6909 "t4txqs"); 6910 if (rc) 6911 return (rc); 6912 6913 if (vi->flags & VI_INIT_DONE) 6914 rc = EBUSY; /* cannot be changed once the queues are created */ 6915 else 6916 vi->qsize_txq = qsize; 6917 6918 end_synchronized_op(sc, LOCK_HELD); 6919 return (rc); 6920 } 6921 6922 static int 6923 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6924 { 6925 struct port_info *pi = arg1; 6926 struct adapter *sc = pi->adapter; 6927 struct link_config *lc = &pi->link_cfg; 6928 int rc; 6929 6930 if (req->newptr == NULL) { 6931 struct sbuf *sb; 6932 static char *bits = "\20\1RX\2TX\3AUTO"; 6933 6934 rc = sysctl_wire_old_buffer(req, 0); 6935 if (rc != 0) 6936 return(rc); 6937 6938 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6939 if (sb == NULL) 6940 return (ENOMEM); 6941 6942 if (lc->link_ok) { 6943 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 6944 (lc->requested_fc & PAUSE_AUTONEG), bits); 6945 } else { 6946 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 6947 PAUSE_RX | PAUSE_AUTONEG), bits); 6948 } 6949 rc = sbuf_finish(sb); 6950 sbuf_delete(sb); 6951 } else { 6952 char s[2]; 6953 int n; 6954 6955 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 6956 PAUSE_AUTONEG)); 6957 s[1] = 0; 6958 6959 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6960 if (rc != 0) 6961 return(rc); 6962 6963 if (s[1] != 0) 6964 return (EINVAL); 6965 if (s[0] < '0' || s[0] > '9') 6966 return (EINVAL); /* not a number */ 6967 n = s[0] - '0'; 6968 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 6969 return (EINVAL); /* some other bit is set too */ 6970 6971 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6972 "t4PAUSE"); 6973 if (rc) 6974 return (rc); 6975 PORT_LOCK(pi); 6976 lc->requested_fc = n; 6977 fixup_link_config(pi); 6978 if (pi->up_vis > 0) 6979 rc = apply_link_config(pi); 6980 set_current_media(pi); 6981 PORT_UNLOCK(pi); 6982 end_synchronized_op(sc, 0); 6983 } 6984 6985 return (rc); 6986 } 6987 6988 static int 6989 sysctl_fec(SYSCTL_HANDLER_ARGS) 6990 { 6991 struct port_info *pi = arg1; 6992 struct adapter *sc = pi->adapter; 6993 struct link_config *lc = &pi->link_cfg; 6994 int rc; 6995 int8_t old; 6996 6997 if (req->newptr == NULL) { 6998 struct sbuf *sb; 6999 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO"; 7000 7001 rc = sysctl_wire_old_buffer(req, 0); 7002 if (rc != 0) 7003 return(rc); 7004 7005 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7006 if (sb == NULL) 7007 return (ENOMEM); 7008 7009 /* 7010 * Display the requested_fec when the link is down -- the actual 7011 * FEC makes sense only when the link is up. 7012 */ 7013 if (lc->link_ok) { 7014 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 7015 (lc->requested_fec & FEC_AUTO), bits); 7016 } else { 7017 sbuf_printf(sb, "%b", lc->requested_fec, bits); 7018 } 7019 rc = sbuf_finish(sb); 7020 sbuf_delete(sb); 7021 } else { 7022 char s[3]; 7023 int n; 7024 7025 snprintf(s, sizeof(s), "%d", 7026 lc->requested_fec == FEC_AUTO ? -1 : 7027 lc->requested_fec & M_FW_PORT_CAP32_FEC); 7028 7029 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7030 if (rc != 0) 7031 return(rc); 7032 7033 n = strtol(&s[0], NULL, 0); 7034 if (n < 0 || n & FEC_AUTO) 7035 n = FEC_AUTO; 7036 else { 7037 if (n & ~M_FW_PORT_CAP32_FEC) 7038 return (EINVAL);/* some other bit is set too */ 7039 if (!powerof2(n)) 7040 return (EINVAL);/* one bit can be set at most */ 7041 } 7042 7043 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7044 "t4fec"); 7045 if (rc) 7046 return (rc); 7047 PORT_LOCK(pi); 7048 old = lc->requested_fec; 7049 if (n == FEC_AUTO) 7050 lc->requested_fec = FEC_AUTO; 7051 else if (n == 0) 7052 lc->requested_fec = FEC_NONE; 7053 else { 7054 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) != 7055 lc->supported) { 7056 rc = ENOTSUP; 7057 goto done; 7058 } 7059 lc->requested_fec = n; 7060 } 7061 fixup_link_config(pi); 7062 if (pi->up_vis > 0) { 7063 rc = apply_link_config(pi); 7064 if (rc != 0) { 7065 lc->requested_fec = old; 7066 if (rc == FW_EPROTO) 7067 rc = ENOTSUP; 7068 } 7069 } 7070 done: 7071 PORT_UNLOCK(pi); 7072 end_synchronized_op(sc, 0); 7073 } 7074 7075 return (rc); 7076 } 7077 7078 static int 7079 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 7080 { 7081 struct port_info *pi = arg1; 7082 struct adapter *sc = pi->adapter; 7083 struct link_config *lc = &pi->link_cfg; 7084 int rc, val; 7085 7086 if (lc->supported & FW_PORT_CAP32_ANEG) 7087 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 7088 else 7089 val = -1; 7090 rc = sysctl_handle_int(oidp, &val, 0, req); 7091 if (rc != 0 || req->newptr == NULL) 7092 return (rc); 7093 if (val == 0) 7094 val = AUTONEG_DISABLE; 7095 else if (val == 1) 7096 val = AUTONEG_ENABLE; 7097 else 7098 val = AUTONEG_AUTO; 7099 7100 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7101 "t4aneg"); 7102 if (rc) 7103 return (rc); 7104 PORT_LOCK(pi); 7105 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) { 7106 rc = ENOTSUP; 7107 goto done; 7108 } 7109 lc->requested_aneg = val; 7110 fixup_link_config(pi); 7111 if (pi->up_vis > 0) 7112 rc = apply_link_config(pi); 7113 set_current_media(pi); 7114 done: 7115 PORT_UNLOCK(pi); 7116 end_synchronized_op(sc, 0); 7117 return (rc); 7118 } 7119 7120 static int 7121 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 7122 { 7123 struct adapter *sc = arg1; 7124 int reg = arg2; 7125 uint64_t val; 7126 7127 val = t4_read_reg64(sc, reg); 7128 7129 return (sysctl_handle_64(oidp, &val, 0, req)); 7130 } 7131 7132 static int 7133 sysctl_temperature(SYSCTL_HANDLER_ARGS) 7134 { 7135 struct adapter *sc = arg1; 7136 int rc, t; 7137 uint32_t param, val; 7138 7139 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 7140 if (rc) 7141 return (rc); 7142 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7143 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7144 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 7145 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7146 end_synchronized_op(sc, 0); 7147 if (rc) 7148 return (rc); 7149 7150 /* unknown is returned as 0 but we display -1 in that case */ 7151 t = val == 0 ? -1 : val; 7152 7153 rc = sysctl_handle_int(oidp, &t, 0, req); 7154 return (rc); 7155 } 7156 7157 static int 7158 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 7159 { 7160 struct adapter *sc = arg1; 7161 struct sbuf *sb; 7162 int rc; 7163 uint32_t param, val; 7164 7165 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 7166 if (rc) 7167 return (rc); 7168 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7169 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 7170 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7171 end_synchronized_op(sc, 0); 7172 if (rc) 7173 return (rc); 7174 7175 rc = sysctl_wire_old_buffer(req, 0); 7176 if (rc != 0) 7177 return (rc); 7178 7179 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7180 if (sb == NULL) 7181 return (ENOMEM); 7182 7183 if (val == 0xffffffff) { 7184 /* Only debug and custom firmwares report load averages. */ 7185 sbuf_printf(sb, "not available"); 7186 } else { 7187 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 7188 (val >> 16) & 0xff); 7189 } 7190 rc = sbuf_finish(sb); 7191 sbuf_delete(sb); 7192 7193 return (rc); 7194 } 7195 7196 static int 7197 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 7198 { 7199 struct adapter *sc = arg1; 7200 struct sbuf *sb; 7201 int rc, i; 7202 uint16_t incr[NMTUS][NCCTRL_WIN]; 7203 static const char *dec_fac[] = { 7204 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 7205 "0.9375" 7206 }; 7207 7208 rc = sysctl_wire_old_buffer(req, 0); 7209 if (rc != 0) 7210 return (rc); 7211 7212 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7213 if (sb == NULL) 7214 return (ENOMEM); 7215 7216 t4_read_cong_tbl(sc, incr); 7217 7218 for (i = 0; i < NCCTRL_WIN; ++i) { 7219 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 7220 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 7221 incr[5][i], incr[6][i], incr[7][i]); 7222 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 7223 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 7224 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 7225 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 7226 } 7227 7228 rc = sbuf_finish(sb); 7229 sbuf_delete(sb); 7230 7231 return (rc); 7232 } 7233 7234 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 7235 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 7236 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 7237 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 7238 }; 7239 7240 static int 7241 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 7242 { 7243 struct adapter *sc = arg1; 7244 struct sbuf *sb; 7245 int rc, i, n, qid = arg2; 7246 uint32_t *buf, *p; 7247 char *qtype; 7248 u_int cim_num_obq = sc->chip_params->cim_num_obq; 7249 7250 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 7251 ("%s: bad qid %d\n", __func__, qid)); 7252 7253 if (qid < CIM_NUM_IBQ) { 7254 /* inbound queue */ 7255 qtype = "IBQ"; 7256 n = 4 * CIM_IBQ_SIZE; 7257 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7258 rc = t4_read_cim_ibq(sc, qid, buf, n); 7259 } else { 7260 /* outbound queue */ 7261 qtype = "OBQ"; 7262 qid -= CIM_NUM_IBQ; 7263 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7264 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7265 rc = t4_read_cim_obq(sc, qid, buf, n); 7266 } 7267 7268 if (rc < 0) { 7269 rc = -rc; 7270 goto done; 7271 } 7272 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7273 7274 rc = sysctl_wire_old_buffer(req, 0); 7275 if (rc != 0) 7276 goto done; 7277 7278 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7279 if (sb == NULL) { 7280 rc = ENOMEM; 7281 goto done; 7282 } 7283 7284 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7285 for (i = 0, p = buf; i < n; i += 16, p += 4) 7286 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7287 p[2], p[3]); 7288 7289 rc = sbuf_finish(sb); 7290 sbuf_delete(sb); 7291 done: 7292 free(buf, M_CXGBE); 7293 return (rc); 7294 } 7295 7296 static void 7297 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7298 { 7299 uint32_t *p; 7300 7301 sbuf_printf(sb, "Status Data PC%s", 7302 cfg & F_UPDBGLACAPTPCONLY ? "" : 7303 " LS0Stat LS0Addr LS0Data"); 7304 7305 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7306 if (cfg & F_UPDBGLACAPTPCONLY) { 7307 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7308 p[6], p[7]); 7309 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7310 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7311 p[4] & 0xff, p[5] >> 8); 7312 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7313 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7314 p[1] & 0xf, p[2] >> 4); 7315 } else { 7316 sbuf_printf(sb, 7317 "\n %02x %x%07x %x%07x %08x %08x " 7318 "%08x%08x%08x%08x", 7319 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7320 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7321 p[6], p[7]); 7322 } 7323 } 7324 } 7325 7326 static void 7327 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7328 { 7329 uint32_t *p; 7330 7331 sbuf_printf(sb, "Status Inst Data PC%s", 7332 cfg & F_UPDBGLACAPTPCONLY ? "" : 7333 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7334 7335 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7336 if (cfg & F_UPDBGLACAPTPCONLY) { 7337 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7338 p[3] & 0xff, p[2], p[1], p[0]); 7339 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7340 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7341 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7342 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7343 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7344 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7345 p[6] >> 16); 7346 } else { 7347 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7348 "%08x %08x %08x %08x %08x %08x", 7349 (p[9] >> 16) & 0xff, 7350 p[9] & 0xffff, p[8] >> 16, 7351 p[8] & 0xffff, p[7] >> 16, 7352 p[7] & 0xffff, p[6] >> 16, 7353 p[2], p[1], p[0], p[5], p[4], p[3]); 7354 } 7355 } 7356 } 7357 7358 static int 7359 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 7360 { 7361 uint32_t cfg, *buf; 7362 int rc; 7363 7364 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7365 if (rc != 0) 7366 return (rc); 7367 7368 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7369 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7370 M_ZERO | flags); 7371 if (buf == NULL) 7372 return (ENOMEM); 7373 7374 rc = -t4_cim_read_la(sc, buf, NULL); 7375 if (rc != 0) 7376 goto done; 7377 if (chip_id(sc) < CHELSIO_T6) 7378 sbuf_cim_la4(sc, sb, buf, cfg); 7379 else 7380 sbuf_cim_la6(sc, sb, buf, cfg); 7381 7382 done: 7383 free(buf, M_CXGBE); 7384 return (rc); 7385 } 7386 7387 static int 7388 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 7389 { 7390 struct adapter *sc = arg1; 7391 struct sbuf *sb; 7392 int rc; 7393 7394 rc = sysctl_wire_old_buffer(req, 0); 7395 if (rc != 0) 7396 return (rc); 7397 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7398 if (sb == NULL) 7399 return (ENOMEM); 7400 7401 rc = sbuf_cim_la(sc, sb, M_WAITOK); 7402 if (rc == 0) 7403 rc = sbuf_finish(sb); 7404 sbuf_delete(sb); 7405 return (rc); 7406 } 7407 7408 bool 7409 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose) 7410 { 7411 struct sbuf sb; 7412 int rc; 7413 7414 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7415 return (false); 7416 rc = sbuf_cim_la(sc, &sb, M_NOWAIT); 7417 if (rc == 0) { 7418 rc = sbuf_finish(&sb); 7419 if (rc == 0) { 7420 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s", 7421 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7422 } 7423 } 7424 sbuf_delete(&sb); 7425 return (false); 7426 } 7427 7428 static int 7429 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 7430 { 7431 struct adapter *sc = arg1; 7432 u_int i; 7433 struct sbuf *sb; 7434 uint32_t *buf, *p; 7435 int rc; 7436 7437 rc = sysctl_wire_old_buffer(req, 0); 7438 if (rc != 0) 7439 return (rc); 7440 7441 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7442 if (sb == NULL) 7443 return (ENOMEM); 7444 7445 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 7446 M_ZERO | M_WAITOK); 7447 7448 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 7449 p = buf; 7450 7451 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7452 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 7453 p[1], p[0]); 7454 } 7455 7456 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 7457 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7458 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 7459 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 7460 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 7461 (p[1] >> 2) | ((p[2] & 3) << 30), 7462 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 7463 p[0] & 1); 7464 } 7465 7466 rc = sbuf_finish(sb); 7467 sbuf_delete(sb); 7468 free(buf, M_CXGBE); 7469 return (rc); 7470 } 7471 7472 static int 7473 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 7474 { 7475 struct adapter *sc = arg1; 7476 u_int i; 7477 struct sbuf *sb; 7478 uint32_t *buf, *p; 7479 int rc; 7480 7481 rc = sysctl_wire_old_buffer(req, 0); 7482 if (rc != 0) 7483 return (rc); 7484 7485 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7486 if (sb == NULL) 7487 return (ENOMEM); 7488 7489 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 7490 M_ZERO | M_WAITOK); 7491 7492 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 7493 p = buf; 7494 7495 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 7496 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7497 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 7498 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 7499 p[4], p[3], p[2], p[1], p[0]); 7500 } 7501 7502 sbuf_printf(sb, "\n\nCntl ID Data"); 7503 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7504 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 7505 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 7506 } 7507 7508 rc = sbuf_finish(sb); 7509 sbuf_delete(sb); 7510 free(buf, M_CXGBE); 7511 return (rc); 7512 } 7513 7514 static int 7515 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 7516 { 7517 struct adapter *sc = arg1; 7518 struct sbuf *sb; 7519 int rc, i; 7520 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7521 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7522 uint16_t thres[CIM_NUM_IBQ]; 7523 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 7524 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 7525 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 7526 7527 cim_num_obq = sc->chip_params->cim_num_obq; 7528 if (is_t4(sc)) { 7529 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 7530 obq_rdaddr = A_UP_OBQ_0_REALADDR; 7531 } else { 7532 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 7533 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 7534 } 7535 nq = CIM_NUM_IBQ + cim_num_obq; 7536 7537 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 7538 if (rc == 0) 7539 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 7540 if (rc != 0) 7541 return (rc); 7542 7543 t4_read_cimq_cfg(sc, base, size, thres); 7544 7545 rc = sysctl_wire_old_buffer(req, 0); 7546 if (rc != 0) 7547 return (rc); 7548 7549 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7550 if (sb == NULL) 7551 return (ENOMEM); 7552 7553 sbuf_printf(sb, 7554 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 7555 7556 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 7557 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 7558 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 7559 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7560 G_QUEREMFLITS(p[2]) * 16); 7561 for ( ; i < nq; i++, p += 4, wr += 2) 7562 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 7563 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 7564 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7565 G_QUEREMFLITS(p[2]) * 16); 7566 7567 rc = sbuf_finish(sb); 7568 sbuf_delete(sb); 7569 7570 return (rc); 7571 } 7572 7573 static int 7574 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 7575 { 7576 struct adapter *sc = arg1; 7577 struct sbuf *sb; 7578 int rc; 7579 struct tp_cpl_stats stats; 7580 7581 rc = sysctl_wire_old_buffer(req, 0); 7582 if (rc != 0) 7583 return (rc); 7584 7585 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7586 if (sb == NULL) 7587 return (ENOMEM); 7588 7589 mtx_lock(&sc->reg_lock); 7590 t4_tp_get_cpl_stats(sc, &stats, 0); 7591 mtx_unlock(&sc->reg_lock); 7592 7593 if (sc->chip_params->nchan > 2) { 7594 sbuf_printf(sb, " channel 0 channel 1" 7595 " channel 2 channel 3"); 7596 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 7597 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 7598 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 7599 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 7600 } else { 7601 sbuf_printf(sb, " channel 0 channel 1"); 7602 sbuf_printf(sb, "\nCPL requests: %10u %10u", 7603 stats.req[0], stats.req[1]); 7604 sbuf_printf(sb, "\nCPL responses: %10u %10u", 7605 stats.rsp[0], stats.rsp[1]); 7606 } 7607 7608 rc = sbuf_finish(sb); 7609 sbuf_delete(sb); 7610 7611 return (rc); 7612 } 7613 7614 static int 7615 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 7616 { 7617 struct adapter *sc = arg1; 7618 struct sbuf *sb; 7619 int rc; 7620 struct tp_usm_stats stats; 7621 7622 rc = sysctl_wire_old_buffer(req, 0); 7623 if (rc != 0) 7624 return(rc); 7625 7626 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7627 if (sb == NULL) 7628 return (ENOMEM); 7629 7630 t4_get_usm_stats(sc, &stats, 1); 7631 7632 sbuf_printf(sb, "Frames: %u\n", stats.frames); 7633 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 7634 sbuf_printf(sb, "Drops: %u", stats.drops); 7635 7636 rc = sbuf_finish(sb); 7637 sbuf_delete(sb); 7638 7639 return (rc); 7640 } 7641 7642 static const char * const devlog_level_strings[] = { 7643 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 7644 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 7645 [FW_DEVLOG_LEVEL_ERR] = "ERR", 7646 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 7647 [FW_DEVLOG_LEVEL_INFO] = "INFO", 7648 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 7649 }; 7650 7651 static const char * const devlog_facility_strings[] = { 7652 [FW_DEVLOG_FACILITY_CORE] = "CORE", 7653 [FW_DEVLOG_FACILITY_CF] = "CF", 7654 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 7655 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 7656 [FW_DEVLOG_FACILITY_RES] = "RES", 7657 [FW_DEVLOG_FACILITY_HW] = "HW", 7658 [FW_DEVLOG_FACILITY_FLR] = "FLR", 7659 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 7660 [FW_DEVLOG_FACILITY_PHY] = "PHY", 7661 [FW_DEVLOG_FACILITY_MAC] = "MAC", 7662 [FW_DEVLOG_FACILITY_PORT] = "PORT", 7663 [FW_DEVLOG_FACILITY_VI] = "VI", 7664 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 7665 [FW_DEVLOG_FACILITY_ACL] = "ACL", 7666 [FW_DEVLOG_FACILITY_TM] = "TM", 7667 [FW_DEVLOG_FACILITY_QFC] = "QFC", 7668 [FW_DEVLOG_FACILITY_DCB] = "DCB", 7669 [FW_DEVLOG_FACILITY_ETH] = "ETH", 7670 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 7671 [FW_DEVLOG_FACILITY_RI] = "RI", 7672 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 7673 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 7674 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 7675 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 7676 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 7677 }; 7678 7679 static int 7680 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 7681 { 7682 int i, j, rc, nentries, first = 0; 7683 struct devlog_params *dparams = &sc->params.devlog; 7684 struct fw_devlog_e *buf, *e; 7685 uint64_t ftstamp = UINT64_MAX; 7686 7687 if (dparams->addr == 0) 7688 return (ENXIO); 7689 7690 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7691 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 7692 if (buf == NULL) 7693 return (ENOMEM); 7694 7695 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 7696 if (rc != 0) 7697 goto done; 7698 7699 nentries = dparams->size / sizeof(struct fw_devlog_e); 7700 for (i = 0; i < nentries; i++) { 7701 e = &buf[i]; 7702 7703 if (e->timestamp == 0) 7704 break; /* end */ 7705 7706 e->timestamp = be64toh(e->timestamp); 7707 e->seqno = be32toh(e->seqno); 7708 for (j = 0; j < 8; j++) 7709 e->params[j] = be32toh(e->params[j]); 7710 7711 if (e->timestamp < ftstamp) { 7712 ftstamp = e->timestamp; 7713 first = i; 7714 } 7715 } 7716 7717 if (buf[first].timestamp == 0) 7718 goto done; /* nothing in the log */ 7719 7720 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7721 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7722 7723 i = first; 7724 do { 7725 e = &buf[i]; 7726 if (e->timestamp == 0) 7727 break; /* end */ 7728 7729 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7730 e->seqno, e->timestamp, 7731 (e->level < nitems(devlog_level_strings) ? 7732 devlog_level_strings[e->level] : "UNKNOWN"), 7733 (e->facility < nitems(devlog_facility_strings) ? 7734 devlog_facility_strings[e->facility] : "UNKNOWN")); 7735 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7736 e->params[2], e->params[3], e->params[4], 7737 e->params[5], e->params[6], e->params[7]); 7738 7739 if (++i == nentries) 7740 i = 0; 7741 } while (i != first); 7742 done: 7743 free(buf, M_CXGBE); 7744 return (rc); 7745 } 7746 7747 static int 7748 sysctl_devlog(SYSCTL_HANDLER_ARGS) 7749 { 7750 struct adapter *sc = arg1; 7751 int rc; 7752 struct sbuf *sb; 7753 7754 rc = sysctl_wire_old_buffer(req, 0); 7755 if (rc != 0) 7756 return (rc); 7757 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7758 if (sb == NULL) 7759 return (ENOMEM); 7760 7761 rc = sbuf_devlog(sc, sb, M_WAITOK); 7762 if (rc == 0) 7763 rc = sbuf_finish(sb); 7764 sbuf_delete(sb); 7765 return (rc); 7766 } 7767 7768 void 7769 t4_os_dump_devlog(struct adapter *sc) 7770 { 7771 int rc; 7772 struct sbuf sb; 7773 7774 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7775 return; 7776 rc = sbuf_devlog(sc, &sb, M_NOWAIT); 7777 if (rc == 0) { 7778 rc = sbuf_finish(&sb); 7779 if (rc == 0) { 7780 log(LOG_DEBUG, "%s: device log follows.\n%s", 7781 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7782 } 7783 } 7784 sbuf_delete(&sb); 7785 } 7786 7787 static int 7788 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7789 { 7790 struct adapter *sc = arg1; 7791 struct sbuf *sb; 7792 int rc; 7793 struct tp_fcoe_stats stats[MAX_NCHAN]; 7794 int i, nchan = sc->chip_params->nchan; 7795 7796 rc = sysctl_wire_old_buffer(req, 0); 7797 if (rc != 0) 7798 return (rc); 7799 7800 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7801 if (sb == NULL) 7802 return (ENOMEM); 7803 7804 for (i = 0; i < nchan; i++) 7805 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7806 7807 if (nchan > 2) { 7808 sbuf_printf(sb, " channel 0 channel 1" 7809 " channel 2 channel 3"); 7810 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7811 stats[0].octets_ddp, stats[1].octets_ddp, 7812 stats[2].octets_ddp, stats[3].octets_ddp); 7813 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7814 stats[0].frames_ddp, stats[1].frames_ddp, 7815 stats[2].frames_ddp, stats[3].frames_ddp); 7816 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7817 stats[0].frames_drop, stats[1].frames_drop, 7818 stats[2].frames_drop, stats[3].frames_drop); 7819 } else { 7820 sbuf_printf(sb, " channel 0 channel 1"); 7821 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7822 stats[0].octets_ddp, stats[1].octets_ddp); 7823 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7824 stats[0].frames_ddp, stats[1].frames_ddp); 7825 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7826 stats[0].frames_drop, stats[1].frames_drop); 7827 } 7828 7829 rc = sbuf_finish(sb); 7830 sbuf_delete(sb); 7831 7832 return (rc); 7833 } 7834 7835 static int 7836 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7837 { 7838 struct adapter *sc = arg1; 7839 struct sbuf *sb; 7840 int rc, i; 7841 unsigned int map, kbps, ipg, mode; 7842 unsigned int pace_tab[NTX_SCHED]; 7843 7844 rc = sysctl_wire_old_buffer(req, 0); 7845 if (rc != 0) 7846 return (rc); 7847 7848 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7849 if (sb == NULL) 7850 return (ENOMEM); 7851 7852 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7853 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7854 t4_read_pace_tbl(sc, pace_tab); 7855 7856 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7857 "Class IPG (0.1 ns) Flow IPG (us)"); 7858 7859 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7860 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7861 sbuf_printf(sb, "\n %u %-5s %u ", i, 7862 (mode & (1 << i)) ? "flow" : "class", map & 3); 7863 if (kbps) 7864 sbuf_printf(sb, "%9u ", kbps); 7865 else 7866 sbuf_printf(sb, " disabled "); 7867 7868 if (ipg) 7869 sbuf_printf(sb, "%13u ", ipg); 7870 else 7871 sbuf_printf(sb, " disabled "); 7872 7873 if (pace_tab[i]) 7874 sbuf_printf(sb, "%10u", pace_tab[i]); 7875 else 7876 sbuf_printf(sb, " disabled"); 7877 } 7878 7879 rc = sbuf_finish(sb); 7880 sbuf_delete(sb); 7881 7882 return (rc); 7883 } 7884 7885 static int 7886 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7887 { 7888 struct adapter *sc = arg1; 7889 struct sbuf *sb; 7890 int rc, i, j; 7891 uint64_t *p0, *p1; 7892 struct lb_port_stats s[2]; 7893 static const char *stat_name[] = { 7894 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7895 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7896 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7897 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7898 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7899 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7900 "BG2FramesTrunc:", "BG3FramesTrunc:" 7901 }; 7902 7903 rc = sysctl_wire_old_buffer(req, 0); 7904 if (rc != 0) 7905 return (rc); 7906 7907 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7908 if (sb == NULL) 7909 return (ENOMEM); 7910 7911 memset(s, 0, sizeof(s)); 7912 7913 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7914 t4_get_lb_stats(sc, i, &s[0]); 7915 t4_get_lb_stats(sc, i + 1, &s[1]); 7916 7917 p0 = &s[0].octets; 7918 p1 = &s[1].octets; 7919 sbuf_printf(sb, "%s Loopback %u" 7920 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7921 7922 for (j = 0; j < nitems(stat_name); j++) 7923 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7924 *p0++, *p1++); 7925 } 7926 7927 rc = sbuf_finish(sb); 7928 sbuf_delete(sb); 7929 7930 return (rc); 7931 } 7932 7933 static int 7934 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7935 { 7936 int rc = 0; 7937 struct port_info *pi = arg1; 7938 struct link_config *lc = &pi->link_cfg; 7939 struct sbuf *sb; 7940 7941 rc = sysctl_wire_old_buffer(req, 0); 7942 if (rc != 0) 7943 return(rc); 7944 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7945 if (sb == NULL) 7946 return (ENOMEM); 7947 7948 if (lc->link_ok || lc->link_down_rc == 255) 7949 sbuf_printf(sb, "n/a"); 7950 else 7951 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7952 7953 rc = sbuf_finish(sb); 7954 sbuf_delete(sb); 7955 7956 return (rc); 7957 } 7958 7959 struct mem_desc { 7960 unsigned int base; 7961 unsigned int limit; 7962 unsigned int idx; 7963 }; 7964 7965 static int 7966 mem_desc_cmp(const void *a, const void *b) 7967 { 7968 return ((const struct mem_desc *)a)->base - 7969 ((const struct mem_desc *)b)->base; 7970 } 7971 7972 static void 7973 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7974 unsigned int to) 7975 { 7976 unsigned int size; 7977 7978 if (from == to) 7979 return; 7980 7981 size = to - from + 1; 7982 if (size == 0) 7983 return; 7984 7985 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7986 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7987 } 7988 7989 static int 7990 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7991 { 7992 struct adapter *sc = arg1; 7993 struct sbuf *sb; 7994 int rc, i, n; 7995 uint32_t lo, hi, used, alloc; 7996 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7997 static const char *region[] = { 7998 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 7999 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 8000 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 8001 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 8002 "RQUDP region:", "PBL region:", "TXPBL region:", 8003 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 8004 "On-chip queues:", "TLS keys:", 8005 }; 8006 struct mem_desc avail[4]; 8007 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 8008 struct mem_desc *md = mem; 8009 8010 rc = sysctl_wire_old_buffer(req, 0); 8011 if (rc != 0) 8012 return (rc); 8013 8014 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8015 if (sb == NULL) 8016 return (ENOMEM); 8017 8018 for (i = 0; i < nitems(mem); i++) { 8019 mem[i].limit = 0; 8020 mem[i].idx = i; 8021 } 8022 8023 /* Find and sort the populated memory ranges */ 8024 i = 0; 8025 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 8026 if (lo & F_EDRAM0_ENABLE) { 8027 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 8028 avail[i].base = G_EDRAM0_BASE(hi) << 20; 8029 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 8030 avail[i].idx = 0; 8031 i++; 8032 } 8033 if (lo & F_EDRAM1_ENABLE) { 8034 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 8035 avail[i].base = G_EDRAM1_BASE(hi) << 20; 8036 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 8037 avail[i].idx = 1; 8038 i++; 8039 } 8040 if (lo & F_EXT_MEM_ENABLE) { 8041 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 8042 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 8043 avail[i].limit = avail[i].base + 8044 (G_EXT_MEM_SIZE(hi) << 20); 8045 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 8046 i++; 8047 } 8048 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 8049 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 8050 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 8051 avail[i].limit = avail[i].base + 8052 (G_EXT_MEM1_SIZE(hi) << 20); 8053 avail[i].idx = 4; 8054 i++; 8055 } 8056 if (!i) /* no memory available */ 8057 return 0; 8058 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 8059 8060 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 8061 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 8062 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 8063 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 8064 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 8065 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 8066 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 8067 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 8068 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 8069 8070 /* the next few have explicit upper bounds */ 8071 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 8072 md->limit = md->base - 1 + 8073 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 8074 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 8075 md++; 8076 8077 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 8078 md->limit = md->base - 1 + 8079 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 8080 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 8081 md++; 8082 8083 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8084 if (chip_id(sc) <= CHELSIO_T5) 8085 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 8086 else 8087 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 8088 md->limit = 0; 8089 } else { 8090 md->base = 0; 8091 md->idx = nitems(region); /* hide it */ 8092 } 8093 md++; 8094 8095 #define ulp_region(reg) \ 8096 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 8097 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 8098 8099 ulp_region(RX_ISCSI); 8100 ulp_region(RX_TDDP); 8101 ulp_region(TX_TPT); 8102 ulp_region(RX_STAG); 8103 ulp_region(RX_RQ); 8104 ulp_region(RX_RQUDP); 8105 ulp_region(RX_PBL); 8106 ulp_region(TX_PBL); 8107 #undef ulp_region 8108 8109 md->base = 0; 8110 md->idx = nitems(region); 8111 if (!is_t4(sc)) { 8112 uint32_t size = 0; 8113 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 8114 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 8115 8116 if (is_t5(sc)) { 8117 if (sge_ctrl & F_VFIFO_ENABLE) 8118 size = G_DBVFIFO_SIZE(fifo_size); 8119 } else 8120 size = G_T6_DBVFIFO_SIZE(fifo_size); 8121 8122 if (size) { 8123 md->base = G_BASEADDR(t4_read_reg(sc, 8124 A_SGE_DBVFIFO_BADDR)); 8125 md->limit = md->base + (size << 2) - 1; 8126 } 8127 } 8128 md++; 8129 8130 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 8131 md->limit = 0; 8132 md++; 8133 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 8134 md->limit = 0; 8135 md++; 8136 8137 md->base = sc->vres.ocq.start; 8138 if (sc->vres.ocq.size) 8139 md->limit = md->base + sc->vres.ocq.size - 1; 8140 else 8141 md->idx = nitems(region); /* hide it */ 8142 md++; 8143 8144 md->base = sc->vres.key.start; 8145 if (sc->vres.key.size) 8146 md->limit = md->base + sc->vres.key.size - 1; 8147 else 8148 md->idx = nitems(region); /* hide it */ 8149 md++; 8150 8151 /* add any address-space holes, there can be up to 3 */ 8152 for (n = 0; n < i - 1; n++) 8153 if (avail[n].limit < avail[n + 1].base) 8154 (md++)->base = avail[n].limit; 8155 if (avail[n].limit) 8156 (md++)->base = avail[n].limit; 8157 8158 n = md - mem; 8159 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 8160 8161 for (lo = 0; lo < i; lo++) 8162 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 8163 avail[lo].limit - 1); 8164 8165 sbuf_printf(sb, "\n"); 8166 for (i = 0; i < n; i++) { 8167 if (mem[i].idx >= nitems(region)) 8168 continue; /* skip holes */ 8169 if (!mem[i].limit) 8170 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 8171 mem_region_show(sb, region[mem[i].idx], mem[i].base, 8172 mem[i].limit); 8173 } 8174 8175 sbuf_printf(sb, "\n"); 8176 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 8177 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 8178 mem_region_show(sb, "uP RAM:", lo, hi); 8179 8180 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 8181 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 8182 mem_region_show(sb, "uP Extmem2:", lo, hi); 8183 8184 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 8185 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 8186 G_PMRXMAXPAGE(lo), 8187 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 8188 (lo & F_PMRXNUMCHN) ? 2 : 1); 8189 8190 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 8191 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 8192 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 8193 G_PMTXMAXPAGE(lo), 8194 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 8195 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 8196 sbuf_printf(sb, "%u p-structs\n", 8197 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 8198 8199 for (i = 0; i < 4; i++) { 8200 if (chip_id(sc) > CHELSIO_T5) 8201 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 8202 else 8203 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 8204 if (is_t5(sc)) { 8205 used = G_T5_USED(lo); 8206 alloc = G_T5_ALLOC(lo); 8207 } else { 8208 used = G_USED(lo); 8209 alloc = G_ALLOC(lo); 8210 } 8211 /* For T6 these are MAC buffer groups */ 8212 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 8213 i, used, alloc); 8214 } 8215 for (i = 0; i < sc->chip_params->nchan; i++) { 8216 if (chip_id(sc) > CHELSIO_T5) 8217 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 8218 else 8219 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 8220 if (is_t5(sc)) { 8221 used = G_T5_USED(lo); 8222 alloc = G_T5_ALLOC(lo); 8223 } else { 8224 used = G_USED(lo); 8225 alloc = G_ALLOC(lo); 8226 } 8227 /* For T6 these are MAC buffer groups */ 8228 sbuf_printf(sb, 8229 "\nLoopback %d using %u pages out of %u allocated", 8230 i, used, alloc); 8231 } 8232 8233 rc = sbuf_finish(sb); 8234 sbuf_delete(sb); 8235 8236 return (rc); 8237 } 8238 8239 static inline void 8240 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 8241 { 8242 *mask = x | y; 8243 y = htobe64(y); 8244 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 8245 } 8246 8247 static int 8248 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 8249 { 8250 struct adapter *sc = arg1; 8251 struct sbuf *sb; 8252 int rc, i; 8253 8254 MPASS(chip_id(sc) <= CHELSIO_T5); 8255 8256 rc = sysctl_wire_old_buffer(req, 0); 8257 if (rc != 0) 8258 return (rc); 8259 8260 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8261 if (sb == NULL) 8262 return (ENOMEM); 8263 8264 sbuf_printf(sb, 8265 "Idx Ethernet address Mask Vld Ports PF" 8266 " VF Replication P0 P1 P2 P3 ML"); 8267 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8268 uint64_t tcamx, tcamy, mask; 8269 uint32_t cls_lo, cls_hi; 8270 uint8_t addr[ETHER_ADDR_LEN]; 8271 8272 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 8273 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 8274 if (tcamx & tcamy) 8275 continue; 8276 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8277 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8278 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8279 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 8280 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 8281 addr[3], addr[4], addr[5], (uintmax_t)mask, 8282 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 8283 G_PORTMAP(cls_hi), G_PF(cls_lo), 8284 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 8285 8286 if (cls_lo & F_REPLICATE) { 8287 struct fw_ldst_cmd ldst_cmd; 8288 8289 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8290 ldst_cmd.op_to_addrspace = 8291 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8292 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8293 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8294 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8295 ldst_cmd.u.mps.rplc.fid_idx = 8296 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8297 V_FW_LDST_CMD_IDX(i)); 8298 8299 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8300 "t4mps"); 8301 if (rc) 8302 break; 8303 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8304 sizeof(ldst_cmd), &ldst_cmd); 8305 end_synchronized_op(sc, 0); 8306 8307 if (rc != 0) { 8308 sbuf_printf(sb, "%36d", rc); 8309 rc = 0; 8310 } else { 8311 sbuf_printf(sb, " %08x %08x %08x %08x", 8312 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8313 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8314 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8315 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8316 } 8317 } else 8318 sbuf_printf(sb, "%36s", ""); 8319 8320 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8321 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8322 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8323 } 8324 8325 if (rc) 8326 (void) sbuf_finish(sb); 8327 else 8328 rc = sbuf_finish(sb); 8329 sbuf_delete(sb); 8330 8331 return (rc); 8332 } 8333 8334 static int 8335 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8336 { 8337 struct adapter *sc = arg1; 8338 struct sbuf *sb; 8339 int rc, i; 8340 8341 MPASS(chip_id(sc) > CHELSIO_T5); 8342 8343 rc = sysctl_wire_old_buffer(req, 0); 8344 if (rc != 0) 8345 return (rc); 8346 8347 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8348 if (sb == NULL) 8349 return (ENOMEM); 8350 8351 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8352 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8353 " Replication" 8354 " P0 P1 P2 P3 ML\n"); 8355 8356 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8357 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8358 uint16_t ivlan; 8359 uint64_t tcamx, tcamy, val, mask; 8360 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8361 uint8_t addr[ETHER_ADDR_LEN]; 8362 8363 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 8364 if (i < 256) 8365 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 8366 else 8367 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 8368 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8369 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8370 tcamy = G_DMACH(val) << 32; 8371 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8372 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8373 lookup_type = G_DATALKPTYPE(data2); 8374 port_num = G_DATAPORTNUM(data2); 8375 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8376 /* Inner header VNI */ 8377 vniy = ((data2 & F_DATAVIDH2) << 23) | 8378 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8379 dip_hit = data2 & F_DATADIPHIT; 8380 vlan_vld = 0; 8381 } else { 8382 vniy = 0; 8383 dip_hit = 0; 8384 vlan_vld = data2 & F_DATAVIDH2; 8385 ivlan = G_VIDL(val); 8386 } 8387 8388 ctl |= V_CTLXYBITSEL(1); 8389 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8390 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8391 tcamx = G_DMACH(val) << 32; 8392 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8393 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8394 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8395 /* Inner header VNI mask */ 8396 vnix = ((data2 & F_DATAVIDH2) << 23) | 8397 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8398 } else 8399 vnix = 0; 8400 8401 if (tcamx & tcamy) 8402 continue; 8403 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8404 8405 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8406 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8407 8408 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8409 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8410 "%012jx %06x %06x - - %3c" 8411 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 8412 addr[1], addr[2], addr[3], addr[4], addr[5], 8413 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 8414 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8415 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8416 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8417 } else { 8418 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8419 "%012jx - - ", i, addr[0], addr[1], 8420 addr[2], addr[3], addr[4], addr[5], 8421 (uintmax_t)mask); 8422 8423 if (vlan_vld) 8424 sbuf_printf(sb, "%4u Y ", ivlan); 8425 else 8426 sbuf_printf(sb, " - N "); 8427 8428 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 8429 lookup_type ? 'I' : 'O', port_num, 8430 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8431 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8432 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8433 } 8434 8435 8436 if (cls_lo & F_T6_REPLICATE) { 8437 struct fw_ldst_cmd ldst_cmd; 8438 8439 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8440 ldst_cmd.op_to_addrspace = 8441 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8442 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8443 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8444 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8445 ldst_cmd.u.mps.rplc.fid_idx = 8446 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8447 V_FW_LDST_CMD_IDX(i)); 8448 8449 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8450 "t6mps"); 8451 if (rc) 8452 break; 8453 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8454 sizeof(ldst_cmd), &ldst_cmd); 8455 end_synchronized_op(sc, 0); 8456 8457 if (rc != 0) { 8458 sbuf_printf(sb, "%72d", rc); 8459 rc = 0; 8460 } else { 8461 sbuf_printf(sb, " %08x %08x %08x %08x" 8462 " %08x %08x %08x %08x", 8463 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 8464 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 8465 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 8466 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 8467 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8468 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8469 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8470 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8471 } 8472 } else 8473 sbuf_printf(sb, "%72s", ""); 8474 8475 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 8476 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 8477 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 8478 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 8479 } 8480 8481 if (rc) 8482 (void) sbuf_finish(sb); 8483 else 8484 rc = sbuf_finish(sb); 8485 sbuf_delete(sb); 8486 8487 return (rc); 8488 } 8489 8490 static int 8491 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 8492 { 8493 struct adapter *sc = arg1; 8494 struct sbuf *sb; 8495 int rc; 8496 uint16_t mtus[NMTUS]; 8497 8498 rc = sysctl_wire_old_buffer(req, 0); 8499 if (rc != 0) 8500 return (rc); 8501 8502 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8503 if (sb == NULL) 8504 return (ENOMEM); 8505 8506 t4_read_mtu_tbl(sc, mtus, NULL); 8507 8508 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 8509 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 8510 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 8511 mtus[14], mtus[15]); 8512 8513 rc = sbuf_finish(sb); 8514 sbuf_delete(sb); 8515 8516 return (rc); 8517 } 8518 8519 static int 8520 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 8521 { 8522 struct adapter *sc = arg1; 8523 struct sbuf *sb; 8524 int rc, i; 8525 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 8526 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 8527 static const char *tx_stats[MAX_PM_NSTATS] = { 8528 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 8529 "Tx FIFO wait", NULL, "Tx latency" 8530 }; 8531 static const char *rx_stats[MAX_PM_NSTATS] = { 8532 "Read:", "Write bypass:", "Write mem:", "Flush:", 8533 "Rx FIFO wait", NULL, "Rx latency" 8534 }; 8535 8536 rc = sysctl_wire_old_buffer(req, 0); 8537 if (rc != 0) 8538 return (rc); 8539 8540 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8541 if (sb == NULL) 8542 return (ENOMEM); 8543 8544 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 8545 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 8546 8547 sbuf_printf(sb, " Tx pcmds Tx bytes"); 8548 for (i = 0; i < 4; i++) { 8549 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8550 tx_cyc[i]); 8551 } 8552 8553 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 8554 for (i = 0; i < 4; i++) { 8555 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8556 rx_cyc[i]); 8557 } 8558 8559 if (chip_id(sc) > CHELSIO_T5) { 8560 sbuf_printf(sb, 8561 "\n Total wait Total occupancy"); 8562 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8563 tx_cyc[i]); 8564 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8565 rx_cyc[i]); 8566 8567 i += 2; 8568 MPASS(i < nitems(tx_stats)); 8569 8570 sbuf_printf(sb, 8571 "\n Reads Total wait"); 8572 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8573 tx_cyc[i]); 8574 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8575 rx_cyc[i]); 8576 } 8577 8578 rc = sbuf_finish(sb); 8579 sbuf_delete(sb); 8580 8581 return (rc); 8582 } 8583 8584 static int 8585 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 8586 { 8587 struct adapter *sc = arg1; 8588 struct sbuf *sb; 8589 int rc; 8590 struct tp_rdma_stats stats; 8591 8592 rc = sysctl_wire_old_buffer(req, 0); 8593 if (rc != 0) 8594 return (rc); 8595 8596 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8597 if (sb == NULL) 8598 return (ENOMEM); 8599 8600 mtx_lock(&sc->reg_lock); 8601 t4_tp_get_rdma_stats(sc, &stats, 0); 8602 mtx_unlock(&sc->reg_lock); 8603 8604 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 8605 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 8606 8607 rc = sbuf_finish(sb); 8608 sbuf_delete(sb); 8609 8610 return (rc); 8611 } 8612 8613 static int 8614 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 8615 { 8616 struct adapter *sc = arg1; 8617 struct sbuf *sb; 8618 int rc; 8619 struct tp_tcp_stats v4, v6; 8620 8621 rc = sysctl_wire_old_buffer(req, 0); 8622 if (rc != 0) 8623 return (rc); 8624 8625 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8626 if (sb == NULL) 8627 return (ENOMEM); 8628 8629 mtx_lock(&sc->reg_lock); 8630 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 8631 mtx_unlock(&sc->reg_lock); 8632 8633 sbuf_printf(sb, 8634 " IP IPv6\n"); 8635 sbuf_printf(sb, "OutRsts: %20u %20u\n", 8636 v4.tcp_out_rsts, v6.tcp_out_rsts); 8637 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 8638 v4.tcp_in_segs, v6.tcp_in_segs); 8639 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 8640 v4.tcp_out_segs, v6.tcp_out_segs); 8641 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 8642 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 8643 8644 rc = sbuf_finish(sb); 8645 sbuf_delete(sb); 8646 8647 return (rc); 8648 } 8649 8650 static int 8651 sysctl_tids(SYSCTL_HANDLER_ARGS) 8652 { 8653 struct adapter *sc = arg1; 8654 struct sbuf *sb; 8655 int rc; 8656 struct tid_info *t = &sc->tids; 8657 8658 rc = sysctl_wire_old_buffer(req, 0); 8659 if (rc != 0) 8660 return (rc); 8661 8662 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8663 if (sb == NULL) 8664 return (ENOMEM); 8665 8666 if (t->natids) { 8667 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 8668 t->atids_in_use); 8669 } 8670 8671 if (t->nhpftids) { 8672 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 8673 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 8674 } 8675 8676 if (t->ntids) { 8677 sbuf_printf(sb, "TID range: "); 8678 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8679 uint32_t b, hb; 8680 8681 if (chip_id(sc) <= CHELSIO_T5) { 8682 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 8683 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 8684 } else { 8685 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 8686 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 8687 } 8688 8689 if (b) 8690 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 8691 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 8692 } else 8693 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 8694 sbuf_printf(sb, ", in use: %u\n", 8695 atomic_load_acq_int(&t->tids_in_use)); 8696 } 8697 8698 if (t->nstids) { 8699 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 8700 t->stid_base + t->nstids - 1, t->stids_in_use); 8701 } 8702 8703 if (t->nftids) { 8704 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 8705 t->ftid_end, t->ftids_in_use); 8706 } 8707 8708 if (t->netids) { 8709 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 8710 t->etid_base + t->netids - 1, t->etids_in_use); 8711 } 8712 8713 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 8714 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 8715 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 8716 8717 rc = sbuf_finish(sb); 8718 sbuf_delete(sb); 8719 8720 return (rc); 8721 } 8722 8723 static int 8724 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 8725 { 8726 struct adapter *sc = arg1; 8727 struct sbuf *sb; 8728 int rc; 8729 struct tp_err_stats stats; 8730 8731 rc = sysctl_wire_old_buffer(req, 0); 8732 if (rc != 0) 8733 return (rc); 8734 8735 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8736 if (sb == NULL) 8737 return (ENOMEM); 8738 8739 mtx_lock(&sc->reg_lock); 8740 t4_tp_get_err_stats(sc, &stats, 0); 8741 mtx_unlock(&sc->reg_lock); 8742 8743 if (sc->chip_params->nchan > 2) { 8744 sbuf_printf(sb, " channel 0 channel 1" 8745 " channel 2 channel 3\n"); 8746 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8747 stats.mac_in_errs[0], stats.mac_in_errs[1], 8748 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8749 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8750 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8751 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8752 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8753 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8754 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8755 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8756 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8757 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8758 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8759 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8760 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8761 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8762 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8763 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8764 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8765 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8766 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8767 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8768 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8769 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8770 } else { 8771 sbuf_printf(sb, " channel 0 channel 1\n"); 8772 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8773 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8774 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8775 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8776 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8777 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8778 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8779 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8780 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8781 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8782 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8783 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8784 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8785 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8786 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8787 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8788 } 8789 8790 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8791 stats.ofld_no_neigh, stats.ofld_cong_defer); 8792 8793 rc = sbuf_finish(sb); 8794 sbuf_delete(sb); 8795 8796 return (rc); 8797 } 8798 8799 static int 8800 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8801 { 8802 struct adapter *sc = arg1; 8803 struct tp_params *tpp = &sc->params.tp; 8804 u_int mask; 8805 int rc; 8806 8807 mask = tpp->la_mask >> 16; 8808 rc = sysctl_handle_int(oidp, &mask, 0, req); 8809 if (rc != 0 || req->newptr == NULL) 8810 return (rc); 8811 if (mask > 0xffff) 8812 return (EINVAL); 8813 tpp->la_mask = mask << 16; 8814 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8815 8816 return (0); 8817 } 8818 8819 struct field_desc { 8820 const char *name; 8821 u_int start; 8822 u_int width; 8823 }; 8824 8825 static void 8826 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8827 { 8828 char buf[32]; 8829 int line_size = 0; 8830 8831 while (f->name) { 8832 uint64_t mask = (1ULL << f->width) - 1; 8833 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8834 ((uintmax_t)v >> f->start) & mask); 8835 8836 if (line_size + len >= 79) { 8837 line_size = 8; 8838 sbuf_printf(sb, "\n "); 8839 } 8840 sbuf_printf(sb, "%s ", buf); 8841 line_size += len + 1; 8842 f++; 8843 } 8844 sbuf_printf(sb, "\n"); 8845 } 8846 8847 static const struct field_desc tp_la0[] = { 8848 { "RcfOpCodeOut", 60, 4 }, 8849 { "State", 56, 4 }, 8850 { "WcfState", 52, 4 }, 8851 { "RcfOpcSrcOut", 50, 2 }, 8852 { "CRxError", 49, 1 }, 8853 { "ERxError", 48, 1 }, 8854 { "SanityFailed", 47, 1 }, 8855 { "SpuriousMsg", 46, 1 }, 8856 { "FlushInputMsg", 45, 1 }, 8857 { "FlushInputCpl", 44, 1 }, 8858 { "RssUpBit", 43, 1 }, 8859 { "RssFilterHit", 42, 1 }, 8860 { "Tid", 32, 10 }, 8861 { "InitTcb", 31, 1 }, 8862 { "LineNumber", 24, 7 }, 8863 { "Emsg", 23, 1 }, 8864 { "EdataOut", 22, 1 }, 8865 { "Cmsg", 21, 1 }, 8866 { "CdataOut", 20, 1 }, 8867 { "EreadPdu", 19, 1 }, 8868 { "CreadPdu", 18, 1 }, 8869 { "TunnelPkt", 17, 1 }, 8870 { "RcfPeerFin", 16, 1 }, 8871 { "RcfReasonOut", 12, 4 }, 8872 { "TxCchannel", 10, 2 }, 8873 { "RcfTxChannel", 8, 2 }, 8874 { "RxEchannel", 6, 2 }, 8875 { "RcfRxChannel", 5, 1 }, 8876 { "RcfDataOutSrdy", 4, 1 }, 8877 { "RxDvld", 3, 1 }, 8878 { "RxOoDvld", 2, 1 }, 8879 { "RxCongestion", 1, 1 }, 8880 { "TxCongestion", 0, 1 }, 8881 { NULL } 8882 }; 8883 8884 static const struct field_desc tp_la1[] = { 8885 { "CplCmdIn", 56, 8 }, 8886 { "CplCmdOut", 48, 8 }, 8887 { "ESynOut", 47, 1 }, 8888 { "EAckOut", 46, 1 }, 8889 { "EFinOut", 45, 1 }, 8890 { "ERstOut", 44, 1 }, 8891 { "SynIn", 43, 1 }, 8892 { "AckIn", 42, 1 }, 8893 { "FinIn", 41, 1 }, 8894 { "RstIn", 40, 1 }, 8895 { "DataIn", 39, 1 }, 8896 { "DataInVld", 38, 1 }, 8897 { "PadIn", 37, 1 }, 8898 { "RxBufEmpty", 36, 1 }, 8899 { "RxDdp", 35, 1 }, 8900 { "RxFbCongestion", 34, 1 }, 8901 { "TxFbCongestion", 33, 1 }, 8902 { "TxPktSumSrdy", 32, 1 }, 8903 { "RcfUlpType", 28, 4 }, 8904 { "Eread", 27, 1 }, 8905 { "Ebypass", 26, 1 }, 8906 { "Esave", 25, 1 }, 8907 { "Static0", 24, 1 }, 8908 { "Cread", 23, 1 }, 8909 { "Cbypass", 22, 1 }, 8910 { "Csave", 21, 1 }, 8911 { "CPktOut", 20, 1 }, 8912 { "RxPagePoolFull", 18, 2 }, 8913 { "RxLpbkPkt", 17, 1 }, 8914 { "TxLpbkPkt", 16, 1 }, 8915 { "RxVfValid", 15, 1 }, 8916 { "SynLearned", 14, 1 }, 8917 { "SetDelEntry", 13, 1 }, 8918 { "SetInvEntry", 12, 1 }, 8919 { "CpcmdDvld", 11, 1 }, 8920 { "CpcmdSave", 10, 1 }, 8921 { "RxPstructsFull", 8, 2 }, 8922 { "EpcmdDvld", 7, 1 }, 8923 { "EpcmdFlush", 6, 1 }, 8924 { "EpcmdTrimPrefix", 5, 1 }, 8925 { "EpcmdTrimPostfix", 4, 1 }, 8926 { "ERssIp4Pkt", 3, 1 }, 8927 { "ERssIp6Pkt", 2, 1 }, 8928 { "ERssTcpUdpPkt", 1, 1 }, 8929 { "ERssFceFipPkt", 0, 1 }, 8930 { NULL } 8931 }; 8932 8933 static const struct field_desc tp_la2[] = { 8934 { "CplCmdIn", 56, 8 }, 8935 { "MpsVfVld", 55, 1 }, 8936 { "MpsPf", 52, 3 }, 8937 { "MpsVf", 44, 8 }, 8938 { "SynIn", 43, 1 }, 8939 { "AckIn", 42, 1 }, 8940 { "FinIn", 41, 1 }, 8941 { "RstIn", 40, 1 }, 8942 { "DataIn", 39, 1 }, 8943 { "DataInVld", 38, 1 }, 8944 { "PadIn", 37, 1 }, 8945 { "RxBufEmpty", 36, 1 }, 8946 { "RxDdp", 35, 1 }, 8947 { "RxFbCongestion", 34, 1 }, 8948 { "TxFbCongestion", 33, 1 }, 8949 { "TxPktSumSrdy", 32, 1 }, 8950 { "RcfUlpType", 28, 4 }, 8951 { "Eread", 27, 1 }, 8952 { "Ebypass", 26, 1 }, 8953 { "Esave", 25, 1 }, 8954 { "Static0", 24, 1 }, 8955 { "Cread", 23, 1 }, 8956 { "Cbypass", 22, 1 }, 8957 { "Csave", 21, 1 }, 8958 { "CPktOut", 20, 1 }, 8959 { "RxPagePoolFull", 18, 2 }, 8960 { "RxLpbkPkt", 17, 1 }, 8961 { "TxLpbkPkt", 16, 1 }, 8962 { "RxVfValid", 15, 1 }, 8963 { "SynLearned", 14, 1 }, 8964 { "SetDelEntry", 13, 1 }, 8965 { "SetInvEntry", 12, 1 }, 8966 { "CpcmdDvld", 11, 1 }, 8967 { "CpcmdSave", 10, 1 }, 8968 { "RxPstructsFull", 8, 2 }, 8969 { "EpcmdDvld", 7, 1 }, 8970 { "EpcmdFlush", 6, 1 }, 8971 { "EpcmdTrimPrefix", 5, 1 }, 8972 { "EpcmdTrimPostfix", 4, 1 }, 8973 { "ERssIp4Pkt", 3, 1 }, 8974 { "ERssIp6Pkt", 2, 1 }, 8975 { "ERssTcpUdpPkt", 1, 1 }, 8976 { "ERssFceFipPkt", 0, 1 }, 8977 { NULL } 8978 }; 8979 8980 static void 8981 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8982 { 8983 8984 field_desc_show(sb, *p, tp_la0); 8985 } 8986 8987 static void 8988 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8989 { 8990 8991 if (idx) 8992 sbuf_printf(sb, "\n"); 8993 field_desc_show(sb, p[0], tp_la0); 8994 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8995 field_desc_show(sb, p[1], tp_la0); 8996 } 8997 8998 static void 8999 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 9000 { 9001 9002 if (idx) 9003 sbuf_printf(sb, "\n"); 9004 field_desc_show(sb, p[0], tp_la0); 9005 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9006 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 9007 } 9008 9009 static int 9010 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 9011 { 9012 struct adapter *sc = arg1; 9013 struct sbuf *sb; 9014 uint64_t *buf, *p; 9015 int rc; 9016 u_int i, inc; 9017 void (*show_func)(struct sbuf *, uint64_t *, int); 9018 9019 rc = sysctl_wire_old_buffer(req, 0); 9020 if (rc != 0) 9021 return (rc); 9022 9023 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9024 if (sb == NULL) 9025 return (ENOMEM); 9026 9027 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 9028 9029 t4_tp_read_la(sc, buf, NULL); 9030 p = buf; 9031 9032 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 9033 case 2: 9034 inc = 2; 9035 show_func = tp_la_show2; 9036 break; 9037 case 3: 9038 inc = 2; 9039 show_func = tp_la_show3; 9040 break; 9041 default: 9042 inc = 1; 9043 show_func = tp_la_show; 9044 } 9045 9046 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 9047 (*show_func)(sb, p, i); 9048 9049 rc = sbuf_finish(sb); 9050 sbuf_delete(sb); 9051 free(buf, M_CXGBE); 9052 return (rc); 9053 } 9054 9055 static int 9056 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 9057 { 9058 struct adapter *sc = arg1; 9059 struct sbuf *sb; 9060 int rc; 9061 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 9062 9063 rc = sysctl_wire_old_buffer(req, 0); 9064 if (rc != 0) 9065 return (rc); 9066 9067 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9068 if (sb == NULL) 9069 return (ENOMEM); 9070 9071 t4_get_chan_txrate(sc, nrate, orate); 9072 9073 if (sc->chip_params->nchan > 2) { 9074 sbuf_printf(sb, " channel 0 channel 1" 9075 " channel 2 channel 3\n"); 9076 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 9077 nrate[0], nrate[1], nrate[2], nrate[3]); 9078 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 9079 orate[0], orate[1], orate[2], orate[3]); 9080 } else { 9081 sbuf_printf(sb, " channel 0 channel 1\n"); 9082 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 9083 nrate[0], nrate[1]); 9084 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 9085 orate[0], orate[1]); 9086 } 9087 9088 rc = sbuf_finish(sb); 9089 sbuf_delete(sb); 9090 9091 return (rc); 9092 } 9093 9094 static int 9095 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 9096 { 9097 struct adapter *sc = arg1; 9098 struct sbuf *sb; 9099 uint32_t *buf, *p; 9100 int rc, i; 9101 9102 rc = sysctl_wire_old_buffer(req, 0); 9103 if (rc != 0) 9104 return (rc); 9105 9106 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9107 if (sb == NULL) 9108 return (ENOMEM); 9109 9110 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 9111 M_ZERO | M_WAITOK); 9112 9113 t4_ulprx_read_la(sc, buf); 9114 p = buf; 9115 9116 sbuf_printf(sb, " Pcmd Type Message" 9117 " Data"); 9118 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 9119 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 9120 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 9121 } 9122 9123 rc = sbuf_finish(sb); 9124 sbuf_delete(sb); 9125 free(buf, M_CXGBE); 9126 return (rc); 9127 } 9128 9129 static int 9130 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 9131 { 9132 struct adapter *sc = arg1; 9133 struct sbuf *sb; 9134 int rc, v; 9135 9136 MPASS(chip_id(sc) >= CHELSIO_T5); 9137 9138 rc = sysctl_wire_old_buffer(req, 0); 9139 if (rc != 0) 9140 return (rc); 9141 9142 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9143 if (sb == NULL) 9144 return (ENOMEM); 9145 9146 v = t4_read_reg(sc, A_SGE_STAT_CFG); 9147 if (G_STATSOURCE_T5(v) == 7) { 9148 int mode; 9149 9150 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 9151 if (mode == 0) { 9152 sbuf_printf(sb, "total %d, incomplete %d", 9153 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9154 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9155 } else if (mode == 1) { 9156 sbuf_printf(sb, "total %d, data overflow %d", 9157 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9158 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9159 } else { 9160 sbuf_printf(sb, "unknown mode %d", mode); 9161 } 9162 } 9163 rc = sbuf_finish(sb); 9164 sbuf_delete(sb); 9165 9166 return (rc); 9167 } 9168 9169 static int 9170 sysctl_cpus(SYSCTL_HANDLER_ARGS) 9171 { 9172 struct adapter *sc = arg1; 9173 enum cpu_sets op = arg2; 9174 cpuset_t cpuset; 9175 struct sbuf *sb; 9176 int i, rc; 9177 9178 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 9179 9180 CPU_ZERO(&cpuset); 9181 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 9182 if (rc != 0) 9183 return (rc); 9184 9185 rc = sysctl_wire_old_buffer(req, 0); 9186 if (rc != 0) 9187 return (rc); 9188 9189 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9190 if (sb == NULL) 9191 return (ENOMEM); 9192 9193 CPU_FOREACH(i) 9194 sbuf_printf(sb, "%d ", i); 9195 rc = sbuf_finish(sb); 9196 sbuf_delete(sb); 9197 9198 return (rc); 9199 } 9200 9201 #ifdef TCP_OFFLOAD 9202 static int 9203 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 9204 { 9205 struct adapter *sc = arg1; 9206 int *old_ports, *new_ports; 9207 int i, new_count, rc; 9208 9209 if (req->newptr == NULL && req->oldptr == NULL) 9210 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 9211 sizeof(sc->tt.tls_rx_ports[0]))); 9212 9213 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 9214 if (rc) 9215 return (rc); 9216 9217 if (sc->tt.num_tls_rx_ports == 0) { 9218 i = -1; 9219 rc = SYSCTL_OUT(req, &i, sizeof(i)); 9220 } else 9221 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 9222 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 9223 if (rc == 0 && req->newptr != NULL) { 9224 new_count = req->newlen / sizeof(new_ports[0]); 9225 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 9226 M_WAITOK); 9227 rc = SYSCTL_IN(req, new_ports, new_count * 9228 sizeof(new_ports[0])); 9229 if (rc) 9230 goto err; 9231 9232 /* Allow setting to a single '-1' to clear the list. */ 9233 if (new_count == 1 && new_ports[0] == -1) { 9234 ADAPTER_LOCK(sc); 9235 old_ports = sc->tt.tls_rx_ports; 9236 sc->tt.tls_rx_ports = NULL; 9237 sc->tt.num_tls_rx_ports = 0; 9238 ADAPTER_UNLOCK(sc); 9239 free(old_ports, M_CXGBE); 9240 } else { 9241 for (i = 0; i < new_count; i++) { 9242 if (new_ports[i] < 1 || 9243 new_ports[i] > IPPORT_MAX) { 9244 rc = EINVAL; 9245 goto err; 9246 } 9247 } 9248 9249 ADAPTER_LOCK(sc); 9250 old_ports = sc->tt.tls_rx_ports; 9251 sc->tt.tls_rx_ports = new_ports; 9252 sc->tt.num_tls_rx_ports = new_count; 9253 ADAPTER_UNLOCK(sc); 9254 free(old_ports, M_CXGBE); 9255 new_ports = NULL; 9256 } 9257 err: 9258 free(new_ports, M_CXGBE); 9259 } 9260 end_synchronized_op(sc, 0); 9261 return (rc); 9262 } 9263 9264 static void 9265 unit_conv(char *buf, size_t len, u_int val, u_int factor) 9266 { 9267 u_int rem = val % factor; 9268 9269 if (rem == 0) 9270 snprintf(buf, len, "%u", val / factor); 9271 else { 9272 while (rem % 10 == 0) 9273 rem /= 10; 9274 snprintf(buf, len, "%u.%u", val / factor, rem); 9275 } 9276 } 9277 9278 static int 9279 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 9280 { 9281 struct adapter *sc = arg1; 9282 char buf[16]; 9283 u_int res, re; 9284 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9285 9286 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9287 switch (arg2) { 9288 case 0: 9289 /* timer_tick */ 9290 re = G_TIMERRESOLUTION(res); 9291 break; 9292 case 1: 9293 /* TCP timestamp tick */ 9294 re = G_TIMESTAMPRESOLUTION(res); 9295 break; 9296 case 2: 9297 /* DACK tick */ 9298 re = G_DELAYEDACKRESOLUTION(res); 9299 break; 9300 default: 9301 return (EDOOFUS); 9302 } 9303 9304 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9305 9306 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9307 } 9308 9309 static int 9310 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9311 { 9312 struct adapter *sc = arg1; 9313 u_int res, dack_re, v; 9314 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9315 9316 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9317 dack_re = G_DELAYEDACKRESOLUTION(res); 9318 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9319 9320 return (sysctl_handle_int(oidp, &v, 0, req)); 9321 } 9322 9323 static int 9324 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9325 { 9326 struct adapter *sc = arg1; 9327 int reg = arg2; 9328 u_int tre; 9329 u_long tp_tick_us, v; 9330 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9331 9332 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 9333 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 9334 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 9335 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 9336 9337 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 9338 tp_tick_us = (cclk_ps << tre) / 1000000; 9339 9340 if (reg == A_TP_INIT_SRTT) 9341 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 9342 else 9343 v = tp_tick_us * t4_read_reg(sc, reg); 9344 9345 return (sysctl_handle_long(oidp, &v, 0, req)); 9346 } 9347 9348 /* 9349 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 9350 * passed to this function. 9351 */ 9352 static int 9353 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 9354 { 9355 struct adapter *sc = arg1; 9356 int idx = arg2; 9357 u_int v; 9358 9359 MPASS(idx >= 0 && idx <= 24); 9360 9361 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 9362 9363 return (sysctl_handle_int(oidp, &v, 0, req)); 9364 } 9365 9366 static int 9367 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 9368 { 9369 struct adapter *sc = arg1; 9370 int idx = arg2; 9371 u_int shift, v, r; 9372 9373 MPASS(idx >= 0 && idx < 16); 9374 9375 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 9376 shift = (idx & 3) << 3; 9377 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 9378 9379 return (sysctl_handle_int(oidp, &v, 0, req)); 9380 } 9381 9382 static int 9383 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 9384 { 9385 struct vi_info *vi = arg1; 9386 struct adapter *sc = vi->pi->adapter; 9387 int idx, rc, i; 9388 struct sge_ofld_rxq *ofld_rxq; 9389 uint8_t v; 9390 9391 idx = vi->ofld_tmr_idx; 9392 9393 rc = sysctl_handle_int(oidp, &idx, 0, req); 9394 if (rc != 0 || req->newptr == NULL) 9395 return (rc); 9396 9397 if (idx < 0 || idx >= SGE_NTIMERS) 9398 return (EINVAL); 9399 9400 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9401 "t4otmr"); 9402 if (rc) 9403 return (rc); 9404 9405 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 9406 for_each_ofld_rxq(vi, i, ofld_rxq) { 9407 #ifdef atomic_store_rel_8 9408 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 9409 #else 9410 ofld_rxq->iq.intr_params = v; 9411 #endif 9412 } 9413 vi->ofld_tmr_idx = idx; 9414 9415 end_synchronized_op(sc, LOCK_HELD); 9416 return (0); 9417 } 9418 9419 static int 9420 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 9421 { 9422 struct vi_info *vi = arg1; 9423 struct adapter *sc = vi->pi->adapter; 9424 int idx, rc; 9425 9426 idx = vi->ofld_pktc_idx; 9427 9428 rc = sysctl_handle_int(oidp, &idx, 0, req); 9429 if (rc != 0 || req->newptr == NULL) 9430 return (rc); 9431 9432 if (idx < -1 || idx >= SGE_NCOUNTERS) 9433 return (EINVAL); 9434 9435 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9436 "t4opktc"); 9437 if (rc) 9438 return (rc); 9439 9440 if (vi->flags & VI_INIT_DONE) 9441 rc = EBUSY; /* cannot be changed once the queues are created */ 9442 else 9443 vi->ofld_pktc_idx = idx; 9444 9445 end_synchronized_op(sc, LOCK_HELD); 9446 return (rc); 9447 } 9448 #endif 9449 9450 static int 9451 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9452 { 9453 int rc; 9454 9455 if (cntxt->cid > M_CTXTQID) 9456 return (EINVAL); 9457 9458 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9459 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9460 return (EINVAL); 9461 9462 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9463 if (rc) 9464 return (rc); 9465 9466 if (sc->flags & FW_OK) { 9467 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9468 &cntxt->data[0]); 9469 if (rc == 0) 9470 goto done; 9471 } 9472 9473 /* 9474 * Read via firmware failed or wasn't even attempted. Read directly via 9475 * the backdoor. 9476 */ 9477 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9478 done: 9479 end_synchronized_op(sc, 0); 9480 return (rc); 9481 } 9482 9483 static int 9484 load_fw(struct adapter *sc, struct t4_data *fw) 9485 { 9486 int rc; 9487 uint8_t *fw_data; 9488 9489 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9490 if (rc) 9491 return (rc); 9492 9493 /* 9494 * The firmware, with the sole exception of the memory parity error 9495 * handler, runs from memory and not flash. It is almost always safe to 9496 * install a new firmware on a running system. Just set bit 1 in 9497 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9498 */ 9499 if (sc->flags & FULL_INIT_DONE && 9500 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9501 rc = EBUSY; 9502 goto done; 9503 } 9504 9505 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9506 if (fw_data == NULL) { 9507 rc = ENOMEM; 9508 goto done; 9509 } 9510 9511 rc = copyin(fw->data, fw_data, fw->len); 9512 if (rc == 0) 9513 rc = -t4_load_fw(sc, fw_data, fw->len); 9514 9515 free(fw_data, M_CXGBE); 9516 done: 9517 end_synchronized_op(sc, 0); 9518 return (rc); 9519 } 9520 9521 static int 9522 load_cfg(struct adapter *sc, struct t4_data *cfg) 9523 { 9524 int rc; 9525 uint8_t *cfg_data = NULL; 9526 9527 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9528 if (rc) 9529 return (rc); 9530 9531 if (cfg->len == 0) { 9532 /* clear */ 9533 rc = -t4_load_cfg(sc, NULL, 0); 9534 goto done; 9535 } 9536 9537 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9538 if (cfg_data == NULL) { 9539 rc = ENOMEM; 9540 goto done; 9541 } 9542 9543 rc = copyin(cfg->data, cfg_data, cfg->len); 9544 if (rc == 0) 9545 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9546 9547 free(cfg_data, M_CXGBE); 9548 done: 9549 end_synchronized_op(sc, 0); 9550 return (rc); 9551 } 9552 9553 static int 9554 load_boot(struct adapter *sc, struct t4_bootrom *br) 9555 { 9556 int rc; 9557 uint8_t *br_data = NULL; 9558 u_int offset; 9559 9560 if (br->len > 1024 * 1024) 9561 return (EFBIG); 9562 9563 if (br->pf_offset == 0) { 9564 /* pfidx */ 9565 if (br->pfidx_addr > 7) 9566 return (EINVAL); 9567 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9568 A_PCIE_PF_EXPROM_OFST))); 9569 } else if (br->pf_offset == 1) { 9570 /* offset */ 9571 offset = G_OFFSET(br->pfidx_addr); 9572 } else { 9573 return (EINVAL); 9574 } 9575 9576 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9577 if (rc) 9578 return (rc); 9579 9580 if (br->len == 0) { 9581 /* clear */ 9582 rc = -t4_load_boot(sc, NULL, offset, 0); 9583 goto done; 9584 } 9585 9586 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9587 if (br_data == NULL) { 9588 rc = ENOMEM; 9589 goto done; 9590 } 9591 9592 rc = copyin(br->data, br_data, br->len); 9593 if (rc == 0) 9594 rc = -t4_load_boot(sc, br_data, offset, br->len); 9595 9596 free(br_data, M_CXGBE); 9597 done: 9598 end_synchronized_op(sc, 0); 9599 return (rc); 9600 } 9601 9602 static int 9603 load_bootcfg(struct adapter *sc, struct t4_data *bc) 9604 { 9605 int rc; 9606 uint8_t *bc_data = NULL; 9607 9608 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9609 if (rc) 9610 return (rc); 9611 9612 if (bc->len == 0) { 9613 /* clear */ 9614 rc = -t4_load_bootcfg(sc, NULL, 0); 9615 goto done; 9616 } 9617 9618 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9619 if (bc_data == NULL) { 9620 rc = ENOMEM; 9621 goto done; 9622 } 9623 9624 rc = copyin(bc->data, bc_data, bc->len); 9625 if (rc == 0) 9626 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9627 9628 free(bc_data, M_CXGBE); 9629 done: 9630 end_synchronized_op(sc, 0); 9631 return (rc); 9632 } 9633 9634 static int 9635 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9636 { 9637 int rc; 9638 struct cudbg_init *cudbg; 9639 void *handle, *buf; 9640 9641 /* buf is large, don't block if no memory is available */ 9642 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9643 if (buf == NULL) 9644 return (ENOMEM); 9645 9646 handle = cudbg_alloc_handle(); 9647 if (handle == NULL) { 9648 rc = ENOMEM; 9649 goto done; 9650 } 9651 9652 cudbg = cudbg_get_init(handle); 9653 cudbg->adap = sc; 9654 cudbg->print = (cudbg_print_cb)printf; 9655 9656 #ifndef notyet 9657 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9658 __func__, dump->wr_flash, dump->len, dump->data); 9659 #endif 9660 9661 if (dump->wr_flash) 9662 cudbg->use_flash = 1; 9663 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9664 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9665 9666 rc = cudbg_collect(handle, buf, &dump->len); 9667 if (rc != 0) 9668 goto done; 9669 9670 rc = copyout(buf, dump->data, dump->len); 9671 done: 9672 cudbg_free_handle(handle); 9673 free(buf, M_CXGBE); 9674 return (rc); 9675 } 9676 9677 static void 9678 free_offload_policy(struct t4_offload_policy *op) 9679 { 9680 struct offload_rule *r; 9681 int i; 9682 9683 if (op == NULL) 9684 return; 9685 9686 r = &op->rule[0]; 9687 for (i = 0; i < op->nrules; i++, r++) { 9688 free(r->bpf_prog.bf_insns, M_CXGBE); 9689 } 9690 free(op->rule, M_CXGBE); 9691 free(op, M_CXGBE); 9692 } 9693 9694 static int 9695 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9696 { 9697 int i, rc, len; 9698 struct t4_offload_policy *op, *old; 9699 struct bpf_program *bf; 9700 const struct offload_settings *s; 9701 struct offload_rule *r; 9702 void *u; 9703 9704 if (!is_offload(sc)) 9705 return (ENODEV); 9706 9707 if (uop->nrules == 0) { 9708 /* Delete installed policies. */ 9709 op = NULL; 9710 goto set_policy; 9711 } if (uop->nrules > 256) { /* arbitrary */ 9712 return (E2BIG); 9713 } 9714 9715 /* Copy userspace offload policy to kernel */ 9716 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9717 op->nrules = uop->nrules; 9718 len = op->nrules * sizeof(struct offload_rule); 9719 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9720 rc = copyin(uop->rule, op->rule, len); 9721 if (rc) { 9722 free(op->rule, M_CXGBE); 9723 free(op, M_CXGBE); 9724 return (rc); 9725 } 9726 9727 r = &op->rule[0]; 9728 for (i = 0; i < op->nrules; i++, r++) { 9729 9730 /* Validate open_type */ 9731 if (r->open_type != OPEN_TYPE_LISTEN && 9732 r->open_type != OPEN_TYPE_ACTIVE && 9733 r->open_type != OPEN_TYPE_PASSIVE && 9734 r->open_type != OPEN_TYPE_DONTCARE) { 9735 error: 9736 /* 9737 * Rules 0 to i have malloc'd filters that need to be 9738 * freed. Rules i+1 to nrules have userspace pointers 9739 * and should be left alone. 9740 */ 9741 op->nrules = i; 9742 free_offload_policy(op); 9743 return (rc); 9744 } 9745 9746 /* Validate settings */ 9747 s = &r->settings; 9748 if ((s->offload != 0 && s->offload != 1) || 9749 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9750 s->sched_class < -1 || 9751 s->sched_class >= sc->chip_params->nsched_cls) { 9752 rc = EINVAL; 9753 goto error; 9754 } 9755 9756 bf = &r->bpf_prog; 9757 u = bf->bf_insns; /* userspace ptr */ 9758 bf->bf_insns = NULL; 9759 if (bf->bf_len == 0) { 9760 /* legal, matches everything */ 9761 continue; 9762 } 9763 len = bf->bf_len * sizeof(*bf->bf_insns); 9764 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9765 rc = copyin(u, bf->bf_insns, len); 9766 if (rc != 0) 9767 goto error; 9768 9769 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9770 rc = EINVAL; 9771 goto error; 9772 } 9773 } 9774 set_policy: 9775 rw_wlock(&sc->policy_lock); 9776 old = sc->policy; 9777 sc->policy = op; 9778 rw_wunlock(&sc->policy_lock); 9779 free_offload_policy(old); 9780 9781 return (0); 9782 } 9783 9784 #define MAX_READ_BUF_SIZE (128 * 1024) 9785 static int 9786 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9787 { 9788 uint32_t addr, remaining, n; 9789 uint32_t *buf; 9790 int rc; 9791 uint8_t *dst; 9792 9793 rc = validate_mem_range(sc, mr->addr, mr->len); 9794 if (rc != 0) 9795 return (rc); 9796 9797 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9798 addr = mr->addr; 9799 remaining = mr->len; 9800 dst = (void *)mr->data; 9801 9802 while (remaining) { 9803 n = min(remaining, MAX_READ_BUF_SIZE); 9804 read_via_memwin(sc, 2, addr, buf, n); 9805 9806 rc = copyout(buf, dst, n); 9807 if (rc != 0) 9808 break; 9809 9810 dst += n; 9811 remaining -= n; 9812 addr += n; 9813 } 9814 9815 free(buf, M_CXGBE); 9816 return (rc); 9817 } 9818 #undef MAX_READ_BUF_SIZE 9819 9820 static int 9821 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9822 { 9823 int rc; 9824 9825 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9826 return (EINVAL); 9827 9828 if (i2cd->len > sizeof(i2cd->data)) 9829 return (EFBIG); 9830 9831 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9832 if (rc) 9833 return (rc); 9834 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9835 i2cd->offset, i2cd->len, &i2cd->data[0]); 9836 end_synchronized_op(sc, 0); 9837 9838 return (rc); 9839 } 9840 9841 static int 9842 clear_stats(struct adapter *sc, u_int port_id) 9843 { 9844 int i, v, bg_map; 9845 struct port_info *pi; 9846 struct vi_info *vi; 9847 struct sge_rxq *rxq; 9848 struct sge_txq *txq; 9849 struct sge_wrq *wrq; 9850 #ifdef TCP_OFFLOAD 9851 struct sge_ofld_rxq *ofld_rxq; 9852 #endif 9853 9854 if (port_id >= sc->params.nports) 9855 return (EINVAL); 9856 pi = sc->port[port_id]; 9857 if (pi == NULL) 9858 return (EIO); 9859 9860 /* MAC stats */ 9861 t4_clr_port_stats(sc, pi->tx_chan); 9862 pi->tx_parse_error = 0; 9863 pi->tnl_cong_drops = 0; 9864 mtx_lock(&sc->reg_lock); 9865 for_each_vi(pi, v, vi) { 9866 if (vi->flags & VI_INIT_DONE) 9867 t4_clr_vi_stats(sc, vi->vin); 9868 } 9869 bg_map = pi->mps_bg_map; 9870 v = 0; /* reuse */ 9871 while (bg_map) { 9872 i = ffs(bg_map) - 1; 9873 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 9874 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 9875 bg_map &= ~(1 << i); 9876 } 9877 mtx_unlock(&sc->reg_lock); 9878 9879 /* 9880 * Since this command accepts a port, clear stats for 9881 * all VIs on this port. 9882 */ 9883 for_each_vi(pi, v, vi) { 9884 if (vi->flags & VI_INIT_DONE) { 9885 9886 for_each_rxq(vi, i, rxq) { 9887 #if defined(INET) || defined(INET6) 9888 rxq->lro.lro_queued = 0; 9889 rxq->lro.lro_flushed = 0; 9890 #endif 9891 rxq->rxcsum = 0; 9892 rxq->vlan_extraction = 0; 9893 9894 rxq->fl.mbuf_allocated = 0; 9895 rxq->fl.mbuf_inlined = 0; 9896 rxq->fl.cl_allocated = 0; 9897 rxq->fl.cl_recycled = 0; 9898 rxq->fl.cl_fast_recycled = 0; 9899 } 9900 9901 for_each_txq(vi, i, txq) { 9902 txq->txcsum = 0; 9903 txq->tso_wrs = 0; 9904 txq->vlan_insertion = 0; 9905 txq->imm_wrs = 0; 9906 txq->sgl_wrs = 0; 9907 txq->txpkt_wrs = 0; 9908 txq->txpkts0_wrs = 0; 9909 txq->txpkts1_wrs = 0; 9910 txq->txpkts0_pkts = 0; 9911 txq->txpkts1_pkts = 0; 9912 txq->raw_wrs = 0; 9913 mp_ring_reset_stats(txq->r); 9914 } 9915 9916 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 9917 for_each_ofld_txq(vi, i, wrq) { 9918 wrq->tx_wrs_direct = 0; 9919 wrq->tx_wrs_copied = 0; 9920 } 9921 #endif 9922 #ifdef TCP_OFFLOAD 9923 for_each_ofld_rxq(vi, i, ofld_rxq) { 9924 ofld_rxq->fl.mbuf_allocated = 0; 9925 ofld_rxq->fl.mbuf_inlined = 0; 9926 ofld_rxq->fl.cl_allocated = 0; 9927 ofld_rxq->fl.cl_recycled = 0; 9928 ofld_rxq->fl.cl_fast_recycled = 0; 9929 } 9930 #endif 9931 9932 if (IS_MAIN_VI(vi)) { 9933 wrq = &sc->sge.ctrlq[pi->port_id]; 9934 wrq->tx_wrs_direct = 0; 9935 wrq->tx_wrs_copied = 0; 9936 } 9937 } 9938 } 9939 9940 return (0); 9941 } 9942 9943 int 9944 t4_os_find_pci_capability(struct adapter *sc, int cap) 9945 { 9946 int i; 9947 9948 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9949 } 9950 9951 int 9952 t4_os_pci_save_state(struct adapter *sc) 9953 { 9954 device_t dev; 9955 struct pci_devinfo *dinfo; 9956 9957 dev = sc->dev; 9958 dinfo = device_get_ivars(dev); 9959 9960 pci_cfg_save(dev, dinfo, 0); 9961 return (0); 9962 } 9963 9964 int 9965 t4_os_pci_restore_state(struct adapter *sc) 9966 { 9967 device_t dev; 9968 struct pci_devinfo *dinfo; 9969 9970 dev = sc->dev; 9971 dinfo = device_get_ivars(dev); 9972 9973 pci_cfg_restore(dev, dinfo); 9974 return (0); 9975 } 9976 9977 void 9978 t4_os_portmod_changed(struct port_info *pi) 9979 { 9980 struct adapter *sc = pi->adapter; 9981 struct vi_info *vi; 9982 struct ifnet *ifp; 9983 static const char *mod_str[] = { 9984 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9985 }; 9986 9987 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 9988 ("%s: port_type %u", __func__, pi->port_type)); 9989 9990 vi = &pi->vi[0]; 9991 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9992 PORT_LOCK(pi); 9993 build_medialist(pi); 9994 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 9995 fixup_link_config(pi); 9996 apply_link_config(pi); 9997 } 9998 PORT_UNLOCK(pi); 9999 end_synchronized_op(sc, LOCK_HELD); 10000 } 10001 10002 ifp = vi->ifp; 10003 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 10004 if_printf(ifp, "transceiver unplugged.\n"); 10005 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 10006 if_printf(ifp, "unknown transceiver inserted.\n"); 10007 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 10008 if_printf(ifp, "unsupported transceiver inserted.\n"); 10009 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 10010 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 10011 port_top_speed(pi), mod_str[pi->mod_type]); 10012 } else { 10013 if_printf(ifp, "transceiver (type %d) inserted.\n", 10014 pi->mod_type); 10015 } 10016 } 10017 10018 void 10019 t4_os_link_changed(struct port_info *pi) 10020 { 10021 struct vi_info *vi; 10022 struct ifnet *ifp; 10023 struct link_config *lc; 10024 int v; 10025 10026 PORT_LOCK_ASSERT_OWNED(pi); 10027 10028 for_each_vi(pi, v, vi) { 10029 ifp = vi->ifp; 10030 if (ifp == NULL) 10031 continue; 10032 10033 lc = &pi->link_cfg; 10034 if (lc->link_ok) { 10035 ifp->if_baudrate = IF_Mbps(lc->speed); 10036 if_link_state_change(ifp, LINK_STATE_UP); 10037 } else { 10038 if_link_state_change(ifp, LINK_STATE_DOWN); 10039 } 10040 } 10041 } 10042 10043 void 10044 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 10045 { 10046 struct adapter *sc; 10047 10048 sx_slock(&t4_list_lock); 10049 SLIST_FOREACH(sc, &t4_list, link) { 10050 /* 10051 * func should not make any assumptions about what state sc is 10052 * in - the only guarantee is that sc->sc_lock is a valid lock. 10053 */ 10054 func(sc, arg); 10055 } 10056 sx_sunlock(&t4_list_lock); 10057 } 10058 10059 static int 10060 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 10061 struct thread *td) 10062 { 10063 int rc; 10064 struct adapter *sc = dev->si_drv1; 10065 10066 rc = priv_check(td, PRIV_DRIVER); 10067 if (rc != 0) 10068 return (rc); 10069 10070 switch (cmd) { 10071 case CHELSIO_T4_GETREG: { 10072 struct t4_reg *edata = (struct t4_reg *)data; 10073 10074 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 10075 return (EFAULT); 10076 10077 if (edata->size == 4) 10078 edata->val = t4_read_reg(sc, edata->addr); 10079 else if (edata->size == 8) 10080 edata->val = t4_read_reg64(sc, edata->addr); 10081 else 10082 return (EINVAL); 10083 10084 break; 10085 } 10086 case CHELSIO_T4_SETREG: { 10087 struct t4_reg *edata = (struct t4_reg *)data; 10088 10089 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 10090 return (EFAULT); 10091 10092 if (edata->size == 4) { 10093 if (edata->val & 0xffffffff00000000) 10094 return (EINVAL); 10095 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 10096 } else if (edata->size == 8) 10097 t4_write_reg64(sc, edata->addr, edata->val); 10098 else 10099 return (EINVAL); 10100 break; 10101 } 10102 case CHELSIO_T4_REGDUMP: { 10103 struct t4_regdump *regs = (struct t4_regdump *)data; 10104 int reglen = t4_get_regs_len(sc); 10105 uint8_t *buf; 10106 10107 if (regs->len < reglen) { 10108 regs->len = reglen; /* hint to the caller */ 10109 return (ENOBUFS); 10110 } 10111 10112 regs->len = reglen; 10113 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 10114 get_regs(sc, regs, buf); 10115 rc = copyout(buf, regs->data, reglen); 10116 free(buf, M_CXGBE); 10117 break; 10118 } 10119 case CHELSIO_T4_GET_FILTER_MODE: 10120 rc = get_filter_mode(sc, (uint32_t *)data); 10121 break; 10122 case CHELSIO_T4_SET_FILTER_MODE: 10123 rc = set_filter_mode(sc, *(uint32_t *)data); 10124 break; 10125 case CHELSIO_T4_GET_FILTER: 10126 rc = get_filter(sc, (struct t4_filter *)data); 10127 break; 10128 case CHELSIO_T4_SET_FILTER: 10129 rc = set_filter(sc, (struct t4_filter *)data); 10130 break; 10131 case CHELSIO_T4_DEL_FILTER: 10132 rc = del_filter(sc, (struct t4_filter *)data); 10133 break; 10134 case CHELSIO_T4_GET_SGE_CONTEXT: 10135 rc = get_sge_context(sc, (struct t4_sge_context *)data); 10136 break; 10137 case CHELSIO_T4_LOAD_FW: 10138 rc = load_fw(sc, (struct t4_data *)data); 10139 break; 10140 case CHELSIO_T4_GET_MEM: 10141 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 10142 break; 10143 case CHELSIO_T4_GET_I2C: 10144 rc = read_i2c(sc, (struct t4_i2c_data *)data); 10145 break; 10146 case CHELSIO_T4_CLEAR_STATS: 10147 rc = clear_stats(sc, *(uint32_t *)data); 10148 break; 10149 case CHELSIO_T4_SCHED_CLASS: 10150 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 10151 break; 10152 case CHELSIO_T4_SCHED_QUEUE: 10153 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 10154 break; 10155 case CHELSIO_T4_GET_TRACER: 10156 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 10157 break; 10158 case CHELSIO_T4_SET_TRACER: 10159 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 10160 break; 10161 case CHELSIO_T4_LOAD_CFG: 10162 rc = load_cfg(sc, (struct t4_data *)data); 10163 break; 10164 case CHELSIO_T4_LOAD_BOOT: 10165 rc = load_boot(sc, (struct t4_bootrom *)data); 10166 break; 10167 case CHELSIO_T4_LOAD_BOOTCFG: 10168 rc = load_bootcfg(sc, (struct t4_data *)data); 10169 break; 10170 case CHELSIO_T4_CUDBG_DUMP: 10171 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 10172 break; 10173 case CHELSIO_T4_SET_OFLD_POLICY: 10174 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 10175 break; 10176 default: 10177 rc = ENOTTY; 10178 } 10179 10180 return (rc); 10181 } 10182 10183 #ifdef TCP_OFFLOAD 10184 static int 10185 toe_capability(struct vi_info *vi, int enable) 10186 { 10187 int rc; 10188 struct port_info *pi = vi->pi; 10189 struct adapter *sc = pi->adapter; 10190 10191 ASSERT_SYNCHRONIZED_OP(sc); 10192 10193 if (!is_offload(sc)) 10194 return (ENODEV); 10195 10196 if (enable) { 10197 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 10198 /* TOE is already enabled. */ 10199 return (0); 10200 } 10201 10202 /* 10203 * We need the port's queues around so that we're able to send 10204 * and receive CPLs to/from the TOE even if the ifnet for this 10205 * port has never been UP'd administratively. 10206 */ 10207 if (!(vi->flags & VI_INIT_DONE)) { 10208 rc = vi_full_init(vi); 10209 if (rc) 10210 return (rc); 10211 } 10212 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 10213 rc = vi_full_init(&pi->vi[0]); 10214 if (rc) 10215 return (rc); 10216 } 10217 10218 if (isset(&sc->offload_map, pi->port_id)) { 10219 /* TOE is enabled on another VI of this port. */ 10220 pi->uld_vis++; 10221 return (0); 10222 } 10223 10224 if (!uld_active(sc, ULD_TOM)) { 10225 rc = t4_activate_uld(sc, ULD_TOM); 10226 if (rc == EAGAIN) { 10227 log(LOG_WARNING, 10228 "You must kldload t4_tom.ko before trying " 10229 "to enable TOE on a cxgbe interface.\n"); 10230 } 10231 if (rc != 0) 10232 return (rc); 10233 KASSERT(sc->tom_softc != NULL, 10234 ("%s: TOM activated but softc NULL", __func__)); 10235 KASSERT(uld_active(sc, ULD_TOM), 10236 ("%s: TOM activated but flag not set", __func__)); 10237 } 10238 10239 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 10240 if (!uld_active(sc, ULD_IWARP)) 10241 (void) t4_activate_uld(sc, ULD_IWARP); 10242 if (!uld_active(sc, ULD_ISCSI)) 10243 (void) t4_activate_uld(sc, ULD_ISCSI); 10244 10245 pi->uld_vis++; 10246 setbit(&sc->offload_map, pi->port_id); 10247 } else { 10248 pi->uld_vis--; 10249 10250 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 10251 return (0); 10252 10253 KASSERT(uld_active(sc, ULD_TOM), 10254 ("%s: TOM never initialized?", __func__)); 10255 clrbit(&sc->offload_map, pi->port_id); 10256 } 10257 10258 return (0); 10259 } 10260 10261 /* 10262 * Add an upper layer driver to the global list. 10263 */ 10264 int 10265 t4_register_uld(struct uld_info *ui) 10266 { 10267 int rc = 0; 10268 struct uld_info *u; 10269 10270 sx_xlock(&t4_uld_list_lock); 10271 SLIST_FOREACH(u, &t4_uld_list, link) { 10272 if (u->uld_id == ui->uld_id) { 10273 rc = EEXIST; 10274 goto done; 10275 } 10276 } 10277 10278 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 10279 ui->refcount = 0; 10280 done: 10281 sx_xunlock(&t4_uld_list_lock); 10282 return (rc); 10283 } 10284 10285 int 10286 t4_unregister_uld(struct uld_info *ui) 10287 { 10288 int rc = EINVAL; 10289 struct uld_info *u; 10290 10291 sx_xlock(&t4_uld_list_lock); 10292 10293 SLIST_FOREACH(u, &t4_uld_list, link) { 10294 if (u == ui) { 10295 if (ui->refcount > 0) { 10296 rc = EBUSY; 10297 goto done; 10298 } 10299 10300 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10301 rc = 0; 10302 goto done; 10303 } 10304 } 10305 done: 10306 sx_xunlock(&t4_uld_list_lock); 10307 return (rc); 10308 } 10309 10310 int 10311 t4_activate_uld(struct adapter *sc, int id) 10312 { 10313 int rc; 10314 struct uld_info *ui; 10315 10316 ASSERT_SYNCHRONIZED_OP(sc); 10317 10318 if (id < 0 || id > ULD_MAX) 10319 return (EINVAL); 10320 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 10321 10322 sx_slock(&t4_uld_list_lock); 10323 10324 SLIST_FOREACH(ui, &t4_uld_list, link) { 10325 if (ui->uld_id == id) { 10326 if (!(sc->flags & FULL_INIT_DONE)) { 10327 rc = adapter_full_init(sc); 10328 if (rc != 0) 10329 break; 10330 } 10331 10332 rc = ui->activate(sc); 10333 if (rc == 0) { 10334 setbit(&sc->active_ulds, id); 10335 ui->refcount++; 10336 } 10337 break; 10338 } 10339 } 10340 10341 sx_sunlock(&t4_uld_list_lock); 10342 10343 return (rc); 10344 } 10345 10346 int 10347 t4_deactivate_uld(struct adapter *sc, int id) 10348 { 10349 int rc; 10350 struct uld_info *ui; 10351 10352 ASSERT_SYNCHRONIZED_OP(sc); 10353 10354 if (id < 0 || id > ULD_MAX) 10355 return (EINVAL); 10356 rc = ENXIO; 10357 10358 sx_slock(&t4_uld_list_lock); 10359 10360 SLIST_FOREACH(ui, &t4_uld_list, link) { 10361 if (ui->uld_id == id) { 10362 rc = ui->deactivate(sc); 10363 if (rc == 0) { 10364 clrbit(&sc->active_ulds, id); 10365 ui->refcount--; 10366 } 10367 break; 10368 } 10369 } 10370 10371 sx_sunlock(&t4_uld_list_lock); 10372 10373 return (rc); 10374 } 10375 10376 int 10377 uld_active(struct adapter *sc, int uld_id) 10378 { 10379 10380 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 10381 10382 return (isset(&sc->active_ulds, uld_id)); 10383 } 10384 #endif 10385 10386 /* 10387 * t = ptr to tunable. 10388 * nc = number of CPUs. 10389 * c = compiled in default for that tunable. 10390 */ 10391 static void 10392 calculate_nqueues(int *t, int nc, const int c) 10393 { 10394 int nq; 10395 10396 if (*t > 0) 10397 return; 10398 nq = *t < 0 ? -*t : c; 10399 *t = min(nc, nq); 10400 } 10401 10402 /* 10403 * Come up with reasonable defaults for some of the tunables, provided they're 10404 * not set by the user (in which case we'll use the values as is). 10405 */ 10406 static void 10407 tweak_tunables(void) 10408 { 10409 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 10410 10411 if (t4_ntxq < 1) { 10412 #ifdef RSS 10413 t4_ntxq = rss_getnumbuckets(); 10414 #else 10415 calculate_nqueues(&t4_ntxq, nc, NTXQ); 10416 #endif 10417 } 10418 10419 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 10420 10421 if (t4_nrxq < 1) { 10422 #ifdef RSS 10423 t4_nrxq = rss_getnumbuckets(); 10424 #else 10425 calculate_nqueues(&t4_nrxq, nc, NRXQ); 10426 #endif 10427 } 10428 10429 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 10430 10431 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10432 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 10433 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 10434 #endif 10435 #ifdef TCP_OFFLOAD 10436 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 10437 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 10438 10439 if (t4_toecaps_allowed == -1) 10440 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 10441 10442 if (t4_rdmacaps_allowed == -1) { 10443 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 10444 FW_CAPS_CONFIG_RDMA_RDMAC; 10445 } 10446 10447 if (t4_iscsicaps_allowed == -1) { 10448 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 10449 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 10450 FW_CAPS_CONFIG_ISCSI_T10DIF; 10451 } 10452 10453 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 10454 t4_tmr_idx_ofld = TMR_IDX_OFLD; 10455 10456 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 10457 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 10458 #else 10459 if (t4_toecaps_allowed == -1) 10460 t4_toecaps_allowed = 0; 10461 10462 if (t4_rdmacaps_allowed == -1) 10463 t4_rdmacaps_allowed = 0; 10464 10465 if (t4_iscsicaps_allowed == -1) 10466 t4_iscsicaps_allowed = 0; 10467 #endif 10468 10469 #ifdef DEV_NETMAP 10470 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 10471 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 10472 #endif 10473 10474 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 10475 t4_tmr_idx = TMR_IDX; 10476 10477 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 10478 t4_pktc_idx = PKTC_IDX; 10479 10480 if (t4_qsize_txq < 128) 10481 t4_qsize_txq = 128; 10482 10483 if (t4_qsize_rxq < 128) 10484 t4_qsize_rxq = 128; 10485 while (t4_qsize_rxq & 7) 10486 t4_qsize_rxq++; 10487 10488 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 10489 10490 /* 10491 * Number of VIs to create per-port. The first VI is the "main" regular 10492 * VI for the port. The rest are additional virtual interfaces on the 10493 * same physical port. Note that the main VI does not have native 10494 * netmap support but the extra VIs do. 10495 * 10496 * Limit the number of VIs per port to the number of available 10497 * MAC addresses per port. 10498 */ 10499 if (t4_num_vis < 1) 10500 t4_num_vis = 1; 10501 if (t4_num_vis > nitems(vi_mac_funcs)) { 10502 t4_num_vis = nitems(vi_mac_funcs); 10503 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 10504 } 10505 10506 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 10507 pcie_relaxed_ordering = 1; 10508 #if defined(__i386__) || defined(__amd64__) 10509 if (cpu_vendor_id == CPU_VENDOR_INTEL) 10510 pcie_relaxed_ordering = 0; 10511 #endif 10512 } 10513 } 10514 10515 #ifdef DDB 10516 static void 10517 t4_dump_tcb(struct adapter *sc, int tid) 10518 { 10519 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10520 10521 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10522 save = t4_read_reg(sc, reg); 10523 base = sc->memwin[2].mw_base; 10524 10525 /* Dump TCB for the tid */ 10526 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10527 tcb_addr += tid * TCB_SIZE; 10528 10529 if (is_t4(sc)) { 10530 pf = 0; 10531 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10532 } else { 10533 pf = V_PFNUM(sc->pf); 10534 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10535 } 10536 t4_write_reg(sc, reg, win_pos | pf); 10537 t4_read_reg(sc, reg); 10538 10539 off = tcb_addr - win_pos; 10540 for (i = 0; i < 4; i++) { 10541 uint32_t buf[8]; 10542 for (j = 0; j < 8; j++, off += 4) 10543 buf[j] = htonl(t4_read_reg(sc, base + off)); 10544 10545 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10546 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10547 buf[7]); 10548 } 10549 10550 t4_write_reg(sc, reg, save); 10551 t4_read_reg(sc, reg); 10552 } 10553 10554 static void 10555 t4_dump_devlog(struct adapter *sc) 10556 { 10557 struct devlog_params *dparams = &sc->params.devlog; 10558 struct fw_devlog_e e; 10559 int i, first, j, m, nentries, rc; 10560 uint64_t ftstamp = UINT64_MAX; 10561 10562 if (dparams->start == 0) { 10563 db_printf("devlog params not valid\n"); 10564 return; 10565 } 10566 10567 nentries = dparams->size / sizeof(struct fw_devlog_e); 10568 m = fwmtype_to_hwmtype(dparams->memtype); 10569 10570 /* Find the first entry. */ 10571 first = -1; 10572 for (i = 0; i < nentries && !db_pager_quit; i++) { 10573 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10574 sizeof(e), (void *)&e); 10575 if (rc != 0) 10576 break; 10577 10578 if (e.timestamp == 0) 10579 break; 10580 10581 e.timestamp = be64toh(e.timestamp); 10582 if (e.timestamp < ftstamp) { 10583 ftstamp = e.timestamp; 10584 first = i; 10585 } 10586 } 10587 10588 if (first == -1) 10589 return; 10590 10591 i = first; 10592 do { 10593 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10594 sizeof(e), (void *)&e); 10595 if (rc != 0) 10596 return; 10597 10598 if (e.timestamp == 0) 10599 return; 10600 10601 e.timestamp = be64toh(e.timestamp); 10602 e.seqno = be32toh(e.seqno); 10603 for (j = 0; j < 8; j++) 10604 e.params[j] = be32toh(e.params[j]); 10605 10606 db_printf("%10d %15ju %8s %8s ", 10607 e.seqno, e.timestamp, 10608 (e.level < nitems(devlog_level_strings) ? 10609 devlog_level_strings[e.level] : "UNKNOWN"), 10610 (e.facility < nitems(devlog_facility_strings) ? 10611 devlog_facility_strings[e.facility] : "UNKNOWN")); 10612 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10613 e.params[3], e.params[4], e.params[5], e.params[6], 10614 e.params[7]); 10615 10616 if (++i == nentries) 10617 i = 0; 10618 } while (i != first && !db_pager_quit); 10619 } 10620 10621 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10622 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10623 10624 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10625 { 10626 device_t dev; 10627 int t; 10628 bool valid; 10629 10630 valid = false; 10631 t = db_read_token(); 10632 if (t == tIDENT) { 10633 dev = device_lookup_by_name(db_tok_string); 10634 valid = true; 10635 } 10636 db_skip_to_eol(); 10637 if (!valid) { 10638 db_printf("usage: show t4 devlog <nexus>\n"); 10639 return; 10640 } 10641 10642 if (dev == NULL) { 10643 db_printf("device not found\n"); 10644 return; 10645 } 10646 10647 t4_dump_devlog(device_get_softc(dev)); 10648 } 10649 10650 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10651 { 10652 device_t dev; 10653 int radix, tid, t; 10654 bool valid; 10655 10656 valid = false; 10657 radix = db_radix; 10658 db_radix = 10; 10659 t = db_read_token(); 10660 if (t == tIDENT) { 10661 dev = device_lookup_by_name(db_tok_string); 10662 t = db_read_token(); 10663 if (t == tNUMBER) { 10664 tid = db_tok_number; 10665 valid = true; 10666 } 10667 } 10668 db_radix = radix; 10669 db_skip_to_eol(); 10670 if (!valid) { 10671 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10672 return; 10673 } 10674 10675 if (dev == NULL) { 10676 db_printf("device not found\n"); 10677 return; 10678 } 10679 if (tid < 0) { 10680 db_printf("invalid tid\n"); 10681 return; 10682 } 10683 10684 t4_dump_tcb(device_get_softc(dev), tid); 10685 } 10686 #endif 10687 10688 /* 10689 * Borrowed from cesa_prep_aes_key(). 10690 * 10691 * NB: The crypto engine wants the words in the decryption key in reverse 10692 * order. 10693 */ 10694 void 10695 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10696 { 10697 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10698 uint32_t *dkey; 10699 int i; 10700 10701 rijndaelKeySetupEnc(ek, enc_key, kbits); 10702 dkey = dec_key; 10703 dkey += (kbits / 8) / 4; 10704 10705 switch (kbits) { 10706 case 128: 10707 for (i = 0; i < 4; i++) 10708 *--dkey = htobe32(ek[4 * 10 + i]); 10709 break; 10710 case 192: 10711 for (i = 0; i < 2; i++) 10712 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10713 for (i = 0; i < 4; i++) 10714 *--dkey = htobe32(ek[4 * 12 + i]); 10715 break; 10716 case 256: 10717 for (i = 0; i < 4; i++) 10718 *--dkey = htobe32(ek[4 * 13 + i]); 10719 for (i = 0; i < 4; i++) 10720 *--dkey = htobe32(ek[4 * 14 + i]); 10721 break; 10722 } 10723 MPASS(dkey == dec_key); 10724 } 10725 10726 static struct sx mlu; /* mod load unload */ 10727 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10728 10729 static int 10730 mod_event(module_t mod, int cmd, void *arg) 10731 { 10732 int rc = 0; 10733 static int loaded = 0; 10734 10735 switch (cmd) { 10736 case MOD_LOAD: 10737 sx_xlock(&mlu); 10738 if (loaded++ == 0) { 10739 t4_sge_modload(); 10740 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10741 t4_filter_rpl, CPL_COOKIE_FILTER); 10742 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10743 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10744 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10745 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10746 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10747 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10748 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10749 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10750 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10751 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10752 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 10753 do_smt_write_rpl); 10754 sx_init(&t4_list_lock, "T4/T5 adapters"); 10755 SLIST_INIT(&t4_list); 10756 callout_init(&fatal_callout, 1); 10757 #ifdef TCP_OFFLOAD 10758 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10759 SLIST_INIT(&t4_uld_list); 10760 #endif 10761 #ifdef INET6 10762 t4_clip_modload(); 10763 #endif 10764 t4_tracer_modload(); 10765 tweak_tunables(); 10766 } 10767 sx_xunlock(&mlu); 10768 break; 10769 10770 case MOD_UNLOAD: 10771 sx_xlock(&mlu); 10772 if (--loaded == 0) { 10773 int tries; 10774 10775 sx_slock(&t4_list_lock); 10776 if (!SLIST_EMPTY(&t4_list)) { 10777 rc = EBUSY; 10778 sx_sunlock(&t4_list_lock); 10779 goto done_unload; 10780 } 10781 #ifdef TCP_OFFLOAD 10782 sx_slock(&t4_uld_list_lock); 10783 if (!SLIST_EMPTY(&t4_uld_list)) { 10784 rc = EBUSY; 10785 sx_sunlock(&t4_uld_list_lock); 10786 sx_sunlock(&t4_list_lock); 10787 goto done_unload; 10788 } 10789 #endif 10790 tries = 0; 10791 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10792 uprintf("%ju clusters with custom free routine " 10793 "still is use.\n", t4_sge_extfree_refs()); 10794 pause("t4unload", 2 * hz); 10795 } 10796 #ifdef TCP_OFFLOAD 10797 sx_sunlock(&t4_uld_list_lock); 10798 #endif 10799 sx_sunlock(&t4_list_lock); 10800 10801 if (t4_sge_extfree_refs() == 0) { 10802 t4_tracer_modunload(); 10803 #ifdef INET6 10804 t4_clip_modunload(); 10805 #endif 10806 #ifdef TCP_OFFLOAD 10807 sx_destroy(&t4_uld_list_lock); 10808 #endif 10809 sx_destroy(&t4_list_lock); 10810 t4_sge_modunload(); 10811 loaded = 0; 10812 } else { 10813 rc = EBUSY; 10814 loaded++; /* undo earlier decrement */ 10815 } 10816 } 10817 done_unload: 10818 sx_xunlock(&mlu); 10819 break; 10820 } 10821 10822 return (rc); 10823 } 10824 10825 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10826 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10827 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10828 10829 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10830 MODULE_VERSION(t4nex, 1); 10831 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10832 #ifdef DEV_NETMAP 10833 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10834 #endif /* DEV_NETMAP */ 10835 10836 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10837 MODULE_VERSION(t5nex, 1); 10838 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10839 #ifdef DEV_NETMAP 10840 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10841 #endif /* DEV_NETMAP */ 10842 10843 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10844 MODULE_VERSION(t6nex, 1); 10845 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10846 #ifdef DEV_NETMAP 10847 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10848 #endif /* DEV_NETMAP */ 10849 10850 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10851 MODULE_VERSION(cxgbe, 1); 10852 10853 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10854 MODULE_VERSION(cxl, 1); 10855 10856 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10857 MODULE_VERSION(cc, 1); 10858 10859 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10860 MODULE_VERSION(vcxgbe, 1); 10861 10862 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10863 MODULE_VERSION(vcxl, 1); 10864 10865 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10866 MODULE_VERSION(vcc, 1); 10867