1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2008 Nathan Whitehorn. All rights reserved. 5 * Copyright 2003 by Peter Grehan. All rights reserved. 6 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * From: 32 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp 33 */ 34 35 /* 36 * BMAC/BMAC+ Macio cell 10/100 ethernet driver 37 * The low-cost, low-feature Apple variant of the Sun HME 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sockio.h> 46 #include <sys/endian.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 53 #include <net/bpf.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_arp.h> 57 #include <net/ethernet.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_types.h> 61 62 #include <machine/pio.h> 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 #include <sys/bus.h> 66 #include <sys/rman.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/mii_bitbang.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/ofw/ofw_bus.h> 73 #include <dev/ofw/openfirm.h> 74 #include <machine/dbdma.h> 75 76 MODULE_DEPEND(bm, ether, 1, 1, 1); 77 MODULE_DEPEND(bm, miibus, 1, 1, 1); 78 79 /* "controller miibus0" required. See GENERIC if you get errors here. */ 80 #include "miibus_if.h" 81 82 #include "if_bmreg.h" 83 #include "if_bmvar.h" 84 85 static int bm_probe (device_t); 86 static int bm_attach (device_t); 87 static int bm_detach (device_t); 88 static int bm_shutdown (device_t); 89 90 static void bm_start (struct ifnet *); 91 static void bm_start_locked (struct ifnet *); 92 static int bm_encap (struct bm_softc *sc, struct mbuf **m_head); 93 static int bm_ioctl (struct ifnet *, u_long, caddr_t); 94 static void bm_init (void *); 95 static void bm_init_locked (struct bm_softc *sc); 96 static void bm_chip_setup (struct bm_softc *sc); 97 static void bm_stop (struct bm_softc *sc); 98 static void bm_setladrf (struct bm_softc *sc); 99 static void bm_dummypacket (struct bm_softc *sc); 100 static void bm_txintr (void *xsc); 101 static void bm_rxintr (void *xsc); 102 103 static int bm_add_rxbuf (struct bm_softc *sc, int i); 104 static int bm_add_rxbuf_dma (struct bm_softc *sc, int i); 105 static void bm_enable_interrupts (struct bm_softc *sc); 106 static void bm_disable_interrupts (struct bm_softc *sc); 107 static void bm_tick (void *xsc); 108 109 static int bm_ifmedia_upd (struct ifnet *); 110 static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111 112 static int bm_miibus_readreg (device_t, int, int); 113 static int bm_miibus_writereg (device_t, int, int, int); 114 static void bm_miibus_statchg (device_t); 115 116 /* 117 * MII bit-bang glue 118 */ 119 static uint32_t bm_mii_bitbang_read(device_t); 120 static void bm_mii_bitbang_write(device_t, uint32_t); 121 122 static const struct mii_bitbang_ops bm_mii_bitbang_ops = { 123 bm_mii_bitbang_read, 124 bm_mii_bitbang_write, 125 { 126 BM_MII_DATAOUT, /* MII_BIT_MDO */ 127 BM_MII_DATAIN, /* MII_BIT_MDI */ 128 BM_MII_CLK, /* MII_BIT_MDC */ 129 BM_MII_OENABLE, /* MII_BIT_DIR_HOST_PHY */ 130 0, /* MII_BIT_DIR_PHY_HOST */ 131 } 132 }; 133 134 static device_method_t bm_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, bm_probe), 137 DEVMETHOD(device_attach, bm_attach), 138 DEVMETHOD(device_detach, bm_detach), 139 DEVMETHOD(device_shutdown, bm_shutdown), 140 141 /* MII interface */ 142 DEVMETHOD(miibus_readreg, bm_miibus_readreg), 143 DEVMETHOD(miibus_writereg, bm_miibus_writereg), 144 DEVMETHOD(miibus_statchg, bm_miibus_statchg), 145 146 DEVMETHOD_END 147 }; 148 149 static driver_t bm_macio_driver = { 150 "bm", 151 bm_methods, 152 sizeof(struct bm_softc) 153 }; 154 155 static devclass_t bm_devclass; 156 157 DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0); 158 DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0); 159 160 /* 161 * MII internal routines 162 */ 163 164 /* 165 * Write the MII serial port for the MII bit-bang module. 166 */ 167 static void 168 bm_mii_bitbang_write(device_t dev, uint32_t val) 169 { 170 struct bm_softc *sc; 171 172 sc = device_get_softc(dev); 173 174 CSR_WRITE_2(sc, BM_MII_CSR, val); 175 CSR_BARRIER(sc, BM_MII_CSR, 2, 176 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 177 } 178 179 /* 180 * Read the MII serial port for the MII bit-bang module. 181 */ 182 static uint32_t 183 bm_mii_bitbang_read(device_t dev) 184 { 185 struct bm_softc *sc; 186 uint32_t reg; 187 188 sc = device_get_softc(dev); 189 190 reg = CSR_READ_2(sc, BM_MII_CSR); 191 CSR_BARRIER(sc, BM_MII_CSR, 2, 192 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 193 194 return (reg); 195 } 196 197 /* 198 * MII bus i/f 199 */ 200 static int 201 bm_miibus_readreg(device_t dev, int phy, int reg) 202 { 203 204 return (mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg)); 205 } 206 207 static int 208 bm_miibus_writereg(device_t dev, int phy, int reg, int data) 209 { 210 211 mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg); 212 213 return (0); 214 } 215 216 static void 217 bm_miibus_statchg(device_t dev) 218 { 219 struct bm_softc *sc = device_get_softc(dev); 220 uint16_t reg; 221 int new_duplex; 222 223 reg = CSR_READ_2(sc, BM_TX_CONFIG); 224 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX; 225 226 if (new_duplex != sc->sc_duplex) { 227 /* Turn off TX MAC while we fiddle its settings */ 228 reg &= ~BM_ENABLE; 229 230 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 231 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE) 232 DELAY(10); 233 } 234 235 if (new_duplex && !sc->sc_duplex) 236 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX; 237 else if (!new_duplex && sc->sc_duplex) 238 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX); 239 240 if (new_duplex != sc->sc_duplex) { 241 /* Turn TX MAC back on */ 242 reg |= BM_ENABLE; 243 244 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 245 sc->sc_duplex = new_duplex; 246 } 247 } 248 249 /* 250 * ifmedia/mii callbacks 251 */ 252 static int 253 bm_ifmedia_upd(struct ifnet *ifp) 254 { 255 struct bm_softc *sc = ifp->if_softc; 256 int error; 257 258 BM_LOCK(sc); 259 error = mii_mediachg(sc->sc_mii); 260 BM_UNLOCK(sc); 261 return (error); 262 } 263 264 static void 265 bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm) 266 { 267 struct bm_softc *sc = ifp->if_softc; 268 269 BM_LOCK(sc); 270 mii_pollstat(sc->sc_mii); 271 ifm->ifm_active = sc->sc_mii->mii_media_active; 272 ifm->ifm_status = sc->sc_mii->mii_media_status; 273 BM_UNLOCK(sc); 274 } 275 276 /* 277 * Macio probe/attach 278 */ 279 static int 280 bm_probe(device_t dev) 281 { 282 const char *dname = ofw_bus_get_name(dev); 283 const char *dcompat = ofw_bus_get_compat(dev); 284 285 /* 286 * BMAC+ cells have a name of "ethernet" and 287 * a compatible property of "bmac+" 288 */ 289 if (strcmp(dname, "bmac") == 0) { 290 device_set_desc(dev, "Apple BMAC Ethernet Adaptor"); 291 } else if (strcmp(dcompat, "bmac+") == 0) { 292 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor"); 293 } else 294 return (ENXIO); 295 296 return (0); 297 } 298 299 static int 300 bm_attach(device_t dev) 301 { 302 phandle_t node; 303 u_char *eaddr; 304 struct ifnet *ifp; 305 int error, cellid, i; 306 struct bm_txsoft *txs; 307 struct bm_softc *sc = device_get_softc(dev); 308 309 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 310 ifp->if_softc = sc; 311 sc->sc_dev = dev; 312 sc->sc_duplex = ~IFM_FDX; 313 314 error = 0; 315 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 316 MTX_DEF); 317 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 318 319 /* Check for an improved version of Paddington */ 320 sc->sc_streaming = 0; 321 cellid = -1; 322 node = ofw_bus_get_node(dev); 323 324 OF_getprop(node, "cell-id", &cellid, sizeof(cellid)); 325 if (cellid >= 0xc4) 326 sc->sc_streaming = 1; 327 328 sc->sc_memrid = 0; 329 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 330 &sc->sc_memrid, RF_ACTIVE); 331 if (sc->sc_memr == NULL) { 332 device_printf(dev, "Could not alloc chip registers!\n"); 333 return (ENXIO); 334 } 335 336 sc->sc_txdmarid = BM_TXDMA_REGISTERS; 337 sc->sc_rxdmarid = BM_RXDMA_REGISTERS; 338 339 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 340 &sc->sc_txdmarid, RF_ACTIVE); 341 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 342 &sc->sc_rxdmarid, RF_ACTIVE); 343 344 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) { 345 device_printf(dev, "Could not map DBDMA registers!\n"); 346 return (ENXIO); 347 } 348 349 error = dbdma_allocate_channel(sc->sc_txdmar, 0, bus_get_dma_tag(dev), 350 BM_MAX_DMA_COMMANDS, &sc->sc_txdma); 351 error += dbdma_allocate_channel(sc->sc_rxdmar, 0, bus_get_dma_tag(dev), 352 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma); 353 354 if (error) { 355 device_printf(dev,"Could not allocate DBDMA channel!\n"); 356 return (ENXIO); 357 } 358 359 /* alloc DMA tags and buffers */ 360 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 361 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 362 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, 363 NULL, &sc->sc_pdma_tag); 364 365 if (error) { 366 device_printf(dev,"Could not allocate DMA tag!\n"); 367 return (ENXIO); 368 } 369 370 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 371 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 372 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag); 373 374 if (error) { 375 device_printf(dev,"Could not allocate RX DMA channel!\n"); 376 return (ENXIO); 377 } 378 379 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR, 380 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS, 381 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag); 382 383 if (error) { 384 device_printf(dev,"Could not allocate TX DMA tag!\n"); 385 return (ENXIO); 386 } 387 388 /* init transmit descriptors */ 389 STAILQ_INIT(&sc->sc_txfreeq); 390 STAILQ_INIT(&sc->sc_txdirtyq); 391 392 /* create TX DMA maps */ 393 error = ENOMEM; 394 for (i = 0; i < BM_MAX_TX_PACKETS; i++) { 395 txs = &sc->sc_txsoft[i]; 396 txs->txs_mbuf = NULL; 397 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap); 398 if (error) { 399 device_printf(sc->sc_dev, 400 "unable to create TX DMA map %d, error = %d\n", 401 i, error); 402 } 403 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 404 } 405 406 /* Create the receive buffer DMA maps. */ 407 for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 408 error = bus_dmamap_create(sc->sc_rdma_tag, 0, 409 &sc->sc_rxsoft[i].rxs_dmamap); 410 if (error) { 411 device_printf(sc->sc_dev, 412 "unable to create RX DMA map %d, error = %d\n", 413 i, error); 414 } 415 sc->sc_rxsoft[i].rxs_mbuf = NULL; 416 } 417 418 /* alloc interrupt */ 419 bm_disable_interrupts(sc); 420 421 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT; 422 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 423 &sc->sc_txdmairqid, RF_ACTIVE); 424 425 if (error) { 426 device_printf(dev,"Could not allocate TX interrupt!\n"); 427 return (ENXIO); 428 } 429 430 bus_setup_intr(dev,sc->sc_txdmairq, 431 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc, 432 &sc->sc_txihtx); 433 434 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT; 435 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 436 &sc->sc_rxdmairqid, RF_ACTIVE); 437 438 if (error) { 439 device_printf(dev,"Could not allocate RX interrupt!\n"); 440 return (ENXIO); 441 } 442 443 bus_setup_intr(dev,sc->sc_rxdmairq, 444 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc, 445 &sc->sc_rxih); 446 447 /* 448 * Get the ethernet address from OpenFirmware 449 */ 450 eaddr = sc->sc_enaddr; 451 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN); 452 453 /* 454 * Setup MII 455 * On Apple BMAC controllers, we end up in a weird state of 456 * partially-completed autonegotiation on boot. So we force 457 * autonegotation to try again. 458 */ 459 error = mii_attach(dev, &sc->sc_miibus, ifp, bm_ifmedia_upd, 460 bm_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 461 MIIF_FORCEANEG); 462 if (error != 0) { 463 device_printf(dev, "attaching PHYs failed\n"); 464 return (error); 465 } 466 467 /* reset the adapter */ 468 bm_chip_setup(sc); 469 470 sc->sc_mii = device_get_softc(sc->sc_miibus); 471 472 if_initname(ifp, device_get_name(sc->sc_dev), 473 device_get_unit(sc->sc_dev)); 474 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 475 ifp->if_start = bm_start; 476 ifp->if_ioctl = bm_ioctl; 477 ifp->if_init = bm_init; 478 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS); 479 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS; 480 IFQ_SET_READY(&ifp->if_snd); 481 482 /* Attach the interface. */ 483 ether_ifattach(ifp, sc->sc_enaddr); 484 ifp->if_hwassist = 0; 485 486 return (0); 487 } 488 489 static int 490 bm_detach(device_t dev) 491 { 492 struct bm_softc *sc = device_get_softc(dev); 493 494 BM_LOCK(sc); 495 bm_stop(sc); 496 BM_UNLOCK(sc); 497 498 callout_drain(&sc->sc_tick_ch); 499 ether_ifdetach(sc->sc_ifp); 500 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx); 501 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih); 502 503 dbdma_free_channel(sc->sc_txdma); 504 dbdma_free_channel(sc->sc_rxdma); 505 506 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr); 507 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid, 508 sc->sc_txdmar); 509 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid, 510 sc->sc_rxdmar); 511 512 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid, 513 sc->sc_txdmairq); 514 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid, 515 sc->sc_rxdmairq); 516 517 mtx_destroy(&sc->sc_mtx); 518 if_free(sc->sc_ifp); 519 520 return (0); 521 } 522 523 static int 524 bm_shutdown(device_t dev) 525 { 526 struct bm_softc *sc; 527 528 sc = device_get_softc(dev); 529 530 BM_LOCK(sc); 531 bm_stop(sc); 532 BM_UNLOCK(sc); 533 534 return (0); 535 } 536 537 static void 538 bm_dummypacket(struct bm_softc *sc) 539 { 540 struct mbuf *m; 541 struct ifnet *ifp; 542 543 ifp = sc->sc_ifp; 544 545 MGETHDR(m, M_NOWAIT, MT_DATA); 546 547 if (m == NULL) 548 return; 549 550 bcopy(sc->sc_enaddr, 551 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 552 bcopy(sc->sc_enaddr, 553 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 554 mtod(m, struct ether_header *)->ether_type = htons(3); 555 mtod(m, unsigned char *)[14] = 0; 556 mtod(m, unsigned char *)[15] = 0; 557 mtod(m, unsigned char *)[16] = 0xE3; 558 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 559 IF_ENQUEUE(&ifp->if_snd, m); 560 bm_start_locked(ifp); 561 } 562 563 static void 564 bm_rxintr(void *xsc) 565 { 566 struct bm_softc *sc = xsc; 567 struct ifnet *ifp = sc->sc_ifp; 568 struct mbuf *m; 569 int i, prev_stop, new_stop; 570 uint16_t status; 571 572 BM_LOCK(sc); 573 574 status = dbdma_get_chan_status(sc->sc_rxdma); 575 if (status & DBDMA_STATUS_DEAD) { 576 dbdma_reset(sc->sc_rxdma); 577 BM_UNLOCK(sc); 578 return; 579 } 580 if (!(status & DBDMA_STATUS_RUN)) { 581 device_printf(sc->sc_dev,"Bad RX Interrupt!\n"); 582 BM_UNLOCK(sc); 583 return; 584 } 585 586 prev_stop = sc->next_rxdma_slot - 1; 587 if (prev_stop < 0) 588 prev_stop = sc->rxdma_loop_slot - 1; 589 590 if (prev_stop < 0) { 591 BM_UNLOCK(sc); 592 return; 593 } 594 595 new_stop = -1; 596 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD); 597 598 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) { 599 if (i == sc->rxdma_loop_slot) 600 i = 0; 601 602 if (i == prev_stop) 603 break; 604 605 status = dbdma_get_cmd_status(sc->sc_rxdma, i); 606 607 if (status == 0) 608 break; 609 610 m = sc->sc_rxsoft[i].rxs_mbuf; 611 612 if (bm_add_rxbuf(sc, i)) { 613 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 614 m = NULL; 615 continue; 616 } 617 618 if (m == NULL) 619 continue; 620 621 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 622 m->m_pkthdr.rcvif = ifp; 623 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2); 624 m->m_pkthdr.len = m->m_len; 625 626 /* Send up the stack */ 627 BM_UNLOCK(sc); 628 (*ifp->if_input)(ifp, m); 629 BM_LOCK(sc); 630 631 /* Clear all fields on this command */ 632 bm_add_rxbuf_dma(sc, i); 633 634 new_stop = i; 635 } 636 637 /* Change the last packet we processed to the ring buffer terminator, 638 * and restore a receive buffer to the old terminator */ 639 if (new_stop >= 0) { 640 dbdma_insert_stop(sc->sc_rxdma, new_stop); 641 bm_add_rxbuf_dma(sc, prev_stop); 642 if (i < sc->rxdma_loop_slot) 643 sc->next_rxdma_slot = i; 644 else 645 sc->next_rxdma_slot = 0; 646 } 647 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 648 649 dbdma_wake(sc->sc_rxdma); 650 651 BM_UNLOCK(sc); 652 } 653 654 static void 655 bm_txintr(void *xsc) 656 { 657 struct bm_softc *sc = xsc; 658 struct ifnet *ifp = sc->sc_ifp; 659 struct bm_txsoft *txs; 660 int progress = 0; 661 662 BM_LOCK(sc); 663 664 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 665 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc)) 666 break; 667 668 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 669 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 670 671 if (txs->txs_mbuf != NULL) { 672 m_freem(txs->txs_mbuf); 673 txs->txs_mbuf = NULL; 674 } 675 676 /* Set the first used TXDMA slot to the location of the 677 * STOP/NOP command associated with this packet. */ 678 679 sc->first_used_txdma_slot = txs->txs_stopdesc; 680 681 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 682 683 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 684 progress = 1; 685 } 686 687 if (progress) { 688 /* 689 * We freed some descriptors, so reset IFF_DRV_OACTIVE 690 * and restart. 691 */ 692 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 693 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 694 695 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 696 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 697 bm_start_locked(ifp); 698 } 699 700 BM_UNLOCK(sc); 701 } 702 703 static void 704 bm_start(struct ifnet *ifp) 705 { 706 struct bm_softc *sc = ifp->if_softc; 707 708 BM_LOCK(sc); 709 bm_start_locked(ifp); 710 BM_UNLOCK(sc); 711 } 712 713 static void 714 bm_start_locked(struct ifnet *ifp) 715 { 716 struct bm_softc *sc = ifp->if_softc; 717 struct mbuf *mb_head; 718 int prev_stop; 719 int txqueued = 0; 720 721 /* 722 * We lay out our DBDMA program in the following manner: 723 * OUTPUT_MORE 724 * ... 725 * OUTPUT_LAST (+ Interrupt) 726 * STOP 727 * 728 * To extend the channel, we append a new program, 729 * then replace STOP with NOP and wake the channel. 730 * If we stalled on the STOP already, the program proceeds, 731 * if not it will sail through the NOP. 732 */ 733 734 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 735 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head); 736 737 if (mb_head == NULL) 738 break; 739 740 prev_stop = sc->next_txdma_slot - 1; 741 742 if (bm_encap(sc, &mb_head)) { 743 /* Put the packet back and stop */ 744 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 745 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head); 746 break; 747 } 748 749 dbdma_insert_nop(sc->sc_txdma, prev_stop); 750 751 txqueued = 1; 752 753 BPF_MTAP(ifp, mb_head); 754 } 755 756 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 757 758 if (txqueued) { 759 dbdma_wake(sc->sc_txdma); 760 sc->sc_wdog_timer = 5; 761 } 762 } 763 764 static int 765 bm_encap(struct bm_softc *sc, struct mbuf **m_head) 766 { 767 bus_dma_segment_t segs[BM_NTXSEGS]; 768 struct bm_txsoft *txs; 769 struct mbuf *m; 770 int nsegs = BM_NTXSEGS; 771 int error = 0; 772 uint8_t branch_type; 773 int i; 774 775 /* Limit the command size to the number of free DBDMA slots */ 776 777 if (sc->next_txdma_slot >= sc->first_used_txdma_slot) 778 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot + 779 sc->first_used_txdma_slot; /* -2 for branch and indexing */ 780 else 781 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot; 782 783 /* Remove one slot for the STOP/NOP terminator */ 784 nsegs--; 785 786 if (nsegs > BM_NTXSEGS) 787 nsegs = BM_NTXSEGS; 788 789 /* Get a work queue entry. */ 790 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 791 /* Ran out of descriptors. */ 792 return (ENOBUFS); 793 } 794 795 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap, 796 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 797 798 if (error == EFBIG) { 799 m = m_collapse(*m_head, M_NOWAIT, nsegs); 800 if (m == NULL) { 801 m_freem(*m_head); 802 *m_head = NULL; 803 return (ENOBUFS); 804 } 805 *m_head = m; 806 807 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, 808 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 809 if (error != 0) { 810 m_freem(*m_head); 811 *m_head = NULL; 812 return (error); 813 } 814 } else if (error != 0) 815 return (error); 816 817 if (nsegs == 0) { 818 m_freem(*m_head); 819 *m_head = NULL; 820 return (EIO); 821 } 822 823 txs->txs_ndescs = nsegs; 824 txs->txs_firstdesc = sc->next_txdma_slot; 825 826 for (i = 0; i < nsegs; i++) { 827 /* Loop back to the beginning if this is our last slot */ 828 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) 829 branch_type = DBDMA_ALWAYS; 830 else 831 branch_type = DBDMA_NEVER; 832 833 if (i+1 == nsegs) 834 txs->txs_lastdesc = sc->next_txdma_slot; 835 836 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++, 837 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST, 838 0, segs[i].ds_addr, segs[i].ds_len, 839 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS, 840 branch_type, DBDMA_NEVER, 0); 841 842 if (branch_type == DBDMA_ALWAYS) 843 sc->next_txdma_slot = 0; 844 } 845 846 /* We have a corner case where the STOP command is the last slot, 847 * but you can't branch in STOP commands. So add a NOP branch here 848 * and the STOP in slot 0. */ 849 850 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) { 851 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0); 852 sc->next_txdma_slot = 0; 853 } 854 855 txs->txs_stopdesc = sc->next_txdma_slot; 856 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++); 857 858 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 859 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 860 txs->txs_mbuf = *m_head; 861 862 return (0); 863 } 864 865 static int 866 bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 867 { 868 struct bm_softc *sc = ifp->if_softc; 869 struct ifreq *ifr = (struct ifreq *)data; 870 int error; 871 872 error = 0; 873 874 switch(cmd) { 875 case SIOCSIFFLAGS: 876 BM_LOCK(sc); 877 if ((ifp->if_flags & IFF_UP) != 0) { 878 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 879 ((ifp->if_flags ^ sc->sc_ifpflags) & 880 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 881 bm_setladrf(sc); 882 else 883 bm_init_locked(sc); 884 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 885 bm_stop(sc); 886 sc->sc_ifpflags = ifp->if_flags; 887 BM_UNLOCK(sc); 888 break; 889 case SIOCADDMULTI: 890 case SIOCDELMULTI: 891 BM_LOCK(sc); 892 bm_setladrf(sc); 893 BM_UNLOCK(sc); 894 case SIOCGIFMEDIA: 895 case SIOCSIFMEDIA: 896 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 897 break; 898 default: 899 error = ether_ioctl(ifp, cmd, data); 900 break; 901 } 902 903 return (error); 904 } 905 906 static void 907 bm_setladrf(struct bm_softc *sc) 908 { 909 struct ifnet *ifp = sc->sc_ifp; 910 struct ifmultiaddr *inm; 911 uint16_t hash[4]; 912 uint16_t reg; 913 uint32_t crc; 914 915 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS; 916 917 /* Turn off RX MAC while we fiddle its settings */ 918 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 919 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE) 920 DELAY(10); 921 922 if ((ifp->if_flags & IFF_PROMISC) != 0) { 923 reg |= BM_PROMISC; 924 925 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 926 927 DELAY(15); 928 929 reg = CSR_READ_2(sc, BM_RX_CONFIG); 930 reg |= BM_ENABLE; 931 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 932 return; 933 } 934 935 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 936 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 937 } else { 938 /* Clear the hash table. */ 939 memset(hash, 0, sizeof(hash)); 940 941 if_maddr_rlock(ifp); 942 CK_STAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 943 if (inm->ifma_addr->sa_family != AF_LINK) 944 continue; 945 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 946 inm->ifma_addr), ETHER_ADDR_LEN); 947 948 /* We just want the 6 most significant bits */ 949 crc >>= 26; 950 951 /* Set the corresponding bit in the filter. */ 952 hash[crc >> 4] |= 1 << (crc & 0xf); 953 } 954 if_maddr_runlock(ifp); 955 } 956 957 /* Write out new hash table */ 958 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]); 959 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]); 960 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]); 961 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]); 962 963 /* And turn the RX MAC back on, this time with the hash bit set */ 964 reg |= BM_HASH_FILTER_ENABLE; 965 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 966 967 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE)) 968 DELAY(10); 969 970 reg = CSR_READ_2(sc, BM_RX_CONFIG); 971 reg |= BM_ENABLE; 972 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 973 } 974 975 static void 976 bm_init(void *xsc) 977 { 978 struct bm_softc *sc = xsc; 979 980 BM_LOCK(sc); 981 bm_init_locked(sc); 982 BM_UNLOCK(sc); 983 } 984 985 static void 986 bm_chip_setup(struct bm_softc *sc) 987 { 988 uint16_t reg; 989 uint16_t *eaddr_sect; 990 991 eaddr_sect = (uint16_t *)(sc->sc_enaddr); 992 dbdma_stop(sc->sc_txdma); 993 dbdma_stop(sc->sc_rxdma); 994 995 /* Reset chip */ 996 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000); 997 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001); 998 do { 999 DELAY(10); 1000 reg = CSR_READ_2(sc, BM_TX_RESET); 1001 } while (reg & 0x0001); 1002 1003 /* Some random junk. OS X uses the system time. We use 1004 * the low 16 bits of the MAC address. */ 1005 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]); 1006 1007 /* Enable transmit */ 1008 reg = CSR_READ_2(sc, BM_TX_IFC); 1009 reg |= BM_ENABLE; 1010 CSR_WRITE_2(sc, BM_TX_IFC, reg); 1011 1012 CSR_READ_2(sc, BM_TX_PEAKCNT); 1013 } 1014 1015 static void 1016 bm_stop(struct bm_softc *sc) 1017 { 1018 struct bm_txsoft *txs; 1019 uint16_t reg; 1020 1021 /* Disable TX and RX MACs */ 1022 reg = CSR_READ_2(sc, BM_TX_CONFIG); 1023 reg &= ~BM_ENABLE; 1024 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1025 1026 reg = CSR_READ_2(sc, BM_RX_CONFIG); 1027 reg &= ~BM_ENABLE; 1028 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1029 1030 DELAY(100); 1031 1032 /* Stop DMA engine */ 1033 dbdma_stop(sc->sc_rxdma); 1034 dbdma_stop(sc->sc_txdma); 1035 sc->next_rxdma_slot = 0; 1036 sc->rxdma_loop_slot = 0; 1037 1038 /* Disable interrupts */ 1039 bm_disable_interrupts(sc); 1040 1041 /* Don't worry about pending transmits anymore */ 1042 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1043 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1044 if (txs->txs_ndescs != 0) { 1045 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap, 1046 BUS_DMASYNC_POSTWRITE); 1047 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap); 1048 if (txs->txs_mbuf != NULL) { 1049 m_freem(txs->txs_mbuf); 1050 txs->txs_mbuf = NULL; 1051 } 1052 } 1053 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1054 } 1055 1056 /* And we're down */ 1057 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1058 sc->sc_wdog_timer = 0; 1059 callout_stop(&sc->sc_tick_ch); 1060 } 1061 1062 static void 1063 bm_init_locked(struct bm_softc *sc) 1064 { 1065 uint16_t reg; 1066 uint16_t *eaddr_sect; 1067 struct bm_rxsoft *rxs; 1068 int i; 1069 1070 eaddr_sect = (uint16_t *)(sc->sc_enaddr); 1071 1072 /* Zero RX slot info and stop DMA */ 1073 dbdma_stop(sc->sc_rxdma); 1074 dbdma_stop(sc->sc_txdma); 1075 sc->next_rxdma_slot = 0; 1076 sc->rxdma_loop_slot = 0; 1077 1078 /* Initialize TX/RX DBDMA programs */ 1079 dbdma_insert_stop(sc->sc_rxdma, 0); 1080 dbdma_insert_stop(sc->sc_txdma, 0); 1081 dbdma_set_current_cmd(sc->sc_rxdma, 0); 1082 dbdma_set_current_cmd(sc->sc_txdma, 0); 1083 1084 sc->next_rxdma_slot = 0; 1085 sc->next_txdma_slot = 1; 1086 sc->first_used_txdma_slot = 0; 1087 1088 for (i = 0; i < BM_MAX_RX_PACKETS; i++) { 1089 rxs = &sc->sc_rxsoft[i]; 1090 rxs->dbdma_slot = i; 1091 1092 if (rxs->rxs_mbuf == NULL) { 1093 bm_add_rxbuf(sc, i); 1094 1095 if (rxs->rxs_mbuf == NULL) { 1096 /* If we can't add anymore, mark the problem */ 1097 rxs->dbdma_slot = -1; 1098 break; 1099 } 1100 } 1101 1102 if (i > 0) 1103 bm_add_rxbuf_dma(sc, i); 1104 } 1105 1106 /* 1107 * Now terminate the RX ring buffer, and follow with the loop to 1108 * the beginning. 1109 */ 1110 dbdma_insert_stop(sc->sc_rxdma, i - 1); 1111 dbdma_insert_branch(sc->sc_rxdma, i, 0); 1112 sc->rxdma_loop_slot = i; 1113 1114 /* Now add in the first element of the RX DMA chain */ 1115 bm_add_rxbuf_dma(sc, 0); 1116 1117 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE); 1118 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE); 1119 1120 /* Zero collision counters */ 1121 CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1122 CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1123 CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1124 CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1125 1126 /* Zero receive counters */ 1127 CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1128 CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1129 CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1130 CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1131 CSR_WRITE_2(sc, BM_RXCV, 0); 1132 1133 /* Prime transmit */ 1134 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff); 1135 1136 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0); 1137 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001); 1138 1139 /* Prime receive */ 1140 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0); 1141 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001); 1142 1143 /* Clear status reg */ 1144 CSR_READ_2(sc, BM_STATUS); 1145 1146 /* Zero hash filters */ 1147 CSR_WRITE_2(sc, BM_HASHTAB0, 0); 1148 CSR_WRITE_2(sc, BM_HASHTAB1, 0); 1149 CSR_WRITE_2(sc, BM_HASHTAB2, 0); 1150 CSR_WRITE_2(sc, BM_HASHTAB3, 0); 1151 1152 /* Write MAC address to chip */ 1153 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]); 1154 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]); 1155 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]); 1156 1157 /* Final receive engine setup */ 1158 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE; 1159 CSR_WRITE_2(sc, BM_RX_CONFIG, reg); 1160 1161 /* Now turn it all on! */ 1162 dbdma_reset(sc->sc_rxdma); 1163 dbdma_reset(sc->sc_txdma); 1164 1165 /* Enable RX and TX MACs. Setting the address filter has 1166 * the side effect of enabling the RX MAC. */ 1167 bm_setladrf(sc); 1168 1169 reg = CSR_READ_2(sc, BM_TX_CONFIG); 1170 reg |= BM_ENABLE; 1171 CSR_WRITE_2(sc, BM_TX_CONFIG, reg); 1172 1173 /* 1174 * Enable interrupts, unwedge the controller with a dummy packet, 1175 * and nudge the DMA queue. 1176 */ 1177 bm_enable_interrupts(sc); 1178 bm_dummypacket(sc); 1179 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */ 1180 1181 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING; 1182 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1183 sc->sc_ifpflags = sc->sc_ifp->if_flags; 1184 1185 /* Resync PHY and MAC states */ 1186 sc->sc_mii = device_get_softc(sc->sc_miibus); 1187 sc->sc_duplex = ~IFM_FDX; 1188 mii_mediachg(sc->sc_mii); 1189 1190 /* Start the one second timer. */ 1191 sc->sc_wdog_timer = 0; 1192 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1193 } 1194 1195 static void 1196 bm_tick(void *arg) 1197 { 1198 struct bm_softc *sc = arg; 1199 1200 /* Read error counters */ 1201 if_inc_counter(sc->sc_ifp, IFCOUNTER_COLLISIONS, 1202 CSR_READ_2(sc, BM_TX_NCCNT) + CSR_READ_2(sc, BM_TX_FCCNT) + 1203 CSR_READ_2(sc, BM_TX_EXCNT) + CSR_READ_2(sc, BM_TX_LTCNT)); 1204 1205 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1206 CSR_READ_2(sc, BM_RX_LECNT) + CSR_READ_2(sc, BM_RX_AECNT) + 1207 CSR_READ_2(sc, BM_RX_FECNT)); 1208 1209 /* Zero collision counters */ 1210 CSR_WRITE_2(sc, BM_TX_NCCNT, 0); 1211 CSR_WRITE_2(sc, BM_TX_FCCNT, 0); 1212 CSR_WRITE_2(sc, BM_TX_EXCNT, 0); 1213 CSR_WRITE_2(sc, BM_TX_LTCNT, 0); 1214 1215 /* Zero receive counters */ 1216 CSR_WRITE_2(sc, BM_RX_FRCNT, 0); 1217 CSR_WRITE_2(sc, BM_RX_LECNT, 0); 1218 CSR_WRITE_2(sc, BM_RX_AECNT, 0); 1219 CSR_WRITE_2(sc, BM_RX_FECNT, 0); 1220 CSR_WRITE_2(sc, BM_RXCV, 0); 1221 1222 /* Check for link changes and run watchdog */ 1223 mii_tick(sc->sc_mii); 1224 bm_miibus_statchg(sc->sc_dev); 1225 1226 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 1227 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc); 1228 return; 1229 } 1230 1231 /* Problems */ 1232 device_printf(sc->sc_dev, "device timeout\n"); 1233 1234 bm_init_locked(sc); 1235 } 1236 1237 static int 1238 bm_add_rxbuf(struct bm_softc *sc, int idx) 1239 { 1240 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1241 struct mbuf *m; 1242 bus_dma_segment_t segs[1]; 1243 int error, nsegs; 1244 1245 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1246 if (m == NULL) 1247 return (ENOBUFS); 1248 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1249 1250 if (rxs->rxs_mbuf != NULL) { 1251 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, 1252 BUS_DMASYNC_POSTREAD); 1253 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap); 1254 } 1255 1256 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m, 1257 segs, &nsegs, BUS_DMA_NOWAIT); 1258 if (error != 0) { 1259 device_printf(sc->sc_dev, 1260 "cannot load RS DMA map %d, error = %d\n", idx, error); 1261 m_freem(m); 1262 return (error); 1263 } 1264 /* If nsegs is wrong then the stack is corrupt. */ 1265 KASSERT(nsegs == 1, 1266 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1267 rxs->rxs_mbuf = m; 1268 rxs->segment = segs[0]; 1269 1270 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 1271 1272 return (0); 1273 } 1274 1275 static int 1276 bm_add_rxbuf_dma(struct bm_softc *sc, int idx) 1277 { 1278 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1279 1280 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0, 1281 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS, 1282 DBDMA_NEVER, DBDMA_NEVER, 0); 1283 1284 return (0); 1285 } 1286 1287 static void 1288 bm_enable_interrupts(struct bm_softc *sc) 1289 { 1290 CSR_WRITE_2(sc, BM_INTR_DISABLE, 1291 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL); 1292 } 1293 1294 static void 1295 bm_disable_interrupts(struct bm_softc *sc) 1296 { 1297 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE); 1298 } 1299