1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/pciio.h> 41 #include <sys/rman.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pci_private.h> 45 46 #include <machine/resource.h> 47 48 #include <linux/list.h> 49 #include <linux/dmapool.h> 50 #include <linux/dma-mapping.h> 51 #include <linux/compiler.h> 52 #include <linux/errno.h> 53 #include <asm/atomic.h> 54 #include <linux/device.h> 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64 }; 65 66 #define MODULE_DEVICE_TABLE(bus, table) 67 68 #define PCI_BASE_CLASS_DISPLAY 0x03 69 #define PCI_CLASS_DISPLAY_VGA 0x0300 70 #define PCI_CLASS_DISPLAY_OTHER 0x0380 71 #define PCI_BASE_CLASS_BRIDGE 0x06 72 #define PCI_CLASS_BRIDGE_ISA 0x0601 73 74 #define PCI_ANY_ID -1U 75 #define PCI_VENDOR_ID_APPLE 0x106b 76 #define PCI_VENDOR_ID_ASUSTEK 0x1043 77 #define PCI_VENDOR_ID_ATI 0x1002 78 #define PCI_VENDOR_ID_DELL 0x1028 79 #define PCI_VENDOR_ID_HP 0x103c 80 #define PCI_VENDOR_ID_IBM 0x1014 81 #define PCI_VENDOR_ID_INTEL 0x8086 82 #define PCI_VENDOR_ID_MELLANOX 0x15b3 83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 85 #define PCI_VENDOR_ID_SONY 0x104d 86 #define PCI_VENDOR_ID_TOPSPIN 0x1867 87 #define PCI_VENDOR_ID_VIA 0x1106 88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96 #define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100 #define PCI_FUNC(devfn) ((devfn) & 0x07) 101 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 102 103 #define PCI_VDEVICE(_vendor, _device) \ 104 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106 #define PCI_DEVICE(_vendor, _device) \ 107 .vendor = (_vendor), .device = (_device), \ 108 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 109 110 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 111 112 #define PCI_VENDOR_ID PCIR_DEVVENDOR 113 #define PCI_COMMAND PCIR_COMMAND 114 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 115 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 116 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 117 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 118 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 119 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 120 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 121 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 122 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 123 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 124 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 125 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 126 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 127 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 128 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 129 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 130 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 131 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 132 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 133 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 134 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 135 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 136 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 137 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 138 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 139 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 140 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 141 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 142 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 143 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 144 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 145 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 146 147 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 148 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 149 #define PCI_EXP_DEVSTA_TRPND 0x0020 150 151 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 152 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 153 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 154 155 enum pci_bus_speed { 156 PCI_SPEED_UNKNOWN = -1, 157 PCIE_SPEED_2_5GT, 158 PCIE_SPEED_5_0GT, 159 PCIE_SPEED_8_0GT, 160 }; 161 162 enum pcie_link_width { 163 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 164 }; 165 166 typedef int pci_power_t; 167 168 #define PCI_D0 PCI_POWERSTATE_D0 169 #define PCI_D1 PCI_POWERSTATE_D1 170 #define PCI_D2 PCI_POWERSTATE_D2 171 #define PCI_D3hot PCI_POWERSTATE_D3 172 #define PCI_D3cold 4 173 174 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 175 176 struct pci_dev; 177 178 struct pci_driver { 179 struct list_head links; 180 char *name; 181 const struct pci_device_id *id_table; 182 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 183 void (*remove)(struct pci_dev *dev); 184 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 185 int (*resume) (struct pci_dev *dev); /* Device woken up */ 186 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 187 driver_t bsddriver; 188 devclass_t bsdclass; 189 struct device_driver driver; 190 const struct pci_error_handlers *err_handler; 191 bool isdrm; 192 }; 193 194 struct pci_bus { 195 struct pci_dev *self; 196 int number; 197 }; 198 199 extern struct list_head pci_drivers; 200 extern struct list_head pci_devices; 201 extern spinlock_t pci_lock; 202 203 #define __devexit_p(x) x 204 205 struct pci_dev { 206 struct device dev; 207 struct list_head links; 208 struct pci_driver *pdrv; 209 struct pci_bus *bus; 210 uint64_t dma_mask; 211 uint16_t device; 212 uint16_t vendor; 213 uint16_t subsystem_vendor; 214 uint16_t subsystem_device; 215 unsigned int irq; 216 unsigned int devfn; 217 uint32_t class; 218 uint8_t revision; 219 }; 220 221 static inline struct resource_list_entry * 222 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 223 { 224 struct pci_devinfo *dinfo; 225 struct resource_list *rl; 226 227 dinfo = device_get_ivars(pdev->dev.bsddev); 228 rl = &dinfo->resources; 229 return resource_list_find(rl, type, rid); 230 } 231 232 static inline struct resource_list_entry * 233 linux_pci_get_bar(struct pci_dev *pdev, int bar) 234 { 235 struct resource_list_entry *rle; 236 237 bar = PCIR_BAR(bar); 238 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 239 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 240 return (rle); 241 } 242 243 static inline struct device * 244 linux_pci_find_irq_dev(unsigned int irq) 245 { 246 struct pci_dev *pdev; 247 struct device *found; 248 249 found = NULL; 250 spin_lock(&pci_lock); 251 list_for_each_entry(pdev, &pci_devices, links) { 252 if (irq == pdev->dev.irq || 253 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 254 found = &pdev->dev; 255 break; 256 } 257 } 258 spin_unlock(&pci_lock); 259 return (found); 260 } 261 262 static inline unsigned long 263 pci_resource_start(struct pci_dev *pdev, int bar) 264 { 265 struct resource_list_entry *rle; 266 267 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 268 return (0); 269 return rle->start; 270 } 271 272 static inline unsigned long 273 pci_resource_len(struct pci_dev *pdev, int bar) 274 { 275 struct resource_list_entry *rle; 276 277 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 278 return (0); 279 return rle->count; 280 } 281 282 static inline int 283 pci_resource_type(struct pci_dev *pdev, int bar) 284 { 285 struct pci_map *pm; 286 287 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 288 if (!pm) 289 return (-1); 290 291 if (PCI_BAR_IO(pm->pm_value)) 292 return (SYS_RES_IOPORT); 293 else 294 return (SYS_RES_MEMORY); 295 } 296 297 /* 298 * All drivers just seem to want to inspect the type not flags. 299 */ 300 static inline int 301 pci_resource_flags(struct pci_dev *pdev, int bar) 302 { 303 int type; 304 305 type = pci_resource_type(pdev, bar); 306 if (type < 0) 307 return (0); 308 return (1 << type); 309 } 310 311 static inline const char * 312 pci_name(struct pci_dev *d) 313 { 314 315 return device_get_desc(d->dev.bsddev); 316 } 317 318 static inline void * 319 pci_get_drvdata(struct pci_dev *pdev) 320 { 321 322 return dev_get_drvdata(&pdev->dev); 323 } 324 325 static inline void 326 pci_set_drvdata(struct pci_dev *pdev, void *data) 327 { 328 329 dev_set_drvdata(&pdev->dev, data); 330 } 331 332 static inline int 333 pci_enable_device(struct pci_dev *pdev) 334 { 335 336 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 337 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 338 return (0); 339 } 340 341 static inline void 342 pci_disable_device(struct pci_dev *pdev) 343 { 344 345 pci_disable_busmaster(pdev->dev.bsddev); 346 } 347 348 static inline int 349 pci_set_master(struct pci_dev *pdev) 350 { 351 352 pci_enable_busmaster(pdev->dev.bsddev); 353 return (0); 354 } 355 356 static inline int 357 pci_set_power_state(struct pci_dev *pdev, int state) 358 { 359 360 pci_set_powerstate(pdev->dev.bsddev, state); 361 return (0); 362 } 363 364 static inline int 365 pci_clear_master(struct pci_dev *pdev) 366 { 367 368 pci_disable_busmaster(pdev->dev.bsddev); 369 return (0); 370 } 371 372 static inline int 373 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 374 { 375 int rid; 376 int type; 377 378 type = pci_resource_type(pdev, bar); 379 if (type < 0) 380 return (-ENODEV); 381 rid = PCIR_BAR(bar); 382 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 383 RF_ACTIVE) == NULL) 384 return (-EINVAL); 385 return (0); 386 } 387 388 static inline void 389 pci_release_region(struct pci_dev *pdev, int bar) 390 { 391 struct resource_list_entry *rle; 392 393 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 394 return; 395 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 396 } 397 398 static inline void 399 pci_release_regions(struct pci_dev *pdev) 400 { 401 int i; 402 403 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 404 pci_release_region(pdev, i); 405 } 406 407 static inline int 408 pci_request_regions(struct pci_dev *pdev, const char *res_name) 409 { 410 int error; 411 int i; 412 413 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 414 error = pci_request_region(pdev, i, res_name); 415 if (error && error != -ENODEV) { 416 pci_release_regions(pdev); 417 return (error); 418 } 419 } 420 return (0); 421 } 422 423 static inline void 424 pci_disable_msix(struct pci_dev *pdev) 425 { 426 427 pci_release_msi(pdev->dev.bsddev); 428 429 /* 430 * The MSIX IRQ numbers associated with this PCI device are no 431 * longer valid and might be re-assigned. Make sure 432 * linux_pci_find_irq_dev() does no longer see them by 433 * resetting their references to zero: 434 */ 435 pdev->dev.msix = 0; 436 pdev->dev.msix_max = 0; 437 } 438 439 static inline bus_addr_t 440 pci_bus_address(struct pci_dev *pdev, int bar) 441 { 442 443 return (pci_resource_start(pdev, bar)); 444 } 445 446 #define PCI_CAP_ID_EXP PCIY_EXPRESS 447 #define PCI_CAP_ID_PCIX PCIY_PCIX 448 #define PCI_CAP_ID_AGP PCIY_AGP 449 #define PCI_CAP_ID_PM PCIY_PMG 450 451 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 452 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 453 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 454 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 455 #define PCI_EXP_LNKSTA PCIER_LINK_STA 456 457 static inline int 458 pci_find_capability(struct pci_dev *pdev, int capid) 459 { 460 int reg; 461 462 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 463 return (0); 464 return (reg); 465 } 466 467 static inline int pci_pcie_cap(struct pci_dev *dev) 468 { 469 return pci_find_capability(dev, PCI_CAP_ID_EXP); 470 } 471 472 473 static inline int 474 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 475 { 476 477 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 478 return (0); 479 } 480 481 static inline int 482 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 483 { 484 485 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 486 return (0); 487 } 488 489 static inline int 490 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 491 { 492 493 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 494 return (0); 495 } 496 497 static inline int 498 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 499 { 500 501 pci_write_config(pdev->dev.bsddev, where, val, 1); 502 return (0); 503 } 504 505 static inline int 506 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 507 { 508 509 pci_write_config(pdev->dev.bsddev, where, val, 2); 510 return (0); 511 } 512 513 static inline int 514 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 515 { 516 517 pci_write_config(pdev->dev.bsddev, where, val, 4); 518 return (0); 519 } 520 521 int linux_pci_register_driver(struct pci_driver *pdrv); 522 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 523 void linux_pci_unregister_driver(struct pci_driver *pdrv); 524 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 525 526 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 527 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 528 529 struct msix_entry { 530 int entry; 531 int vector; 532 }; 533 534 /* 535 * Enable msix, positive errors indicate actual number of available 536 * vectors. Negative errors are failures. 537 * 538 * NB: define added to prevent this definition of pci_enable_msix from 539 * clashing with the native FreeBSD version. 540 */ 541 #define pci_enable_msix(...) \ 542 linux_pci_enable_msix(__VA_ARGS__) 543 544 static inline int 545 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 546 { 547 struct resource_list_entry *rle; 548 int error; 549 int avail; 550 int i; 551 552 avail = pci_msix_count(pdev->dev.bsddev); 553 if (avail < nreq) { 554 if (avail == 0) 555 return -EINVAL; 556 return avail; 557 } 558 avail = nreq; 559 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 560 return error; 561 /* 562 * Handle case where "pci_alloc_msix()" may allocate less 563 * interrupts than available and return with no error: 564 */ 565 if (avail < nreq) { 566 pci_release_msi(pdev->dev.bsddev); 567 return avail; 568 } 569 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 570 pdev->dev.msix = rle->start; 571 pdev->dev.msix_max = rle->start + avail; 572 for (i = 0; i < nreq; i++) 573 entries[i].vector = pdev->dev.msix + i; 574 return (0); 575 } 576 577 #define pci_enable_msix_range(...) \ 578 linux_pci_enable_msix_range(__VA_ARGS__) 579 580 static inline int 581 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 582 int minvec, int maxvec) 583 { 584 int nvec = maxvec; 585 int rc; 586 587 if (maxvec < minvec) 588 return (-ERANGE); 589 590 do { 591 rc = pci_enable_msix(dev, entries, nvec); 592 if (rc < 0) { 593 return (rc); 594 } else if (rc > 0) { 595 if (rc < minvec) 596 return (-ENOSPC); 597 nvec = rc; 598 } 599 } while (rc); 600 return (nvec); 601 } 602 603 static inline int 604 pci_channel_offline(struct pci_dev *pdev) 605 { 606 607 return (pci_get_vendor(pdev->dev.bsddev) == PCIV_INVALID); 608 } 609 610 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 611 { 612 return -ENODEV; 613 } 614 static inline void pci_disable_sriov(struct pci_dev *dev) 615 { 616 } 617 618 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 619 const struct pci_device_id _table[] __devinitdata 620 621 622 /* XXX This should not be necessary. */ 623 #define pcix_set_mmrbc(d, v) 0 624 #define pcix_get_max_mmrbc(d) 0 625 #define pcie_set_readrq(d, v) 0 626 627 #define PCI_DMA_BIDIRECTIONAL 0 628 #define PCI_DMA_TODEVICE 1 629 #define PCI_DMA_FROMDEVICE 2 630 #define PCI_DMA_NONE 3 631 632 #define pci_pool dma_pool 633 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 634 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 635 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 636 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 637 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 638 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 639 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 640 _size, _vaddr, _dma_handle) 641 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 642 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 643 _sg, _nents, (enum dma_data_direction)_dir) 644 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 645 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 646 (_ptr), (_size), (enum dma_data_direction)_dir) 647 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 648 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 649 _addr, _size, (enum dma_data_direction)_dir) 650 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 651 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 652 _sg, _nents, (enum dma_data_direction)_dir) 653 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 654 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 655 _offset, _size, (enum dma_data_direction)_dir) 656 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 657 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 658 _dma_address, _size, (enum dma_data_direction)_dir) 659 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 660 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 661 dma_mapping_error(&(_pdev)->dev, _dma_addr) 662 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 663 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 664 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 665 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 666 #define pci_unmap_addr dma_unmap_addr 667 #define pci_unmap_addr_set dma_unmap_addr_set 668 #define pci_unmap_len dma_unmap_len 669 #define pci_unmap_len_set dma_unmap_len_set 670 671 typedef unsigned int __bitwise pci_channel_state_t; 672 typedef unsigned int __bitwise pci_ers_result_t; 673 674 enum pci_channel_state { 675 pci_channel_io_normal = 1, 676 pci_channel_io_frozen = 2, 677 pci_channel_io_perm_failure = 3, 678 }; 679 680 enum pci_ers_result { 681 PCI_ERS_RESULT_NONE = 1, 682 PCI_ERS_RESULT_CAN_RECOVER = 2, 683 PCI_ERS_RESULT_NEED_RESET = 3, 684 PCI_ERS_RESULT_DISCONNECT = 4, 685 PCI_ERS_RESULT_RECOVERED = 5, 686 }; 687 688 689 /* PCI bus error event callbacks */ 690 struct pci_error_handlers { 691 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 692 enum pci_channel_state error); 693 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 694 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 695 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 696 void (*resume)(struct pci_dev *dev); 697 }; 698 699 /* FreeBSD does not support SRIOV - yet */ 700 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 701 { 702 return dev; 703 } 704 705 static inline bool pci_is_pcie(struct pci_dev *dev) 706 { 707 return !!pci_pcie_cap(dev); 708 } 709 710 static inline u16 pcie_flags_reg(struct pci_dev *dev) 711 { 712 int pos; 713 u16 reg16; 714 715 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 716 if (!pos) 717 return 0; 718 719 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 720 721 return reg16; 722 } 723 724 725 static inline int pci_pcie_type(struct pci_dev *dev) 726 { 727 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 728 } 729 730 static inline int pcie_cap_version(struct pci_dev *dev) 731 { 732 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 733 } 734 735 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 736 { 737 int type = pci_pcie_type(dev); 738 739 return pcie_cap_version(dev) > 1 || 740 type == PCI_EXP_TYPE_ROOT_PORT || 741 type == PCI_EXP_TYPE_ENDPOINT || 742 type == PCI_EXP_TYPE_LEG_END; 743 } 744 745 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 746 { 747 return true; 748 } 749 750 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 751 { 752 int type = pci_pcie_type(dev); 753 754 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 755 (type == PCI_EXP_TYPE_DOWNSTREAM && 756 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 757 } 758 759 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 760 { 761 int type = pci_pcie_type(dev); 762 763 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 764 type == PCI_EXP_TYPE_RC_EC; 765 } 766 767 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 768 { 769 if (!pci_is_pcie(dev)) 770 return false; 771 772 switch (pos) { 773 case PCI_EXP_FLAGS_TYPE: 774 return true; 775 case PCI_EXP_DEVCAP: 776 case PCI_EXP_DEVCTL: 777 case PCI_EXP_DEVSTA: 778 return pcie_cap_has_devctl(dev); 779 case PCI_EXP_LNKCAP: 780 case PCI_EXP_LNKCTL: 781 case PCI_EXP_LNKSTA: 782 return pcie_cap_has_lnkctl(dev); 783 case PCI_EXP_SLTCAP: 784 case PCI_EXP_SLTCTL: 785 case PCI_EXP_SLTSTA: 786 return pcie_cap_has_sltctl(dev); 787 case PCI_EXP_RTCTL: 788 case PCI_EXP_RTCAP: 789 case PCI_EXP_RTSTA: 790 return pcie_cap_has_rtctl(dev); 791 case PCI_EXP_DEVCAP2: 792 case PCI_EXP_DEVCTL2: 793 case PCI_EXP_LNKCAP2: 794 case PCI_EXP_LNKCTL2: 795 case PCI_EXP_LNKSTA2: 796 return pcie_cap_version(dev) > 1; 797 default: 798 return false; 799 } 800 } 801 802 static inline int 803 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 804 { 805 if (pos & 3) 806 return -EINVAL; 807 808 if (!pcie_capability_reg_implemented(dev, pos)) 809 return -EINVAL; 810 811 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 812 } 813 814 static inline int 815 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 816 { 817 if (pos & 3) 818 return -EINVAL; 819 820 if (!pcie_capability_reg_implemented(dev, pos)) 821 return -EINVAL; 822 823 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 824 } 825 826 static inline int 827 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 828 { 829 if (pos & 1) 830 return -EINVAL; 831 832 if (!pcie_capability_reg_implemented(dev, pos)) 833 return 0; 834 835 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 836 } 837 838 static inline int pcie_get_minimum_link(struct pci_dev *dev, 839 enum pci_bus_speed *speed, enum pcie_link_width *width) 840 { 841 *speed = PCI_SPEED_UNKNOWN; 842 *width = PCIE_LNK_WIDTH_UNKNOWN; 843 return (0); 844 } 845 846 static inline int 847 pci_num_vf(struct pci_dev *dev) 848 { 849 return (0); 850 } 851 852 #endif /* _LINUX_PCI_H_ */ 853