1.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" This software is provided by Joseph Koshy ``as is'' and 13.\" any express or implied warranties, including, but not limited to, the 14.\" implied warranties of merchantability and fitness for a particular purpose 15.\" are disclaimed. in no event shall Joseph Koshy be liable 16.\" for any direct, indirect, incidental, special, exemplary, or consequential 17.\" damages (including, but not limited to, procurement of substitute goods 18.\" or services; loss of use, data, or profits; or business interruption) 19.\" however caused and on any theory of liability, whether in contract, strict 20.\" liability, or tort (including negligence or otherwise) arising in any way 21.\" out of the use of this software, even if advised of the possibility of 22.\" such damage. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd October 4, 2008 27.Dt PMC.P4 3 28.Os 29.Sh NAME 30.Nm pmc.p4 31.Nd measurement events for 32.Tn "Intel Pentium 4" 33and other 34.Tn Netburst 35architecture CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41Intel P4 PMCs are present in Intel 42.Tn "Pentium 4" 43and 44.Tn Xeon 45processors that use the 46.Tn Netburst 47CPU architecture. 48.Pp 49These PMCs are documented in 50.Rs 51.%B "IA-32 Intel(R) Architecture Software Developer's Manual" 52.%T "Volume 3: System Programming Guide" 53.%N "Order Number 245472-012" 54.%D 2003 55.%Q "Intel Corporation" 56.Re 57Further information about using these PMCs may be found in 58.Rs 59.%B "IA-32 Intel(R) Architecture Optimization Guide" 60.%D 2003 61.%N "Order Number 248966-009" 62.%Q "Intel Corporation" 63.Re 64Some of these events are affected by processor errata described in 65.Rs 66.%B "Intel(R) Pentium(R) 4 Processor Specification Update" 67.%N "Document Number: 249199-059" 68.%D "April 2005" 69.%Q "Intel Corporation" 70.Re 71.Ss PMC Features 72Intel Pentium 4 PMCs are 40 bits wide. 73Each CPU contains 18 PMCs, divided into 4 groups with 4, 4, 4 and 6 74PMCs respectively. 75On processors with hyperthreading support, PMC resources are shared 76between logical processors. 77These PMCs support the following capabilities: 78.Bl -column "PMC_CAP_INTERRUPT" "Support" 79.It Em Capability Ta Em Support 80.It PMC_CAP_CASCADE Ta Yes 81.It PMC_CAP_EDGE Ta Yes 82.It PMC_CAP_INTERRUPT Ta Yes 83.It PMC_CAP_INVERT Ta Yes 84.It PMC_CAP_READ Ta Yes 85.It PMC_CAP_PRECISE Ta Unimplemented 86.It PMC_CAP_SYSTEM Ta Yes 87.It PMC_CAP_TAGGING Ta Yes 88.It PMC_CAP_THRESHOLD Ta Yes 89.It PMC_CAP_USER Ta Yes 90.It PMC_CAP_WRITE Ta Yes 91.El 92.Ss Event Qualifiers 93.Pp 94Event specifiers for Intel P4 PMCs can have the following common 95qualifiers: 96.Bl -tag -width indent 97.It Li active= Ns Ar choice 98(On P4 HTT CPUs) Filter event counting based on which logical 99processors are active. 100The allowed values of 101.Ar choice 102are: 103.Pp 104.Bl -tag -width indent -compact 105.It Li any 106Count when either logical processor is active. 107.It Li both 108Count when both logical processors are active. 109.It Li none 110Count only when neither logical processor is active. 111.It Li single 112Count only when one logical processor is active. 113.El 114.Pp 115The default is 116.Dq Li both . 117.It Li cascade 118Configure the PMC to cascade onto its partner. 119See 120.Sx "Cascading P4 PMCs" 121below for more information. 122.It Li edge 123Configure the counter to count false to true transitions of the threshold 124comparison output. 125This qualifier only takes effect if a threshold qualifier has also been 126specified. 127.It Li complement 128Configure the counter to increment only when the event count seen is 129less than the threshold qualifier value specified. 130.It Li mask= Ns Ar qualifier 131Many event specifiers for Intel P4 PMCs need to be additionally 132qualified using a mask qualifier. 133The allowed syntax for these qualifiers is event specific and is 134described along with the events. 135.It Li os 136Configure the PMC to count when the CPL of the processor is 0. 137.It Li precise 138Select precise event based sampling. 139Precise sampling is supported by the hardware for a limited set of 140events. 141.It Li tag= Ns Ar value 142Configure the PMC to tag the internal uop selected by the other 143fields in this event specifier with value 144.Ar value . 145This feature is used when cascading PMCs. 146.It Li threshold= Ns Ar value 147Configure the PMC to increment only when the event counts seen are 148greater than the specified threshold value 149.Ar value . 150.It Li usr 151Configure the PMC to count when the CPL of the processor is 1, 2 or 3. 152.El 153.Pp 154If neither of the 155.Dq Li os 156or 157.Dq Li usr 158qualifiers are specified, the default is to enable both. 159.Pp 160On Intel Pentium 4 processors with HTT, events are 161divided into two classes: 162.Pp 163.Bl -tag -width indent -compact 164.It "TS Events" 165are those where hardware can differentiate between events 166generated on one logical processor from those generated on the 167other. 168.It "TI Events" 169are those where hardware cannot differentiate between events 170generated by multiple logical processors in a package. 171.El 172.Pp 173Only TS events are allowed for use with process-mode PMCs on 174Pentium-4/HTT CPUs. 175.Pp 176The event specifiers supported by Intel P4 PMCs are: 177.Bl -tag -width indent 178.It Li p4-128bit-mmx-uop Op Li ,mask= Ns Ar flags 179.Pq "TI event" 180Count integer SIMD SSE2 instructions that operate on 128 bit SIMD 181operands. 182Qualifier 183.Ar flags 184can take the following value (which is also the default): 185.Pp 186.Bl -tag -width indent -compact 187.It Li all 188Count all uops operating on 128 bit SIMD integer operands in memory or 189XMM register. 190.El 191.Pp 192If an instruction contains more than one 128 bit MMX uop, then each 193uop will be counted. 194.It Li p4-64bit-mmx-uop Op Li ,mask= Ns Ar flags 195.Pq "TI event" 196Count MMX instructions that operate on 64 bit SIMD operands. 197Qualifier 198.Ar flags 199can take the following value (which is also the default): 200.Pp 201.Bl -tag -width indent -compact 202.It Li all 203Count all uops operating on 64 bit SIMD integer operands in memory or 204in MMX registers. 205.El 206.Pp 207If an instruction contains more than one 64 bit MMX uop, then each 208uop will be counted. 209.It Li p4-b2b-cycles 210.Pq "TI event" 211Count back-to-back bus cycles. 212Further documentation for this event is unavailable. 213.It Li p4-bnr 214.Pq "TI event" 215Count bus-not-ready conditions. 216Further documentation for this event is unavailable. 217.It Li p4-bpu-fetch-request Op Li ,mask= Ns Ar qualifier 218.Pq "TS event" 219Count instruction fetch requests qualified by additional 220flags specified in 221.Ar qualifier . 222At this point only one flag is supported: 223.Pp 224.Bl -tag -width indent -compact 225.It Li tcmiss 226Count trace cache lookup misses. 227.El 228.Pp 229The default qualifier is also 230.Dq Li mask=tcmiss . 231.It Li p4-branch-retired Op Li ,mask= Ns Ar flags 232.Pq "TS event" 233Counts retired branches. 234Qualifier 235.Ar flags 236is a list of the following 237.Ql + 238separated strings: 239.Pp 240.Bl -tag -width indent -compact 241.It Li mmnp 242Count branches not-taken and predicted. 243.It Li mmnm 244Count branches not-taken and mis-predicted. 245.It Li mmtp 246Count branches taken and predicted. 247.It Li mmtm 248Count branches taken and mis-predicted. 249.El 250.Pp 251The default qualifier counts all four kinds of branches. 252.It Li p4-bsq-active-entries Op Li ,mask= Ns Ar qualifier 253.Pq "TS event" 254Count the number of entries (clipped at 15) currently active in the 255BSQ. 256Qualifier 257.Ar qualifier 258is a 259.Ql + 260separated set of the following flags: 261.Pp 262.Bl -tag -width indent -compact 263.It Li req-type0 , Li req-type1 264Forms a 2-bit number used to select the request type encoding: 265.Pp 266.Bl -tag -width indent -compact 267.It Li 0 268reads excluding read invalidate 269.It Li 1 270read invalidates 271.It Li 2 272writes other than writebacks 273.It Li 3 274writebacks 275.El 276.Pp 277Bit 278.Dq Li req-type1 279is the MSB for this two bit number. 280.It Li req-len0 , Li req-len1 281Forms a two-bit number that specifies the request length encoding: 282.Pp 283.Bl -tag -width indent -compact 284.It Li 0 2850 chunks 286.It Li 1 2871 chunk 288.It Li 3 2898 chunks 290.El 291.Pp 292Bit 293.Dq Li req-len1 294is the MSB for this two bit number. 295.It Li req-io-type 296Count requests that are input or output requests. 297.It Li req-lock-type 298Count requests that lock the bus. 299.It Li req-lock-cache 300Count requests that lock the cache. 301.It Li req-split-type 302Count requests that is a bus 8-byte chunk that is split across an 3038-byte boundary. 304.It Li req-dem-type 305Count requests that are demand (not prefetches) if set. 306Count requests that are prefetches if not set. 307.It Li req-ord-type 308Count requests that are ordered. 309.It Li mem-type0 , Li mem-type1 , Li mem-type2 310Forms a 3-bit number that specifies a memory type encoding: 311.Pp 312.Bl -tag -width indent -compact 313.It Li 0 314UC 315.It Li 1 316USWC 317.It Li 4 318WT 319.It Li 5 320WP 321.It Li 6 322WB 323.El 324.Pp 325Bit 326.Dq Li mem-type2 327is the MSB of this 3-bit number. 328.El 329.Pp 330The default qualifier has all the above bits set. 331.Pp 332Edge triggering using the 333.Dq Li edge 334qualifier should not be used with this event when counting cycles. 335.It Li p4-bsq-allocation Op Li ,mask= Ns Ar qualifier 336.Pq "TS event" 337Count allocations in the bus sequence unit according to the flags 338specified in 339.Ar qualifier , 340which is a 341.Ql + 342separated set of the following flags: 343.Pp 344.Bl -tag -width indent -compact 345.It Li req-type0 , Li req-type1 346Forms a 2-bit number used to select the request type encoding: 347.Pp 348.Bl -tag -width indent -compact 349.It Li 0 350reads excluding read invalidate 351.It Li 1 352read invalidates 353.It Li 2 354writes other than writebacks 355.It Li 3 356writebacks 357.El 358.Pp 359Bit 360.Dq Li req-type1 361is the MSB for this two bit number. 362.It Li req-len0 , Li req-len1 363Forms a two-bit number that specifies the request length encoding: 364.Pp 365.Bl -tag -width indent -compact 366.It Li 0 3670 chunks 368.It Li 1 3691 chunk 370.It Li 3 3718 chunks 372.El 373.Pp 374Bit 375.Dq Li req-len1 376is the MSB for this two bit number. 377.It Li req-io-type 378Count requests that are input or output requests. 379.It Li req-lock-type 380Count requests that lock the bus. 381.It Li req-lock-cache 382Count requests that lock the cache. 383.It Li req-split-type 384Count requests that is a bus 8-byte chunk that is split across an 3858-byte boundary. 386.It Li req-dem-type 387Count requests that are demand (not prefetches) if set. 388Count requests that are prefetches if not set. 389.It Li req-ord-type 390Count requests that are ordered. 391.It Li mem-type0 , Li mem-type1 , Li mem-type2 392Forms a 3-bit number that specifies a memory type encoding: 393.Pp 394.Bl -tag -width indent -compact 395.It Li 0 396UC 397.It Li 1 398USWC 399.It Li 4 400WT 401.It Li 5 402WP 403.It Li 6 404WB 405.El 406.Pp 407Bit 408.Dq Li mem-type2 409is the MSB of this 3-bit number. 410.El 411.Pp 412The default qualifier has all the above bits set. 413.Pp 414This event is usually used along with the 415.Dq Li edge 416qualifier to avoid multiple counting. 417.It Li p4-bsq-cache-reference Op Li ,mask= Ns Ar qualifier 418.Pq "TS event" 419Count cache references as seen by the bus unit (2nd or 3rd level 420cache references). 421Qualifier 422.Ar qualifier 423is a 424.Ql + 425separated list of the following keywords: 426.Pp 427.Bl -tag -width indent -compact 428.It Li rd-2ndl-hits 429Count 2nd level cache hits in the shared state. 430.It Li rd-2ndl-hite 431Count 2nd level cache hits in the exclusive state. 432.It Li rd-2ndl-hitm 433Count 2nd level cache hits in the modified state. 434.It Li rd-3rdl-hits 435Count 3rd level cache hits in the shared state. 436.It Li rd-3rdl-hite 437Count 3rd level cache hits in the exclusive state. 438.It Li rd-3rdl-hitm 439Count 3rd level cache hits in the modified state. 440.It Li rd-2ndl-miss 441Count 2nd level cache misses. 442.It Li rd-3rdl-miss 443Count 3rd level cache misses. 444.It Li wr-2ndl-miss 445Count write-back lookups from the data access cache that miss the 2nd 446level cache. 447.El 448.Pp 449The default is to count all the above events. 450.It Li p4-execution-event Op Li ,mask= Ns Ar flags 451.Pq "TS event" 452Count the retirement of tagged uops selected through the execution 453tagging mechanism. 454Qualifier 455.Ar flags 456can contain the following strings separated by 457.Ql + 458characters: 459.Pp 460.Bl -tag -width indent -compact 461.It Li nbogus0 , Li nbogus1 , Li nbogus2 , Li nbogus3 462The marked uops are not bogus. 463.It Li bogus0 , Li bogus1 , Li bogus2 , Li bogus3 464The marked uops are bogus. 465.El 466.Pp 467This event requires additional (upstream) events to be allocated to 468perform the desired uop tagging. 469The default is to set all the above flags. 470This event can be used for precise event based sampling. 471.It Li p4-front-end-event Op Li ,mask= Ns Ar flags 472.Pq "TS event" 473Count the retirement of tagged uops selected through the front-end 474tagging mechanism. 475Qualifier 476.Ar flags 477can contain the following strings separated by 478.Ql + 479characters: 480.Pp 481.Bl -tag -width indent -compact 482.It Li nbogus 483The marked uops are not bogus. 484.It Li bogus 485The marked uops are bogus. 486.El 487.Pp 488This event requires additional (upstream) events to be allocated to 489perform the desired uop tagging. 490The default is to select both kinds of events. 491This event can be used for precise event based sampling. 492.It Li p4-fsb-data-activity Op Li ,mask= Ns Ar flags 493.Pq "TI event" 494Count each DBSY or DRDY event selected by qualifier 495.Ar flags . 496Qualifier 497.Ar flags 498is a 499.Ql + 500separated set of the following flags: 501.Pp 502.Bl -tag -width indent -compact 503.It Li drdy-drv 504Count when this processor is driving data onto the bus. 505.It Li drdy-own 506Count when this processor is reading data from the bus. 507.It Li drdy-other 508Count when data is on the bus but not being sampled by this processor. 509.It Li dbsy-drv 510Count when this processor reserves the bus for use in the next cycle 511in order to drive data. 512.It Li dbsy-own 513Count when some agent reserves the bus for use in the next bus cycle 514to drive data that this processor will sample. 515.It Li dbsy-other 516Count when some agent reserves the bus for use in the next bus cycle 517to drive data that this processor will not sample. 518.El 519.Pp 520Flags 521.Dq Li drdy-own 522and 523.Dq Li drdy-other 524are mutually exclusive. 525Flags 526.Dq Li dbsy-own 527and 528.Dq Li dbsy-other 529are mutually exclusive. 530The default value for 531.Ar qualifier 532is 533.Dq Li drdy-drv+drdy-own+dbsy-drv+dbsy-own . 534.It Li p4-global-power-events Op Li ,mask= Ns Ar flags 535.Pq "TS event" 536Count cycles during which the processor is not stopped. 537Qualifier 538.Ar flags 539can take the following value (which is also the default): 540.Pp 541.Bl -tag -width indent -compact 542.It Li running 543Count cycles when the processor is active. 544.El 545.Pp 546.It Li p4-instr-retired Op Li ,mask= Ns Ar flags 547.Pq "TS event" 548Count instructions retired during a clock cycle. 549Qualifier 550.Ar flags 551comprises of the following strings separated by 552.Ql + 553characters: 554.Pp 555.Bl -tag -width indent -compact 556.It Li nbogusntag 557Count non-bogus instructions that are not tagged. 558.It Li nbogustag 559Count non-bogus instructions that are tagged. 560.It Li bogusntag 561Count bogus instructions that are not tagged. 562.It Li bogustag 563Count bogus instructions that are tagged. 564.El 565.Pp 566The default qualifier counts all the above kinds of instructions. 567.It Li p4-ioq-active-entries Xo 568.Op Li ,mask= Ns Ar qualifier 569.Op Li ,busreqtype= Ns Ar req-type 570.Xc 571.Pq "TS event" 572Count the number of entries (clipped at 15) in the IOQ that are 573active. 574The event masks are specified by qualifier 575.Ar qualifier 576and 577.Ar req-type . 578.Pp 579Qualifier 580.Ar qualifier 581is a 582.Ql + 583separated set of the following flags: 584.Pp 585.Bl -tag -width indent -compact 586.It Li all-read 587Count read entries. 588.It Li all-write 589Count write entries. 590.It Li mem-uc 591Count entries accessing un-cacheable memory. 592.It Li mem-wc 593Count entries accessing write-combining memory. 594.It Li mem-wt 595Count entries accessing write-through memory. 596.It Li mem-wp 597Count entries accessing write-protected memory 598.It Li mem-wb 599Count entries accessing write-back memory. 600.It Li own 601Count store requests driven by the processor (i.e., not by other 602processors or by DMA). 603.It Li other 604Count store requests driven by other processors or by DMA. 605.It Li prefetch 606Include hardware and software prefetch requests in the count. 607.El 608.Pp 609The default value for 610.Ar qualifier 611is to enable all the above flags. 612.Pp 613The 614.Ar req-type 615qualifier is a 5-bit number can be additionally used to select a 616specific bus request type. 617The default is 0. 618.Pp 619The 620.Dq Li edge 621qualifier should not be used when counting cycles with this event. 622The exact behavior of this event depends on the processor revision. 623.It Li p4-ioq-allocation Xo 624.Op Li ,mask= Ns Ar qualifier 625.Op Li ,busreqtype= Ns Ar req-type 626.Xc 627.Pq "TS event" 628Count various types of transactions on the bus matching the flags set 629in 630.Ar qualifier 631and 632.Ar req-type . 633.Pp 634Qualifier 635.Ar qualifier 636is a 637.Ql + 638separated set of the following flags: 639.Pp 640.Bl -tag -width indent -compact 641.It Li all-read 642Count read entries. 643.It Li all-write 644Count write entries. 645.It Li mem-uc 646Count entries accessing un-cacheable memory. 647.It Li mem-wc 648Count entries accessing write-combining memory. 649.It Li mem-wt 650Count entries accessing write-through memory. 651.It Li mem-wp 652Count entries accessing write-protected memory 653.It Li mem-wb 654Count entries accessing write-back memory. 655.It Li own 656Count store requests driven by the processor (i.e., not by other 657processors or by DMA). 658.It Li other 659Count store requests driven by other processors or by DMA. 660.It Li prefetch 661Include hardware and software prefetch requests in the count. 662.El 663.Pp 664The default value for 665.Ar qualifier 666is to enable all the above flags. 667.Pp 668The 669.Ar req-type 670qualifier is a 5-bit number can be additionally used to select a 671specific bus request type. 672The default is 0. 673.Pp 674The 675.Dq Li edge 676qualifier is normally used with this event to prevent multiple 677counting. 678The exact behavior of this event depends on the processor revision. 679.It Li p4-itlb-reference Op mask= Ns Ar qualifier 680.Pq "TS event" 681Count translations using the instruction translation look-aside 682buffer. 683The 684.Ar qualifier 685argument is a list of the following strings separated by 686.Ql + 687characters. 688.Pp 689.Bl -tag -width indent -compact 690.It Li hit 691Count ITLB hits. 692.It Li miss 693Count ITLB misses. 694.It Li hit-uc 695Count un-cacheable ITLB hits. 696.El 697.Pp 698If no 699.Ar qualifier 700is specified the default is to count all the three kinds of ITLB 701translations. 702.It Li p4-load-port-replay Op Li ,mask= Ns Ar qualifier 703.Pq "TS event" 704Count replayed events at the load port. 705Qualifier 706.Ar qualifier 707can take on one value: 708.Pp 709.Bl -tag -width indent -compact 710.It Li split-ld 711Count split loads. 712.El 713.Pp 714The default value for 715.Ar qualifier 716is 717.Dq Li split-ld . 718.It Li p4-mispred-branch-retired Op Li ,mask= Ns Ar flags 719.Pq "TS event" 720Count mispredicted IA-32 branch instructions. 721Qualifier 722.Ar flags 723can take the following value (which is also the default): 724.Pp 725.Bl -tag -width indent -compact 726.It Li nbogus 727Count non-bogus retired branch instructions. 728.El 729.It Li p4-machine-clear Op Li ,mask= Ns Ar flags 730.Pq "TS event" 731Count the number of pipeline clears seen by the processor. 732Qualifier 733.Ar flags 734is a list of the following strings separated by 735.Ql + 736characters: 737.Pp 738.Bl -tag -width indent -compact 739.It Li clear 740Count for a portion of the many cycles when the machine is being 741cleared for any reason. 742.It Li moclear 743Count machine clears due to memory ordering issues. 744.It Li smclear 745Count machine clears due to self-modifying code. 746.El 747.Pp 748Use qualifier 749.Dq Li edge 750to get a count of occurrences of machine clears. 751The default qualifier is 752.Dq Li clear . 753.It Li p4-memory-cancel Op Li ,mask= Ns Ar event-list 754.Pq "TS event" 755Count the canceling of various kinds of requests in the data cache 756address control unit of the CPU. 757The qualifier 758.Ar event-list 759is a list of the following strings separated by 760.Ql + 761characters: 762.Pp 763.Bl -tag -width indent -compact 764.It Li st-rb-full 765Requests cancelled because no store request buffer was available. 766.It Li 64k-conf 767Requests that conflict due to 64K aliasing. 768.El 769.Pp 770If 771.Ar event-list 772is not specified, then the default is to count both kinds of events. 773.It Li p4-memory-complete Op Li ,mask= Ns Ar event-list 774.Pq "TS event" 775Count the completion of load split, store split, un-cacheable split and 776un-cacheable load operations selected by qualifier 777.Ar event-list . 778The qualifier 779.Ar event-list 780is a 781.Ql + 782separated list of the following flags: 783.Pp 784.Bl -tag -width indent -compact 785.It Li lsc 786Count load splits completed, excluding loads from un-cacheable or 787write-combining areas. 788.It Li ssc 789Count any split stores completed. 790.El 791.Pp 792The default is to count both kinds of operations. 793.It Li p4-mob-load-replay Op Li ,mask= Ns Ar qualifier 794.Pq "TS event" 795Count load replays triggered by the memory order buffer. 796Qualifier 797.Ar qualifier 798can be a 799.Ql + 800separated list of the following flags: 801.Pp 802.Bl -tag -width indent -compact 803.It Li no-sta 804Count replays because of unknown store addresses. 805.It Li no-std 806Count replays because of unknown store data. 807.It Li partial-data 808Count replays because of partially overlapped data accesses between 809load and store operations. 810.It Li unalgn-addr 811Count replays because of mismatches in the lower 4 bits of load and 812store operations. 813.El 814.Pp 815The default qualifier is 816.Ar no-sta+no-std+partial-data+unalgn-addr . 817.It Li p4-packed-dp-uop Op Li ,mask= Ns Ar flags 818.Pq "TI event" 819Count packed double-precision uops. 820Qualifier 821.Ar flags 822can take the following value (which is also the default): 823.Pp 824.Bl -tag -width indent -compact 825.It Li all 826Count all uops operating on packed double-precision operands. 827.El 828.It Li p4-packed-sp-uop Op Li ,mask= Ns Ar flags 829.Pq "TI event" 830Count packed single-precision uops. 831Qualifier 832.Ar flags 833can take the following value (which is also the default): 834.Pp 835.Bl -tag -width indent -compact 836.It Li all 837Count all uops operating on packed single-precision operands. 838.El 839.It Li p4-page-walk-type Op Li ,mask= Ns Ar qualifier 840.Pq "TI event" 841Count page walks performed by the page miss handler. 842Qualifier 843.Ar qualifier 844can be a 845.Ql + 846separated list of the following keywords: 847.Pp 848.Bl -tag -width indent -compact 849.It Li dtmiss 850Count page walks for data TLB misses. 851.It Li itmiss 852Count page walks for instruction TLB misses. 853.El 854.Pp 855The default value for 856.Ar qualifier 857is 858.Dq Li dtmiss+itmiss . 859.It Li p4-replay-event Op Li ,mask= Ns Ar flags 860.Pq "TS event" 861Count the retirement of tagged uops selected through the replay 862tagging mechanism. 863Qualifier 864.Ar flags 865contains a 866.Ql + 867separated set of the following strings: 868.Pp 869.Bl -tag -width indent -compact 870.It Li nbogus 871The marked uops are not bogus. 872.It Li bogus 873The marked uops are bogus. 874.El 875.Pp 876This event requires additional (upstream) events to be allocated to 877perform the desired uop tagging. 878The default qualifier counts both kinds of uops. 879This event can be used for precise event based sampling. 880.It Li p4-resource-stall Op Li ,mask= Ns Ar flags 881.Pq "TS event" 882Count the occurrence or latency of stalls in the allocator. 883Qualifier 884.Ar flags 885can take the following value (which is also the default): 886.Pp 887.Bl -tag -width indent -compact 888.It Li sbfull 889A stall due to the lack of store buffers. 890.El 891.It Li p4-response 892.Pq "TI event" 893Count different types of responses. 894Further documentation on this event is not available. 895.It Li p4-retired-branch-type Op Li ,mask= Ns Ar flags 896.Pq "TS event" 897Count branches retired. 898Qualifier 899.Ar flags 900contains a 901.Ql + 902separated list of strings: 903.Pp 904.Bl -tag -width indent -compact 905.It Li conditional 906Count conditional jumps. 907.It Li call 908Count direct and indirect call branches. 909.It Li return 910Count return branches. 911.It Li indirect 912Count returns, indirect calls or indirect jumps. 913.El 914.Pp 915The default qualifier counts all the above branch types. 916.It Li p4-retired-mispred-branch-type Op Li ,mask= Ns Ar flags 917.Pq "TS event" 918Count mispredicted branches retired. 919Qualifier 920.Ar flags 921contains a 922.Ql + 923separated list of strings: 924.Pp 925.Bl -tag -width indent -compact 926.It Li conditional 927Count conditional jumps. 928.It Li call 929Count indirect call branches. 930.It Li return 931Count return branches. 932.It Li indirect 933Count returns, indirect calls or indirect jumps. 934.El 935.Pp 936The default qualifier counts all the above branch types. 937.It Li p4-scalar-dp-uop Op Li ,mask= Ns Ar flags 938.Pq "TI event" 939Count the number of scalar double-precision uops. 940Qualifier 941.Ar flags 942can take the following value (which is also the default): 943.Pp 944.Bl -tag -width indent -compact 945.It Li all 946Count the number of scalar double-precision uops. 947.El 948.It Li p4-scalar-sp-uop Op Li ,mask= Ns Ar flags 949.Pq "TI event" 950Count the number of scalar single-precision uops. 951Qualifier 952.Ar flags 953can take the following value (which is also the default): 954.Pp 955.Bl -tag -width indent -compact 956.It Li all 957Count all uops operating on scalar single-precision operands. 958.El 959.It Li p4-snoop 960.Pq "TI event" 961Count snoop traffic. 962Further documentation on this event is not available. 963.It Li p4-sse-input-assist Op Li ,mask= Ns Ar flags 964.Pq "TI event" 965Count the number of times an assist is required to handle problems 966with the operands for SSE and SSE2 operations. 967Qualifier 968.Ar flags 969can take the following value (which is also the default): 970.Pp 971.Bl -tag -width indent -compact 972.It Li all 973Count assists for all SSE and SSE2 uops. 974.El 975.It Li p4-store-port-replay Op Li ,mask= Ns Ar qualifier 976.Pq "TS event" 977Count events replayed at the store port. 978Qualifier 979.Ar qualifier 980can take on one value: 981.Pp 982.Bl -tag -width indent -compact 983.It Li split-st 984Count split stores. 985.El 986.Pp 987The default value for 988.Ar qualifier 989is 990.Dq Li split-st . 991.It Li p4-tc-deliver-mode Op Li ,mask= Ns Ar qualifier 992.Pq "TI event" 993Count the duration in cycles of operating modes of the trace cache and 994decode engine. 995The desired operating mode is selected by 996.Ar qualifier , 997which is a list of the following strings separated by 998.Ql + 999characters: 1000.Pp 1001.Bl -tag -width indent -compact 1002.It Li DD 1003Both logical processors are in deliver mode. 1004.It Li DB 1005Logical processor 0 is in deliver mode while logical processor 1 is in 1006build mode. 1007.It Li DI 1008Logical processor 0 is in deliver mode while logical processor 1 is 1009halted, or in machine clear, or transitioning to a long microcode 1010flow. 1011.It Li BD 1012Logical processor 0 is in build mode while logical processor 1 is in 1013deliver mode. 1014.It Li BB 1015Both logical processors are in build mode. 1016.It Li BI 1017Logical processor 0 is in build mode while logical processor 1 is 1018halted, or in machine clear or transitioning to a long microcode 1019flow. 1020.It Li ID 1021Logical processor 0 is halted, or in machine clear or transitioning to 1022a long microcode flow while logical processor 1 is in deliver mode. 1023.It Li IB 1024Logical processor 0 is halted, or in machine clear or transitioning to 1025a long microcode flow while logical processor 1 is in build mode. 1026.El 1027.Pp 1028If there is only one logical processor in the processor package then 1029the qualifier for logical processor 1 is ignored. 1030If no qualifier is specified, the default qualifier is 1031.Dq Li DD+DB+DI+BD+BB+BI+ID+IB . 1032.It Li p4-tc-ms-xfer Op Li ,mask= Ns Ar flags 1033.Pq "TI event" 1034Count the number of times uop delivery changed from the trace cache to 1035MS ROM. 1036Qualifier 1037.Ar flags 1038can take the following value (which is also the default): 1039.Pp 1040.Bl -tag -width indent -compact 1041.It Li cisc 1042Count TC to MS transfers. 1043.El 1044.It Li p4-uop-queue-writes Op Li ,mask= Ns Ar flags 1045.Pq "TS event" 1046Count the number of valid uops written to the uop queue. 1047Qualifier 1048.Ar flags 1049is a list of the following strings, separated by 1050.Ql + 1051characters: 1052.Pp 1053.Bl -tag -width indent -compact 1054.It Li from-tc-build 1055Count uops being written from the trace cache in build mode. 1056.It Li from-tc-deliver 1057Count uops being written from the trace cache in deliver mode. 1058.It Li from-rom 1059Count uops being written from microcode ROM. 1060.El 1061.Pp 1062The default qualifier counts all the above kinds of uops. 1063.It Li p4-uop-type Op Li ,mask= Ns Ar flags 1064.Pq "TS event" 1065This event is used in conjunction with the front-end at-retirement 1066mechanism to tag load and store uops. 1067Qualifier 1068.Ar flags 1069comprises the following strings separated by 1070.Ql + 1071characters: 1072.Pp 1073.Bl -tag -width indent -compact 1074.It Li tagloads 1075Mark uops that are load operations. 1076.It Li tagstores 1077Mark uops that are store operations. 1078.El 1079.Pp 1080The default qualifier counts both kinds of uops. 1081.It Li p4-uops-retired Op Li ,mask= Ns Ar flags 1082.Pq "TS event" 1083Count uops retired during a clock cycle. 1084Qualifier 1085.Ar flags 1086comprises the following strings separated by 1087.Ql + 1088characters: 1089.Pp 1090.Bl -tag -width indent -compact 1091.It Li nbogus 1092Count marked uops that are not bogus. 1093.It Li bogus 1094Count marked uops that are bogus. 1095.El 1096.Pp 1097The default qualifier counts both kinds of uops. 1098.It Li p4-wc-buffer Op Li ,mask= Ns Ar flags 1099.Pq "TI event" 1100Count write-combining buffer operations. 1101Qualifier 1102.Ar flags 1103contains the following strings separated by 1104.Ql + 1105characters: 1106.Pp 1107.Bl -tag -width indent -compact 1108.It Li wcb-evicts 1109WC buffer evictions due to any cause. 1110.It Li wcb-full-evict 1111WC buffer evictions due to no WC buffer being available. 1112.El 1113.Pp 1114The default qualifier counts both kinds of evictions. 1115.It Li p4-x87-assist Op Li ,mask= Ns Ar flags 1116.Pq "TS event" 1117Count the retirement of x87 instructions that required special 1118handling. 1119Qualifier 1120.Ar flags 1121contains the following strings separated by 1122.Ql + 1123characters: 1124.Pp 1125.Bl -tag -width indent -compact 1126.It Li fpsu 1127Count instructions that saw an FP stack underflow. 1128.It Li fpso 1129Count instructions that saw an FP stack overflow. 1130.It Li poao 1131Count instructions that saw an x87 output overflow. 1132.It Li poau 1133Count instructions that saw an x87 output underflow. 1134.It Li prea 1135Count instructions that needed an x87 input assist. 1136.El 1137.Pp 1138The default qualifier counts all the above types of instruction 1139retirements. 1140.It Li p4-x87-fp-uop Op Li ,mask= Ns Ar flags 1141.Pq "TI event" 1142Count x87 floating-point uops. 1143Qualifier 1144.Ar flags 1145can take the following value (which is also the default): 1146.Pp 1147.Bl -tag -width indent -compact 1148.It Li all 1149Count all x87 floating-point uops. 1150.El 1151.Pp 1152If an instruction contains more than one x87 floating-point uops, then 1153all x87 floating-point uops will be counted. 1154This event does not count x87 floating-point data movement operations. 1155.It Li p4-x87-simd-moves-uop Op Li ,mask= Ns Ar flags 1156.Pq "TI event" 1157Count each x87 FPU, MMX, SSE, or SSE2 uops that load data or store 1158data or perform register-to-register moves. 1159This event does not count integer move uops. 1160Qualifier 1161.Ar flags 1162may contain the following keywords separated by 1163.Ql + 1164characters: 1165.Pp 1166.Bl -tag -width indent -compact 1167.It Li allp0 1168Count all x87 and SIMD store and move uops. 1169.It Li allp2 1170Count all x87 and SIMD load uops. 1171.El 1172.Pp 1173The default is to count all uops. 1174.Pq Errata 1175This event may be affected by processor errata N43. 1176.El 1177.Ss "Cascading P4 PMCs" 1178PMC cascading support is currently poorly implemented. 1179While individual event counters may be allocated with a 1180.Dq Li cascade 1181qualifier, the current API does not offer the ability 1182to name and allocate all the resources needed for a 1183cascaded event counter pair in a single operation. 1184.Ss "Precise Event Based Sampling" 1185Support for precise event based sampling is currently 1186unimplemented. 1187.Ss Event Name Aliases 1188The following table shows the mapping between the PMC-independent 1189aliases supported by 1190.Lb libpmc 1191and the underlying hardware events used. 1192.Bl -column "branch-mispredicts" "Description" 1193.It Em Alias Ta Em Event 1194.It Li branches Ta Li p4-branch-retired,mask=mmtp+mmtm 1195.It Li branch-mispredicts Ta Li p4-mispred-branch-retired 1196.It Li dc-misses Ta (unsupported) 1197.It Li ic-misses Ta (unsupported) 1198.It Li instructions Ta Li p4-instr-retired,mask=nbogusntag+nbogustag 1199.It Li interrupts Ta Li (unsupported) 1200.It Li unhalted-cycles Ta Li p4-global-power-events 1201.El 1202.Sh SEE ALSO 1203.Xr pmc 3 , 1204.Xr pmc.atom 3 , 1205.Xr pmc.core 3 , 1206.Xr pmc.core2 3 , 1207.Xr pmc.iaf 3 , 1208.Xr pmc.k7 3 , 1209.Xr pmc.k8 3 , 1210.Xr pmc.p5 3 , 1211.Xr pmc.p6 3 , 1212.Xr pmc.tsc 3 , 1213.Xr pmclog 3 , 1214.Xr hwpmc 4 1215.Sh HISTORY 1216The 1217.Nm pmc 1218library first appeared in 1219.Fx 6.0 . 1220.Sh AUTHORS 1221The 1222.Lb libpmc 1223library was written by 1224.An "Joseph Koshy" 1225.Aq [email protected] . 1226