1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 25 #define MRM_MAPPING \ 26 MAP(C0, 32) \ 27 MAP(C1, 33) \ 28 MAP(C2, 34) \ 29 MAP(C3, 35) \ 30 MAP(C4, 36) \ 31 MAP(C8, 37) \ 32 MAP(C9, 38) \ 33 MAP(CA, 39) \ 34 MAP(CB, 40) \ 35 MAP(D0, 41) \ 36 MAP(D1, 42) \ 37 MAP(D4, 43) \ 38 MAP(D5, 44) \ 39 MAP(D6, 45) \ 40 MAP(D8, 46) \ 41 MAP(D9, 47) \ 42 MAP(DA, 48) \ 43 MAP(DB, 49) \ 44 MAP(DC, 50) \ 45 MAP(DD, 51) \ 46 MAP(DE, 52) \ 47 MAP(DF, 53) \ 48 MAP(E0, 54) \ 49 MAP(E1, 55) \ 50 MAP(E2, 56) \ 51 MAP(E3, 57) \ 52 MAP(E4, 58) \ 53 MAP(E5, 59) \ 54 MAP(E8, 60) \ 55 MAP(E9, 61) \ 56 MAP(EA, 62) \ 57 MAP(EB, 63) \ 58 MAP(EC, 64) \ 59 MAP(ED, 65) \ 60 MAP(EE, 66) \ 61 MAP(F0, 67) \ 62 MAP(F1, 68) \ 63 MAP(F2, 69) \ 64 MAP(F3, 70) \ 65 MAP(F4, 71) \ 66 MAP(F5, 72) \ 67 MAP(F6, 73) \ 68 MAP(F7, 74) \ 69 MAP(F8, 75) \ 70 MAP(F9, 76) \ 71 MAP(FA, 77) \ 72 MAP(FB, 78) \ 73 MAP(FC, 79) \ 74 MAP(FD, 80) \ 75 MAP(FE, 81) \ 76 MAP(FF, 82) 77 78 // A clone of X86 since we can't depend on something that is generated. 79 namespace X86Local { 80 enum { 81 Pseudo = 0, 82 RawFrm = 1, 83 AddRegFrm = 2, 84 MRMDestReg = 3, 85 MRMDestMem = 4, 86 MRMSrcReg = 5, 87 MRMSrcMem = 6, 88 RawFrmMemOffs = 7, 89 RawFrmSrc = 8, 90 RawFrmDst = 9, 91 RawFrmDstSrc = 10, 92 RawFrmImm8 = 11, 93 RawFrmImm16 = 12, 94 MRMXr = 14, MRMXm = 15, 95 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, 96 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, 97 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, 98 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, 99 #define MAP(from, to) MRM_##from = to, 100 MRM_MAPPING 101 #undef MAP 102 lastMRM 103 }; 104 105 enum { 106 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6 107 }; 108 109 enum { 110 PS = 1, PD = 2, XS = 3, XD = 4 111 }; 112 113 enum { 114 VEX = 1, XOP = 2, EVEX = 3 115 }; 116 117 enum { 118 OpSize16 = 1, OpSize32 = 2 119 }; 120 } 121 122 using namespace X86Disassembler; 123 124 /// isRegFormat - Indicates whether a particular form requires the Mod field of 125 /// the ModR/M byte to be 0b11. 126 /// 127 /// @param form - The form of the instruction. 128 /// @return - true if the form implies that Mod must be 0b11, false 129 /// otherwise. 130 static bool isRegFormat(uint8_t form) { 131 return (form == X86Local::MRMDestReg || 132 form == X86Local::MRMSrcReg || 133 form == X86Local::MRMXr || 134 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); 135 } 136 137 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 138 /// Useful for switch statements and the like. 139 /// 140 /// @param init - A reference to the BitsInit to be decoded. 141 /// @return - The field, with the first bit in the BitsInit as the lowest 142 /// order bit. 143 static uint8_t byteFromBitsInit(BitsInit &init) { 144 int width = init.getNumBits(); 145 146 assert(width <= 8 && "Field is too large for uint8_t!"); 147 148 int index; 149 uint8_t mask = 0x01; 150 151 uint8_t ret = 0; 152 153 for (index = 0; index < width; index++) { 154 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 155 ret |= mask; 156 157 mask <<= 1; 158 } 159 160 return ret; 161 } 162 163 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 164 /// name of the field. 165 /// 166 /// @param rec - The record from which to extract the value. 167 /// @param name - The name of the field in the record. 168 /// @return - The field, as translated by byteFromBitsInit(). 169 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 170 BitsInit* bits = rec->getValueAsBitsInit(name); 171 return byteFromBitsInit(*bits); 172 } 173 174 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 175 const CodeGenInstruction &insn, 176 InstrUID uid) { 177 UID = uid; 178 179 Rec = insn.TheDef; 180 Name = Rec->getName(); 181 Spec = &tables.specForUID(UID); 182 183 if (!Rec->isSubClassOf("X86Inst")) { 184 ShouldBeEmitted = false; 185 return; 186 } 187 188 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 189 OpMap = byteFromRec(Rec, "OpMapBits"); 190 Opcode = byteFromRec(Rec, "Opcode"); 191 Form = byteFromRec(Rec, "FormBits"); 192 Encoding = byteFromRec(Rec, "OpEncBits"); 193 194 OpSize = byteFromRec(Rec, "OpSizeBits"); 195 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix"); 196 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 197 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 198 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3"); 199 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); 200 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix"); 201 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 202 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 203 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 204 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 205 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 206 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 207 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 208 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 209 210 Name = Rec->getName(); 211 AsmString = Rec->getValueAsString("AsmString"); 212 213 Operands = &insn.Operands.OperandList; 214 215 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 216 217 // Check for 64-bit inst which does not require REX 218 Is32Bit = false; 219 Is64Bit = false; 220 // FIXME: Is there some better way to check for In64BitMode? 221 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 222 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 223 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 224 Predicates[i]->getName().find("In32Bit") != Name.npos) { 225 Is32Bit = true; 226 break; 227 } 228 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 229 Is64Bit = true; 230 break; 231 } 232 } 233 234 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 235 ShouldBeEmitted = false; 236 return; 237 } 238 239 // Special case since there is no attribute class for 64-bit and VEX 240 if (Name == "VMASKMOVDQU64") { 241 ShouldBeEmitted = false; 242 return; 243 } 244 245 ShouldBeEmitted = true; 246 } 247 248 void RecognizableInstr::processInstr(DisassemblerTables &tables, 249 const CodeGenInstruction &insn, 250 InstrUID uid) 251 { 252 // Ignore "asm parser only" instructions. 253 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 254 return; 255 256 RecognizableInstr recogInstr(tables, insn, uid); 257 258 if (recogInstr.shouldBeEmitted()) { 259 recogInstr.emitInstructionSpecifier(); 260 recogInstr.emitDecodePath(tables); 261 } 262 } 263 264 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 265 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 266 (HasEVEX_KZ ? n##_KZ : \ 267 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 268 269 InstructionContext RecognizableInstr::insnContext() const { 270 InstructionContext insnContext; 271 272 if (Encoding == X86Local::EVEX) { 273 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 274 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 275 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 276 } 277 // VEX_L & VEX_W 278 if (HasVEX_LPrefix && HasVEX_WPrefix) { 279 if (OpPrefix == X86Local::PD) 280 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 281 else if (OpPrefix == X86Local::XS) 282 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 283 else if (OpPrefix == X86Local::XD) 284 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 285 else if (OpPrefix == X86Local::PS) 286 insnContext = EVEX_KB(IC_EVEX_L_W); 287 else { 288 errs() << "Instruction does not use a prefix: " << Name << "\n"; 289 llvm_unreachable("Invalid prefix"); 290 } 291 } else if (HasVEX_LPrefix) { 292 // VEX_L 293 if (OpPrefix == X86Local::PD) 294 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 295 else if (OpPrefix == X86Local::XS) 296 insnContext = EVEX_KB(IC_EVEX_L_XS); 297 else if (OpPrefix == X86Local::XD) 298 insnContext = EVEX_KB(IC_EVEX_L_XD); 299 else if (OpPrefix == X86Local::PS) 300 insnContext = EVEX_KB(IC_EVEX_L); 301 else { 302 errs() << "Instruction does not use a prefix: " << Name << "\n"; 303 llvm_unreachable("Invalid prefix"); 304 } 305 } 306 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) { 307 // EVEX_L2 & VEX_W 308 if (OpPrefix == X86Local::PD) 309 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 310 else if (OpPrefix == X86Local::XS) 311 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 312 else if (OpPrefix == X86Local::XD) 313 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 314 else if (OpPrefix == X86Local::PS) 315 insnContext = EVEX_KB(IC_EVEX_L2_W); 316 else { 317 errs() << "Instruction does not use a prefix: " << Name << "\n"; 318 llvm_unreachable("Invalid prefix"); 319 } 320 } else if (HasEVEX_L2Prefix) { 321 // EVEX_L2 322 if (OpPrefix == X86Local::PD) 323 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 324 else if (OpPrefix == X86Local::XD) 325 insnContext = EVEX_KB(IC_EVEX_L2_XD); 326 else if (OpPrefix == X86Local::XS) 327 insnContext = EVEX_KB(IC_EVEX_L2_XS); 328 else if (OpPrefix == X86Local::PS) 329 insnContext = EVEX_KB(IC_EVEX_L2); 330 else { 331 errs() << "Instruction does not use a prefix: " << Name << "\n"; 332 llvm_unreachable("Invalid prefix"); 333 } 334 } 335 else if (HasVEX_WPrefix) { 336 // VEX_W 337 if (OpPrefix == X86Local::PD) 338 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 339 else if (OpPrefix == X86Local::XS) 340 insnContext = EVEX_KB(IC_EVEX_W_XS); 341 else if (OpPrefix == X86Local::XD) 342 insnContext = EVEX_KB(IC_EVEX_W_XD); 343 else if (OpPrefix == X86Local::PS) 344 insnContext = EVEX_KB(IC_EVEX_W); 345 else { 346 errs() << "Instruction does not use a prefix: " << Name << "\n"; 347 llvm_unreachable("Invalid prefix"); 348 } 349 } 350 // No L, no W 351 else if (OpPrefix == X86Local::PD) 352 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 353 else if (OpPrefix == X86Local::XD) 354 insnContext = EVEX_KB(IC_EVEX_XD); 355 else if (OpPrefix == X86Local::XS) 356 insnContext = EVEX_KB(IC_EVEX_XS); 357 else 358 insnContext = EVEX_KB(IC_EVEX); 359 /// eof EVEX 360 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 361 if (HasVEX_LPrefix && HasVEX_WPrefix) { 362 if (OpPrefix == X86Local::PD) 363 insnContext = IC_VEX_L_W_OPSIZE; 364 else if (OpPrefix == X86Local::XS) 365 insnContext = IC_VEX_L_W_XS; 366 else if (OpPrefix == X86Local::XD) 367 insnContext = IC_VEX_L_W_XD; 368 else if (OpPrefix == X86Local::PS) 369 insnContext = IC_VEX_L_W; 370 else { 371 errs() << "Instruction does not use a prefix: " << Name << "\n"; 372 llvm_unreachable("Invalid prefix"); 373 } 374 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 375 insnContext = IC_VEX_L_OPSIZE; 376 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix) 377 insnContext = IC_VEX_W_OPSIZE; 378 else if (OpPrefix == X86Local::PD) 379 insnContext = IC_VEX_OPSIZE; 380 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 381 insnContext = IC_VEX_L_XS; 382 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 383 insnContext = IC_VEX_L_XD; 384 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS) 385 insnContext = IC_VEX_W_XS; 386 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD) 387 insnContext = IC_VEX_W_XD; 388 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS) 389 insnContext = IC_VEX_W; 390 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 391 insnContext = IC_VEX_L; 392 else if (OpPrefix == X86Local::XD) 393 insnContext = IC_VEX_XD; 394 else if (OpPrefix == X86Local::XS) 395 insnContext = IC_VEX_XS; 396 else if (OpPrefix == X86Local::PS) 397 insnContext = IC_VEX; 398 else { 399 errs() << "Instruction does not use a prefix: " << Name << "\n"; 400 llvm_unreachable("Invalid prefix"); 401 } 402 } else if (Is64Bit || HasREX_WPrefix) { 403 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 404 insnContext = IC_64BIT_REXW_OPSIZE; 405 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 406 insnContext = IC_64BIT_XD_OPSIZE; 407 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 408 insnContext = IC_64BIT_XS_OPSIZE; 409 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 410 insnContext = IC_64BIT_OPSIZE; 411 else if (HasAdSizePrefix) 412 insnContext = IC_64BIT_ADSIZE; 413 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 414 insnContext = IC_64BIT_REXW_XS; 415 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 416 insnContext = IC_64BIT_REXW_XD; 417 else if (OpPrefix == X86Local::XD) 418 insnContext = IC_64BIT_XD; 419 else if (OpPrefix == X86Local::XS) 420 insnContext = IC_64BIT_XS; 421 else if (HasREX_WPrefix) 422 insnContext = IC_64BIT_REXW; 423 else 424 insnContext = IC_64BIT; 425 } else { 426 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 427 insnContext = IC_XD_OPSIZE; 428 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 429 insnContext = IC_XS_OPSIZE; 430 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 431 insnContext = IC_OPSIZE; 432 else if (HasAdSizePrefix) 433 insnContext = IC_ADSIZE; 434 else if (OpPrefix == X86Local::XD) 435 insnContext = IC_XD; 436 else if (OpPrefix == X86Local::XS) 437 insnContext = IC_XS; 438 else 439 insnContext = IC; 440 } 441 442 return insnContext; 443 } 444 445 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 446 // The scaling factor for AVX512 compressed displacement encoding is an 447 // instruction attribute. Adjust the ModRM encoding type to include the 448 // scale for compressed displacement. 449 if (encoding != ENCODING_RM || CD8_Scale == 0) 450 return; 451 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 452 assert(encoding <= ENCODING_RM_CD64 && "Invalid CDisp scaling"); 453 } 454 455 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 456 unsigned &physicalOperandIndex, 457 unsigned &numPhysicalOperands, 458 const unsigned *operandMapping, 459 OperandEncoding (*encodingFromString) 460 (const std::string&, 461 uint8_t OpSize)) { 462 if (optional) { 463 if (physicalOperandIndex >= numPhysicalOperands) 464 return; 465 } else { 466 assert(physicalOperandIndex < numPhysicalOperands); 467 } 468 469 while (operandMapping[operandIndex] != operandIndex) { 470 Spec->operands[operandIndex].encoding = ENCODING_DUP; 471 Spec->operands[operandIndex].type = 472 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 473 ++operandIndex; 474 } 475 476 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 477 478 OperandEncoding encoding = encodingFromString(typeName, OpSize); 479 // Adjust the encoding type for an operand based on the instruction. 480 adjustOperandEncoding(encoding); 481 Spec->operands[operandIndex].encoding = encoding; 482 Spec->operands[operandIndex].type = typeFromString(typeName, 483 HasREX_WPrefix, OpSize); 484 485 ++operandIndex; 486 ++physicalOperandIndex; 487 } 488 489 void RecognizableInstr::emitInstructionSpecifier() { 490 Spec->name = Name; 491 492 Spec->insnContext = insnContext(); 493 494 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 495 496 unsigned numOperands = OperandList.size(); 497 unsigned numPhysicalOperands = 0; 498 499 // operandMapping maps from operands in OperandList to their originals. 500 // If operandMapping[i] != i, then the entry is a duplicate. 501 unsigned operandMapping[X86_MAX_OPERANDS]; 502 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 503 504 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 505 if (OperandList[operandIndex].Constraints.size()) { 506 const CGIOperandList::ConstraintInfo &Constraint = 507 OperandList[operandIndex].Constraints[0]; 508 if (Constraint.isTied()) { 509 operandMapping[operandIndex] = operandIndex; 510 operandMapping[Constraint.getTiedOperand()] = operandIndex; 511 } else { 512 ++numPhysicalOperands; 513 operandMapping[operandIndex] = operandIndex; 514 } 515 } else { 516 ++numPhysicalOperands; 517 operandMapping[operandIndex] = operandIndex; 518 } 519 } 520 521 #define HANDLE_OPERAND(class) \ 522 handleOperand(false, \ 523 operandIndex, \ 524 physicalOperandIndex, \ 525 numPhysicalOperands, \ 526 operandMapping, \ 527 class##EncodingFromString); 528 529 #define HANDLE_OPTIONAL(class) \ 530 handleOperand(true, \ 531 operandIndex, \ 532 physicalOperandIndex, \ 533 numPhysicalOperands, \ 534 operandMapping, \ 535 class##EncodingFromString); 536 537 // operandIndex should always be < numOperands 538 unsigned operandIndex = 0; 539 // physicalOperandIndex should always be < numPhysicalOperands 540 unsigned physicalOperandIndex = 0; 541 542 switch (Form) { 543 default: llvm_unreachable("Unhandled form"); 544 case X86Local::RawFrmSrc: 545 HANDLE_OPERAND(relocation); 546 return; 547 case X86Local::RawFrmDst: 548 HANDLE_OPERAND(relocation); 549 return; 550 case X86Local::RawFrmDstSrc: 551 HANDLE_OPERAND(relocation); 552 HANDLE_OPERAND(relocation); 553 return; 554 case X86Local::RawFrm: 555 // Operand 1 (optional) is an address or immediate. 556 // Operand 2 (optional) is an immediate. 557 assert(numPhysicalOperands <= 2 && 558 "Unexpected number of operands for RawFrm"); 559 HANDLE_OPTIONAL(relocation) 560 HANDLE_OPTIONAL(immediate) 561 break; 562 case X86Local::RawFrmMemOffs: 563 // Operand 1 is an address. 564 HANDLE_OPERAND(relocation); 565 break; 566 case X86Local::AddRegFrm: 567 // Operand 1 is added to the opcode. 568 // Operand 2 (optional) is an address. 569 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 570 "Unexpected number of operands for AddRegFrm"); 571 HANDLE_OPERAND(opcodeModifier) 572 HANDLE_OPTIONAL(relocation) 573 break; 574 case X86Local::MRMDestReg: 575 // Operand 1 is a register operand in the R/M field. 576 // Operand 2 is a register operand in the Reg/Opcode field. 577 // - In AVX, there is a register operand in the VEX.vvvv field here - 578 // Operand 3 (optional) is an immediate. 579 if (HasVEX_4V) 580 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 581 "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); 582 else 583 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 584 "Unexpected number of operands for MRMDestRegFrm"); 585 586 HANDLE_OPERAND(rmRegister) 587 588 if (HasVEX_4V) 589 // FIXME: In AVX, the register below becomes the one encoded 590 // in ModRMVEX and the one above the one in the VEX.VVVV field 591 HANDLE_OPERAND(vvvvRegister) 592 593 HANDLE_OPERAND(roRegister) 594 HANDLE_OPTIONAL(immediate) 595 break; 596 case X86Local::MRMDestMem: 597 // Operand 1 is a memory operand (possibly SIB-extended) 598 // Operand 2 is a register operand in the Reg/Opcode field. 599 // - In AVX, there is a register operand in the VEX.vvvv field here - 600 // Operand 3 (optional) is an immediate. 601 if (HasVEX_4V) 602 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 603 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 604 else 605 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 606 "Unexpected number of operands for MRMDestMemFrm"); 607 HANDLE_OPERAND(memory) 608 609 if (HasEVEX_K) 610 HANDLE_OPERAND(writemaskRegister) 611 612 if (HasVEX_4V) 613 // FIXME: In AVX, the register below becomes the one encoded 614 // in ModRMVEX and the one above the one in the VEX.VVVV field 615 HANDLE_OPERAND(vvvvRegister) 616 617 HANDLE_OPERAND(roRegister) 618 HANDLE_OPTIONAL(immediate) 619 break; 620 case X86Local::MRMSrcReg: 621 // Operand 1 is a register operand in the Reg/Opcode field. 622 // Operand 2 is a register operand in the R/M field. 623 // - In AVX, there is a register operand in the VEX.vvvv field here - 624 // Operand 3 (optional) is an immediate. 625 // Operand 4 (optional) is an immediate. 626 627 if (HasVEX_4V || HasVEX_4VOp3) 628 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 629 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); 630 else 631 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 && 632 "Unexpected number of operands for MRMSrcRegFrm"); 633 634 HANDLE_OPERAND(roRegister) 635 636 if (HasEVEX_K) 637 HANDLE_OPERAND(writemaskRegister) 638 639 if (HasVEX_4V) 640 // FIXME: In AVX, the register below becomes the one encoded 641 // in ModRMVEX and the one above the one in the VEX.VVVV field 642 HANDLE_OPERAND(vvvvRegister) 643 644 if (HasMemOp4Prefix) 645 HANDLE_OPERAND(immediate) 646 647 HANDLE_OPERAND(rmRegister) 648 649 if (HasVEX_4VOp3) 650 HANDLE_OPERAND(vvvvRegister) 651 652 if (!HasMemOp4Prefix) 653 HANDLE_OPTIONAL(immediate) 654 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 655 HANDLE_OPTIONAL(immediate) 656 break; 657 case X86Local::MRMSrcMem: 658 // Operand 1 is a register operand in the Reg/Opcode field. 659 // Operand 2 is a memory operand (possibly SIB-extended) 660 // - In AVX, there is a register operand in the VEX.vvvv field here - 661 // Operand 3 (optional) is an immediate. 662 663 if (HasVEX_4V || HasVEX_4VOp3) 664 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 665 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 666 else 667 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 668 "Unexpected number of operands for MRMSrcMemFrm"); 669 670 HANDLE_OPERAND(roRegister) 671 672 if (HasEVEX_K) 673 HANDLE_OPERAND(writemaskRegister) 674 675 if (HasVEX_4V) 676 // FIXME: In AVX, the register below becomes the one encoded 677 // in ModRMVEX and the one above the one in the VEX.VVVV field 678 HANDLE_OPERAND(vvvvRegister) 679 680 if (HasMemOp4Prefix) 681 HANDLE_OPERAND(immediate) 682 683 HANDLE_OPERAND(memory) 684 685 if (HasVEX_4VOp3) 686 HANDLE_OPERAND(vvvvRegister) 687 688 if (!HasMemOp4Prefix) 689 HANDLE_OPTIONAL(immediate) 690 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 691 break; 692 case X86Local::MRMXr: 693 case X86Local::MRM0r: 694 case X86Local::MRM1r: 695 case X86Local::MRM2r: 696 case X86Local::MRM3r: 697 case X86Local::MRM4r: 698 case X86Local::MRM5r: 699 case X86Local::MRM6r: 700 case X86Local::MRM7r: 701 { 702 // Operand 1 is a register operand in the R/M field. 703 // Operand 2 (optional) is an immediate or relocation. 704 // Operand 3 (optional) is an immediate. 705 unsigned kOp = (HasEVEX_K) ? 1:0; 706 unsigned Op4v = (HasVEX_4V) ? 1:0; 707 if (numPhysicalOperands > 3 + kOp + Op4v) 708 llvm_unreachable("Unexpected number of operands for MRMnr"); 709 } 710 if (HasVEX_4V) 711 HANDLE_OPERAND(vvvvRegister) 712 713 if (HasEVEX_K) 714 HANDLE_OPERAND(writemaskRegister) 715 HANDLE_OPTIONAL(rmRegister) 716 HANDLE_OPTIONAL(relocation) 717 HANDLE_OPTIONAL(immediate) 718 break; 719 case X86Local::MRMXm: 720 case X86Local::MRM0m: 721 case X86Local::MRM1m: 722 case X86Local::MRM2m: 723 case X86Local::MRM3m: 724 case X86Local::MRM4m: 725 case X86Local::MRM5m: 726 case X86Local::MRM6m: 727 case X86Local::MRM7m: 728 { 729 // Operand 1 is a memory operand (possibly SIB-extended) 730 // Operand 2 (optional) is an immediate or relocation. 731 unsigned kOp = (HasEVEX_K) ? 1:0; 732 unsigned Op4v = (HasVEX_4V) ? 1:0; 733 if (numPhysicalOperands < 1 + kOp + Op4v || 734 numPhysicalOperands > 2 + kOp + Op4v) 735 llvm_unreachable("Unexpected number of operands for MRMnm"); 736 } 737 if (HasVEX_4V) 738 HANDLE_OPERAND(vvvvRegister) 739 if (HasEVEX_K) 740 HANDLE_OPERAND(writemaskRegister) 741 HANDLE_OPERAND(memory) 742 HANDLE_OPTIONAL(relocation) 743 break; 744 case X86Local::RawFrmImm8: 745 // operand 1 is a 16-bit immediate 746 // operand 2 is an 8-bit immediate 747 assert(numPhysicalOperands == 2 && 748 "Unexpected number of operands for X86Local::RawFrmImm8"); 749 HANDLE_OPERAND(immediate) 750 HANDLE_OPERAND(immediate) 751 break; 752 case X86Local::RawFrmImm16: 753 // operand 1 is a 16-bit immediate 754 // operand 2 is a 16-bit immediate 755 HANDLE_OPERAND(immediate) 756 HANDLE_OPERAND(immediate) 757 break; 758 case X86Local::MRM_F8: 759 if (Opcode == 0xc6) { 760 assert(numPhysicalOperands == 1 && 761 "Unexpected number of operands for X86Local::MRM_F8"); 762 HANDLE_OPERAND(immediate) 763 } else if (Opcode == 0xc7) { 764 assert(numPhysicalOperands == 1 && 765 "Unexpected number of operands for X86Local::MRM_F8"); 766 HANDLE_OPERAND(relocation) 767 } 768 break; 769 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: 770 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: 771 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: 772 case X86Local::MRM_D0: case X86Local::MRM_D1: case X86Local::MRM_D4: 773 case X86Local::MRM_D5: case X86Local::MRM_D6: case X86Local::MRM_D8: 774 case X86Local::MRM_D9: case X86Local::MRM_DA: case X86Local::MRM_DB: 775 case X86Local::MRM_DC: case X86Local::MRM_DD: case X86Local::MRM_DE: 776 case X86Local::MRM_DF: case X86Local::MRM_E0: case X86Local::MRM_E1: 777 case X86Local::MRM_E2: case X86Local::MRM_E3: case X86Local::MRM_E4: 778 case X86Local::MRM_E5: case X86Local::MRM_E8: case X86Local::MRM_E9: 779 case X86Local::MRM_EA: case X86Local::MRM_EB: case X86Local::MRM_EC: 780 case X86Local::MRM_ED: case X86Local::MRM_EE: case X86Local::MRM_F0: 781 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3: 782 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6: 783 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA: 784 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD: 785 case X86Local::MRM_FE: case X86Local::MRM_FF: 786 // Ignored. 787 break; 788 } 789 790 #undef HANDLE_OPERAND 791 #undef HANDLE_OPTIONAL 792 } 793 794 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 795 // Special cases where the LLVM tables are not complete 796 797 #define MAP(from, to) \ 798 case X86Local::MRM_##from: \ 799 filter = new ExactFilter(0x##from); \ 800 break; 801 802 OpcodeType opcodeType = (OpcodeType)-1; 803 804 ModRMFilter* filter = nullptr; 805 uint8_t opcodeToSet = 0; 806 807 switch (OpMap) { 808 default: llvm_unreachable("Invalid map!"); 809 case X86Local::OB: 810 case X86Local::TB: 811 case X86Local::T8: 812 case X86Local::TA: 813 case X86Local::XOP8: 814 case X86Local::XOP9: 815 case X86Local::XOPA: 816 switch (OpMap) { 817 default: llvm_unreachable("Unexpected map!"); 818 case X86Local::OB: opcodeType = ONEBYTE; break; 819 case X86Local::TB: opcodeType = TWOBYTE; break; 820 case X86Local::T8: opcodeType = THREEBYTE_38; break; 821 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 822 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 823 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 824 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 825 } 826 827 switch (Form) { 828 default: 829 filter = new DumbFilter(); 830 break; 831 case X86Local::MRMDestReg: case X86Local::MRMDestMem: 832 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem: 833 case X86Local::MRMXr: case X86Local::MRMXm: 834 filter = new ModFilter(isRegFormat(Form)); 835 break; 836 case X86Local::MRM0r: case X86Local::MRM1r: 837 case X86Local::MRM2r: case X86Local::MRM3r: 838 case X86Local::MRM4r: case X86Local::MRM5r: 839 case X86Local::MRM6r: case X86Local::MRM7r: 840 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 841 break; 842 case X86Local::MRM0m: case X86Local::MRM1m: 843 case X86Local::MRM2m: case X86Local::MRM3m: 844 case X86Local::MRM4m: case X86Local::MRM5m: 845 case X86Local::MRM6m: case X86Local::MRM7m: 846 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 847 break; 848 MRM_MAPPING 849 } // switch (Form) 850 851 opcodeToSet = Opcode; 852 break; 853 } // switch (OpMap) 854 855 assert(opcodeType != (OpcodeType)-1 && 856 "Opcode type not set"); 857 assert(filter && "Filter not set"); 858 859 if (Form == X86Local::AddRegFrm) { 860 assert(((opcodeToSet & 7) == 0) && 861 "ADDREG_FRM opcode not aligned"); 862 863 uint8_t currentOpcode; 864 865 for (currentOpcode = opcodeToSet; 866 currentOpcode < opcodeToSet + 8; 867 ++currentOpcode) 868 tables.setTableFields(opcodeType, 869 insnContext(), 870 currentOpcode, 871 *filter, 872 UID, Is32Bit, IgnoresVEX_L); 873 } else { 874 tables.setTableFields(opcodeType, 875 insnContext(), 876 opcodeToSet, 877 *filter, 878 UID, Is32Bit, IgnoresVEX_L); 879 } 880 881 delete filter; 882 883 #undef MAP 884 } 885 886 #define TYPE(str, type) if (s == str) return type; 887 OperandType RecognizableInstr::typeFromString(const std::string &s, 888 bool hasREX_WPrefix, 889 uint8_t OpSize) { 890 if(hasREX_WPrefix) { 891 // For instructions with a REX_W prefix, a declared 32-bit register encoding 892 // is special. 893 TYPE("GR32", TYPE_R32) 894 } 895 if(OpSize == X86Local::OpSize16) { 896 // For OpSize16 instructions, a declared 16-bit register or 897 // immediate encoding is special. 898 TYPE("GR16", TYPE_Rv) 899 TYPE("i16imm", TYPE_IMMv) 900 } else if(OpSize == X86Local::OpSize32) { 901 // For OpSize32 instructions, a declared 32-bit register or 902 // immediate encoding is special. 903 TYPE("GR32", TYPE_Rv) 904 } 905 TYPE("i16mem", TYPE_Mv) 906 TYPE("i16imm", TYPE_IMM16) 907 TYPE("i16i8imm", TYPE_IMMv) 908 TYPE("GR16", TYPE_R16) 909 TYPE("i32mem", TYPE_Mv) 910 TYPE("i32imm", TYPE_IMMv) 911 TYPE("i32i8imm", TYPE_IMM32) 912 TYPE("u32u8imm", TYPE_IMM32) 913 TYPE("GR32", TYPE_R32) 914 TYPE("GR32orGR64", TYPE_R32) 915 TYPE("i64mem", TYPE_Mv) 916 TYPE("i64i32imm", TYPE_IMM64) 917 TYPE("i64i8imm", TYPE_IMM64) 918 TYPE("GR64", TYPE_R64) 919 TYPE("i8mem", TYPE_M8) 920 TYPE("i8imm", TYPE_IMM8) 921 TYPE("GR8", TYPE_R8) 922 TYPE("VR128", TYPE_XMM128) 923 TYPE("VR128X", TYPE_XMM128) 924 TYPE("f128mem", TYPE_M128) 925 TYPE("f256mem", TYPE_M256) 926 TYPE("f512mem", TYPE_M512) 927 TYPE("FR64", TYPE_XMM64) 928 TYPE("FR64X", TYPE_XMM64) 929 TYPE("f64mem", TYPE_M64FP) 930 TYPE("sdmem", TYPE_M64FP) 931 TYPE("FR32", TYPE_XMM32) 932 TYPE("FR32X", TYPE_XMM32) 933 TYPE("f32mem", TYPE_M32FP) 934 TYPE("ssmem", TYPE_M32FP) 935 TYPE("RST", TYPE_ST) 936 TYPE("i128mem", TYPE_M128) 937 TYPE("i256mem", TYPE_M256) 938 TYPE("i512mem", TYPE_M512) 939 TYPE("i64i32imm_pcrel", TYPE_REL64) 940 TYPE("i16imm_pcrel", TYPE_REL16) 941 TYPE("i32imm_pcrel", TYPE_REL32) 942 TYPE("SSECC", TYPE_IMM3) 943 TYPE("AVXCC", TYPE_IMM5) 944 TYPE("AVX512RC", TYPE_IMM32) 945 TYPE("brtarget", TYPE_RELv) 946 TYPE("uncondbrtarget", TYPE_RELv) 947 TYPE("brtarget8", TYPE_REL8) 948 TYPE("f80mem", TYPE_M80FP) 949 TYPE("lea32mem", TYPE_LEA) 950 TYPE("lea64_32mem", TYPE_LEA) 951 TYPE("lea64mem", TYPE_LEA) 952 TYPE("VR64", TYPE_MM64) 953 TYPE("i64imm", TYPE_IMMv) 954 TYPE("opaque32mem", TYPE_M1616) 955 TYPE("opaque48mem", TYPE_M1632) 956 TYPE("opaque80mem", TYPE_M1664) 957 TYPE("opaque512mem", TYPE_M512) 958 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 959 TYPE("DEBUG_REG", TYPE_DEBUGREG) 960 TYPE("CONTROL_REG", TYPE_CONTROLREG) 961 TYPE("srcidx8", TYPE_SRCIDX8) 962 TYPE("srcidx16", TYPE_SRCIDX16) 963 TYPE("srcidx32", TYPE_SRCIDX32) 964 TYPE("srcidx64", TYPE_SRCIDX64) 965 TYPE("dstidx8", TYPE_DSTIDX8) 966 TYPE("dstidx16", TYPE_DSTIDX16) 967 TYPE("dstidx32", TYPE_DSTIDX32) 968 TYPE("dstidx64", TYPE_DSTIDX64) 969 TYPE("offset8", TYPE_MOFFS8) 970 TYPE("offset16", TYPE_MOFFS16) 971 TYPE("offset32", TYPE_MOFFS32) 972 TYPE("offset64", TYPE_MOFFS64) 973 TYPE("VR256", TYPE_XMM256) 974 TYPE("VR256X", TYPE_XMM256) 975 TYPE("VR512", TYPE_XMM512) 976 TYPE("VK1", TYPE_VK1) 977 TYPE("VK1WM", TYPE_VK1) 978 TYPE("VK2", TYPE_VK2) 979 TYPE("VK2WM", TYPE_VK2) 980 TYPE("VK4", TYPE_VK4) 981 TYPE("VK4WM", TYPE_VK4) 982 TYPE("VK8", TYPE_VK8) 983 TYPE("VK8WM", TYPE_VK8) 984 TYPE("VK16", TYPE_VK16) 985 TYPE("VK16WM", TYPE_VK16) 986 TYPE("VK32", TYPE_VK32) 987 TYPE("VK32WM", TYPE_VK32) 988 TYPE("VK64", TYPE_VK64) 989 TYPE("VK64WM", TYPE_VK64) 990 TYPE("GR16_NOAX", TYPE_Rv) 991 TYPE("GR32_NOAX", TYPE_Rv) 992 TYPE("GR64_NOAX", TYPE_R64) 993 TYPE("vx32mem", TYPE_M32) 994 TYPE("vy32mem", TYPE_M32) 995 TYPE("vz32mem", TYPE_M32) 996 TYPE("vx64mem", TYPE_M64) 997 TYPE("vy64mem", TYPE_M64) 998 TYPE("vy64xmem", TYPE_M64) 999 TYPE("vz64mem", TYPE_M64) 1000 errs() << "Unhandled type string " << s << "\n"; 1001 llvm_unreachable("Unhandled type string"); 1002 } 1003 #undef TYPE 1004 1005 #define ENCODING(str, encoding) if (s == str) return encoding; 1006 OperandEncoding 1007 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1008 uint8_t OpSize) { 1009 if(OpSize != X86Local::OpSize16) { 1010 // For instructions without an OpSize prefix, a declared 16-bit register or 1011 // immediate encoding is special. 1012 ENCODING("i16imm", ENCODING_IW) 1013 } 1014 ENCODING("i32i8imm", ENCODING_IB) 1015 ENCODING("u32u8imm", ENCODING_IB) 1016 ENCODING("SSECC", ENCODING_IB) 1017 ENCODING("AVXCC", ENCODING_IB) 1018 ENCODING("AVX512RC", ENCODING_IB) 1019 ENCODING("i16imm", ENCODING_Iv) 1020 ENCODING("i16i8imm", ENCODING_IB) 1021 ENCODING("i32imm", ENCODING_Iv) 1022 ENCODING("i64i32imm", ENCODING_ID) 1023 ENCODING("i64i8imm", ENCODING_IB) 1024 ENCODING("i8imm", ENCODING_IB) 1025 // This is not a typo. Instructions like BLENDVPD put 1026 // register IDs in 8-bit immediates nowadays. 1027 ENCODING("FR32", ENCODING_IB) 1028 ENCODING("FR64", ENCODING_IB) 1029 ENCODING("VR128", ENCODING_IB) 1030 ENCODING("VR256", ENCODING_IB) 1031 ENCODING("FR32X", ENCODING_IB) 1032 ENCODING("FR64X", ENCODING_IB) 1033 ENCODING("VR128X", ENCODING_IB) 1034 ENCODING("VR256X", ENCODING_IB) 1035 ENCODING("VR512", ENCODING_IB) 1036 errs() << "Unhandled immediate encoding " << s << "\n"; 1037 llvm_unreachable("Unhandled immediate encoding"); 1038 } 1039 1040 OperandEncoding 1041 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1042 uint8_t OpSize) { 1043 ENCODING("RST", ENCODING_FP) 1044 ENCODING("GR16", ENCODING_RM) 1045 ENCODING("GR32", ENCODING_RM) 1046 ENCODING("GR32orGR64", ENCODING_RM) 1047 ENCODING("GR64", ENCODING_RM) 1048 ENCODING("GR8", ENCODING_RM) 1049 ENCODING("VR128", ENCODING_RM) 1050 ENCODING("VR128X", ENCODING_RM) 1051 ENCODING("FR64", ENCODING_RM) 1052 ENCODING("FR32", ENCODING_RM) 1053 ENCODING("FR64X", ENCODING_RM) 1054 ENCODING("FR32X", ENCODING_RM) 1055 ENCODING("VR64", ENCODING_RM) 1056 ENCODING("VR256", ENCODING_RM) 1057 ENCODING("VR256X", ENCODING_RM) 1058 ENCODING("VR512", ENCODING_RM) 1059 ENCODING("VK1", ENCODING_RM) 1060 ENCODING("VK8", ENCODING_RM) 1061 ENCODING("VK16", ENCODING_RM) 1062 errs() << "Unhandled R/M register encoding " << s << "\n"; 1063 llvm_unreachable("Unhandled R/M register encoding"); 1064 } 1065 1066 OperandEncoding 1067 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1068 uint8_t OpSize) { 1069 ENCODING("GR16", ENCODING_REG) 1070 ENCODING("GR32", ENCODING_REG) 1071 ENCODING("GR32orGR64", ENCODING_REG) 1072 ENCODING("GR64", ENCODING_REG) 1073 ENCODING("GR8", ENCODING_REG) 1074 ENCODING("VR128", ENCODING_REG) 1075 ENCODING("FR64", ENCODING_REG) 1076 ENCODING("FR32", ENCODING_REG) 1077 ENCODING("VR64", ENCODING_REG) 1078 ENCODING("SEGMENT_REG", ENCODING_REG) 1079 ENCODING("DEBUG_REG", ENCODING_REG) 1080 ENCODING("CONTROL_REG", ENCODING_REG) 1081 ENCODING("VR256", ENCODING_REG) 1082 ENCODING("VR256X", ENCODING_REG) 1083 ENCODING("VR128X", ENCODING_REG) 1084 ENCODING("FR64X", ENCODING_REG) 1085 ENCODING("FR32X", ENCODING_REG) 1086 ENCODING("VR512", ENCODING_REG) 1087 ENCODING("VK1", ENCODING_REG) 1088 ENCODING("VK8", ENCODING_REG) 1089 ENCODING("VK16", ENCODING_REG) 1090 ENCODING("VK1WM", ENCODING_REG) 1091 ENCODING("VK8WM", ENCODING_REG) 1092 ENCODING("VK16WM", ENCODING_REG) 1093 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1094 llvm_unreachable("Unhandled reg/opcode register encoding"); 1095 } 1096 1097 OperandEncoding 1098 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1099 uint8_t OpSize) { 1100 ENCODING("GR32", ENCODING_VVVV) 1101 ENCODING("GR64", ENCODING_VVVV) 1102 ENCODING("FR32", ENCODING_VVVV) 1103 ENCODING("FR64", ENCODING_VVVV) 1104 ENCODING("VR128", ENCODING_VVVV) 1105 ENCODING("VR256", ENCODING_VVVV) 1106 ENCODING("FR32X", ENCODING_VVVV) 1107 ENCODING("FR64X", ENCODING_VVVV) 1108 ENCODING("VR128X", ENCODING_VVVV) 1109 ENCODING("VR256X", ENCODING_VVVV) 1110 ENCODING("VR512", ENCODING_VVVV) 1111 ENCODING("VK1", ENCODING_VVVV) 1112 ENCODING("VK2", ENCODING_VVVV) 1113 ENCODING("VK4", ENCODING_VVVV) 1114 ENCODING("VK8", ENCODING_VVVV) 1115 ENCODING("VK16", ENCODING_VVVV) 1116 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1117 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1118 } 1119 1120 OperandEncoding 1121 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1122 uint8_t OpSize) { 1123 ENCODING("VK1WM", ENCODING_WRITEMASK) 1124 ENCODING("VK2WM", ENCODING_WRITEMASK) 1125 ENCODING("VK4WM", ENCODING_WRITEMASK) 1126 ENCODING("VK8WM", ENCODING_WRITEMASK) 1127 ENCODING("VK16WM", ENCODING_WRITEMASK) 1128 ENCODING("VK32WM", ENCODING_WRITEMASK) 1129 ENCODING("VK64WM", ENCODING_WRITEMASK) 1130 errs() << "Unhandled mask register encoding " << s << "\n"; 1131 llvm_unreachable("Unhandled mask register encoding"); 1132 } 1133 1134 OperandEncoding 1135 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1136 uint8_t OpSize) { 1137 ENCODING("i16mem", ENCODING_RM) 1138 ENCODING("i32mem", ENCODING_RM) 1139 ENCODING("i64mem", ENCODING_RM) 1140 ENCODING("i8mem", ENCODING_RM) 1141 ENCODING("ssmem", ENCODING_RM) 1142 ENCODING("sdmem", ENCODING_RM) 1143 ENCODING("f128mem", ENCODING_RM) 1144 ENCODING("f256mem", ENCODING_RM) 1145 ENCODING("f512mem", ENCODING_RM) 1146 ENCODING("f64mem", ENCODING_RM) 1147 ENCODING("f32mem", ENCODING_RM) 1148 ENCODING("i128mem", ENCODING_RM) 1149 ENCODING("i256mem", ENCODING_RM) 1150 ENCODING("i512mem", ENCODING_RM) 1151 ENCODING("f80mem", ENCODING_RM) 1152 ENCODING("lea32mem", ENCODING_RM) 1153 ENCODING("lea64_32mem", ENCODING_RM) 1154 ENCODING("lea64mem", ENCODING_RM) 1155 ENCODING("opaque32mem", ENCODING_RM) 1156 ENCODING("opaque48mem", ENCODING_RM) 1157 ENCODING("opaque80mem", ENCODING_RM) 1158 ENCODING("opaque512mem", ENCODING_RM) 1159 ENCODING("vx32mem", ENCODING_RM) 1160 ENCODING("vy32mem", ENCODING_RM) 1161 ENCODING("vz32mem", ENCODING_RM) 1162 ENCODING("vx64mem", ENCODING_RM) 1163 ENCODING("vy64mem", ENCODING_RM) 1164 ENCODING("vy64xmem", ENCODING_RM) 1165 ENCODING("vz64mem", ENCODING_RM) 1166 errs() << "Unhandled memory encoding " << s << "\n"; 1167 llvm_unreachable("Unhandled memory encoding"); 1168 } 1169 1170 OperandEncoding 1171 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1172 uint8_t OpSize) { 1173 if(OpSize != X86Local::OpSize16) { 1174 // For instructions without an OpSize prefix, a declared 16-bit register or 1175 // immediate encoding is special. 1176 ENCODING("i16imm", ENCODING_IW) 1177 } 1178 ENCODING("i16imm", ENCODING_Iv) 1179 ENCODING("i16i8imm", ENCODING_IB) 1180 ENCODING("i32imm", ENCODING_Iv) 1181 ENCODING("i32i8imm", ENCODING_IB) 1182 ENCODING("i64i32imm", ENCODING_ID) 1183 ENCODING("i64i8imm", ENCODING_IB) 1184 ENCODING("i8imm", ENCODING_IB) 1185 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1186 ENCODING("i16imm_pcrel", ENCODING_IW) 1187 ENCODING("i32imm_pcrel", ENCODING_ID) 1188 ENCODING("brtarget", ENCODING_Iv) 1189 ENCODING("brtarget8", ENCODING_IB) 1190 ENCODING("i64imm", ENCODING_IO) 1191 ENCODING("offset8", ENCODING_Ia) 1192 ENCODING("offset16", ENCODING_Ia) 1193 ENCODING("offset32", ENCODING_Ia) 1194 ENCODING("offset64", ENCODING_Ia) 1195 ENCODING("srcidx8", ENCODING_SI) 1196 ENCODING("srcidx16", ENCODING_SI) 1197 ENCODING("srcidx32", ENCODING_SI) 1198 ENCODING("srcidx64", ENCODING_SI) 1199 ENCODING("dstidx8", ENCODING_DI) 1200 ENCODING("dstidx16", ENCODING_DI) 1201 ENCODING("dstidx32", ENCODING_DI) 1202 ENCODING("dstidx64", ENCODING_DI) 1203 errs() << "Unhandled relocation encoding " << s << "\n"; 1204 llvm_unreachable("Unhandled relocation encoding"); 1205 } 1206 1207 OperandEncoding 1208 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1209 uint8_t OpSize) { 1210 ENCODING("GR32", ENCODING_Rv) 1211 ENCODING("GR64", ENCODING_RO) 1212 ENCODING("GR16", ENCODING_Rv) 1213 ENCODING("GR8", ENCODING_RB) 1214 ENCODING("GR16_NOAX", ENCODING_Rv) 1215 ENCODING("GR32_NOAX", ENCODING_Rv) 1216 ENCODING("GR64_NOAX", ENCODING_RO) 1217 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1218 llvm_unreachable("Unhandled opcode modifier encoding"); 1219 } 1220 #undef ENCODING 1221