1 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
11 /// compression tables.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "CodeGenDAGPatterns.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/TableGen/Error.h"
18 #include "llvm/TableGen/TableGenBackend.h"
19 
20 using namespace llvm;
21 
22 namespace {
23 
24 class X86EVEX2VEXTablesEmitter {
25   CodeGenTarget Target;
26 
27   // Hold all non-masked & non-broadcasted EVEX encoded instructions
28   std::vector<const CodeGenInstruction *> EVEXInsts;
29   // Hold all VEX encoded instructions. Divided into groups with same opcodes
30   // to make the search more efficient
31   std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
32 
33   typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
34 
35   // Represent both compress tables
36   std::vector<Entry> EVEX2VEX128;
37   std::vector<Entry> EVEX2VEX256;
38 
39   // Represents a manually added entry to the tables
40   struct ManualEntry {
41     const char *EVEXInstStr;
42     const char *VEXInstStr;
43     bool Is128Bit;
44   };
45 
46 public:
47   X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Target(R) {}
48 
49   // run - Output X86 EVEX2VEX tables.
50   void run(raw_ostream &OS);
51 
52 private:
53   // Prints the given table as a C++ array of type
54   // X86EvexToVexCompressTableEntry
55   void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
56 
57   bool inExceptionList(const CodeGenInstruction *Inst) {
58     // List of EVEX instructions that match VEX instructions by the encoding
59     // but do not perform the same operation.
60     static constexpr const char *ExceptionList[] = {
61         "VCVTQQ2PD",
62         "VCVTQQ2PS",
63         "VPMAXSQ",
64         "VPMAXUQ",
65         "VPMINSQ",
66         "VPMINUQ",
67         "VPMULLQ",
68         "VPSRAQ",
69         "VDBPSADBW",
70         "VRNDSCALE",
71         "VSCALEFPS"
72     };
73     // Instruction's name starts with one of the entries in the exception list
74     for (StringRef InstStr : ExceptionList) {
75       if (Inst->TheDef->getName().startswith(InstStr))
76         return true;
77     }
78     return false;
79   }
80 
81 };
82 
83 void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
84                                           raw_ostream &OS) {
85   std::string Size = (Table == EVEX2VEX128) ? "128" : "256";
86 
87   OS << "// X86 EVEX encoded instructions that have a VEX " << Size
88      << " encoding\n"
89      << "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
90      << "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
91      << "CompressTable[] = {\n"
92      << "  // EVEX scalar with corresponding VEX.\n";
93 
94   // Print all entries added to the table
95   for (auto Pair : Table) {
96     OS << "  { X86::" << Pair.first->TheDef->getName()
97        << ", X86::" << Pair.second->TheDef->getName() << " },\n";
98   }
99 
100   // Some VEX instructions were duplicated to multiple EVEX versions due the
101   // introduction of mask variants, and thus some of the EVEX versions have
102   // different encoding than the VEX instruction. In order to maximize the
103   // compression we add these entries manually.
104   static constexpr ManualEntry ManuallyAddedEntries[] = {
105       // EVEX-Inst            VEX-Inst           Is128-bit
106       {"VMOVDQU8Z128mr",      "VMOVDQUmr",       true},
107       {"VMOVDQU8Z128rm",      "VMOVDQUrm",       true},
108       {"VMOVDQU8Z128rr",      "VMOVDQUrr",       true},
109       {"VMOVDQU8Z128rr_REV",  "VMOVDQUrr_REV",   true},
110       {"VMOVDQU16Z128mr",     "VMOVDQUmr",       true},
111       {"VMOVDQU16Z128rm",     "VMOVDQUrm",       true},
112       {"VMOVDQU16Z128rr",     "VMOVDQUrr",       true},
113       {"VMOVDQU16Z128rr_REV", "VMOVDQUrr_REV",   true},
114       {"VMOVDQU8Z256mr",      "VMOVDQUYmr",      false},
115       {"VMOVDQU8Z256rm",      "VMOVDQUYrm",      false},
116       {"VMOVDQU8Z256rr",      "VMOVDQUYrr",      false},
117       {"VMOVDQU8Z256rr_REV",  "VMOVDQUYrr_REV",  false},
118       {"VMOVDQU16Z256mr",     "VMOVDQUYmr",      false},
119       {"VMOVDQU16Z256rm",     "VMOVDQUYrm",      false},
120       {"VMOVDQU16Z256rr",     "VMOVDQUYrr",      false},
121       {"VMOVDQU16Z256rr_REV", "VMOVDQUYrr_REV",  false},
122 
123       {"VPERMILPDZ128mi",     "VPERMILPDmi",     true},
124       {"VPERMILPDZ128ri",     "VPERMILPDri",     true},
125       {"VPERMILPDZ128rm",     "VPERMILPDrm",     true},
126       {"VPERMILPDZ128rr",     "VPERMILPDrr",     true},
127       {"VPERMILPDZ256mi",     "VPERMILPDYmi",    false},
128       {"VPERMILPDZ256ri",     "VPERMILPDYri",    false},
129       {"VPERMILPDZ256rm",     "VPERMILPDYrm",    false},
130       {"VPERMILPDZ256rr",     "VPERMILPDYrr",    false},
131 
132       {"VPBROADCASTQZ128m",   "VPBROADCASTQrm",  true},
133       {"VPBROADCASTQZ128r",   "VPBROADCASTQrr",  true},
134       {"VPBROADCASTQZ256m",   "VPBROADCASTQYrm", false},
135       {"VPBROADCASTQZ256r",   "VPBROADCASTQYrr", false},
136 
137       {"VBROADCASTSDZ256m",   "VBROADCASTSDYrm", false},
138       {"VBROADCASTSDZ256r",   "VBROADCASTSDYrr", false},
139 
140       {"VEXTRACTF64x2Z256mr", "VEXTRACTF128mr",  false},
141       {"VEXTRACTF64x2Z256rr", "VEXTRACTF128rr",  false},
142       {"VEXTRACTI64x2Z256mr", "VEXTRACTI128mr",  false},
143       {"VEXTRACTI64x2Z256rr", "VEXTRACTI128rr",  false},
144 
145       {"VINSERTF64x2Z256rm",  "VINSERTF128rm",   false},
146       {"VINSERTF64x2Z256rr",  "VINSERTF128rr",   false},
147       {"VINSERTI64x2Z256rm",  "VINSERTI128rm",   false},
148       {"VINSERTI64x2Z256rr",  "VINSERTI128rr",   false}
149   };
150 
151   // Print the manually added entries
152   for (const ManualEntry &Entry : ManuallyAddedEntries) {
153     if ((Table == EVEX2VEX128 && Entry.Is128Bit) ||
154         (Table == EVEX2VEX256 && !Entry.Is128Bit)) {
155       OS << "  { X86::" << Entry.EVEXInstStr << ", X86::" << Entry.VEXInstStr
156          << " },\n";
157     }
158   }
159 
160   OS << "};\n\n";
161 }
162 
163 // Return true if the 2 BitsInits are equal
164 static inline bool equalBitsInits(const BitsInit *B1, const BitsInit *B2) {
165   if (B1->getNumBits() != B2->getNumBits())
166     PrintFatalError("Comparing two BitsInits with different sizes!");
167 
168   for (unsigned i = 0, e = B1->getNumBits(); i != e; ++i) {
169     if (BitInit *Bit1 = dyn_cast<BitInit>(B1->getBit(i))) {
170       if (BitInit *Bit2 = dyn_cast<BitInit>(B2->getBit(i))) {
171         if (Bit1->getValue() != Bit2->getValue())
172           return false;
173       } else
174         PrintFatalError("Invalid BitsInit bit");
175     } else
176       PrintFatalError("Invalid BitsInit bit");
177   }
178   return true;
179 }
180 
181 // Calculates the integer value residing BitsInit object
182 static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
183   uint64_t Value = 0;
184   for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
185     if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
186       Value |= uint64_t(Bit->getValue()) << i;
187     else
188       PrintFatalError("Invalid VectSize bit");
189   }
190   return Value;
191 }
192 
193 // Function object - Operator() returns true if the given VEX instruction
194 // matches the EVEX instruction of this object.
195 class IsMatch {
196   const CodeGenInstruction *Inst;
197 
198 public:
199   IsMatch(const CodeGenInstruction *Inst) : Inst(Inst) {}
200 
201   bool operator()(const CodeGenInstruction *Inst2) {
202     Record *Rec1 = Inst->TheDef;
203     Record *Rec2 = Inst2->TheDef;
204     uint64_t Rec1WVEX =
205         getValueFromBitsInit(Rec1->getValueAsBitsInit("VEX_WPrefix"));
206     uint64_t Rec2WVEX =
207         getValueFromBitsInit(Rec2->getValueAsBitsInit("VEX_WPrefix"));
208 
209     if (Rec2->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
210         // VEX/EVEX fields
211         Rec2->getValueAsDef("OpPrefix") != Rec1->getValueAsDef("OpPrefix") ||
212         Rec2->getValueAsDef("OpMap") != Rec1->getValueAsDef("OpMap") ||
213         Rec2->getValueAsBit("hasVEX_4V") != Rec1->getValueAsBit("hasVEX_4V") ||
214         !equalBitsInits(Rec2->getValueAsBitsInit("EVEX_LL"),
215                         Rec1->getValueAsBitsInit("EVEX_LL")) ||
216         (Rec1WVEX != 2 && Rec2WVEX != 2 && Rec1WVEX != Rec2WVEX) ||
217         // Instruction's format
218         Rec2->getValueAsDef("Form") != Rec1->getValueAsDef("Form") ||
219         Rec2->getValueAsBit("isAsmParserOnly") !=
220             Rec1->getValueAsBit("isAsmParserOnly"))
221       return false;
222 
223     // This is needed for instructions with intrinsic version (_Int).
224     // Where the only difference is the size of the operands.
225     // For example: VUCOMISDZrm and Int_VUCOMISDrm
226     // Also for instructions that their EVEX version was upgraded to work with
227     // k-registers. For example VPCMPEQBrm (xmm output register) and
228     // VPCMPEQBZ128rm (k register output register).
229     for (unsigned i = 0; i < Inst->Operands.size(); i++) {
230       Record *OpRec1 = Inst->Operands[i].Rec;
231       Record *OpRec2 = Inst2->Operands[i].Rec;
232 
233       if (OpRec1 == OpRec2)
234         continue;
235 
236       if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
237         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
238           return false;
239       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
240         return false;
241       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
242         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type"))
243           return false;
244       } else
245         return false;
246     }
247 
248     return true;
249   }
250 
251 private:
252   static inline bool isRegisterOperand(const Record *Rec) {
253     return Rec->isSubClassOf("RegisterClass") ||
254            Rec->isSubClassOf("RegisterOperand");
255   }
256 
257   static inline bool isMemoryOperand(const Record *Rec) {
258     return Rec->isSubClassOf("Operand") &&
259            Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
260   }
261 
262   static inline bool isImmediateOperand(const Record *Rec) {
263     return Rec->isSubClassOf("Operand") &&
264            Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
265   }
266 
267   static inline unsigned int getRegOperandSize(const Record *RegRec) {
268     if (RegRec->isSubClassOf("RegisterClass"))
269       return RegRec->getValueAsInt("Alignment");
270     if (RegRec->isSubClassOf("RegisterOperand"))
271       return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
272 
273     llvm_unreachable("Register operand's size not known!");
274   }
275 };
276 
277 void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
278   emitSourceFileHeader("X86 EVEX2VEX tables", OS);
279 
280   ArrayRef<const CodeGenInstruction *> NumberedInstructions =
281       Target.getInstructionsByEnumValue();
282 
283   for (const CodeGenInstruction *Inst : NumberedInstructions) {
284     // Filter non-X86 instructions.
285     if (!Inst->TheDef->isSubClassOf("X86Inst"))
286       continue;
287 
288     // Add VEX encoded instructions to one of VEXInsts vectors according to
289     // it's opcode.
290     if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
291       uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
292                                              getValueAsBitsInit("Opcode"));
293       VEXInsts[Opcode].push_back(Inst);
294     }
295     // Add relevant EVEX encoded instructions to EVEXInsts
296     else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
297              !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
298              !Inst->TheDef->getValueAsBit("hasEVEX_B") &&
299              getValueFromBitsInit(Inst->TheDef->
300                                         getValueAsBitsInit("EVEX_LL")) != 2 &&
301              !inExceptionList(Inst))
302       EVEXInsts.push_back(Inst);
303   }
304 
305   for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
306     uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
307                                            getValueAsBitsInit("Opcode"));
308     // For each EVEX instruction look for a VEX match in the appropriate vector
309     // (instructions with the same opcode) using function object IsMatch.
310     auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
311     if (Match != VEXInsts[Opcode].end()) {
312       const CodeGenInstruction *VEXInst = *Match;
313 
314       // In case a match is found add new entry to the appropriate table
315       switch (getValueFromBitsInit(
316           EVEXInst->TheDef->getValueAsBitsInit("EVEX_LL"))) {
317       case 0:
318         EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
319         break;
320       case 1:
321         EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
322         break;
323       default:
324         llvm_unreachable("Instruction's size not fit for the mapping!");
325       }
326     }
327   }
328 
329   // Print both tables
330   printTable(EVEX2VEX128, OS);
331   printTable(EVEX2VEX256, OS);
332 }
333 }
334 
335 namespace llvm {
336 void EmitX86EVEX2VEXTables(RecordKeeper &RK, raw_ostream &OS) {
337   X86EVEX2VEXTablesEmitter(RK).run(OS);
338 }
339 }
340