1*b5893f02SDimitry Andric //===--------------------- DispatchStatistics.cpp ---------------------*- C++
2*b5893f02SDimitry Andric //-*-===//
3*b5893f02SDimitry Andric //
4*b5893f02SDimitry Andric // The LLVM Compiler Infrastructure
5*b5893f02SDimitry Andric //
6*b5893f02SDimitry Andric // This file is distributed under the University of Illinois Open Source
7*b5893f02SDimitry Andric // License. See LICENSE.TXT for details.
8*b5893f02SDimitry Andric //
9*b5893f02SDimitry Andric //===----------------------------------------------------------------------===//
10*b5893f02SDimitry Andric /// \file
11*b5893f02SDimitry Andric ///
12*b5893f02SDimitry Andric /// This file implements the DispatchStatistics interface.
13*b5893f02SDimitry Andric ///
14*b5893f02SDimitry Andric //===----------------------------------------------------------------------===//
15*b5893f02SDimitry Andric
16*b5893f02SDimitry Andric #include "Views/DispatchStatistics.h"
17*b5893f02SDimitry Andric #include "llvm/Support/Format.h"
18*b5893f02SDimitry Andric
19*b5893f02SDimitry Andric namespace llvm {
20*b5893f02SDimitry Andric namespace mca {
21*b5893f02SDimitry Andric
onEvent(const HWStallEvent & Event)22*b5893f02SDimitry Andric void DispatchStatistics::onEvent(const HWStallEvent &Event) {
23*b5893f02SDimitry Andric if (Event.Type < HWStallEvent::LastGenericEvent)
24*b5893f02SDimitry Andric HWStalls[Event.Type]++;
25*b5893f02SDimitry Andric }
26*b5893f02SDimitry Andric
onEvent(const HWInstructionEvent & Event)27*b5893f02SDimitry Andric void DispatchStatistics::onEvent(const HWInstructionEvent &Event) {
28*b5893f02SDimitry Andric if (Event.Type != HWInstructionEvent::Dispatched)
29*b5893f02SDimitry Andric return;
30*b5893f02SDimitry Andric
31*b5893f02SDimitry Andric const auto &DE = static_cast<const HWInstructionDispatchedEvent &>(Event);
32*b5893f02SDimitry Andric NumDispatched += DE.MicroOpcodes;
33*b5893f02SDimitry Andric }
34*b5893f02SDimitry Andric
printDispatchHistogram(raw_ostream & OS) const35*b5893f02SDimitry Andric void DispatchStatistics::printDispatchHistogram(raw_ostream &OS) const {
36*b5893f02SDimitry Andric std::string Buffer;
37*b5893f02SDimitry Andric raw_string_ostream TempStream(Buffer);
38*b5893f02SDimitry Andric TempStream << "\n\nDispatch Logic - "
39*b5893f02SDimitry Andric << "number of cycles where we saw N micro opcodes dispatched:\n";
40*b5893f02SDimitry Andric TempStream << "[# dispatched], [# cycles]\n";
41*b5893f02SDimitry Andric for (const std::pair<unsigned, unsigned> &Entry : DispatchGroupSizePerCycle) {
42*b5893f02SDimitry Andric double Percentage = ((double)Entry.second / NumCycles) * 100.0;
43*b5893f02SDimitry Andric TempStream << " " << Entry.first << ", " << Entry.second
44*b5893f02SDimitry Andric << " (" << format("%.1f", floor((Percentage * 10) + 0.5) / 10)
45*b5893f02SDimitry Andric << "%)\n";
46*b5893f02SDimitry Andric }
47*b5893f02SDimitry Andric
48*b5893f02SDimitry Andric TempStream.flush();
49*b5893f02SDimitry Andric OS << Buffer;
50*b5893f02SDimitry Andric }
51*b5893f02SDimitry Andric
printStalls(raw_ostream & OS,unsigned NumStalls,unsigned NumCycles)52*b5893f02SDimitry Andric static void printStalls(raw_ostream &OS, unsigned NumStalls,
53*b5893f02SDimitry Andric unsigned NumCycles) {
54*b5893f02SDimitry Andric if (!NumStalls) {
55*b5893f02SDimitry Andric OS << NumStalls;
56*b5893f02SDimitry Andric return;
57*b5893f02SDimitry Andric }
58*b5893f02SDimitry Andric
59*b5893f02SDimitry Andric double Percentage = ((double)NumStalls / NumCycles) * 100.0;
60*b5893f02SDimitry Andric OS << NumStalls << " ("
61*b5893f02SDimitry Andric << format("%.1f", floor((Percentage * 10) + 0.5) / 10) << "%)";
62*b5893f02SDimitry Andric }
63*b5893f02SDimitry Andric
printDispatchStalls(raw_ostream & OS) const64*b5893f02SDimitry Andric void DispatchStatistics::printDispatchStalls(raw_ostream &OS) const {
65*b5893f02SDimitry Andric std::string Buffer;
66*b5893f02SDimitry Andric raw_string_ostream SS(Buffer);
67*b5893f02SDimitry Andric SS << "\n\nDynamic Dispatch Stall Cycles:\n";
68*b5893f02SDimitry Andric SS << "RAT - Register unavailable: ";
69*b5893f02SDimitry Andric printStalls(SS, HWStalls[HWStallEvent::RegisterFileStall], NumCycles);
70*b5893f02SDimitry Andric SS << "\nRCU - Retire tokens unavailable: ";
71*b5893f02SDimitry Andric printStalls(SS, HWStalls[HWStallEvent::RetireControlUnitStall], NumCycles);
72*b5893f02SDimitry Andric SS << "\nSCHEDQ - Scheduler full: ";
73*b5893f02SDimitry Andric printStalls(SS, HWStalls[HWStallEvent::SchedulerQueueFull], NumCycles);
74*b5893f02SDimitry Andric SS << "\nLQ - Load queue full: ";
75*b5893f02SDimitry Andric printStalls(SS, HWStalls[HWStallEvent::LoadQueueFull], NumCycles);
76*b5893f02SDimitry Andric SS << "\nSQ - Store queue full: ";
77*b5893f02SDimitry Andric printStalls(SS, HWStalls[HWStallEvent::StoreQueueFull], NumCycles);
78*b5893f02SDimitry Andric SS << "\nGROUP - Static restrictions on the dispatch group: ";
79*b5893f02SDimitry Andric printStalls(SS, HWStalls[HWStallEvent::DispatchGroupStall], NumCycles);
80*b5893f02SDimitry Andric SS << '\n';
81*b5893f02SDimitry Andric SS.flush();
82*b5893f02SDimitry Andric OS << Buffer;
83*b5893f02SDimitry Andric }
84*b5893f02SDimitry Andric
85*b5893f02SDimitry Andric } // namespace mca
86*b5893f02SDimitry Andric } // namespace llvm
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