1 //===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "lldb/Utility/ArchSpec.h" 11 12 #include "lldb/Utility/Log.h" 13 #include "lldb/Utility/NameMatches.h" 14 #include "lldb/Utility/Stream.h" 15 #include "lldb/Utility/StringList.h" 16 #include "lldb/lldb-defines.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/BinaryFormat/COFF.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/BinaryFormat/MachO.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/Host.h" 24 25 using namespace lldb; 26 using namespace lldb_private; 27 28 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 29 bool try_inverse, bool enforce_exact_match); 30 31 namespace lldb_private { 32 33 struct CoreDefinition { 34 ByteOrder default_byte_order; 35 uint32_t addr_byte_size; 36 uint32_t min_opcode_byte_size; 37 uint32_t max_opcode_byte_size; 38 llvm::Triple::ArchType machine; 39 ArchSpec::Core core; 40 const char *const name; 41 }; 42 43 } // namespace lldb_private 44 45 // This core information can be looked using the ArchSpec::Core as the index 46 static const CoreDefinition g_core_definitions[] = { 47 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic, 48 "arm"}, 49 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4, 50 "armv4"}, 51 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t, 52 "armv4t"}, 53 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5, 54 "armv5"}, 55 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e, 56 "armv5e"}, 57 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t, 58 "armv5t"}, 59 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6, 60 "armv6"}, 61 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m, 62 "armv6m"}, 63 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7, 64 "armv7"}, 65 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f, 66 "armv7f"}, 67 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s, 68 "armv7s"}, 69 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k, 70 "armv7k"}, 71 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m, 72 "armv7m"}, 73 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em, 74 "armv7em"}, 75 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale, 76 "xscale"}, 77 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb, 78 "thumb"}, 79 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t, 80 "thumbv4t"}, 81 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5, 82 "thumbv5"}, 83 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e, 84 "thumbv5e"}, 85 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6, 86 "thumbv6"}, 87 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m, 88 "thumbv6m"}, 89 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7, 90 "thumbv7"}, 91 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f, 92 "thumbv7f"}, 93 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s, 94 "thumbv7s"}, 95 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k, 96 "thumbv7k"}, 97 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m, 98 "thumbv7m"}, 99 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em, 100 "thumbv7em"}, 101 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 102 ArchSpec::eCore_arm_arm64, "arm64"}, 103 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 104 ArchSpec::eCore_arm_armv8, "armv8"}, 105 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, 106 ArchSpec::eCore_arm_aarch64, "aarch64"}, 107 108 // mips32, mips32r2, mips32r3, mips32r5, mips32r6 109 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32, 110 "mips"}, 111 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2, 112 "mipsr2"}, 113 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3, 114 "mipsr3"}, 115 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5, 116 "mipsr5"}, 117 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6, 118 "mipsr6"}, 119 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el, 120 "mipsel"}, 121 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 122 ArchSpec::eCore_mips32r2el, "mipsr2el"}, 123 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 124 ArchSpec::eCore_mips32r3el, "mipsr3el"}, 125 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 126 ArchSpec::eCore_mips32r5el, "mipsr5el"}, 127 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, 128 ArchSpec::eCore_mips32r6el, "mipsr6el"}, 129 130 // mips64, mips64r2, mips64r3, mips64r5, mips64r6 131 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64, 132 "mips64"}, 133 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2, 134 "mips64r2"}, 135 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3, 136 "mips64r3"}, 137 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5, 138 "mips64r5"}, 139 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6, 140 "mips64r6"}, 141 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 142 ArchSpec::eCore_mips64el, "mips64el"}, 143 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 144 ArchSpec::eCore_mips64r2el, "mips64r2el"}, 145 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 146 ArchSpec::eCore_mips64r3el, "mips64r3el"}, 147 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 148 ArchSpec::eCore_mips64r5el, "mips64r5el"}, 149 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, 150 ArchSpec::eCore_mips64r6el, "mips64r6el"}, 151 152 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic, 153 "powerpc"}, 154 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601, 155 "ppc601"}, 156 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602, 157 "ppc602"}, 158 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603, 159 "ppc603"}, 160 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e, 161 "ppc603e"}, 162 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev, 163 "ppc603ev"}, 164 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604, 165 "ppc604"}, 166 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e, 167 "ppc604e"}, 168 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620, 169 "ppc620"}, 170 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750, 171 "ppc750"}, 172 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400, 173 "ppc7400"}, 174 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450, 175 "ppc7450"}, 176 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970, 177 "ppc970"}, 178 179 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le, 180 ArchSpec::eCore_ppc64le_generic, "powerpc64le"}, 181 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic, 182 "powerpc64"}, 183 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, 184 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"}, 185 186 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz, 187 ArchSpec::eCore_s390x_generic, "s390x"}, 188 189 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc, 190 ArchSpec::eCore_sparc_generic, "sparc"}, 191 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, 192 ArchSpec::eCore_sparc9_generic, "sparcv9"}, 193 194 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386, 195 "i386"}, 196 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486, 197 "i486"}, 198 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, 199 ArchSpec::eCore_x86_32_i486sx, "i486sx"}, 200 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686, 201 "i686"}, 202 203 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 204 ArchSpec::eCore_x86_64_x86_64, "x86_64"}, 205 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64, 206 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"}, 207 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 208 ArchSpec::eCore_hexagon_generic, "hexagon"}, 209 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 210 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"}, 211 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, 212 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, 213 214 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, 215 ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, 216 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, 217 ArchSpec::eCore_uknownMach64, "unknown-mach-64"}, 218 219 {eByteOrderBig, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba3, 220 "kalimba3"}, 221 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba4, 222 "kalimba4"}, 223 {eByteOrderLittle, 4, 1, 1, llvm::Triple::kalimba, ArchSpec::eCore_kalimba5, 224 "kalimba5"}}; 225 226 // Ensure that we have an entry in the g_core_definitions for each core. If you 227 // comment out an entry above, you will need to comment out the corresponding 228 // ArchSpec::Core enumeration. 229 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) == 230 ArchSpec::kNumCores, 231 "make sure we have one core definition for each core"); 232 233 struct ArchDefinitionEntry { 234 ArchSpec::Core core; 235 uint32_t cpu; 236 uint32_t sub; 237 uint32_t cpu_mask; 238 uint32_t sub_mask; 239 }; 240 241 struct ArchDefinition { 242 ArchitectureType type; 243 size_t num_entries; 244 const ArchDefinitionEntry *entries; 245 const char *name; 246 }; 247 248 void ArchSpec::ListSupportedArchNames(StringList &list) { 249 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) 250 list.AppendString(g_core_definitions[i].name); 251 } 252 253 size_t ArchSpec::AutoComplete(CompletionRequest &request) { 254 if (!request.GetCursorArgumentPrefix().empty()) { 255 for (uint32_t i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 256 if (NameMatches(g_core_definitions[i].name, NameMatch::StartsWith, 257 request.GetCursorArgumentPrefix())) 258 request.AddCompletion(g_core_definitions[i].name); 259 } 260 } else { 261 StringList matches; 262 ListSupportedArchNames(matches); 263 request.AddCompletions(matches); 264 } 265 return request.GetNumberOfMatches(); 266 } 267 268 #define CPU_ANY (UINT32_MAX) 269 270 //===----------------------------------------------------------------------===// 271 // A table that gets searched linearly for matches. This table is used to 272 // convert cpu type and subtypes to architecture names, and to convert 273 // architecture names to cpu types and subtypes. The ordering is important and 274 // allows the precedence to be set when the table is built. 275 #define SUBTYPE_MASK 0x00FFFFFFu 276 277 static const ArchDefinitionEntry g_macho_arch_entries[] = { 278 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, 279 UINT32_MAX, UINT32_MAX}, 280 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 281 SUBTYPE_MASK}, 282 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 283 SUBTYPE_MASK}, 284 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 285 SUBTYPE_MASK}, 286 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 287 SUBTYPE_MASK}, 288 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 289 SUBTYPE_MASK}, 290 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 291 SUBTYPE_MASK}, 292 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 293 SUBTYPE_MASK}, 294 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 295 SUBTYPE_MASK}, 296 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, 8, UINT32_MAX, 297 SUBTYPE_MASK}, 298 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 299 SUBTYPE_MASK}, 300 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 301 SUBTYPE_MASK}, 302 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 303 SUBTYPE_MASK}, 304 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 305 SUBTYPE_MASK}, 306 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 307 SUBTYPE_MASK}, 308 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 309 SUBTYPE_MASK}, 310 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 1, UINT32_MAX, 311 SUBTYPE_MASK}, 312 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 0, UINT32_MAX, 313 SUBTYPE_MASK}, 314 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, 315 SUBTYPE_MASK}, 316 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, 317 UINT32_MAX, SUBTYPE_MASK}, 318 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, 0, UINT32_MAX, 319 SUBTYPE_MASK}, 320 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, 5, UINT32_MAX, 321 SUBTYPE_MASK}, 322 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 323 SUBTYPE_MASK}, 324 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, 7, UINT32_MAX, 325 SUBTYPE_MASK}, 326 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, 6, UINT32_MAX, 327 SUBTYPE_MASK}, 328 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, 14, UINT32_MAX, 329 SUBTYPE_MASK}, 330 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, 9, UINT32_MAX, 331 SUBTYPE_MASK}, 332 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, 333 SUBTYPE_MASK}, 334 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, 11, UINT32_MAX, 335 SUBTYPE_MASK}, 336 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, 12, UINT32_MAX, 337 SUBTYPE_MASK}, 338 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, 15, UINT32_MAX, 339 SUBTYPE_MASK}, 340 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, 16, UINT32_MAX, 341 SUBTYPE_MASK}, 342 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, 343 UINT32_MAX, UINT32_MAX}, 344 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, 0, UINT32_MAX, 345 SUBTYPE_MASK}, 346 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, 1, UINT32_MAX, 347 SUBTYPE_MASK}, 348 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, 2, UINT32_MAX, 349 SUBTYPE_MASK}, 350 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, 3, UINT32_MAX, 351 SUBTYPE_MASK}, 352 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, 4, UINT32_MAX, 353 SUBTYPE_MASK}, 354 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, 5, UINT32_MAX, 355 SUBTYPE_MASK}, 356 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, 6, UINT32_MAX, 357 SUBTYPE_MASK}, 358 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, 7, UINT32_MAX, 359 SUBTYPE_MASK}, 360 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, 8, UINT32_MAX, 361 SUBTYPE_MASK}, 362 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, 9, UINT32_MAX, 363 SUBTYPE_MASK}, 364 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, 10, UINT32_MAX, 365 SUBTYPE_MASK}, 366 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, 11, UINT32_MAX, 367 SUBTYPE_MASK}, 368 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, 100, UINT32_MAX, 369 SUBTYPE_MASK}, 370 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, 0, 371 UINT32_MAX, SUBTYPE_MASK}, 372 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, 373 UINT32_MAX, SUBTYPE_MASK}, 374 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, 375 UINT32_MAX, SUBTYPE_MASK}, 376 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, 3, UINT32_MAX, 377 SUBTYPE_MASK}, 378 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, 4, UINT32_MAX, 379 SUBTYPE_MASK}, 380 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, 0x84, 381 UINT32_MAX, SUBTYPE_MASK}, 382 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, 383 UINT32_MAX, UINT32_MAX}, 384 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 3, UINT32_MAX, 385 SUBTYPE_MASK}, 386 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, 4, UINT32_MAX, 387 SUBTYPE_MASK}, 388 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, 8, 389 UINT32_MAX, SUBTYPE_MASK}, 390 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, 391 UINT32_MAX, UINT32_MAX}, 392 // Catch any unknown mach architectures so we can always use the object and 393 // symbol mach-o files 394 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u}, 395 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 396 0x00000000u}}; 397 398 static const ArchDefinition g_macho_arch_def = { 399 eArchTypeMachO, llvm::array_lengthof(g_macho_arch_entries), 400 g_macho_arch_entries, "mach-o"}; 401 402 //===----------------------------------------------------------------------===// 403 // A table that gets searched linearly for matches. This table is used to 404 // convert cpu type and subtypes to architecture names, and to convert 405 // architecture names to cpu types and subtypes. The ordering is important and 406 // allows the precedence to be set when the table is built. 407 static const ArchDefinitionEntry g_elf_arch_entries[] = { 408 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE, 409 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc 410 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE, 411 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386 412 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE, 413 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct? 414 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE, 415 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 416 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 417 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le 418 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE, 419 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64 420 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE, 421 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 422 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 423 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64 424 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE, 425 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ 426 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9, 427 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9 428 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE, 429 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64 430 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32, 431 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32 432 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS, 433 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2 434 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS, 435 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6 436 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS, 437 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el 438 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS, 439 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el 440 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS, 441 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el 442 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64, 443 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64 444 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS, 445 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2 446 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS, 447 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6 448 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS, 449 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el 450 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS, 451 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el 452 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS, 453 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el 454 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON, 455 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON 456 {ArchSpec::eCore_kalimba3, llvm::ELF::EM_CSR_KALIMBA, 457 llvm::Triple::KalimbaSubArch_v3, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 458 {ArchSpec::eCore_kalimba4, llvm::ELF::EM_CSR_KALIMBA, 459 llvm::Triple::KalimbaSubArch_v4, 0xFFFFFFFFu, 0xFFFFFFFFu}, // KALIMBA 460 {ArchSpec::eCore_kalimba5, llvm::ELF::EM_CSR_KALIMBA, 461 llvm::Triple::KalimbaSubArch_v5, 0xFFFFFFFFu, 0xFFFFFFFFu} // KALIMBA 462 }; 463 464 static const ArchDefinition g_elf_arch_def = { 465 eArchTypeELF, 466 llvm::array_lengthof(g_elf_arch_entries), 467 g_elf_arch_entries, 468 "elf", 469 }; 470 471 static const ArchDefinitionEntry g_coff_arch_entries[] = { 472 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386, 473 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86 474 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC, 475 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC 476 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, 477 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU) 478 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM, 479 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM 480 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT, 481 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 482 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB, 483 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7 484 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64, 485 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // AMD64 486 }; 487 488 static const ArchDefinition g_coff_arch_def = { 489 eArchTypeCOFF, 490 llvm::array_lengthof(g_coff_arch_entries), 491 g_coff_arch_entries, 492 "pe-coff", 493 }; 494 495 //===----------------------------------------------------------------------===// 496 // Table of all ArchDefinitions 497 static const ArchDefinition *g_arch_definitions[] = { 498 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def}; 499 500 static const size_t k_num_arch_definitions = 501 llvm::array_lengthof(g_arch_definitions); 502 503 //===----------------------------------------------------------------------===// 504 // Static helper functions. 505 506 // Get the architecture definition for a given object type. 507 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) { 508 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) { 509 const ArchDefinition *def = g_arch_definitions[i]; 510 if (def->type == arch_type) 511 return def; 512 } 513 return nullptr; 514 } 515 516 // Get an architecture definition by name. 517 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) { 518 for (unsigned int i = 0; i < llvm::array_lengthof(g_core_definitions); ++i) { 519 if (name.equals_lower(g_core_definitions[i].name)) 520 return &g_core_definitions[i]; 521 } 522 return nullptr; 523 } 524 525 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) { 526 if (core < llvm::array_lengthof(g_core_definitions)) 527 return &g_core_definitions[core]; 528 return nullptr; 529 } 530 531 // Get a definition entry by cpu type and subtype. 532 static const ArchDefinitionEntry * 533 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) { 534 if (def == nullptr) 535 return nullptr; 536 537 const ArchDefinitionEntry *entries = def->entries; 538 for (size_t i = 0; i < def->num_entries; ++i) { 539 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 540 if (entries[i].sub == (sub & entries[i].sub_mask)) 541 return &entries[i]; 542 } 543 return nullptr; 544 } 545 546 static const ArchDefinitionEntry * 547 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) { 548 if (def == nullptr) 549 return nullptr; 550 551 const ArchDefinitionEntry *entries = def->entries; 552 for (size_t i = 0; i < def->num_entries; ++i) { 553 if (entries[i].core == core) 554 return &entries[i]; 555 } 556 return nullptr; 557 } 558 559 //===----------------------------------------------------------------------===// 560 // Constructors and destructors. 561 562 ArchSpec::ArchSpec() {} 563 564 ArchSpec::ArchSpec(const char *triple_cstr) { 565 if (triple_cstr) 566 SetTriple(triple_cstr); 567 } 568 569 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); } 570 571 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); } 572 573 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) { 574 SetArchitecture(arch_type, cpu, subtype); 575 } 576 577 ArchSpec::~ArchSpec() = default; 578 579 //===----------------------------------------------------------------------===// 580 // Assignment and initialization. 581 582 const ArchSpec &ArchSpec::operator=(const ArchSpec &rhs) { 583 if (this != &rhs) { 584 m_triple = rhs.m_triple; 585 m_core = rhs.m_core; 586 m_byte_order = rhs.m_byte_order; 587 m_distribution_id = rhs.m_distribution_id; 588 m_flags = rhs.m_flags; 589 } 590 return *this; 591 } 592 593 void ArchSpec::Clear() { 594 m_triple = llvm::Triple(); 595 m_core = kCore_invalid; 596 m_byte_order = eByteOrderInvalid; 597 m_distribution_id.Clear(); 598 m_flags = 0; 599 } 600 601 //===----------------------------------------------------------------------===// 602 // Predicates. 603 604 const char *ArchSpec::GetArchitectureName() const { 605 const CoreDefinition *core_def = FindCoreDefinition(m_core); 606 if (core_def) 607 return core_def->name; 608 return "unknown"; 609 } 610 611 bool ArchSpec::IsMIPS() const { 612 const llvm::Triple::ArchType machine = GetMachine(); 613 return machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 614 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el; 615 } 616 617 std::string ArchSpec::GetTargetABI() const { 618 619 std::string abi; 620 621 if (IsMIPS()) { 622 switch (GetFlags() & ArchSpec::eMIPSABI_mask) { 623 case ArchSpec::eMIPSABI_N64: 624 abi = "n64"; 625 return abi; 626 case ArchSpec::eMIPSABI_N32: 627 abi = "n32"; 628 return abi; 629 case ArchSpec::eMIPSABI_O32: 630 abi = "o32"; 631 return abi; 632 default: 633 return abi; 634 } 635 } 636 return abi; 637 } 638 639 void ArchSpec::SetFlags(std::string elf_abi) { 640 641 uint32_t flag = GetFlags(); 642 if (IsMIPS()) { 643 if (elf_abi == "n64") 644 flag |= ArchSpec::eMIPSABI_N64; 645 else if (elf_abi == "n32") 646 flag |= ArchSpec::eMIPSABI_N32; 647 else if (elf_abi == "o32") 648 flag |= ArchSpec::eMIPSABI_O32; 649 } 650 SetFlags(flag); 651 } 652 653 std::string ArchSpec::GetClangTargetCPU() const { 654 std::string cpu; 655 const llvm::Triple::ArchType machine = GetMachine(); 656 657 if (machine == llvm::Triple::mips || machine == llvm::Triple::mipsel || 658 machine == llvm::Triple::mips64 || machine == llvm::Triple::mips64el) { 659 switch (m_core) { 660 case ArchSpec::eCore_mips32: 661 case ArchSpec::eCore_mips32el: 662 cpu = "mips32"; 663 break; 664 case ArchSpec::eCore_mips32r2: 665 case ArchSpec::eCore_mips32r2el: 666 cpu = "mips32r2"; 667 break; 668 case ArchSpec::eCore_mips32r3: 669 case ArchSpec::eCore_mips32r3el: 670 cpu = "mips32r3"; 671 break; 672 case ArchSpec::eCore_mips32r5: 673 case ArchSpec::eCore_mips32r5el: 674 cpu = "mips32r5"; 675 break; 676 case ArchSpec::eCore_mips32r6: 677 case ArchSpec::eCore_mips32r6el: 678 cpu = "mips32r6"; 679 break; 680 case ArchSpec::eCore_mips64: 681 case ArchSpec::eCore_mips64el: 682 cpu = "mips64"; 683 break; 684 case ArchSpec::eCore_mips64r2: 685 case ArchSpec::eCore_mips64r2el: 686 cpu = "mips64r2"; 687 break; 688 case ArchSpec::eCore_mips64r3: 689 case ArchSpec::eCore_mips64r3el: 690 cpu = "mips64r3"; 691 break; 692 case ArchSpec::eCore_mips64r5: 693 case ArchSpec::eCore_mips64r5el: 694 cpu = "mips64r5"; 695 break; 696 case ArchSpec::eCore_mips64r6: 697 case ArchSpec::eCore_mips64r6el: 698 cpu = "mips64r6"; 699 break; 700 default: 701 break; 702 } 703 } 704 return cpu; 705 } 706 707 uint32_t ArchSpec::GetMachOCPUType() const { 708 const CoreDefinition *core_def = FindCoreDefinition(m_core); 709 if (core_def) { 710 const ArchDefinitionEntry *arch_def = 711 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 712 if (arch_def) { 713 return arch_def->cpu; 714 } 715 } 716 return LLDB_INVALID_CPUTYPE; 717 } 718 719 uint32_t ArchSpec::GetMachOCPUSubType() const { 720 const CoreDefinition *core_def = FindCoreDefinition(m_core); 721 if (core_def) { 722 const ArchDefinitionEntry *arch_def = 723 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core); 724 if (arch_def) { 725 return arch_def->sub; 726 } 727 } 728 return LLDB_INVALID_CPUTYPE; 729 } 730 731 uint32_t ArchSpec::GetDataByteSize() const { 732 switch (m_core) { 733 case eCore_kalimba3: 734 return 4; 735 case eCore_kalimba4: 736 return 1; 737 case eCore_kalimba5: 738 return 4; 739 default: 740 return 1; 741 } 742 return 1; 743 } 744 745 uint32_t ArchSpec::GetCodeByteSize() const { 746 switch (m_core) { 747 case eCore_kalimba3: 748 return 4; 749 case eCore_kalimba4: 750 return 1; 751 case eCore_kalimba5: 752 return 1; 753 default: 754 return 1; 755 } 756 return 1; 757 } 758 759 llvm::Triple::ArchType ArchSpec::GetMachine() const { 760 const CoreDefinition *core_def = FindCoreDefinition(m_core); 761 if (core_def) 762 return core_def->machine; 763 764 return llvm::Triple::UnknownArch; 765 } 766 767 const ConstString &ArchSpec::GetDistributionId() const { 768 return m_distribution_id; 769 } 770 771 void ArchSpec::SetDistributionId(const char *distribution_id) { 772 m_distribution_id.SetCString(distribution_id); 773 } 774 775 uint32_t ArchSpec::GetAddressByteSize() const { 776 const CoreDefinition *core_def = FindCoreDefinition(m_core); 777 if (core_def) { 778 if (core_def->machine == llvm::Triple::mips64 || 779 core_def->machine == llvm::Triple::mips64el) { 780 // For N32/O32 applications Address size is 4 bytes. 781 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32)) 782 return 4; 783 } 784 return core_def->addr_byte_size; 785 } 786 return 0; 787 } 788 789 ByteOrder ArchSpec::GetDefaultEndian() const { 790 const CoreDefinition *core_def = FindCoreDefinition(m_core); 791 if (core_def) 792 return core_def->default_byte_order; 793 return eByteOrderInvalid; 794 } 795 796 bool ArchSpec::CharIsSignedByDefault() const { 797 switch (m_triple.getArch()) { 798 default: 799 return true; 800 801 case llvm::Triple::aarch64: 802 case llvm::Triple::aarch64_be: 803 case llvm::Triple::arm: 804 case llvm::Triple::armeb: 805 case llvm::Triple::thumb: 806 case llvm::Triple::thumbeb: 807 return m_triple.isOSDarwin() || m_triple.isOSWindows(); 808 809 case llvm::Triple::ppc: 810 case llvm::Triple::ppc64: 811 return m_triple.isOSDarwin(); 812 813 case llvm::Triple::ppc64le: 814 case llvm::Triple::systemz: 815 case llvm::Triple::xcore: 816 case llvm::Triple::arc: 817 return false; 818 } 819 } 820 821 lldb::ByteOrder ArchSpec::GetByteOrder() const { 822 if (m_byte_order == eByteOrderInvalid) 823 return GetDefaultEndian(); 824 return m_byte_order; 825 } 826 827 //===----------------------------------------------------------------------===// 828 // Mutators. 829 830 bool ArchSpec::SetTriple(const llvm::Triple &triple) { 831 m_triple = triple; 832 UpdateCore(); 833 return IsValid(); 834 } 835 836 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 837 ArchSpec &arch) { 838 // Accept "12-10" or "12.10" as cpu type/subtype 839 if (triple_str.empty()) 840 return false; 841 842 size_t pos = triple_str.find_first_of("-."); 843 if (pos == llvm::StringRef::npos) 844 return false; 845 846 llvm::StringRef cpu_str = triple_str.substr(0, pos); 847 llvm::StringRef remainder = triple_str.substr(pos + 1); 848 if (cpu_str.empty() || remainder.empty()) 849 return false; 850 851 llvm::StringRef sub_str; 852 llvm::StringRef vendor; 853 llvm::StringRef os; 854 std::tie(sub_str, remainder) = remainder.split('-'); 855 std::tie(vendor, os) = remainder.split('-'); 856 857 uint32_t cpu = 0; 858 uint32_t sub = 0; 859 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub)) 860 return false; 861 862 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub)) 863 return false; 864 if (!vendor.empty() && !os.empty()) { 865 arch.GetTriple().setVendorName(vendor); 866 arch.GetTriple().setOSName(os); 867 } 868 869 return true; 870 } 871 872 bool ArchSpec::SetTriple(llvm::StringRef triple) { 873 if (triple.empty()) { 874 Clear(); 875 return false; 876 } 877 878 if (ParseMachCPUDashSubtypeTriple(triple, *this)) 879 return true; 880 881 SetTriple(llvm::Triple(llvm::Triple::normalize(triple))); 882 return IsValid(); 883 } 884 885 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) { 886 return !normalized_triple.getArchName().empty() && 887 normalized_triple.getOSName().empty() && 888 normalized_triple.getVendorName().empty() && 889 normalized_triple.getEnvironmentName().empty(); 890 } 891 892 void ArchSpec::MergeFrom(const ArchSpec &other) { 893 if (TripleVendorIsUnspecifiedUnknown() && 894 !other.TripleVendorIsUnspecifiedUnknown()) 895 GetTriple().setVendor(other.GetTriple().getVendor()); 896 if (TripleOSIsUnspecifiedUnknown() && !other.TripleOSIsUnspecifiedUnknown()) 897 GetTriple().setOS(other.GetTriple().getOS()); 898 if (GetTriple().getArch() == llvm::Triple::UnknownArch) { 899 GetTriple().setArch(other.GetTriple().getArch()); 900 901 // MachO unknown64 isn't really invalid as the debugger can still obtain 902 // information from the binary, e.g. line tables. As such, we don't update 903 // the core here. 904 if (other.GetCore() != eCore_uknownMach64) 905 UpdateCore(); 906 } 907 if (GetTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 908 !TripleVendorWasSpecified()) { 909 if (other.TripleVendorWasSpecified()) 910 GetTriple().setEnvironment(other.GetTriple().getEnvironment()); 911 } 912 // If this and other are both arm ArchSpecs and this ArchSpec is a generic 913 // "some kind of arm" spec but the other ArchSpec is a specific arm core, 914 // adopt the specific arm core. 915 if (GetTriple().getArch() == llvm::Triple::arm && 916 other.GetTriple().getArch() == llvm::Triple::arm && 917 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic && 918 other.GetCore() != ArchSpec::eCore_arm_generic) { 919 m_core = other.GetCore(); 920 CoreUpdated(true); 921 } 922 if (GetFlags() == 0) { 923 SetFlags(other.GetFlags()); 924 } 925 } 926 927 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu, 928 uint32_t sub, uint32_t os) { 929 m_core = kCore_invalid; 930 bool update_triple = true; 931 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 932 if (arch_def) { 933 const ArchDefinitionEntry *arch_def_entry = 934 FindArchDefinitionEntry(arch_def, cpu, sub); 935 if (arch_def_entry) { 936 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core); 937 if (core_def) { 938 m_core = core_def->core; 939 update_triple = false; 940 // Always use the architecture name because it might be more 941 // descriptive than the architecture enum ("armv7" -> 942 // llvm::Triple::arm). 943 m_triple.setArchName(llvm::StringRef(core_def->name)); 944 if (arch_type == eArchTypeMachO) { 945 m_triple.setVendor(llvm::Triple::Apple); 946 947 // Don't set the OS. It could be simulator, macosx, ios, watchos, 948 // tvos, bridgeos. We could get close with the cpu type - but we 949 // can't get it right all of the time. Better to leave this unset 950 // so other sections of code will set it when they have more 951 // information. NB: don't call m_triple.setOS (llvm::Triple::UnknownOS). 952 // That sets the OSName to "unknown" and the 953 // ArchSpec::TripleVendorWasSpecified() method says that any OSName 954 // setting means it was specified. 955 } else if (arch_type == eArchTypeELF) { 956 switch (os) { 957 case llvm::ELF::ELFOSABI_AIX: 958 m_triple.setOS(llvm::Triple::OSType::AIX); 959 break; 960 case llvm::ELF::ELFOSABI_FREEBSD: 961 m_triple.setOS(llvm::Triple::OSType::FreeBSD); 962 break; 963 case llvm::ELF::ELFOSABI_GNU: 964 m_triple.setOS(llvm::Triple::OSType::Linux); 965 break; 966 case llvm::ELF::ELFOSABI_NETBSD: 967 m_triple.setOS(llvm::Triple::OSType::NetBSD); 968 break; 969 case llvm::ELF::ELFOSABI_OPENBSD: 970 m_triple.setOS(llvm::Triple::OSType::OpenBSD); 971 break; 972 case llvm::ELF::ELFOSABI_SOLARIS: 973 m_triple.setOS(llvm::Triple::OSType::Solaris); 974 break; 975 } 976 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) { 977 m_triple.setVendor(llvm::Triple::PC); 978 m_triple.setOS(llvm::Triple::Win32); 979 } else { 980 m_triple.setVendor(llvm::Triple::UnknownVendor); 981 m_triple.setOS(llvm::Triple::UnknownOS); 982 } 983 // Fall back onto setting the machine type if the arch by name 984 // failed... 985 if (m_triple.getArch() == llvm::Triple::UnknownArch) 986 m_triple.setArch(core_def->machine); 987 } 988 } else { 989 Log *log(lldb_private::GetLogIfAnyCategoriesSet(LIBLLDB_LOG_TARGET | LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_PLATFORM)); 990 if (log) 991 log->Printf("Unable to find a core definition for cpu 0x%" PRIx32 " sub %" PRId32, cpu, sub); 992 } 993 } 994 CoreUpdated(update_triple); 995 return IsValid(); 996 } 997 998 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const { 999 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1000 if (core_def) 1001 return core_def->min_opcode_byte_size; 1002 return 0; 1003 } 1004 1005 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const { 1006 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1007 if (core_def) 1008 return core_def->max_opcode_byte_size; 1009 return 0; 1010 } 1011 1012 bool ArchSpec::IsExactMatch(const ArchSpec &rhs) const { 1013 return IsEqualTo(rhs, true); 1014 } 1015 1016 bool ArchSpec::IsCompatibleMatch(const ArchSpec &rhs) const { 1017 return IsEqualTo(rhs, false); 1018 } 1019 1020 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs, 1021 llvm::Triple::EnvironmentType rhs) { 1022 if (lhs == rhs) 1023 return true; 1024 1025 // If any of the environment is unknown then they are compatible 1026 if (lhs == llvm::Triple::UnknownEnvironment || 1027 rhs == llvm::Triple::UnknownEnvironment) 1028 return true; 1029 1030 // If one of the environment is Android and the other one is EABI then they 1031 // are considered to be compatible. This is required as a workaround for 1032 // shared libraries compiled for Android without the NOTE section indicating 1033 // that they are using the Android ABI. 1034 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) || 1035 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) || 1036 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) || 1037 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) || 1038 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) || 1039 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF)) 1040 return true; 1041 1042 return false; 1043 } 1044 1045 bool ArchSpec::IsEqualTo(const ArchSpec &rhs, bool exact_match) const { 1046 // explicitly ignoring m_distribution_id in this method. 1047 1048 if (GetByteOrder() != rhs.GetByteOrder()) 1049 return false; 1050 1051 const ArchSpec::Core lhs_core = GetCore(); 1052 const ArchSpec::Core rhs_core = rhs.GetCore(); 1053 1054 const bool core_match = cores_match(lhs_core, rhs_core, true, exact_match); 1055 1056 if (core_match) { 1057 const llvm::Triple &lhs_triple = GetTriple(); 1058 const llvm::Triple &rhs_triple = rhs.GetTriple(); 1059 1060 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 1061 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 1062 if (lhs_triple_vendor != rhs_triple_vendor) { 1063 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 1064 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 1065 // Both architectures had the vendor specified, so if they aren't equal 1066 // then we return false 1067 if (rhs_vendor_specified && lhs_vendor_specified) 1068 return false; 1069 1070 // Only fail if both vendor types are not unknown 1071 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 1072 rhs_triple_vendor != llvm::Triple::UnknownVendor) 1073 return false; 1074 } 1075 1076 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 1077 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 1078 if (lhs_triple_os != rhs_triple_os) { 1079 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 1080 const bool lhs_os_specified = TripleOSWasSpecified(); 1081 // Both architectures had the OS specified, so if they aren't equal then 1082 // we return false 1083 if (rhs_os_specified && lhs_os_specified) 1084 return false; 1085 1086 // Only fail if both os types are not unknown 1087 if (lhs_triple_os != llvm::Triple::UnknownOS && 1088 rhs_triple_os != llvm::Triple::UnknownOS) 1089 return false; 1090 } 1091 1092 const llvm::Triple::EnvironmentType lhs_triple_env = 1093 lhs_triple.getEnvironment(); 1094 const llvm::Triple::EnvironmentType rhs_triple_env = 1095 rhs_triple.getEnvironment(); 1096 1097 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env); 1098 } 1099 return false; 1100 } 1101 1102 void ArchSpec::UpdateCore() { 1103 llvm::StringRef arch_name(m_triple.getArchName()); 1104 const CoreDefinition *core_def = FindCoreDefinition(arch_name); 1105 if (core_def) { 1106 m_core = core_def->core; 1107 // Set the byte order to the default byte order for an architecture. This 1108 // can be modified if needed for cases when cores handle both big and 1109 // little endian 1110 m_byte_order = core_def->default_byte_order; 1111 } else { 1112 Clear(); 1113 } 1114 } 1115 1116 //===----------------------------------------------------------------------===// 1117 // Helper methods. 1118 1119 void ArchSpec::CoreUpdated(bool update_triple) { 1120 const CoreDefinition *core_def = FindCoreDefinition(m_core); 1121 if (core_def) { 1122 if (update_triple) 1123 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 1124 m_byte_order = core_def->default_byte_order; 1125 } else { 1126 if (update_triple) 1127 m_triple = llvm::Triple(); 1128 m_byte_order = eByteOrderInvalid; 1129 } 1130 } 1131 1132 //===----------------------------------------------------------------------===// 1133 // Operators. 1134 1135 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, 1136 bool try_inverse, bool enforce_exact_match) { 1137 if (core1 == core2) 1138 return true; 1139 1140 switch (core1) { 1141 case ArchSpec::kCore_any: 1142 return true; 1143 1144 case ArchSpec::eCore_arm_generic: 1145 if (enforce_exact_match) 1146 break; 1147 LLVM_FALLTHROUGH; 1148 case ArchSpec::kCore_arm_any: 1149 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 1150 return true; 1151 if (core2 >= ArchSpec::kCore_thumb_first && 1152 core2 <= ArchSpec::kCore_thumb_last) 1153 return true; 1154 if (core2 == ArchSpec::kCore_arm_any) 1155 return true; 1156 break; 1157 1158 case ArchSpec::kCore_x86_32_any: 1159 if ((core2 >= ArchSpec::kCore_x86_32_first && 1160 core2 <= ArchSpec::kCore_x86_32_last) || 1161 (core2 == ArchSpec::kCore_x86_32_any)) 1162 return true; 1163 break; 1164 1165 case ArchSpec::kCore_x86_64_any: 1166 if ((core2 >= ArchSpec::kCore_x86_64_first && 1167 core2 <= ArchSpec::kCore_x86_64_last) || 1168 (core2 == ArchSpec::kCore_x86_64_any)) 1169 return true; 1170 break; 1171 1172 case ArchSpec::kCore_ppc_any: 1173 if ((core2 >= ArchSpec::kCore_ppc_first && 1174 core2 <= ArchSpec::kCore_ppc_last) || 1175 (core2 == ArchSpec::kCore_ppc_any)) 1176 return true; 1177 break; 1178 1179 case ArchSpec::kCore_ppc64_any: 1180 if ((core2 >= ArchSpec::kCore_ppc64_first && 1181 core2 <= ArchSpec::kCore_ppc64_last) || 1182 (core2 == ArchSpec::kCore_ppc64_any)) 1183 return true; 1184 break; 1185 1186 case ArchSpec::eCore_arm_armv6m: 1187 if (!enforce_exact_match) { 1188 if (core2 == ArchSpec::eCore_arm_generic) 1189 return true; 1190 try_inverse = false; 1191 if (core2 == ArchSpec::eCore_arm_armv7) 1192 return true; 1193 if (core2 == ArchSpec::eCore_arm_armv6m) 1194 return true; 1195 } 1196 break; 1197 1198 case ArchSpec::kCore_hexagon_any: 1199 if ((core2 >= ArchSpec::kCore_hexagon_first && 1200 core2 <= ArchSpec::kCore_hexagon_last) || 1201 (core2 == ArchSpec::kCore_hexagon_any)) 1202 return true; 1203 break; 1204 1205 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1206 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1207 // ARMv7E-M - armv7em 1208 case ArchSpec::eCore_arm_armv7em: 1209 if (!enforce_exact_match) { 1210 if (core2 == ArchSpec::eCore_arm_generic) 1211 return true; 1212 if (core2 == ArchSpec::eCore_arm_armv7m) 1213 return true; 1214 if (core2 == ArchSpec::eCore_arm_armv6m) 1215 return true; 1216 if (core2 == ArchSpec::eCore_arm_armv7) 1217 return true; 1218 try_inverse = true; 1219 } 1220 break; 1221 1222 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization 1223 // Cortex-M0 - ARMv6-M - armv6m Cortex-M3 - ARMv7-M - armv7m Cortex-M4 - 1224 // ARMv7E-M - armv7em 1225 case ArchSpec::eCore_arm_armv7m: 1226 if (!enforce_exact_match) { 1227 if (core2 == ArchSpec::eCore_arm_generic) 1228 return true; 1229 if (core2 == ArchSpec::eCore_arm_armv6m) 1230 return true; 1231 if (core2 == ArchSpec::eCore_arm_armv7) 1232 return true; 1233 if (core2 == ArchSpec::eCore_arm_armv7em) 1234 return true; 1235 try_inverse = true; 1236 } 1237 break; 1238 1239 case ArchSpec::eCore_arm_armv7f: 1240 case ArchSpec::eCore_arm_armv7k: 1241 case ArchSpec::eCore_arm_armv7s: 1242 if (!enforce_exact_match) { 1243 if (core2 == ArchSpec::eCore_arm_generic) 1244 return true; 1245 if (core2 == ArchSpec::eCore_arm_armv7) 1246 return true; 1247 try_inverse = false; 1248 } 1249 break; 1250 1251 case ArchSpec::eCore_x86_64_x86_64h: 1252 if (!enforce_exact_match) { 1253 try_inverse = false; 1254 if (core2 == ArchSpec::eCore_x86_64_x86_64) 1255 return true; 1256 } 1257 break; 1258 1259 case ArchSpec::eCore_arm_armv8: 1260 if (!enforce_exact_match) { 1261 if (core2 == ArchSpec::eCore_arm_arm64) 1262 return true; 1263 if (core2 == ArchSpec::eCore_arm_aarch64) 1264 return true; 1265 try_inverse = false; 1266 } 1267 break; 1268 1269 case ArchSpec::eCore_arm_aarch64: 1270 if (!enforce_exact_match) { 1271 if (core2 == ArchSpec::eCore_arm_arm64) 1272 return true; 1273 if (core2 == ArchSpec::eCore_arm_armv8) 1274 return true; 1275 try_inverse = false; 1276 } 1277 break; 1278 1279 case ArchSpec::eCore_arm_arm64: 1280 if (!enforce_exact_match) { 1281 if (core2 == ArchSpec::eCore_arm_aarch64) 1282 return true; 1283 if (core2 == ArchSpec::eCore_arm_armv8) 1284 return true; 1285 try_inverse = false; 1286 } 1287 break; 1288 1289 case ArchSpec::eCore_mips32: 1290 if (!enforce_exact_match) { 1291 if (core2 >= ArchSpec::kCore_mips32_first && 1292 core2 <= ArchSpec::kCore_mips32_last) 1293 return true; 1294 try_inverse = false; 1295 } 1296 break; 1297 1298 case ArchSpec::eCore_mips32el: 1299 if (!enforce_exact_match) { 1300 if (core2 >= ArchSpec::kCore_mips32el_first && 1301 core2 <= ArchSpec::kCore_mips32el_last) 1302 return true; 1303 try_inverse = true; 1304 } 1305 break; 1306 1307 case ArchSpec::eCore_mips64: 1308 if (!enforce_exact_match) { 1309 if (core2 >= ArchSpec::kCore_mips32_first && 1310 core2 <= ArchSpec::kCore_mips32_last) 1311 return true; 1312 if (core2 >= ArchSpec::kCore_mips64_first && 1313 core2 <= ArchSpec::kCore_mips64_last) 1314 return true; 1315 try_inverse = false; 1316 } 1317 break; 1318 1319 case ArchSpec::eCore_mips64el: 1320 if (!enforce_exact_match) { 1321 if (core2 >= ArchSpec::kCore_mips32el_first && 1322 core2 <= ArchSpec::kCore_mips32el_last) 1323 return true; 1324 if (core2 >= ArchSpec::kCore_mips64el_first && 1325 core2 <= ArchSpec::kCore_mips64el_last) 1326 return true; 1327 try_inverse = false; 1328 } 1329 break; 1330 1331 case ArchSpec::eCore_mips64r2: 1332 case ArchSpec::eCore_mips64r3: 1333 case ArchSpec::eCore_mips64r5: 1334 if (!enforce_exact_match) { 1335 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10)) 1336 return true; 1337 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1)) 1338 return true; 1339 try_inverse = false; 1340 } 1341 break; 1342 1343 case ArchSpec::eCore_mips64r2el: 1344 case ArchSpec::eCore_mips64r3el: 1345 case ArchSpec::eCore_mips64r5el: 1346 if (!enforce_exact_match) { 1347 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10)) 1348 return true; 1349 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1)) 1350 return true; 1351 try_inverse = false; 1352 } 1353 break; 1354 1355 case ArchSpec::eCore_mips32r2: 1356 case ArchSpec::eCore_mips32r3: 1357 case ArchSpec::eCore_mips32r5: 1358 if (!enforce_exact_match) { 1359 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1) 1360 return true; 1361 } 1362 break; 1363 1364 case ArchSpec::eCore_mips32r2el: 1365 case ArchSpec::eCore_mips32r3el: 1366 case ArchSpec::eCore_mips32r5el: 1367 if (!enforce_exact_match) { 1368 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1) 1369 return true; 1370 } 1371 break; 1372 1373 case ArchSpec::eCore_mips32r6: 1374 if (!enforce_exact_match) { 1375 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1376 return true; 1377 } 1378 break; 1379 1380 case ArchSpec::eCore_mips32r6el: 1381 if (!enforce_exact_match) { 1382 if (core2 == ArchSpec::eCore_mips32el || 1383 core2 == ArchSpec::eCore_mips32r6el) 1384 return true; 1385 } 1386 break; 1387 1388 case ArchSpec::eCore_mips64r6: 1389 if (!enforce_exact_match) { 1390 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6) 1391 return true; 1392 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6) 1393 return true; 1394 } 1395 break; 1396 1397 case ArchSpec::eCore_mips64r6el: 1398 if (!enforce_exact_match) { 1399 if (core2 == ArchSpec::eCore_mips32el || 1400 core2 == ArchSpec::eCore_mips32r6el) 1401 return true; 1402 if (core2 == ArchSpec::eCore_mips64el || 1403 core2 == ArchSpec::eCore_mips64r6el) 1404 return true; 1405 } 1406 break; 1407 1408 default: 1409 break; 1410 } 1411 if (try_inverse) 1412 return cores_match(core2, core1, false, enforce_exact_match); 1413 return false; 1414 } 1415 1416 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) { 1417 const ArchSpec::Core lhs_core = lhs.GetCore(); 1418 const ArchSpec::Core rhs_core = rhs.GetCore(); 1419 return lhs_core < rhs_core; 1420 } 1421 1422 1423 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) { 1424 return lhs.GetCore() == rhs.GetCore(); 1425 } 1426 1427 bool ArchSpec::IsFullySpecifiedTriple() const { 1428 const auto &user_specified_triple = GetTriple(); 1429 1430 bool user_triple_fully_specified = false; 1431 1432 if ((user_specified_triple.getOS() != llvm::Triple::UnknownOS) || 1433 TripleOSWasSpecified()) { 1434 if ((user_specified_triple.getVendor() != llvm::Triple::UnknownVendor) || 1435 TripleVendorWasSpecified()) { 1436 const unsigned unspecified = 0; 1437 if (user_specified_triple.getOSMajorVersion() != unspecified) { 1438 user_triple_fully_specified = true; 1439 } 1440 } 1441 } 1442 1443 return user_triple_fully_specified; 1444 } 1445 1446 void ArchSpec::PiecewiseTripleCompare( 1447 const ArchSpec &other, bool &arch_different, bool &vendor_different, 1448 bool &os_different, bool &os_version_different, bool &env_different) const { 1449 const llvm::Triple &me(GetTriple()); 1450 const llvm::Triple &them(other.GetTriple()); 1451 1452 arch_different = (me.getArch() != them.getArch()); 1453 1454 vendor_different = (me.getVendor() != them.getVendor()); 1455 1456 os_different = (me.getOS() != them.getOS()); 1457 1458 os_version_different = (me.getOSMajorVersion() != them.getOSMajorVersion()); 1459 1460 env_different = (me.getEnvironment() != them.getEnvironment()); 1461 } 1462 1463 bool ArchSpec::IsAlwaysThumbInstructions() const { 1464 std::string Status; 1465 if (GetTriple().getArch() == llvm::Triple::arm || 1466 GetTriple().getArch() == llvm::Triple::thumb) { 1467 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M 1468 // 1469 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only 1470 // execute thumb instructions. We map the cores to arch names like this: 1471 // 1472 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4, 1473 // Cortex-M7: armv7em 1474 1475 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || 1476 GetCore() == ArchSpec::Core::eCore_arm_armv7em || 1477 GetCore() == ArchSpec::Core::eCore_arm_armv6m || 1478 GetCore() == ArchSpec::Core::eCore_thumbv7m || 1479 GetCore() == ArchSpec::Core::eCore_thumbv7em || 1480 GetCore() == ArchSpec::Core::eCore_thumbv6m) { 1481 return true; 1482 } 1483 } 1484 return false; 1485 } 1486 1487 void ArchSpec::DumpTriple(Stream &s) const { 1488 const llvm::Triple &triple = GetTriple(); 1489 llvm::StringRef arch_str = triple.getArchName(); 1490 llvm::StringRef vendor_str = triple.getVendorName(); 1491 llvm::StringRef os_str = triple.getOSName(); 1492 llvm::StringRef environ_str = triple.getEnvironmentName(); 1493 1494 s.Printf("%s-%s-%s", arch_str.empty() ? "*" : arch_str.str().c_str(), 1495 vendor_str.empty() ? "*" : vendor_str.str().c_str(), 1496 os_str.empty() ? "*" : os_str.str().c_str()); 1497 1498 if (!environ_str.empty()) 1499 s.Printf("-%s", environ_str.str().c_str()); 1500 } 1501