1*f678e45dSDimitry Andric //===-- RegisterInfoPOSIX_arm.cpp ------------------------------*- C++ -*-===//
2*f678e45dSDimitry Andric //
3*f678e45dSDimitry Andric // The LLVM Compiler Infrastructure
4*f678e45dSDimitry Andric //
5*f678e45dSDimitry Andric // This file is distributed under the University of Illinois Open Source
6*f678e45dSDimitry Andric // License. See LICENSE.TXT for details.
7*f678e45dSDimitry Andric //
8*f678e45dSDimitry Andric //===---------------------------------------------------------------------===//
9*f678e45dSDimitry Andric
10*f678e45dSDimitry Andric #include <cassert>
11*f678e45dSDimitry Andric #include <stddef.h>
12*f678e45dSDimitry Andric #include <vector>
13*f678e45dSDimitry Andric
14*f678e45dSDimitry Andric #include "lldb/lldb-defines.h"
15*f678e45dSDimitry Andric #include "llvm/Support/Compiler.h"
16*f678e45dSDimitry Andric
17*f678e45dSDimitry Andric #include "RegisterInfoPOSIX_arm.h"
18*f678e45dSDimitry Andric
19*f678e45dSDimitry Andric using namespace lldb;
20*f678e45dSDimitry Andric using namespace lldb_private;
21*f678e45dSDimitry Andric
22*f678e45dSDimitry Andric // Based on RegisterContextDarwin_arm.cpp
23*f678e45dSDimitry Andric #define GPR_OFFSET(idx) ((idx)*4)
24*f678e45dSDimitry Andric #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterInfoPOSIX_arm::GPR))
25*f678e45dSDimitry Andric #define FPSCR_OFFSET \
26*f678e45dSDimitry Andric (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm::FPU, fpscr) + \
27*f678e45dSDimitry Andric sizeof(RegisterInfoPOSIX_arm::GPR))
28*f678e45dSDimitry Andric #define EXC_OFFSET(idx) \
29*f678e45dSDimitry Andric ((idx)*4 + sizeof(RegisterInfoPOSIX_arm::GPR) + \
30*f678e45dSDimitry Andric sizeof(RegisterInfoPOSIX_arm::FPU))
31*f678e45dSDimitry Andric #define DBG_OFFSET(reg) \
32*f678e45dSDimitry Andric ((LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm::DBG, reg) + \
33*f678e45dSDimitry Andric sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
34*f678e45dSDimitry Andric sizeof(RegisterInfoPOSIX_arm::EXC)))
35*f678e45dSDimitry Andric
36*f678e45dSDimitry Andric #define DEFINE_DBG(reg, i) \
37*f678e45dSDimitry Andric #reg, NULL, sizeof(((RegisterInfoPOSIX_arm::DBG *) NULL)->reg[i]), \
38*f678e45dSDimitry Andric DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \
39*f678e45dSDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
40*f678e45dSDimitry Andric LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
41*f678e45dSDimitry Andric dbg_##reg##i }, \
42*f678e45dSDimitry Andric NULL, NULL, NULL, 0
43*f678e45dSDimitry Andric #define REG_CONTEXT_SIZE \
44*f678e45dSDimitry Andric (sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
45*f678e45dSDimitry Andric sizeof(RegisterInfoPOSIX_arm::EXC))
46*f678e45dSDimitry Andric
47*f678e45dSDimitry Andric //-----------------------------------------------------------------------------
48*f678e45dSDimitry Andric // Include RegisterInfos_arm to declare our g_register_infos_arm structure.
49*f678e45dSDimitry Andric //-----------------------------------------------------------------------------
50*f678e45dSDimitry Andric #define DECLARE_REGISTER_INFOS_ARM_STRUCT
51*f678e45dSDimitry Andric #include "RegisterInfos_arm.h"
52*f678e45dSDimitry Andric #undef DECLARE_REGISTER_INFOS_ARM_STRUCT
53*f678e45dSDimitry Andric
54*f678e45dSDimitry Andric static const lldb_private::RegisterInfo *
GetRegisterInfoPtr(const lldb_private::ArchSpec & target_arch)55*f678e45dSDimitry Andric GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
56*f678e45dSDimitry Andric switch (target_arch.GetMachine()) {
57*f678e45dSDimitry Andric case llvm::Triple::arm:
58*f678e45dSDimitry Andric return g_register_infos_arm;
59*f678e45dSDimitry Andric default:
60*f678e45dSDimitry Andric assert(false && "Unhandled target architecture.");
61*f678e45dSDimitry Andric return NULL;
62*f678e45dSDimitry Andric }
63*f678e45dSDimitry Andric }
64*f678e45dSDimitry Andric
65*f678e45dSDimitry Andric static uint32_t
GetRegisterInfoCount(const lldb_private::ArchSpec & target_arch)66*f678e45dSDimitry Andric GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
67*f678e45dSDimitry Andric switch (target_arch.GetMachine()) {
68*f678e45dSDimitry Andric case llvm::Triple::arm:
69*f678e45dSDimitry Andric return static_cast<uint32_t>(sizeof(g_register_infos_arm) /
70*f678e45dSDimitry Andric sizeof(g_register_infos_arm[0]));
71*f678e45dSDimitry Andric default:
72*f678e45dSDimitry Andric assert(false && "Unhandled target architecture.");
73*f678e45dSDimitry Andric return 0;
74*f678e45dSDimitry Andric }
75*f678e45dSDimitry Andric }
76*f678e45dSDimitry Andric
RegisterInfoPOSIX_arm(const lldb_private::ArchSpec & target_arch)77*f678e45dSDimitry Andric RegisterInfoPOSIX_arm::RegisterInfoPOSIX_arm(
78*f678e45dSDimitry Andric const lldb_private::ArchSpec &target_arch)
79*f678e45dSDimitry Andric : lldb_private::RegisterInfoInterface(target_arch),
80*f678e45dSDimitry Andric m_register_info_p(GetRegisterInfoPtr(target_arch)),
81*f678e45dSDimitry Andric m_register_info_count(GetRegisterInfoCount(target_arch)) {}
82*f678e45dSDimitry Andric
GetGPRSize() const83*f678e45dSDimitry Andric size_t RegisterInfoPOSIX_arm::GetGPRSize() const {
84*f678e45dSDimitry Andric return sizeof(struct RegisterInfoPOSIX_arm::GPR);
85*f678e45dSDimitry Andric }
86*f678e45dSDimitry Andric
87*f678e45dSDimitry Andric const lldb_private::RegisterInfo *
GetRegisterInfo() const88*f678e45dSDimitry Andric RegisterInfoPOSIX_arm::GetRegisterInfo() const {
89*f678e45dSDimitry Andric return m_register_info_p;
90*f678e45dSDimitry Andric }
91*f678e45dSDimitry Andric
GetRegisterCount() const92*f678e45dSDimitry Andric uint32_t RegisterInfoPOSIX_arm::GetRegisterCount() const {
93*f678e45dSDimitry Andric return m_register_info_count;
94*f678e45dSDimitry Andric }
95