11c3bbb01SEd Maste //===-- RegisterContextLinux_mips.cpp ------------------------*- C++ -*-===//
21c3bbb01SEd Maste //
31c3bbb01SEd Maste //                     The LLVM Compiler Infrastructure
41c3bbb01SEd Maste //
51c3bbb01SEd Maste // This file is distributed under the University of Illinois Open Source
61c3bbb01SEd Maste // License. See LICENSE.TXT for details.
71c3bbb01SEd Maste //
81c3bbb01SEd Maste //===---------------------------------------------------------------------===//
91c3bbb01SEd Maste 
101c3bbb01SEd Maste #include <stddef.h>
11435933ddSDimitry Andric #include <vector>
121c3bbb01SEd Maste 
139f2f44ceSEd Maste // For eh_frame and DWARF Register numbers
141c3bbb01SEd Maste #include "RegisterContextLinux_mips.h"
151c3bbb01SEd Maste 
161c3bbb01SEd Maste // Internal codes for mips registers
17b6c25e0eSDimitry Andric #include "lldb-mips-linux-register-enums.h"
18b6c25e0eSDimitry Andric 
19b6c25e0eSDimitry Andric // For GP and FP buffers
20b6c25e0eSDimitry Andric #include "RegisterContext_mips.h"
211c3bbb01SEd Maste 
221c3bbb01SEd Maste using namespace lldb_private;
231c3bbb01SEd Maste using namespace lldb;
241c3bbb01SEd Maste 
251c3bbb01SEd Maste //---------------------------------------------------------------------------
261c3bbb01SEd Maste // Include RegisterInfos_mips to declare our g_register_infos_mips structure.
271c3bbb01SEd Maste //---------------------------------------------------------------------------
281c3bbb01SEd Maste #define DECLARE_REGISTER_INFOS_MIPS_STRUCT
291c3bbb01SEd Maste #include "RegisterInfos_mips.h"
301c3bbb01SEd Maste #undef DECLARE_REGISTER_INFOS_MIPS_STRUCT
311c3bbb01SEd Maste 
32*f678e45dSDimitry Andric // mips general purpose registers.
33*f678e45dSDimitry Andric const uint32_t g_gp_regnums_mips[] = {
34*f678e45dSDimitry Andric     gpr_zero_mips,      gpr_r1_mips,    gpr_r2_mips,      gpr_r3_mips,
35*f678e45dSDimitry Andric     gpr_r4_mips,        gpr_r5_mips,    gpr_r6_mips,      gpr_r7_mips,
36*f678e45dSDimitry Andric     gpr_r8_mips,        gpr_r9_mips,    gpr_r10_mips,     gpr_r11_mips,
37*f678e45dSDimitry Andric     gpr_r12_mips,       gpr_r13_mips,   gpr_r14_mips,     gpr_r15_mips,
38*f678e45dSDimitry Andric     gpr_r16_mips,       gpr_r17_mips,   gpr_r18_mips,     gpr_r19_mips,
39*f678e45dSDimitry Andric     gpr_r20_mips,       gpr_r21_mips,   gpr_r22_mips,     gpr_r23_mips,
40*f678e45dSDimitry Andric     gpr_r24_mips,       gpr_r25_mips,   gpr_r26_mips,     gpr_r27_mips,
41*f678e45dSDimitry Andric     gpr_gp_mips,        gpr_sp_mips,    gpr_r30_mips,     gpr_ra_mips,
42*f678e45dSDimitry Andric     gpr_sr_mips,        gpr_mullo_mips, gpr_mulhi_mips,   gpr_badvaddr_mips,
43*f678e45dSDimitry Andric     gpr_cause_mips,     gpr_pc_mips,    gpr_config5_mips,
44*f678e45dSDimitry Andric     LLDB_INVALID_REGNUM // register sets need to end with this flag
45*f678e45dSDimitry Andric };
46*f678e45dSDimitry Andric 
47*f678e45dSDimitry Andric static_assert((sizeof(g_gp_regnums_mips) / sizeof(g_gp_regnums_mips[0])) - 1 ==
48*f678e45dSDimitry Andric                   k_num_gpr_registers_mips,
49*f678e45dSDimitry Andric               "g_gp_regnums_mips has wrong number of register infos");
50*f678e45dSDimitry Andric // mips floating point registers.
51*f678e45dSDimitry Andric const uint32_t g_fp_regnums_mips[] = {
52*f678e45dSDimitry Andric     fpr_f0_mips,        fpr_f1_mips,  fpr_f2_mips,      fpr_f3_mips,
53*f678e45dSDimitry Andric     fpr_f4_mips,        fpr_f5_mips,  fpr_f6_mips,      fpr_f7_mips,
54*f678e45dSDimitry Andric     fpr_f8_mips,        fpr_f9_mips,  fpr_f10_mips,     fpr_f11_mips,
55*f678e45dSDimitry Andric     fpr_f12_mips,       fpr_f13_mips, fpr_f14_mips,     fpr_f15_mips,
56*f678e45dSDimitry Andric     fpr_f16_mips,       fpr_f17_mips, fpr_f18_mips,     fpr_f19_mips,
57*f678e45dSDimitry Andric     fpr_f20_mips,       fpr_f21_mips, fpr_f22_mips,     fpr_f23_mips,
58*f678e45dSDimitry Andric     fpr_f24_mips,       fpr_f25_mips, fpr_f26_mips,     fpr_f27_mips,
59*f678e45dSDimitry Andric     fpr_f28_mips,       fpr_f29_mips, fpr_f30_mips,     fpr_f31_mips,
60*f678e45dSDimitry Andric     fpr_fcsr_mips,      fpr_fir_mips, fpr_config5_mips,
61*f678e45dSDimitry Andric     LLDB_INVALID_REGNUM // register sets need to end with this flag
62*f678e45dSDimitry Andric };
63*f678e45dSDimitry Andric 
64*f678e45dSDimitry Andric static_assert((sizeof(g_fp_regnums_mips) / sizeof(g_fp_regnums_mips[0])) - 1 ==
65*f678e45dSDimitry Andric                   k_num_fpr_registers_mips,
66*f678e45dSDimitry Andric               "g_fp_regnums_mips has wrong number of register infos");
67*f678e45dSDimitry Andric 
68*f678e45dSDimitry Andric // mips MSA registers.
69*f678e45dSDimitry Andric const uint32_t g_msa_regnums_mips[] = {
70*f678e45dSDimitry Andric     msa_w0_mips,        msa_w1_mips,  msa_w2_mips,   msa_w3_mips,
71*f678e45dSDimitry Andric     msa_w4_mips,        msa_w5_mips,  msa_w6_mips,   msa_w7_mips,
72*f678e45dSDimitry Andric     msa_w8_mips,        msa_w9_mips,  msa_w10_mips,  msa_w11_mips,
73*f678e45dSDimitry Andric     msa_w12_mips,       msa_w13_mips, msa_w14_mips,  msa_w15_mips,
74*f678e45dSDimitry Andric     msa_w16_mips,       msa_w17_mips, msa_w18_mips,  msa_w19_mips,
75*f678e45dSDimitry Andric     msa_w20_mips,       msa_w21_mips, msa_w22_mips,  msa_w23_mips,
76*f678e45dSDimitry Andric     msa_w24_mips,       msa_w25_mips, msa_w26_mips,  msa_w27_mips,
77*f678e45dSDimitry Andric     msa_w28_mips,       msa_w29_mips, msa_w30_mips,  msa_w31_mips,
78*f678e45dSDimitry Andric     msa_fcsr_mips,      msa_fir_mips, msa_mcsr_mips, msa_mir_mips,
79*f678e45dSDimitry Andric     msa_config5_mips,
80*f678e45dSDimitry Andric     LLDB_INVALID_REGNUM // register sets need to end with this flag
81*f678e45dSDimitry Andric };
82*f678e45dSDimitry Andric 
83*f678e45dSDimitry Andric static_assert((sizeof(g_msa_regnums_mips) / sizeof(g_msa_regnums_mips[0])) -
84*f678e45dSDimitry Andric                       1 ==
85*f678e45dSDimitry Andric                   k_num_msa_registers_mips,
86*f678e45dSDimitry Andric               "g_msa_regnums_mips has wrong number of register infos");
87*f678e45dSDimitry Andric 
88*f678e45dSDimitry Andric // Number of register sets provided by this context.
89*f678e45dSDimitry Andric constexpr size_t k_num_register_sets = 3;
90*f678e45dSDimitry Andric 
91*f678e45dSDimitry Andric // Register sets for mips.
92*f678e45dSDimitry Andric static const RegisterSet g_reg_sets_mips[k_num_register_sets] = {
93*f678e45dSDimitry Andric     {"General Purpose Registers", "gpr", k_num_gpr_registers_mips,
94*f678e45dSDimitry Andric      g_gp_regnums_mips},
95*f678e45dSDimitry Andric     {"Floating Point Registers", "fpu", k_num_fpr_registers_mips,
96*f678e45dSDimitry Andric      g_fp_regnums_mips},
97*f678e45dSDimitry Andric     {"MSA Registers", "msa", k_num_msa_registers_mips, g_msa_regnums_mips}};
98*f678e45dSDimitry Andric 
GetUserRegisterInfoCount(bool msa_present)99435933ddSDimitry Andric uint32_t GetUserRegisterInfoCount(bool msa_present) {
1009f2f44ceSEd Maste   if (msa_present)
1019f2f44ceSEd Maste     return static_cast<uint32_t>(k_num_user_registers_mips);
102435933ddSDimitry Andric   return static_cast<uint32_t>(k_num_user_registers_mips -
103435933ddSDimitry Andric                                k_num_msa_registers_mips);
1049f2f44ceSEd Maste }
1059f2f44ceSEd Maste 
RegisterContextLinux_mips(const ArchSpec & target_arch,bool msa_present)106435933ddSDimitry Andric RegisterContextLinux_mips::RegisterContextLinux_mips(
107435933ddSDimitry Andric     const ArchSpec &target_arch, bool msa_present)
108435933ddSDimitry Andric     : RegisterInfoInterface(target_arch),
109435933ddSDimitry Andric       m_user_register_count(GetUserRegisterInfoCount(msa_present)) {}
1101c3bbb01SEd Maste 
GetGPRSize() const111435933ddSDimitry Andric size_t RegisterContextLinux_mips::GetGPRSize() const {
112b6c25e0eSDimitry Andric   return sizeof(GPR_linux_mips);
1131c3bbb01SEd Maste }
1141c3bbb01SEd Maste 
GetRegisterInfo() const115435933ddSDimitry Andric const RegisterInfo *RegisterContextLinux_mips::GetRegisterInfo() const {
116435933ddSDimitry Andric   switch (m_target_arch.GetMachine()) {
1171c3bbb01SEd Maste   case llvm::Triple::mips:
1181c3bbb01SEd Maste   case llvm::Triple::mipsel:
1191c3bbb01SEd Maste     return g_register_infos_mips;
1201c3bbb01SEd Maste   default:
1211c3bbb01SEd Maste     assert(false && "Unhandled target architecture.");
1221c3bbb01SEd Maste     return NULL;
1231c3bbb01SEd Maste   }
1241c3bbb01SEd Maste }
1251c3bbb01SEd Maste 
126*f678e45dSDimitry Andric const RegisterSet *
GetRegisterSet(size_t set) const127*f678e45dSDimitry Andric RegisterContextLinux_mips::GetRegisterSet(size_t set) const {
128*f678e45dSDimitry Andric   if (set >= k_num_register_sets)
129*f678e45dSDimitry Andric     return nullptr;
130*f678e45dSDimitry Andric   switch (m_target_arch.GetMachine()) {
131*f678e45dSDimitry Andric     case llvm::Triple::mips:
132*f678e45dSDimitry Andric     case llvm::Triple::mipsel:
133*f678e45dSDimitry Andric       return &g_reg_sets_mips[set];
134*f678e45dSDimitry Andric     default:
135*f678e45dSDimitry Andric       assert(false && "Unhandled target architecture.");
136*f678e45dSDimitry Andric       return nullptr;
137*f678e45dSDimitry Andric   }
138*f678e45dSDimitry Andric }
139*f678e45dSDimitry Andric 
140*f678e45dSDimitry Andric size_t
GetRegisterSetCount() const141*f678e45dSDimitry Andric RegisterContextLinux_mips::GetRegisterSetCount() const {
142*f678e45dSDimitry Andric   return k_num_register_sets;
143*f678e45dSDimitry Andric }
144*f678e45dSDimitry Andric 
GetRegisterCount() const145435933ddSDimitry Andric uint32_t RegisterContextLinux_mips::GetRegisterCount() const {
146435933ddSDimitry Andric   return static_cast<uint32_t>(sizeof(g_register_infos_mips) /
147435933ddSDimitry Andric                                sizeof(g_register_infos_mips[0]));
1481c3bbb01SEd Maste }
149b6c25e0eSDimitry Andric 
GetUserRegisterCount() const150435933ddSDimitry Andric uint32_t RegisterContextLinux_mips::GetUserRegisterCount() const {
1519f2f44ceSEd Maste   return static_cast<uint32_t>(m_user_register_count);
152b6c25e0eSDimitry Andric }
153