1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements X86 TargetInfo objects. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86.h" 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Diagnostic.h" 17 #include "clang/Basic/TargetBuiltins.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 21 namespace clang { 22 namespace targets { 23 24 const Builtin::Info BuiltinInfoX86[] = { 25 #define BUILTIN(ID, TYPE, ATTRS) \ 26 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 28 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 30 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 31 #include "clang/Basic/BuiltinsX86.def" 32 33 #define BUILTIN(ID, TYPE, ATTRS) \ 34 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 36 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 38 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 39 #include "clang/Basic/BuiltinsX86_64.def" 40 }; 41 42 static const char *const GCCRegNames[] = { 43 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 44 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 45 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 46 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 47 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 48 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 49 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 50 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 51 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 52 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 53 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 54 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 55 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 56 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 57 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 58 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 59 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 60 "k2", "k3", "k4", "k5", "k6", "k7", 61 "cr0", "cr2", "cr3", "cr4", "cr8", 62 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 63 "bnd0", "bnd1", "bnd2", "bnd3", 64 }; 65 66 const TargetInfo::AddlRegName AddlRegNames[] = { 67 {{"al", "ah", "eax", "rax"}, 0}, 68 {{"bl", "bh", "ebx", "rbx"}, 3}, 69 {{"cl", "ch", "ecx", "rcx"}, 2}, 70 {{"dl", "dh", "edx", "rdx"}, 1}, 71 {{"esi", "rsi"}, 4}, 72 {{"edi", "rdi"}, 5}, 73 {{"esp", "rsp"}, 7}, 74 {{"ebp", "rbp"}, 6}, 75 {{"r8d", "r8w", "r8b"}, 38}, 76 {{"r9d", "r9w", "r9b"}, 39}, 77 {{"r10d", "r10w", "r10b"}, 40}, 78 {{"r11d", "r11w", "r11b"}, 41}, 79 {{"r12d", "r12w", "r12b"}, 42}, 80 {{"r13d", "r13w", "r13b"}, 43}, 81 {{"r14d", "r14w", "r14b"}, 44}, 82 {{"r15d", "r15w", "r15b"}, 45}, 83 }; 84 85 } // namespace targets 86 } // namespace clang 87 88 using namespace clang; 89 using namespace clang::targets; 90 91 bool X86TargetInfo::setFPMath(StringRef Name) { 92 if (Name == "387") { 93 FPMath = FP_387; 94 return true; 95 } 96 if (Name == "sse") { 97 FPMath = FP_SSE; 98 return true; 99 } 100 return false; 101 } 102 103 bool X86TargetInfo::initFeatureMap( 104 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 105 const std::vector<std::string> &FeaturesVec) const { 106 // FIXME: This *really* should not be here. 107 // X86_64 always has SSE2. 108 if (getTriple().getArch() == llvm::Triple::x86_64) 109 setFeatureEnabledImpl(Features, "sse2", true); 110 111 const CPUKind Kind = getCPUKind(CPU); 112 113 // Enable X87 for all X86 processors but Lakemont. 114 if (Kind != CK_Lakemont) 115 setFeatureEnabledImpl(Features, "x87", true); 116 117 switch (Kind) { 118 case CK_Generic: 119 case CK_i386: 120 case CK_i486: 121 case CK_i586: 122 case CK_Pentium: 123 case CK_PentiumPro: 124 case CK_Lakemont: 125 break; 126 127 case CK_PentiumMMX: 128 case CK_Pentium2: 129 case CK_K6: 130 case CK_WinChipC6: 131 setFeatureEnabledImpl(Features, "mmx", true); 132 break; 133 134 case CK_Icelake: 135 setFeatureEnabledImpl(Features, "vaes", true); 136 setFeatureEnabledImpl(Features, "gfni", true); 137 setFeatureEnabledImpl(Features, "vpclmulqdq", true); 138 setFeatureEnabledImpl(Features, "avx512bitalg", true); 139 setFeatureEnabledImpl(Features, "avx512vnni", true); 140 setFeatureEnabledImpl(Features, "avx512vbmi2", true); 141 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 142 LLVM_FALLTHROUGH; 143 case CK_Cannonlake: 144 setFeatureEnabledImpl(Features, "avx512ifma", true); 145 setFeatureEnabledImpl(Features, "avx512vbmi", true); 146 setFeatureEnabledImpl(Features, "sha", true); 147 LLVM_FALLTHROUGH; 148 case CK_SkylakeServer: 149 setFeatureEnabledImpl(Features, "avx512f", true); 150 setFeatureEnabledImpl(Features, "avx512cd", true); 151 setFeatureEnabledImpl(Features, "avx512dq", true); 152 setFeatureEnabledImpl(Features, "avx512bw", true); 153 setFeatureEnabledImpl(Features, "avx512vl", true); 154 setFeatureEnabledImpl(Features, "pku", true); 155 if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB 156 setFeatureEnabledImpl(Features, "clwb", true); 157 LLVM_FALLTHROUGH; 158 case CK_SkylakeClient: 159 setFeatureEnabledImpl(Features, "xsavec", true); 160 setFeatureEnabledImpl(Features, "xsaves", true); 161 setFeatureEnabledImpl(Features, "mpx", true); 162 setFeatureEnabledImpl(Features, "sgx", true); 163 setFeatureEnabledImpl(Features, "clflushopt", true); 164 setFeatureEnabledImpl(Features, "rtm", true); 165 LLVM_FALLTHROUGH; 166 case CK_Broadwell: 167 setFeatureEnabledImpl(Features, "rdseed", true); 168 setFeatureEnabledImpl(Features, "adx", true); 169 setFeatureEnabledImpl(Features, "prfchw", true); 170 LLVM_FALLTHROUGH; 171 case CK_Haswell: 172 setFeatureEnabledImpl(Features, "avx2", true); 173 setFeatureEnabledImpl(Features, "lzcnt", true); 174 setFeatureEnabledImpl(Features, "bmi", true); 175 setFeatureEnabledImpl(Features, "bmi2", true); 176 setFeatureEnabledImpl(Features, "fma", true); 177 setFeatureEnabledImpl(Features, "movbe", true); 178 LLVM_FALLTHROUGH; 179 case CK_IvyBridge: 180 setFeatureEnabledImpl(Features, "rdrnd", true); 181 setFeatureEnabledImpl(Features, "f16c", true); 182 setFeatureEnabledImpl(Features, "fsgsbase", true); 183 LLVM_FALLTHROUGH; 184 case CK_SandyBridge: 185 setFeatureEnabledImpl(Features, "avx", true); 186 setFeatureEnabledImpl(Features, "xsave", true); 187 setFeatureEnabledImpl(Features, "xsaveopt", true); 188 LLVM_FALLTHROUGH; 189 case CK_Westmere: 190 setFeatureEnabledImpl(Features, "aes", true); 191 setFeatureEnabledImpl(Features, "pclmul", true); 192 LLVM_FALLTHROUGH; 193 case CK_Nehalem: 194 setFeatureEnabledImpl(Features, "sse4.2", true); 195 LLVM_FALLTHROUGH; 196 case CK_Penryn: 197 setFeatureEnabledImpl(Features, "sse4.1", true); 198 LLVM_FALLTHROUGH; 199 case CK_Core2: 200 setFeatureEnabledImpl(Features, "ssse3", true); 201 setFeatureEnabledImpl(Features, "sahf", true); 202 LLVM_FALLTHROUGH; 203 case CK_Yonah: 204 case CK_Prescott: 205 case CK_Nocona: 206 setFeatureEnabledImpl(Features, "sse3", true); 207 setFeatureEnabledImpl(Features, "cx16", true); 208 LLVM_FALLTHROUGH; 209 case CK_PentiumM: 210 case CK_Pentium4: 211 case CK_x86_64: 212 setFeatureEnabledImpl(Features, "sse2", true); 213 LLVM_FALLTHROUGH; 214 case CK_Pentium3: 215 case CK_C3_2: 216 setFeatureEnabledImpl(Features, "sse", true); 217 setFeatureEnabledImpl(Features, "fxsr", true); 218 break; 219 220 case CK_Goldmont: 221 setFeatureEnabledImpl(Features, "sha", true); 222 setFeatureEnabledImpl(Features, "rdrnd", true); 223 setFeatureEnabledImpl(Features, "rdseed", true); 224 setFeatureEnabledImpl(Features, "xsave", true); 225 setFeatureEnabledImpl(Features, "xsaveopt", true); 226 setFeatureEnabledImpl(Features, "xsavec", true); 227 setFeatureEnabledImpl(Features, "xsaves", true); 228 setFeatureEnabledImpl(Features, "clflushopt", true); 229 setFeatureEnabledImpl(Features, "mpx", true); 230 setFeatureEnabledImpl(Features, "fsgsbase", true); 231 LLVM_FALLTHROUGH; 232 case CK_Silvermont: 233 setFeatureEnabledImpl(Features, "aes", true); 234 setFeatureEnabledImpl(Features, "pclmul", true); 235 setFeatureEnabledImpl(Features, "sse4.2", true); 236 setFeatureEnabledImpl(Features, "prfchw", true); 237 LLVM_FALLTHROUGH; 238 case CK_Bonnell: 239 setFeatureEnabledImpl(Features, "movbe", true); 240 setFeatureEnabledImpl(Features, "ssse3", true); 241 setFeatureEnabledImpl(Features, "fxsr", true); 242 setFeatureEnabledImpl(Features, "cx16", true); 243 setFeatureEnabledImpl(Features, "sahf", true); 244 break; 245 246 case CK_KNM: 247 // TODO: Add avx5124fmaps/avx5124vnniw. 248 setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); 249 LLVM_FALLTHROUGH; 250 case CK_KNL: 251 setFeatureEnabledImpl(Features, "avx512f", true); 252 setFeatureEnabledImpl(Features, "avx512cd", true); 253 setFeatureEnabledImpl(Features, "avx512er", true); 254 setFeatureEnabledImpl(Features, "avx512pf", true); 255 setFeatureEnabledImpl(Features, "prfchw", true); 256 setFeatureEnabledImpl(Features, "prefetchwt1", true); 257 setFeatureEnabledImpl(Features, "fxsr", true); 258 setFeatureEnabledImpl(Features, "rdseed", true); 259 setFeatureEnabledImpl(Features, "adx", true); 260 setFeatureEnabledImpl(Features, "lzcnt", true); 261 setFeatureEnabledImpl(Features, "bmi", true); 262 setFeatureEnabledImpl(Features, "bmi2", true); 263 setFeatureEnabledImpl(Features, "rtm", true); 264 setFeatureEnabledImpl(Features, "fma", true); 265 setFeatureEnabledImpl(Features, "rdrnd", true); 266 setFeatureEnabledImpl(Features, "f16c", true); 267 setFeatureEnabledImpl(Features, "fsgsbase", true); 268 setFeatureEnabledImpl(Features, "aes", true); 269 setFeatureEnabledImpl(Features, "pclmul", true); 270 setFeatureEnabledImpl(Features, "cx16", true); 271 setFeatureEnabledImpl(Features, "xsaveopt", true); 272 setFeatureEnabledImpl(Features, "xsave", true); 273 setFeatureEnabledImpl(Features, "movbe", true); 274 setFeatureEnabledImpl(Features, "sahf", true); 275 break; 276 277 case CK_K6_2: 278 case CK_K6_3: 279 case CK_WinChip2: 280 case CK_C3: 281 setFeatureEnabledImpl(Features, "3dnow", true); 282 break; 283 284 case CK_AMDFAM10: 285 setFeatureEnabledImpl(Features, "sse4a", true); 286 setFeatureEnabledImpl(Features, "lzcnt", true); 287 setFeatureEnabledImpl(Features, "popcnt", true); 288 setFeatureEnabledImpl(Features, "sahf", true); 289 LLVM_FALLTHROUGH; 290 case CK_K8SSE3: 291 setFeatureEnabledImpl(Features, "sse3", true); 292 LLVM_FALLTHROUGH; 293 case CK_K8: 294 setFeatureEnabledImpl(Features, "sse2", true); 295 LLVM_FALLTHROUGH; 296 case CK_AthlonXP: 297 setFeatureEnabledImpl(Features, "sse", true); 298 setFeatureEnabledImpl(Features, "fxsr", true); 299 LLVM_FALLTHROUGH; 300 case CK_Athlon: 301 case CK_Geode: 302 setFeatureEnabledImpl(Features, "3dnowa", true); 303 break; 304 305 case CK_BTVER2: 306 setFeatureEnabledImpl(Features, "avx", true); 307 setFeatureEnabledImpl(Features, "aes", true); 308 setFeatureEnabledImpl(Features, "pclmul", true); 309 setFeatureEnabledImpl(Features, "bmi", true); 310 setFeatureEnabledImpl(Features, "f16c", true); 311 setFeatureEnabledImpl(Features, "xsaveopt", true); 312 setFeatureEnabledImpl(Features, "movbe", true); 313 LLVM_FALLTHROUGH; 314 case CK_BTVER1: 315 setFeatureEnabledImpl(Features, "ssse3", true); 316 setFeatureEnabledImpl(Features, "sse4a", true); 317 setFeatureEnabledImpl(Features, "lzcnt", true); 318 setFeatureEnabledImpl(Features, "popcnt", true); 319 setFeatureEnabledImpl(Features, "prfchw", true); 320 setFeatureEnabledImpl(Features, "cx16", true); 321 setFeatureEnabledImpl(Features, "fxsr", true); 322 setFeatureEnabledImpl(Features, "sahf", true); 323 break; 324 325 case CK_ZNVER1: 326 setFeatureEnabledImpl(Features, "adx", true); 327 setFeatureEnabledImpl(Features, "aes", true); 328 setFeatureEnabledImpl(Features, "avx2", true); 329 setFeatureEnabledImpl(Features, "bmi", true); 330 setFeatureEnabledImpl(Features, "bmi2", true); 331 setFeatureEnabledImpl(Features, "clflushopt", true); 332 setFeatureEnabledImpl(Features, "clzero", true); 333 setFeatureEnabledImpl(Features, "cx16", true); 334 setFeatureEnabledImpl(Features, "f16c", true); 335 setFeatureEnabledImpl(Features, "fma", true); 336 setFeatureEnabledImpl(Features, "fsgsbase", true); 337 setFeatureEnabledImpl(Features, "fxsr", true); 338 setFeatureEnabledImpl(Features, "lzcnt", true); 339 setFeatureEnabledImpl(Features, "mwaitx", true); 340 setFeatureEnabledImpl(Features, "movbe", true); 341 setFeatureEnabledImpl(Features, "pclmul", true); 342 setFeatureEnabledImpl(Features, "popcnt", true); 343 setFeatureEnabledImpl(Features, "prfchw", true); 344 setFeatureEnabledImpl(Features, "rdrnd", true); 345 setFeatureEnabledImpl(Features, "rdseed", true); 346 setFeatureEnabledImpl(Features, "sahf", true); 347 setFeatureEnabledImpl(Features, "sha", true); 348 setFeatureEnabledImpl(Features, "sse4a", true); 349 setFeatureEnabledImpl(Features, "xsave", true); 350 setFeatureEnabledImpl(Features, "xsavec", true); 351 setFeatureEnabledImpl(Features, "xsaveopt", true); 352 setFeatureEnabledImpl(Features, "xsaves", true); 353 break; 354 355 case CK_BDVER4: 356 setFeatureEnabledImpl(Features, "avx2", true); 357 setFeatureEnabledImpl(Features, "bmi2", true); 358 setFeatureEnabledImpl(Features, "mwaitx", true); 359 LLVM_FALLTHROUGH; 360 case CK_BDVER3: 361 setFeatureEnabledImpl(Features, "fsgsbase", true); 362 setFeatureEnabledImpl(Features, "xsaveopt", true); 363 LLVM_FALLTHROUGH; 364 case CK_BDVER2: 365 setFeatureEnabledImpl(Features, "bmi", true); 366 setFeatureEnabledImpl(Features, "fma", true); 367 setFeatureEnabledImpl(Features, "f16c", true); 368 setFeatureEnabledImpl(Features, "tbm", true); 369 LLVM_FALLTHROUGH; 370 case CK_BDVER1: 371 // xop implies avx, sse4a and fma4. 372 setFeatureEnabledImpl(Features, "xop", true); 373 setFeatureEnabledImpl(Features, "lwp", true); 374 setFeatureEnabledImpl(Features, "lzcnt", true); 375 setFeatureEnabledImpl(Features, "aes", true); 376 setFeatureEnabledImpl(Features, "pclmul", true); 377 setFeatureEnabledImpl(Features, "prfchw", true); 378 setFeatureEnabledImpl(Features, "cx16", true); 379 setFeatureEnabledImpl(Features, "fxsr", true); 380 setFeatureEnabledImpl(Features, "xsave", true); 381 setFeatureEnabledImpl(Features, "sahf", true); 382 break; 383 } 384 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 385 return false; 386 387 // Can't do this earlier because we need to be able to explicitly enable 388 // or disable these features and the things that they depend upon. 389 390 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 391 auto I = Features.find("sse4.2"); 392 if (I != Features.end() && I->getValue() && 393 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 394 FeaturesVec.end()) 395 Features["popcnt"] = true; 396 397 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 398 I = Features.find("3dnow"); 399 if (I != Features.end() && I->getValue() && 400 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 401 FeaturesVec.end()) 402 Features["prfchw"] = true; 403 404 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 405 // then enable MMX. 406 I = Features.find("sse"); 407 if (I != Features.end() && I->getValue() && 408 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 409 FeaturesVec.end()) 410 Features["mmx"] = true; 411 412 return true; 413 } 414 415 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 416 X86SSEEnum Level, bool Enabled) { 417 if (Enabled) { 418 switch (Level) { 419 case AVX512F: 420 Features["avx512f"] = Features["fma"] = Features["f16c"] = true; 421 LLVM_FALLTHROUGH; 422 case AVX2: 423 Features["avx2"] = true; 424 LLVM_FALLTHROUGH; 425 case AVX: 426 Features["avx"] = true; 427 Features["xsave"] = true; 428 LLVM_FALLTHROUGH; 429 case SSE42: 430 Features["sse4.2"] = true; 431 LLVM_FALLTHROUGH; 432 case SSE41: 433 Features["sse4.1"] = true; 434 LLVM_FALLTHROUGH; 435 case SSSE3: 436 Features["ssse3"] = true; 437 LLVM_FALLTHROUGH; 438 case SSE3: 439 Features["sse3"] = true; 440 LLVM_FALLTHROUGH; 441 case SSE2: 442 Features["sse2"] = true; 443 LLVM_FALLTHROUGH; 444 case SSE1: 445 Features["sse"] = true; 446 LLVM_FALLTHROUGH; 447 case NoSSE: 448 break; 449 } 450 return; 451 } 452 453 switch (Level) { 454 case NoSSE: 455 case SSE1: 456 Features["sse"] = false; 457 LLVM_FALLTHROUGH; 458 case SSE2: 459 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = 460 Features["gfni"] = false; 461 LLVM_FALLTHROUGH; 462 case SSE3: 463 Features["sse3"] = false; 464 setXOPLevel(Features, NoXOP, false); 465 LLVM_FALLTHROUGH; 466 case SSSE3: 467 Features["ssse3"] = false; 468 LLVM_FALLTHROUGH; 469 case SSE41: 470 Features["sse4.1"] = false; 471 LLVM_FALLTHROUGH; 472 case SSE42: 473 Features["sse4.2"] = false; 474 LLVM_FALLTHROUGH; 475 case AVX: 476 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 477 Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false; 478 setXOPLevel(Features, FMA4, false); 479 LLVM_FALLTHROUGH; 480 case AVX2: 481 Features["avx2"] = false; 482 LLVM_FALLTHROUGH; 483 case AVX512F: 484 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 485 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 486 Features["avx512vl"] = Features["avx512vbmi"] = 487 Features["avx512ifma"] = Features["avx512vpopcntdq"] = 488 Features["avx512bitalg"] = Features["avx512vnni"] = 489 Features["avx512vbmi2"] = false; 490 break; 491 } 492 } 493 494 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 495 MMX3DNowEnum Level, bool Enabled) { 496 if (Enabled) { 497 switch (Level) { 498 case AMD3DNowAthlon: 499 Features["3dnowa"] = true; 500 LLVM_FALLTHROUGH; 501 case AMD3DNow: 502 Features["3dnow"] = true; 503 LLVM_FALLTHROUGH; 504 case MMX: 505 Features["mmx"] = true; 506 LLVM_FALLTHROUGH; 507 case NoMMX3DNow: 508 break; 509 } 510 return; 511 } 512 513 switch (Level) { 514 case NoMMX3DNow: 515 case MMX: 516 Features["mmx"] = false; 517 LLVM_FALLTHROUGH; 518 case AMD3DNow: 519 Features["3dnow"] = false; 520 LLVM_FALLTHROUGH; 521 case AMD3DNowAthlon: 522 Features["3dnowa"] = false; 523 break; 524 } 525 } 526 527 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 528 bool Enabled) { 529 if (Enabled) { 530 switch (Level) { 531 case XOP: 532 Features["xop"] = true; 533 LLVM_FALLTHROUGH; 534 case FMA4: 535 Features["fma4"] = true; 536 setSSELevel(Features, AVX, true); 537 LLVM_FALLTHROUGH; 538 case SSE4A: 539 Features["sse4a"] = true; 540 setSSELevel(Features, SSE3, true); 541 LLVM_FALLTHROUGH; 542 case NoXOP: 543 break; 544 } 545 return; 546 } 547 548 switch (Level) { 549 case NoXOP: 550 case SSE4A: 551 Features["sse4a"] = false; 552 LLVM_FALLTHROUGH; 553 case FMA4: 554 Features["fma4"] = false; 555 LLVM_FALLTHROUGH; 556 case XOP: 557 Features["xop"] = false; 558 break; 559 } 560 } 561 562 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 563 StringRef Name, bool Enabled) { 564 // This is a bit of a hack to deal with the sse4 target feature when used 565 // as part of the target attribute. We handle sse4 correctly everywhere 566 // else. See below for more information on how we handle the sse4 options. 567 if (Name != "sse4") 568 Features[Name] = Enabled; 569 570 if (Name == "mmx") { 571 setMMXLevel(Features, MMX, Enabled); 572 } else if (Name == "sse") { 573 setSSELevel(Features, SSE1, Enabled); 574 } else if (Name == "sse2") { 575 setSSELevel(Features, SSE2, Enabled); 576 } else if (Name == "sse3") { 577 setSSELevel(Features, SSE3, Enabled); 578 } else if (Name == "ssse3") { 579 setSSELevel(Features, SSSE3, Enabled); 580 } else if (Name == "sse4.2") { 581 setSSELevel(Features, SSE42, Enabled); 582 } else if (Name == "sse4.1") { 583 setSSELevel(Features, SSE41, Enabled); 584 } else if (Name == "3dnow") { 585 setMMXLevel(Features, AMD3DNow, Enabled); 586 } else if (Name == "3dnowa") { 587 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 588 } else if (Name == "aes") { 589 if (Enabled) 590 setSSELevel(Features, SSE2, Enabled); 591 else 592 Features["vaes"] = false; 593 } else if (Name == "vaes") { 594 if (Enabled) { 595 setSSELevel(Features, AVX, Enabled); 596 Features["aes"] = true; 597 } 598 } else if (Name == "pclmul") { 599 if (Enabled) 600 setSSELevel(Features, SSE2, Enabled); 601 else 602 Features["vpclmulqdq"] = false; 603 } else if (Name == "vpclmulqdq") { 604 if (Enabled) { 605 setSSELevel(Features, AVX, Enabled); 606 Features["pclmul"] = true; 607 } 608 } else if (Name == "gfni") { 609 if (Enabled) 610 setSSELevel(Features, SSE2, Enabled); 611 } else if (Name == "avx") { 612 setSSELevel(Features, AVX, Enabled); 613 } else if (Name == "avx2") { 614 setSSELevel(Features, AVX2, Enabled); 615 } else if (Name == "avx512f") { 616 setSSELevel(Features, AVX512F, Enabled); 617 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 618 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 619 Name == "avx512vbmi" || Name == "avx512ifma" || 620 Name == "avx512vpopcntdq" || Name == "avx512bitalg" || 621 Name == "avx512vnni" || Name == "avx512vbmi2") { 622 if (Enabled) 623 setSSELevel(Features, AVX512F, Enabled); 624 // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. 625 if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) 626 Features["avx512bw"] = true; 627 // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. 628 if (Name == "avx512bw" && !Enabled) 629 Features["avx512vbmi"] = Features["avx512vbmi2"] = 630 Features["avx512bitalg"] = false; 631 } else if (Name == "fma") { 632 if (Enabled) 633 setSSELevel(Features, AVX, Enabled); 634 else 635 setSSELevel(Features, AVX512F, Enabled); 636 } else if (Name == "fma4") { 637 setXOPLevel(Features, FMA4, Enabled); 638 } else if (Name == "xop") { 639 setXOPLevel(Features, XOP, Enabled); 640 } else if (Name == "sse4a") { 641 setXOPLevel(Features, SSE4A, Enabled); 642 } else if (Name == "f16c") { 643 if (Enabled) 644 setSSELevel(Features, AVX, Enabled); 645 else 646 setSSELevel(Features, AVX512F, Enabled); 647 } else if (Name == "sha") { 648 if (Enabled) 649 setSSELevel(Features, SSE2, Enabled); 650 } else if (Name == "sse4") { 651 // We can get here via the __target__ attribute since that's not controlled 652 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 653 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 654 // disabled. 655 if (Enabled) 656 setSSELevel(Features, SSE42, Enabled); 657 else 658 setSSELevel(Features, SSE41, Enabled); 659 } else if (Name == "xsave") { 660 if (!Enabled) 661 Features["xsaveopt"] = false; 662 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 663 if (Enabled) 664 Features["xsave"] = true; 665 } 666 } 667 668 /// handleTargetFeatures - Perform initialization based on the user 669 /// configured set of features. 670 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 671 DiagnosticsEngine &Diags) { 672 for (const auto &Feature : Features) { 673 if (Feature[0] != '+') 674 continue; 675 676 if (Feature == "+aes") { 677 HasAES = true; 678 } else if (Feature == "+vaes") { 679 HasVAES = true; 680 } else if (Feature == "+pclmul") { 681 HasPCLMUL = true; 682 } else if (Feature == "+vpclmulqdq") { 683 HasVPCLMULQDQ = true; 684 } else if (Feature == "+lzcnt") { 685 HasLZCNT = true; 686 } else if (Feature == "+rdrnd") { 687 HasRDRND = true; 688 } else if (Feature == "+fsgsbase") { 689 HasFSGSBASE = true; 690 } else if (Feature == "+bmi") { 691 HasBMI = true; 692 } else if (Feature == "+bmi2") { 693 HasBMI2 = true; 694 } else if (Feature == "+popcnt") { 695 HasPOPCNT = true; 696 } else if (Feature == "+rtm") { 697 HasRTM = true; 698 } else if (Feature == "+prfchw") { 699 HasPRFCHW = true; 700 } else if (Feature == "+rdseed") { 701 HasRDSEED = true; 702 } else if (Feature == "+adx") { 703 HasADX = true; 704 } else if (Feature == "+tbm") { 705 HasTBM = true; 706 } else if (Feature == "+lwp") { 707 HasLWP = true; 708 } else if (Feature == "+fma") { 709 HasFMA = true; 710 } else if (Feature == "+f16c") { 711 HasF16C = true; 712 } else if (Feature == "+gfni") { 713 HasGFNI = true; 714 } else if (Feature == "+avx512cd") { 715 HasAVX512CD = true; 716 } else if (Feature == "+avx512vpopcntdq") { 717 HasAVX512VPOPCNTDQ = true; 718 } else if (Feature == "+avx512vnni") { 719 HasAVX512VNNI = true; 720 } else if (Feature == "+avx512er") { 721 HasAVX512ER = true; 722 } else if (Feature == "+avx512pf") { 723 HasAVX512PF = true; 724 } else if (Feature == "+avx512dq") { 725 HasAVX512DQ = true; 726 } else if (Feature == "+avx512bitalg") { 727 HasAVX512BITALG = true; 728 } else if (Feature == "+avx512bw") { 729 HasAVX512BW = true; 730 } else if (Feature == "+avx512vl") { 731 HasAVX512VL = true; 732 } else if (Feature == "+avx512vbmi") { 733 HasAVX512VBMI = true; 734 } else if (Feature == "+avx512vbmi2") { 735 HasAVX512VBMI2 = true; 736 } else if (Feature == "+avx512ifma") { 737 HasAVX512IFMA = true; 738 } else if (Feature == "+sha") { 739 HasSHA = true; 740 } else if (Feature == "+mpx") { 741 HasMPX = true; 742 } else if (Feature == "+shstk") { 743 HasSHSTK = true; 744 } else if (Feature == "+ibt") { 745 HasIBT = true; 746 } else if (Feature == "+movbe") { 747 HasMOVBE = true; 748 } else if (Feature == "+sgx") { 749 HasSGX = true; 750 } else if (Feature == "+cx16") { 751 HasCX16 = true; 752 } else if (Feature == "+fxsr") { 753 HasFXSR = true; 754 } else if (Feature == "+xsave") { 755 HasXSAVE = true; 756 } else if (Feature == "+xsaveopt") { 757 HasXSAVEOPT = true; 758 } else if (Feature == "+xsavec") { 759 HasXSAVEC = true; 760 } else if (Feature == "+xsaves") { 761 HasXSAVES = true; 762 } else if (Feature == "+mwaitx") { 763 HasMWAITX = true; 764 } else if (Feature == "+pku") { 765 HasPKU = true; 766 } else if (Feature == "+clflushopt") { 767 HasCLFLUSHOPT = true; 768 } else if (Feature == "+clwb") { 769 HasCLWB = true; 770 } else if (Feature == "+prefetchwt1") { 771 HasPREFETCHWT1 = true; 772 } else if (Feature == "+clzero") { 773 HasCLZERO = true; 774 } else if (Feature == "+retpoline") { 775 HasRetpoline = true; 776 } else if (Feature == "+retpoline-external-thunk") { 777 HasRetpolineExternalThunk = true; 778 } else if (Feature == "+sahf") { 779 HasLAHFSAHF = true; 780 } 781 782 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 783 .Case("+avx512f", AVX512F) 784 .Case("+avx2", AVX2) 785 .Case("+avx", AVX) 786 .Case("+sse4.2", SSE42) 787 .Case("+sse4.1", SSE41) 788 .Case("+ssse3", SSSE3) 789 .Case("+sse3", SSE3) 790 .Case("+sse2", SSE2) 791 .Case("+sse", SSE1) 792 .Default(NoSSE); 793 SSELevel = std::max(SSELevel, Level); 794 795 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 796 .Case("+3dnowa", AMD3DNowAthlon) 797 .Case("+3dnow", AMD3DNow) 798 .Case("+mmx", MMX) 799 .Default(NoMMX3DNow); 800 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 801 802 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 803 .Case("+xop", XOP) 804 .Case("+fma4", FMA4) 805 .Case("+sse4a", SSE4A) 806 .Default(NoXOP); 807 XOPLevel = std::max(XOPLevel, XLevel); 808 } 809 810 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 811 // matches the selected sse level. 812 if ((FPMath == FP_SSE && SSELevel < SSE1) || 813 (FPMath == FP_387 && SSELevel >= SSE1)) { 814 Diags.Report(diag::err_target_unsupported_fpmath) 815 << (FPMath == FP_SSE ? "sse" : "387"); 816 return false; 817 } 818 819 SimdDefaultAlign = 820 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 821 return true; 822 } 823 824 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 825 /// definitions for this particular subtarget. 826 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 827 MacroBuilder &Builder) const { 828 // Target identification. 829 if (getTriple().getArch() == llvm::Triple::x86_64) { 830 Builder.defineMacro("__amd64__"); 831 Builder.defineMacro("__amd64"); 832 Builder.defineMacro("__x86_64"); 833 Builder.defineMacro("__x86_64__"); 834 if (getTriple().getArchName() == "x86_64h") { 835 Builder.defineMacro("__x86_64h"); 836 Builder.defineMacro("__x86_64h__"); 837 } 838 } else { 839 DefineStd(Builder, "i386", Opts); 840 } 841 842 // Subtarget options. 843 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 844 // truly should be based on -mtune options. 845 switch (CPU) { 846 case CK_Generic: 847 break; 848 case CK_i386: 849 // The rest are coming from the i386 define above. 850 Builder.defineMacro("__tune_i386__"); 851 break; 852 case CK_i486: 853 case CK_WinChipC6: 854 case CK_WinChip2: 855 case CK_C3: 856 defineCPUMacros(Builder, "i486"); 857 break; 858 case CK_PentiumMMX: 859 Builder.defineMacro("__pentium_mmx__"); 860 Builder.defineMacro("__tune_pentium_mmx__"); 861 LLVM_FALLTHROUGH; 862 case CK_i586: 863 case CK_Pentium: 864 defineCPUMacros(Builder, "i586"); 865 defineCPUMacros(Builder, "pentium"); 866 break; 867 case CK_Pentium3: 868 case CK_PentiumM: 869 Builder.defineMacro("__tune_pentium3__"); 870 LLVM_FALLTHROUGH; 871 case CK_Pentium2: 872 case CK_C3_2: 873 Builder.defineMacro("__tune_pentium2__"); 874 LLVM_FALLTHROUGH; 875 case CK_PentiumPro: 876 defineCPUMacros(Builder, "i686"); 877 defineCPUMacros(Builder, "pentiumpro"); 878 break; 879 case CK_Pentium4: 880 defineCPUMacros(Builder, "pentium4"); 881 break; 882 case CK_Yonah: 883 case CK_Prescott: 884 case CK_Nocona: 885 defineCPUMacros(Builder, "nocona"); 886 break; 887 case CK_Core2: 888 case CK_Penryn: 889 defineCPUMacros(Builder, "core2"); 890 break; 891 case CK_Bonnell: 892 defineCPUMacros(Builder, "atom"); 893 break; 894 case CK_Silvermont: 895 defineCPUMacros(Builder, "slm"); 896 break; 897 case CK_Goldmont: 898 defineCPUMacros(Builder, "goldmont"); 899 break; 900 case CK_Nehalem: 901 case CK_Westmere: 902 case CK_SandyBridge: 903 case CK_IvyBridge: 904 case CK_Haswell: 905 case CK_Broadwell: 906 case CK_SkylakeClient: 907 case CK_SkylakeServer: 908 case CK_Cannonlake: 909 case CK_Icelake: 910 // FIXME: Historically, we defined this legacy name, it would be nice to 911 // remove it at some point. We've never exposed fine-grained names for 912 // recent primary x86 CPUs, and we should keep it that way. 913 defineCPUMacros(Builder, "corei7"); 914 break; 915 case CK_KNL: 916 defineCPUMacros(Builder, "knl"); 917 break; 918 case CK_KNM: 919 break; 920 case CK_Lakemont: 921 defineCPUMacros(Builder, "i586", /*Tuning*/false); 922 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 923 Builder.defineMacro("__tune_lakemont__"); 924 break; 925 case CK_K6_2: 926 Builder.defineMacro("__k6_2__"); 927 Builder.defineMacro("__tune_k6_2__"); 928 LLVM_FALLTHROUGH; 929 case CK_K6_3: 930 if (CPU != CK_K6_2) { // In case of fallthrough 931 // FIXME: GCC may be enabling these in cases where some other k6 932 // architecture is specified but -m3dnow is explicitly provided. The 933 // exact semantics need to be determined and emulated here. 934 Builder.defineMacro("__k6_3__"); 935 Builder.defineMacro("__tune_k6_3__"); 936 } 937 LLVM_FALLTHROUGH; 938 case CK_K6: 939 defineCPUMacros(Builder, "k6"); 940 break; 941 case CK_Athlon: 942 case CK_AthlonXP: 943 defineCPUMacros(Builder, "athlon"); 944 if (SSELevel != NoSSE) { 945 Builder.defineMacro("__athlon_sse__"); 946 Builder.defineMacro("__tune_athlon_sse__"); 947 } 948 break; 949 case CK_K8: 950 case CK_K8SSE3: 951 case CK_x86_64: 952 defineCPUMacros(Builder, "k8"); 953 break; 954 case CK_AMDFAM10: 955 defineCPUMacros(Builder, "amdfam10"); 956 break; 957 case CK_BTVER1: 958 defineCPUMacros(Builder, "btver1"); 959 break; 960 case CK_BTVER2: 961 defineCPUMacros(Builder, "btver2"); 962 break; 963 case CK_BDVER1: 964 defineCPUMacros(Builder, "bdver1"); 965 break; 966 case CK_BDVER2: 967 defineCPUMacros(Builder, "bdver2"); 968 break; 969 case CK_BDVER3: 970 defineCPUMacros(Builder, "bdver3"); 971 break; 972 case CK_BDVER4: 973 defineCPUMacros(Builder, "bdver4"); 974 break; 975 case CK_ZNVER1: 976 defineCPUMacros(Builder, "znver1"); 977 break; 978 case CK_Geode: 979 defineCPUMacros(Builder, "geode"); 980 break; 981 } 982 983 // Target properties. 984 Builder.defineMacro("__REGISTER_PREFIX__", ""); 985 986 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 987 // functions in glibc header files that use FP Stack inline asm which the 988 // backend can't deal with (PR879). 989 Builder.defineMacro("__NO_MATH_INLINES"); 990 991 if (HasAES) 992 Builder.defineMacro("__AES__"); 993 994 if (HasVAES) 995 Builder.defineMacro("__VAES__"); 996 997 if (HasPCLMUL) 998 Builder.defineMacro("__PCLMUL__"); 999 1000 if (HasVPCLMULQDQ) 1001 Builder.defineMacro("__VPCLMULQDQ__"); 1002 1003 if (HasLZCNT) 1004 Builder.defineMacro("__LZCNT__"); 1005 1006 if (HasRDRND) 1007 Builder.defineMacro("__RDRND__"); 1008 1009 if (HasFSGSBASE) 1010 Builder.defineMacro("__FSGSBASE__"); 1011 1012 if (HasBMI) 1013 Builder.defineMacro("__BMI__"); 1014 1015 if (HasBMI2) 1016 Builder.defineMacro("__BMI2__"); 1017 1018 if (HasPOPCNT) 1019 Builder.defineMacro("__POPCNT__"); 1020 1021 if (HasRTM) 1022 Builder.defineMacro("__RTM__"); 1023 1024 if (HasPRFCHW) 1025 Builder.defineMacro("__PRFCHW__"); 1026 1027 if (HasRDSEED) 1028 Builder.defineMacro("__RDSEED__"); 1029 1030 if (HasADX) 1031 Builder.defineMacro("__ADX__"); 1032 1033 if (HasTBM) 1034 Builder.defineMacro("__TBM__"); 1035 1036 if (HasLWP) 1037 Builder.defineMacro("__LWP__"); 1038 1039 if (HasMWAITX) 1040 Builder.defineMacro("__MWAITX__"); 1041 1042 switch (XOPLevel) { 1043 case XOP: 1044 Builder.defineMacro("__XOP__"); 1045 LLVM_FALLTHROUGH; 1046 case FMA4: 1047 Builder.defineMacro("__FMA4__"); 1048 LLVM_FALLTHROUGH; 1049 case SSE4A: 1050 Builder.defineMacro("__SSE4A__"); 1051 LLVM_FALLTHROUGH; 1052 case NoXOP: 1053 break; 1054 } 1055 1056 if (HasFMA) 1057 Builder.defineMacro("__FMA__"); 1058 1059 if (HasF16C) 1060 Builder.defineMacro("__F16C__"); 1061 1062 if (HasGFNI) 1063 Builder.defineMacro("__GFNI__"); 1064 1065 if (HasAVX512CD) 1066 Builder.defineMacro("__AVX512CD__"); 1067 if (HasAVX512VPOPCNTDQ) 1068 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 1069 if (HasAVX512VNNI) 1070 Builder.defineMacro("__AVX512VNNI__"); 1071 if (HasAVX512ER) 1072 Builder.defineMacro("__AVX512ER__"); 1073 if (HasAVX512PF) 1074 Builder.defineMacro("__AVX512PF__"); 1075 if (HasAVX512DQ) 1076 Builder.defineMacro("__AVX512DQ__"); 1077 if (HasAVX512BITALG) 1078 Builder.defineMacro("__AVX512BITALG__"); 1079 if (HasAVX512BW) 1080 Builder.defineMacro("__AVX512BW__"); 1081 if (HasAVX512VL) 1082 Builder.defineMacro("__AVX512VL__"); 1083 if (HasAVX512VBMI) 1084 Builder.defineMacro("__AVX512VBMI__"); 1085 if (HasAVX512VBMI2) 1086 Builder.defineMacro("__AVX512VBMI2__"); 1087 if (HasAVX512IFMA) 1088 Builder.defineMacro("__AVX512IFMA__"); 1089 1090 if (HasSHA) 1091 Builder.defineMacro("__SHA__"); 1092 1093 if (HasFXSR) 1094 Builder.defineMacro("__FXSR__"); 1095 if (HasXSAVE) 1096 Builder.defineMacro("__XSAVE__"); 1097 if (HasXSAVEOPT) 1098 Builder.defineMacro("__XSAVEOPT__"); 1099 if (HasXSAVEC) 1100 Builder.defineMacro("__XSAVEC__"); 1101 if (HasXSAVES) 1102 Builder.defineMacro("__XSAVES__"); 1103 if (HasPKU) 1104 Builder.defineMacro("__PKU__"); 1105 if (HasCX16) 1106 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1107 if (HasCLFLUSHOPT) 1108 Builder.defineMacro("__CLFLUSHOPT__"); 1109 if (HasCLWB) 1110 Builder.defineMacro("__CLWB__"); 1111 if (HasMPX) 1112 Builder.defineMacro("__MPX__"); 1113 if (HasSHSTK) 1114 Builder.defineMacro("__SHSTK__"); 1115 if (HasSGX) 1116 Builder.defineMacro("__SGX__"); 1117 if (HasPREFETCHWT1) 1118 Builder.defineMacro("__PREFETCHWT1__"); 1119 if (HasCLZERO) 1120 Builder.defineMacro("__CLZERO__"); 1121 1122 // Each case falls through to the previous one here. 1123 switch (SSELevel) { 1124 case AVX512F: 1125 Builder.defineMacro("__AVX512F__"); 1126 LLVM_FALLTHROUGH; 1127 case AVX2: 1128 Builder.defineMacro("__AVX2__"); 1129 LLVM_FALLTHROUGH; 1130 case AVX: 1131 Builder.defineMacro("__AVX__"); 1132 LLVM_FALLTHROUGH; 1133 case SSE42: 1134 Builder.defineMacro("__SSE4_2__"); 1135 LLVM_FALLTHROUGH; 1136 case SSE41: 1137 Builder.defineMacro("__SSE4_1__"); 1138 LLVM_FALLTHROUGH; 1139 case SSSE3: 1140 Builder.defineMacro("__SSSE3__"); 1141 LLVM_FALLTHROUGH; 1142 case SSE3: 1143 Builder.defineMacro("__SSE3__"); 1144 LLVM_FALLTHROUGH; 1145 case SSE2: 1146 Builder.defineMacro("__SSE2__"); 1147 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1148 LLVM_FALLTHROUGH; 1149 case SSE1: 1150 Builder.defineMacro("__SSE__"); 1151 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1152 LLVM_FALLTHROUGH; 1153 case NoSSE: 1154 break; 1155 } 1156 1157 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1158 switch (SSELevel) { 1159 case AVX512F: 1160 case AVX2: 1161 case AVX: 1162 case SSE42: 1163 case SSE41: 1164 case SSSE3: 1165 case SSE3: 1166 case SSE2: 1167 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1168 break; 1169 case SSE1: 1170 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1171 break; 1172 default: 1173 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1174 break; 1175 } 1176 } 1177 1178 // Each case falls through to the previous one here. 1179 switch (MMX3DNowLevel) { 1180 case AMD3DNowAthlon: 1181 Builder.defineMacro("__3dNOW_A__"); 1182 LLVM_FALLTHROUGH; 1183 case AMD3DNow: 1184 Builder.defineMacro("__3dNOW__"); 1185 LLVM_FALLTHROUGH; 1186 case MMX: 1187 Builder.defineMacro("__MMX__"); 1188 LLVM_FALLTHROUGH; 1189 case NoMMX3DNow: 1190 break; 1191 } 1192 1193 if (CPU >= CK_i486) { 1194 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1195 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1196 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1197 } 1198 if (CPU >= CK_i586) 1199 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1200 1201 if (HasFloat128) 1202 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1203 } 1204 1205 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1206 return llvm::StringSwitch<bool>(Name) 1207 .Case("3dnow", true) 1208 .Case("3dnowa", true) 1209 .Case("adx", true) 1210 .Case("aes", true) 1211 .Case("avx", true) 1212 .Case("avx2", true) 1213 .Case("avx512f", true) 1214 .Case("avx512cd", true) 1215 .Case("avx512vpopcntdq", true) 1216 .Case("avx512vnni", true) 1217 .Case("avx512er", true) 1218 .Case("avx512pf", true) 1219 .Case("avx512dq", true) 1220 .Case("avx512bitalg", true) 1221 .Case("avx512bw", true) 1222 .Case("avx512vl", true) 1223 .Case("avx512vbmi", true) 1224 .Case("avx512vbmi2", true) 1225 .Case("avx512ifma", true) 1226 .Case("bmi", true) 1227 .Case("bmi2", true) 1228 .Case("clflushopt", true) 1229 .Case("clwb", true) 1230 .Case("clzero", true) 1231 .Case("cx16", true) 1232 .Case("f16c", true) 1233 .Case("fma", true) 1234 .Case("fma4", true) 1235 .Case("fsgsbase", true) 1236 .Case("fxsr", true) 1237 .Case("gfni", true) 1238 .Case("lwp", true) 1239 .Case("lzcnt", true) 1240 .Case("mmx", true) 1241 .Case("movbe", true) 1242 .Case("mpx", true) 1243 .Case("mwaitx", true) 1244 .Case("pclmul", true) 1245 .Case("pku", true) 1246 .Case("popcnt", true) 1247 .Case("prefetchwt1", true) 1248 .Case("prfchw", true) 1249 .Case("rdrnd", true) 1250 .Case("rdseed", true) 1251 .Case("rtm", true) 1252 .Case("sahf", true) 1253 .Case("sgx", true) 1254 .Case("sha", true) 1255 .Case("shstk", true) 1256 .Case("sse", true) 1257 .Case("sse2", true) 1258 .Case("sse3", true) 1259 .Case("ssse3", true) 1260 .Case("sse4", true) 1261 .Case("sse4.1", true) 1262 .Case("sse4.2", true) 1263 .Case("sse4a", true) 1264 .Case("tbm", true) 1265 .Case("vaes", true) 1266 .Case("vpclmulqdq", true) 1267 .Case("x87", true) 1268 .Case("xop", true) 1269 .Case("xsave", true) 1270 .Case("xsavec", true) 1271 .Case("xsaves", true) 1272 .Case("xsaveopt", true) 1273 .Default(false); 1274 } 1275 1276 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1277 return llvm::StringSwitch<bool>(Feature) 1278 .Case("adx", HasADX) 1279 .Case("aes", HasAES) 1280 .Case("avx", SSELevel >= AVX) 1281 .Case("avx2", SSELevel >= AVX2) 1282 .Case("avx512f", SSELevel >= AVX512F) 1283 .Case("avx512cd", HasAVX512CD) 1284 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1285 .Case("avx512vnni", HasAVX512VNNI) 1286 .Case("avx512er", HasAVX512ER) 1287 .Case("avx512pf", HasAVX512PF) 1288 .Case("avx512dq", HasAVX512DQ) 1289 .Case("avx512bitalg", HasAVX512BITALG) 1290 .Case("avx512bw", HasAVX512BW) 1291 .Case("avx512vl", HasAVX512VL) 1292 .Case("avx512vbmi", HasAVX512VBMI) 1293 .Case("avx512vbmi2", HasAVX512VBMI2) 1294 .Case("avx512ifma", HasAVX512IFMA) 1295 .Case("bmi", HasBMI) 1296 .Case("bmi2", HasBMI2) 1297 .Case("clflushopt", HasCLFLUSHOPT) 1298 .Case("clwb", HasCLWB) 1299 .Case("clzero", HasCLZERO) 1300 .Case("cx16", HasCX16) 1301 .Case("f16c", HasF16C) 1302 .Case("fma", HasFMA) 1303 .Case("fma4", XOPLevel >= FMA4) 1304 .Case("fsgsbase", HasFSGSBASE) 1305 .Case("fxsr", HasFXSR) 1306 .Case("gfni", HasGFNI) 1307 .Case("ibt", HasIBT) 1308 .Case("lwp", HasLWP) 1309 .Case("lzcnt", HasLZCNT) 1310 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1311 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1312 .Case("mmx", MMX3DNowLevel >= MMX) 1313 .Case("movbe", HasMOVBE) 1314 .Case("mpx", HasMPX) 1315 .Case("mwaitx", HasMWAITX) 1316 .Case("pclmul", HasPCLMUL) 1317 .Case("pku", HasPKU) 1318 .Case("popcnt", HasPOPCNT) 1319 .Case("prefetchwt1", HasPREFETCHWT1) 1320 .Case("prfchw", HasPRFCHW) 1321 .Case("rdrnd", HasRDRND) 1322 .Case("rdseed", HasRDSEED) 1323 .Case("retpoline", HasRetpoline) 1324 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1325 .Case("rtm", HasRTM) 1326 .Case("sahf", HasLAHFSAHF) 1327 .Case("sgx", HasSGX) 1328 .Case("sha", HasSHA) 1329 .Case("shstk", HasSHSTK) 1330 .Case("sse", SSELevel >= SSE1) 1331 .Case("sse2", SSELevel >= SSE2) 1332 .Case("sse3", SSELevel >= SSE3) 1333 .Case("ssse3", SSELevel >= SSSE3) 1334 .Case("sse4.1", SSELevel >= SSE41) 1335 .Case("sse4.2", SSELevel >= SSE42) 1336 .Case("sse4a", XOPLevel >= SSE4A) 1337 .Case("tbm", HasTBM) 1338 .Case("vaes", HasVAES) 1339 .Case("vpclmulqdq", HasVPCLMULQDQ) 1340 .Case("x86", true) 1341 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1342 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1343 .Case("xop", XOPLevel >= XOP) 1344 .Case("xsave", HasXSAVE) 1345 .Case("xsavec", HasXSAVEC) 1346 .Case("xsaves", HasXSAVES) 1347 .Case("xsaveopt", HasXSAVEOPT) 1348 .Default(false); 1349 } 1350 1351 // We can't use a generic validation scheme for the features accepted here 1352 // versus subtarget features accepted in the target attribute because the 1353 // bitfield structure that's initialized in the runtime only supports the 1354 // below currently rather than the full range of subtarget features. (See 1355 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1356 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1357 return llvm::StringSwitch<bool>(FeatureStr) 1358 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) 1359 #include "llvm/Support/X86TargetParser.def" 1360 .Default(false); 1361 } 1362 1363 // We can't use a generic validation scheme for the cpus accepted here 1364 // versus subtarget cpus accepted in the target attribute because the 1365 // variables intitialized by the runtime only support the below currently 1366 // rather than the full range of cpus. 1367 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1368 return llvm::StringSwitch<bool>(FeatureStr) 1369 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1370 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ 1371 .Cases(STR, ALIAS, true) 1372 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1373 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) 1374 #include "llvm/Support/X86TargetParser.def" 1375 .Default(false); 1376 } 1377 1378 bool X86TargetInfo::validateAsmConstraint( 1379 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1380 switch (*Name) { 1381 default: 1382 return false; 1383 // Constant constraints. 1384 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1385 // instructions. 1386 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1387 // x86_64 instructions. 1388 case 's': 1389 Info.setRequiresImmediate(); 1390 return true; 1391 case 'I': 1392 Info.setRequiresImmediate(0, 31); 1393 return true; 1394 case 'J': 1395 Info.setRequiresImmediate(0, 63); 1396 return true; 1397 case 'K': 1398 Info.setRequiresImmediate(-128, 127); 1399 return true; 1400 case 'L': 1401 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1402 return true; 1403 case 'M': 1404 Info.setRequiresImmediate(0, 3); 1405 return true; 1406 case 'N': 1407 Info.setRequiresImmediate(0, 255); 1408 return true; 1409 case 'O': 1410 Info.setRequiresImmediate(0, 127); 1411 return true; 1412 // Register constraints. 1413 case 'Y': // 'Y' is the first character for several 2-character constraints. 1414 // Shift the pointer to the second character of the constraint. 1415 Name++; 1416 switch (*Name) { 1417 default: 1418 return false; 1419 case 'z': 1420 case '0': // First SSE register. 1421 case '2': 1422 case 't': // Any SSE register, when SSE2 is enabled. 1423 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1424 case 'm': // Any MMX register, when inter-unit moves enabled. 1425 case 'k': // AVX512 arch mask registers: k1-k7. 1426 Info.setAllowsRegister(); 1427 return true; 1428 } 1429 case 'f': // Any x87 floating point stack register. 1430 // Constraint 'f' cannot be used for output operands. 1431 if (Info.ConstraintStr[0] == '=') 1432 return false; 1433 Info.setAllowsRegister(); 1434 return true; 1435 case 'a': // eax. 1436 case 'b': // ebx. 1437 case 'c': // ecx. 1438 case 'd': // edx. 1439 case 'S': // esi. 1440 case 'D': // edi. 1441 case 'A': // edx:eax. 1442 case 't': // Top of floating point stack. 1443 case 'u': // Second from top of floating point stack. 1444 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1445 case 'y': // Any MMX register. 1446 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1447 case 'x': // Any SSE register. 1448 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 1449 // for intermideate k reg operations). 1450 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1451 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1452 case 'l': // "Index" registers: any general register that can be used as an 1453 // index in a base+index memory access. 1454 Info.setAllowsRegister(); 1455 return true; 1456 // Floating point constant constraints. 1457 case 'C': // SSE floating point constant. 1458 case 'G': // x87 floating point constant. 1459 return true; 1460 } 1461 } 1462 1463 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 1464 unsigned Size) const { 1465 // Strip off constraint modifiers. 1466 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1467 Constraint = Constraint.substr(1); 1468 1469 return validateOperandSize(Constraint, Size); 1470 } 1471 1472 bool X86TargetInfo::validateInputSize(StringRef Constraint, 1473 unsigned Size) const { 1474 return validateOperandSize(Constraint, Size); 1475 } 1476 1477 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 1478 unsigned Size) const { 1479 switch (Constraint[0]) { 1480 default: 1481 break; 1482 case 'k': 1483 // Registers k0-k7 (AVX512) size limit is 64 bit. 1484 case 'y': 1485 return Size <= 64; 1486 case 'f': 1487 case 't': 1488 case 'u': 1489 return Size <= 128; 1490 case 'Y': 1491 // 'Y' is the first character for several 2-character constraints. 1492 switch (Constraint[1]) { 1493 default: 1494 return false; 1495 case 'm': 1496 // 'Ym' is synonymous with 'y'. 1497 case 'k': 1498 return Size <= 64; 1499 case 'z': 1500 case '0': 1501 // XMM0 1502 if (SSELevel >= SSE1) 1503 return Size <= 128U; 1504 return false; 1505 case 'i': 1506 case 't': 1507 case '2': 1508 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1509 if (SSELevel < SSE2) 1510 return false; 1511 break; 1512 } 1513 case 'v': 1514 case 'x': 1515 if (SSELevel >= AVX512F) 1516 // 512-bit zmm registers can be used if target supports AVX512F. 1517 return Size <= 512U; 1518 else if (SSELevel >= AVX) 1519 // 256-bit ymm registers can be used if target supports AVX. 1520 return Size <= 256U; 1521 return Size <= 128U; 1522 1523 } 1524 1525 return true; 1526 } 1527 1528 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1529 switch (*Constraint) { 1530 case 'a': 1531 return std::string("{ax}"); 1532 case 'b': 1533 return std::string("{bx}"); 1534 case 'c': 1535 return std::string("{cx}"); 1536 case 'd': 1537 return std::string("{dx}"); 1538 case 'S': 1539 return std::string("{si}"); 1540 case 'D': 1541 return std::string("{di}"); 1542 case 'p': // address 1543 return std::string("im"); 1544 case 't': // top of floating point stack. 1545 return std::string("{st}"); 1546 case 'u': // second from top of floating point stack. 1547 return std::string("{st(1)}"); // second from top of floating point stack. 1548 case 'Y': 1549 switch (Constraint[1]) { 1550 default: 1551 // Break from inner switch and fall through (copy single char), 1552 // continue parsing after copying the current constraint into 1553 // the return string. 1554 break; 1555 case 'k': 1556 case 'm': 1557 case 'i': 1558 case 't': 1559 case 'z': 1560 case '0': 1561 case '2': 1562 // "^" hints llvm that this is a 2 letter constraint. 1563 // "Constraint++" is used to promote the string iterator 1564 // to the next constraint. 1565 return std::string("^") + std::string(Constraint++, 2); 1566 } 1567 LLVM_FALLTHROUGH; 1568 default: 1569 return std::string(1, *Constraint); 1570 } 1571 } 1572 1573 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { 1574 // Perform any per-CPU checks necessary to determine if this CPU is 1575 // acceptable. 1576 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1577 // invalid without explaining *why*. 1578 switch (Kind) { 1579 case CK_Generic: 1580 // No processor selected! 1581 return false; 1582 #define PROC(ENUM, STRING, IS64BIT) \ 1583 case CK_##ENUM: \ 1584 return IS64BIT || getTriple().getArch() == llvm::Triple::x86; 1585 #include "clang/Basic/X86Target.def" 1586 } 1587 llvm_unreachable("Unhandled CPU kind"); 1588 } 1589 1590 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { 1591 return llvm::StringSwitch<CPUKind>(CPU) 1592 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) 1593 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) 1594 #include "clang/Basic/X86Target.def" 1595 .Default(CK_Generic); 1596 } 1597 1598 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1599 return llvm::makeArrayRef(GCCRegNames); 1600 } 1601 1602 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1603 return llvm::makeArrayRef(AddlRegNames); 1604 } 1605 1606 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1607 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1608 Builtin::FirstTSBuiltin + 1); 1609 } 1610 1611 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1612 return llvm::makeArrayRef(BuiltinInfoX86, 1613 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1614 } 1615