1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 // Ananas target 115 template<typename Target> 116 class AnanasTargetInfo : public OSTargetInfo<Target> { 117 protected: 118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 119 MacroBuilder &Builder) const override { 120 // Ananas defines 121 Builder.defineMacro("__Ananas__"); 122 Builder.defineMacro("__ELF__"); 123 } 124 public: 125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 126 : OSTargetInfo<Target>(Triple, Opts) {} 127 }; 128 129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 130 const llvm::Triple &Triple, 131 StringRef &PlatformName, 132 VersionTuple &PlatformMinVersion) { 133 Builder.defineMacro("__APPLE_CC__", "6000"); 134 Builder.defineMacro("__APPLE__"); 135 Builder.defineMacro("__STDC_NO_THREADS__"); 136 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 137 // AddressSanitizer doesn't play well with source fortification, which is on 138 // by default on Darwin. 139 if (Opts.Sanitize.has(SanitizerKind::Address)) 140 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 141 142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 143 if (!Opts.ObjC1) { 144 // __weak is always defined, for use in blocks and with objc pointers. 145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 146 Builder.defineMacro("__strong", ""); 147 Builder.defineMacro("__unsafe_unretained", ""); 148 } 149 150 if (Opts.Static) 151 Builder.defineMacro("__STATIC__"); 152 else 153 Builder.defineMacro("__DYNAMIC__"); 154 155 if (Opts.POSIXThreads) 156 Builder.defineMacro("_REENTRANT"); 157 158 // Get the platform type and version number from the triple. 159 unsigned Maj, Min, Rev; 160 if (Triple.isMacOSX()) { 161 Triple.getMacOSXVersion(Maj, Min, Rev); 162 PlatformName = "macos"; 163 } else { 164 Triple.getOSVersion(Maj, Min, Rev); 165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 166 } 167 168 // If -target arch-pc-win32-macho option specified, we're 169 // generating code for Win32 ABI. No need to emit 170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 171 if (PlatformName == "win32") { 172 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 173 return; 174 } 175 176 // Set the appropriate OS version define. 177 if (Triple.isiOS()) { 178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 179 char Str[7]; 180 if (Maj < 10) { 181 Str[0] = '0' + Maj; 182 Str[1] = '0' + (Min / 10); 183 Str[2] = '0' + (Min % 10); 184 Str[3] = '0' + (Rev / 10); 185 Str[4] = '0' + (Rev % 10); 186 Str[5] = '\0'; 187 } else { 188 // Handle versions >= 10. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 if (Triple.isTvOS()) 198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 199 else 200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 201 Str); 202 203 } else if (Triple.isWatchOS()) { 204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 205 char Str[6]; 206 Str[0] = '0' + Maj; 207 Str[1] = '0' + (Min / 10); 208 Str[2] = '0' + (Min % 10); 209 Str[3] = '0' + (Rev / 10); 210 Str[4] = '0' + (Rev % 10); 211 Str[5] = '\0'; 212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 213 } else if (Triple.isMacOSX()) { 214 // Note that the Driver allows versions which aren't representable in the 215 // define (because we only get a single digit for the minor and micro 216 // revision numbers). So, we limit them to the maximum representable 217 // version. 218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 219 char Str[7]; 220 if (Maj < 10 || (Maj == 10 && Min < 10)) { 221 Str[0] = '0' + (Maj / 10); 222 Str[1] = '0' + (Maj % 10); 223 Str[2] = '0' + std::min(Min, 9U); 224 Str[3] = '0' + std::min(Rev, 9U); 225 Str[4] = '\0'; 226 } else { 227 // Handle versions > 10.9. 228 Str[0] = '0' + (Maj / 10); 229 Str[1] = '0' + (Maj % 10); 230 Str[2] = '0' + (Min / 10); 231 Str[3] = '0' + (Min % 10); 232 Str[4] = '0' + (Rev / 10); 233 Str[5] = '0' + (Rev % 10); 234 Str[6] = '\0'; 235 } 236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 237 } 238 239 // Tell users about the kernel if there is one. 240 if (Triple.isOSDarwin()) 241 Builder.defineMacro("__MACH__"); 242 243 // The Watch ABI uses Dwarf EH. 244 if(Triple.isWatchABI()) 245 Builder.defineMacro("__ARM_DWARF_EH__"); 246 247 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 248 } 249 250 template<typename Target> 251 class DarwinTargetInfo : public OSTargetInfo<Target> { 252 protected: 253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 254 MacroBuilder &Builder) const override { 255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 256 this->PlatformMinVersion); 257 } 258 259 public: 260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 261 : OSTargetInfo<Target>(Triple, Opts) { 262 // By default, no TLS, and we whitelist permitted architecture/OS 263 // combinations. 264 this->TLSSupported = false; 265 266 if (Triple.isMacOSX()) 267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 268 else if (Triple.isiOS()) { 269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 270 if (Triple.getArch() == llvm::Triple::x86_64 || 271 Triple.getArch() == llvm::Triple::aarch64) 272 this->TLSSupported = !Triple.isOSVersionLT(8); 273 else if (Triple.getArch() == llvm::Triple::x86 || 274 Triple.getArch() == llvm::Triple::arm || 275 Triple.getArch() == llvm::Triple::thumb) 276 this->TLSSupported = !Triple.isOSVersionLT(9); 277 } else if (Triple.isWatchOS()) 278 this->TLSSupported = !Triple.isOSVersionLT(2); 279 280 this->MCountName = "\01mcount"; 281 } 282 283 std::string isValidSectionSpecifier(StringRef SR) const override { 284 // Let MCSectionMachO validate this. 285 StringRef Segment, Section; 286 unsigned TAA, StubSize; 287 bool HasTAA; 288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 289 TAA, HasTAA, StubSize); 290 } 291 292 const char *getStaticInitSectionSpecifier() const override { 293 // FIXME: We should return 0 when building kexts. 294 return "__TEXT,__StaticInit,regular,pure_instructions"; 295 } 296 297 /// Darwin does not support protected visibility. Darwin's "default" 298 /// is very similar to ELF's "protected"; Darwin requires a "weak" 299 /// attribute on declarations that can be dynamically replaced. 300 bool hasProtectedVisibility() const override { 301 return false; 302 } 303 304 unsigned getExnObjectAlignment() const override { 305 // The alignment of an exception object is 8-bytes for darwin since 306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 307 // and therefore doesn't guarantee 16-byte alignment. 308 return 64; 309 } 310 }; 311 312 313 // DragonFlyBSD Target 314 template<typename Target> 315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 316 protected: 317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 318 MacroBuilder &Builder) const override { 319 // DragonFly defines; list based off of gcc output 320 Builder.defineMacro("__DragonFly__"); 321 Builder.defineMacro("__DragonFly_cc_version", "100001"); 322 Builder.defineMacro("__ELF__"); 323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 324 Builder.defineMacro("__tune_i386__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 329 : OSTargetInfo<Target>(Triple, Opts) { 330 switch (Triple.getArch()) { 331 default: 332 case llvm::Triple::x86: 333 case llvm::Triple::x86_64: 334 this->MCountName = ".mcount"; 335 break; 336 } 337 } 338 }; 339 340 #ifndef FREEBSD_CC_VERSION 341 #define FREEBSD_CC_VERSION 0U 342 #endif 343 344 // FreeBSD Target 345 template<typename Target> 346 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 347 protected: 348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 349 MacroBuilder &Builder) const override { 350 // FreeBSD defines; list based off of gcc output 351 352 unsigned Release = Triple.getOSMajorVersion(); 353 if (Release == 0U) 354 Release = 8U; 355 unsigned CCVersion = FREEBSD_CC_VERSION; 356 if (CCVersion == 0U) 357 CCVersion = Release * 100000U + 1U; 358 359 Builder.defineMacro("__FreeBSD__", Twine(Release)); 360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 365 // On FreeBSD, wchar_t contains the number of the code point as 366 // used by the character set of the locale. These character sets are 367 // not necessarily a superset of ASCII. 368 // 369 // FIXME: This is wrong; the macro refers to the numerical values 370 // of wchar_t *literals*, which are not locale-dependent. However, 371 // FreeBSD systems apparently depend on us getting this wrong, and 372 // setting this to 1 is conforming even if all the basic source 373 // character literals have the same encoding as char and wchar_t. 374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 375 } 376 public: 377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 378 : OSTargetInfo<Target>(Triple, Opts) { 379 switch (Triple.getArch()) { 380 default: 381 case llvm::Triple::x86: 382 case llvm::Triple::x86_64: 383 this->MCountName = ".mcount"; 384 break; 385 case llvm::Triple::mips: 386 case llvm::Triple::mipsel: 387 case llvm::Triple::ppc: 388 case llvm::Triple::ppc64: 389 case llvm::Triple::ppc64le: 390 this->MCountName = "_mcount"; 391 break; 392 case llvm::Triple::arm: 393 this->MCountName = "__mcount"; 394 break; 395 } 396 } 397 }; 398 399 // GNU/kFreeBSD Target 400 template<typename Target> 401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 402 protected: 403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 404 MacroBuilder &Builder) const override { 405 // GNU/kFreeBSD defines; list based off of gcc output 406 407 DefineStd(Builder, "unix", Opts); 408 Builder.defineMacro("__FreeBSD_kernel__"); 409 Builder.defineMacro("__GLIBC__"); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 if (Opts.CPlusPlus) 414 Builder.defineMacro("_GNU_SOURCE"); 415 } 416 public: 417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) {} 419 }; 420 421 // Haiku Target 422 template<typename Target> 423 class HaikuTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Haiku defines; list based off of gcc output 428 Builder.defineMacro("__HAIKU__"); 429 Builder.defineMacro("__ELF__"); 430 DefineStd(Builder, "unix", Opts); 431 } 432 public: 433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 434 : OSTargetInfo<Target>(Triple, Opts) { 435 this->SizeType = TargetInfo::UnsignedLong; 436 this->IntPtrType = TargetInfo::SignedLong; 437 this->PtrDiffType = TargetInfo::SignedLong; 438 this->ProcessIDType = TargetInfo::SignedLong; 439 this->TLSSupported = false; 440 441 } 442 }; 443 444 // Minix Target 445 template<typename Target> 446 class MinixTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // Minix defines 451 452 Builder.defineMacro("__minix", "3"); 453 Builder.defineMacro("_EM_WSIZE", "4"); 454 Builder.defineMacro("_EM_PSIZE", "4"); 455 Builder.defineMacro("_EM_SSIZE", "2"); 456 Builder.defineMacro("_EM_LSIZE", "4"); 457 Builder.defineMacro("_EM_FSIZE", "4"); 458 Builder.defineMacro("_EM_DSIZE", "8"); 459 Builder.defineMacro("__ELF__"); 460 DefineStd(Builder, "unix", Opts); 461 } 462 public: 463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 464 : OSTargetInfo<Target>(Triple, Opts) {} 465 }; 466 467 // Linux target 468 template<typename Target> 469 class LinuxTargetInfo : public OSTargetInfo<Target> { 470 protected: 471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 472 MacroBuilder &Builder) const override { 473 // Linux defines; list based off of gcc output 474 DefineStd(Builder, "unix", Opts); 475 DefineStd(Builder, "linux", Opts); 476 Builder.defineMacro("__gnu_linux__"); 477 Builder.defineMacro("__ELF__"); 478 if (Triple.isAndroid()) { 479 Builder.defineMacro("__ANDROID__", "1"); 480 unsigned Maj, Min, Rev; 481 Triple.getEnvironmentVersion(Maj, Min, Rev); 482 this->PlatformName = "android"; 483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 484 if (Maj) 485 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 486 } 487 if (Opts.POSIXThreads) 488 Builder.defineMacro("_REENTRANT"); 489 if (Opts.CPlusPlus) 490 Builder.defineMacro("_GNU_SOURCE"); 491 if (this->HasFloat128) 492 Builder.defineMacro("__FLOAT128__"); 493 } 494 public: 495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 496 : OSTargetInfo<Target>(Triple, Opts) { 497 this->WIntType = TargetInfo::UnsignedInt; 498 499 switch (Triple.getArch()) { 500 default: 501 break; 502 case llvm::Triple::mips: 503 case llvm::Triple::mipsel: 504 case llvm::Triple::mips64: 505 case llvm::Triple::mips64el: 506 case llvm::Triple::ppc: 507 case llvm::Triple::ppc64: 508 case llvm::Triple::ppc64le: 509 this->MCountName = "_mcount"; 510 break; 511 case llvm::Triple::x86: 512 case llvm::Triple::x86_64: 513 case llvm::Triple::systemz: 514 this->HasFloat128 = true; 515 break; 516 } 517 } 518 519 const char *getStaticInitSectionSpecifier() const override { 520 return ".text.startup"; 521 } 522 }; 523 524 // NetBSD Target 525 template<typename Target> 526 class NetBSDTargetInfo : public OSTargetInfo<Target> { 527 protected: 528 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 529 MacroBuilder &Builder) const override { 530 // NetBSD defines; list based off of gcc output 531 Builder.defineMacro("__NetBSD__"); 532 Builder.defineMacro("__unix__"); 533 Builder.defineMacro("__ELF__"); 534 if (Opts.POSIXThreads) 535 Builder.defineMacro("_REENTRANT"); 536 537 switch (Triple.getArch()) { 538 default: 539 break; 540 case llvm::Triple::arm: 541 case llvm::Triple::armeb: 542 case llvm::Triple::thumb: 543 case llvm::Triple::thumbeb: 544 Builder.defineMacro("__ARM_DWARF_EH__"); 545 break; 546 } 547 } 548 public: 549 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 550 : OSTargetInfo<Target>(Triple, Opts) { 551 this->MCountName = "_mcount"; 552 } 553 }; 554 555 // OpenBSD Target 556 template<typename Target> 557 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 558 protected: 559 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 560 MacroBuilder &Builder) const override { 561 // OpenBSD defines; list based off of gcc output 562 563 Builder.defineMacro("__OpenBSD__"); 564 DefineStd(Builder, "unix", Opts); 565 Builder.defineMacro("__ELF__"); 566 if (Opts.POSIXThreads) 567 Builder.defineMacro("_REENTRANT"); 568 if (this->HasFloat128) 569 Builder.defineMacro("__FLOAT128__"); 570 } 571 public: 572 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 573 : OSTargetInfo<Target>(Triple, Opts) { 574 switch (Triple.getArch()) { 575 case llvm::Triple::x86: 576 case llvm::Triple::x86_64: 577 this->HasFloat128 = true; 578 // FALLTHROUGH 579 default: 580 this->MCountName = "__mcount"; 581 break; 582 case llvm::Triple::mips64: 583 case llvm::Triple::mips64el: 584 case llvm::Triple::ppc: 585 case llvm::Triple::sparcv9: 586 this->MCountName = "_mcount"; 587 break; 588 } 589 } 590 }; 591 592 // Bitrig Target 593 template<typename Target> 594 class BitrigTargetInfo : public OSTargetInfo<Target> { 595 protected: 596 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 597 MacroBuilder &Builder) const override { 598 // Bitrig defines; list based off of gcc output 599 600 Builder.defineMacro("__Bitrig__"); 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 if (Opts.POSIXThreads) 604 Builder.defineMacro("_REENTRANT"); 605 606 switch (Triple.getArch()) { 607 default: 608 break; 609 case llvm::Triple::arm: 610 case llvm::Triple::armeb: 611 case llvm::Triple::thumb: 612 case llvm::Triple::thumbeb: 613 Builder.defineMacro("__ARM_DWARF_EH__"); 614 break; 615 } 616 } 617 public: 618 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 619 : OSTargetInfo<Target>(Triple, Opts) { 620 this->MCountName = "__mcount"; 621 } 622 }; 623 624 // PSP Target 625 template<typename Target> 626 class PSPTargetInfo : public OSTargetInfo<Target> { 627 protected: 628 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 629 MacroBuilder &Builder) const override { 630 // PSP defines; list based on the output of the pspdev gcc toolchain. 631 Builder.defineMacro("PSP"); 632 Builder.defineMacro("_PSP"); 633 Builder.defineMacro("__psp__"); 634 Builder.defineMacro("__ELF__"); 635 } 636 public: 637 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 638 }; 639 640 // PS3 PPU Target 641 template<typename Target> 642 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 643 protected: 644 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 645 MacroBuilder &Builder) const override { 646 // PS3 PPU defines. 647 Builder.defineMacro("__PPC__"); 648 Builder.defineMacro("__PPU__"); 649 Builder.defineMacro("__CELLOS_LV2__"); 650 Builder.defineMacro("__ELF__"); 651 Builder.defineMacro("__LP32__"); 652 Builder.defineMacro("_ARCH_PPC64"); 653 Builder.defineMacro("__powerpc64__"); 654 } 655 public: 656 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 657 : OSTargetInfo<Target>(Triple, Opts) { 658 this->LongWidth = this->LongAlign = 32; 659 this->PointerWidth = this->PointerAlign = 32; 660 this->IntMaxType = TargetInfo::SignedLongLong; 661 this->Int64Type = TargetInfo::SignedLongLong; 662 this->SizeType = TargetInfo::UnsignedInt; 663 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 664 } 665 }; 666 667 template <typename Target> 668 class PS4OSTargetInfo : public OSTargetInfo<Target> { 669 protected: 670 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 671 MacroBuilder &Builder) const override { 672 Builder.defineMacro("__FreeBSD__", "9"); 673 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 674 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 675 DefineStd(Builder, "unix", Opts); 676 Builder.defineMacro("__ELF__"); 677 Builder.defineMacro("__ORBIS__"); 678 } 679 public: 680 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 681 : OSTargetInfo<Target>(Triple, Opts) { 682 this->WCharType = this->UnsignedShort; 683 684 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 685 this->MaxTLSAlign = 256; 686 687 // On PS4, do not honor explicit bit field alignment, 688 // as in "__attribute__((aligned(2))) int b : 1;". 689 this->UseExplicitBitFieldAlignment = false; 690 691 switch (Triple.getArch()) { 692 default: 693 case llvm::Triple::x86_64: 694 this->MCountName = ".mcount"; 695 break; 696 } 697 } 698 }; 699 700 // Solaris target 701 template<typename Target> 702 class SolarisTargetInfo : public OSTargetInfo<Target> { 703 protected: 704 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 705 MacroBuilder &Builder) const override { 706 DefineStd(Builder, "sun", Opts); 707 DefineStd(Builder, "unix", Opts); 708 Builder.defineMacro("__ELF__"); 709 Builder.defineMacro("__svr4__"); 710 Builder.defineMacro("__SVR4"); 711 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 712 // newer, but to 500 for everything else. feature_test.h has a check to 713 // ensure that you are not using C99 with an old version of X/Open or C89 714 // with a new version. 715 if (Opts.C99) 716 Builder.defineMacro("_XOPEN_SOURCE", "600"); 717 else 718 Builder.defineMacro("_XOPEN_SOURCE", "500"); 719 if (Opts.CPlusPlus) 720 Builder.defineMacro("__C99FEATURES__"); 721 Builder.defineMacro("_LARGEFILE_SOURCE"); 722 Builder.defineMacro("_LARGEFILE64_SOURCE"); 723 Builder.defineMacro("__EXTENSIONS__"); 724 Builder.defineMacro("_REENTRANT"); 725 } 726 public: 727 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 728 : OSTargetInfo<Target>(Triple, Opts) { 729 this->WCharType = this->SignedInt; 730 // FIXME: WIntType should be SignedLong 731 } 732 }; 733 734 // Windows target 735 template<typename Target> 736 class WindowsTargetInfo : public OSTargetInfo<Target> { 737 protected: 738 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 739 MacroBuilder &Builder) const override { 740 Builder.defineMacro("_WIN32"); 741 } 742 void getVisualStudioDefines(const LangOptions &Opts, 743 MacroBuilder &Builder) const { 744 if (Opts.CPlusPlus) { 745 if (Opts.RTTIData) 746 Builder.defineMacro("_CPPRTTI"); 747 748 if (Opts.CXXExceptions) 749 Builder.defineMacro("_CPPUNWIND"); 750 } 751 752 if (Opts.Bool) 753 Builder.defineMacro("__BOOL_DEFINED"); 754 755 if (!Opts.CharIsSigned) 756 Builder.defineMacro("_CHAR_UNSIGNED"); 757 758 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 759 // but it works for now. 760 if (Opts.POSIXThreads) 761 Builder.defineMacro("_MT"); 762 763 if (Opts.MSCompatibilityVersion) { 764 Builder.defineMacro("_MSC_VER", 765 Twine(Opts.MSCompatibilityVersion / 100000)); 766 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 767 // FIXME We cannot encode the revision information into 32-bits 768 Builder.defineMacro("_MSC_BUILD", Twine(1)); 769 770 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 771 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 772 773 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 774 if (Opts.CPlusPlus1z) 775 Builder.defineMacro("_MSVC_LANG", "201403L"); 776 else if (Opts.CPlusPlus14) 777 Builder.defineMacro("_MSVC_LANG", "201402L"); 778 } 779 } 780 781 if (Opts.MicrosoftExt) { 782 Builder.defineMacro("_MSC_EXTENSIONS"); 783 784 if (Opts.CPlusPlus11) { 785 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 786 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 787 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 788 } 789 } 790 791 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 792 } 793 794 public: 795 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 796 : OSTargetInfo<Target>(Triple, Opts) {} 797 }; 798 799 template <typename Target> 800 class NaClTargetInfo : public OSTargetInfo<Target> { 801 protected: 802 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 803 MacroBuilder &Builder) const override { 804 if (Opts.POSIXThreads) 805 Builder.defineMacro("_REENTRANT"); 806 if (Opts.CPlusPlus) 807 Builder.defineMacro("_GNU_SOURCE"); 808 809 DefineStd(Builder, "unix", Opts); 810 Builder.defineMacro("__ELF__"); 811 Builder.defineMacro("__native_client__"); 812 } 813 814 public: 815 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 816 : OSTargetInfo<Target>(Triple, Opts) { 817 this->LongAlign = 32; 818 this->LongWidth = 32; 819 this->PointerAlign = 32; 820 this->PointerWidth = 32; 821 this->IntMaxType = TargetInfo::SignedLongLong; 822 this->Int64Type = TargetInfo::SignedLongLong; 823 this->DoubleAlign = 64; 824 this->LongDoubleWidth = 64; 825 this->LongDoubleAlign = 64; 826 this->LongLongWidth = 64; 827 this->LongLongAlign = 64; 828 this->SizeType = TargetInfo::UnsignedInt; 829 this->PtrDiffType = TargetInfo::SignedInt; 830 this->IntPtrType = TargetInfo::SignedInt; 831 // RegParmMax is inherited from the underlying architecture. 832 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 833 if (Triple.getArch() == llvm::Triple::arm) { 834 // Handled in ARM's setABI(). 835 } else if (Triple.getArch() == llvm::Triple::x86) { 836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 837 } else if (Triple.getArch() == llvm::Triple::x86_64) { 838 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 839 } else if (Triple.getArch() == llvm::Triple::mipsel) { 840 // Handled on mips' setDataLayout. 841 } else { 842 assert(Triple.getArch() == llvm::Triple::le32); 843 this->resetDataLayout("e-p:32:32-i64:64"); 844 } 845 } 846 }; 847 848 // Fuchsia Target 849 template<typename Target> 850 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 851 protected: 852 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 853 MacroBuilder &Builder) const override { 854 Builder.defineMacro("__Fuchsia__"); 855 Builder.defineMacro("__ELF__"); 856 if (Opts.POSIXThreads) 857 Builder.defineMacro("_REENTRANT"); 858 // Required by the libc++ locale support. 859 if (Opts.CPlusPlus) 860 Builder.defineMacro("_GNU_SOURCE"); 861 } 862 public: 863 FuchsiaTargetInfo(const llvm::Triple &Triple, 864 const TargetOptions &Opts) 865 : OSTargetInfo<Target>(Triple, Opts) { 866 this->MCountName = "__mcount"; 867 } 868 }; 869 870 // WebAssembly target 871 template <typename Target> 872 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 873 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 874 MacroBuilder &Builder) const final { 875 // A common platform macro. 876 if (Opts.POSIXThreads) 877 Builder.defineMacro("_REENTRANT"); 878 // Follow g++ convention and predefine _GNU_SOURCE for C++. 879 if (Opts.CPlusPlus) 880 Builder.defineMacro("_GNU_SOURCE"); 881 } 882 883 // As an optimization, group static init code together in a section. 884 const char *getStaticInitSectionSpecifier() const final { 885 return ".text.__startup"; 886 } 887 888 public: 889 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 890 const TargetOptions &Opts) 891 : OSTargetInfo<Target>(Triple, Opts) { 892 this->MCountName = "__mcount"; 893 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 894 } 895 }; 896 897 //===----------------------------------------------------------------------===// 898 // Specific target implementations. 899 //===----------------------------------------------------------------------===// 900 901 // PPC abstract base class 902 class PPCTargetInfo : public TargetInfo { 903 static const Builtin::Info BuiltinInfo[]; 904 static const char * const GCCRegNames[]; 905 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 906 std::string CPU; 907 908 // Target cpu features. 909 bool HasAltivec; 910 bool HasVSX; 911 bool HasP8Vector; 912 bool HasP8Crypto; 913 bool HasDirectMove; 914 bool HasQPX; 915 bool HasHTM; 916 bool HasBPERMD; 917 bool HasExtDiv; 918 bool HasP9Vector; 919 920 protected: 921 std::string ABI; 922 923 public: 924 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 925 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 926 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 927 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 928 SuitableAlign = 128; 929 SimdDefaultAlign = 128; 930 LongDoubleWidth = LongDoubleAlign = 128; 931 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 932 } 933 934 /// \brief Flags for architecture specific defines. 935 typedef enum { 936 ArchDefineNone = 0, 937 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 938 ArchDefinePpcgr = 1 << 1, 939 ArchDefinePpcsq = 1 << 2, 940 ArchDefine440 = 1 << 3, 941 ArchDefine603 = 1 << 4, 942 ArchDefine604 = 1 << 5, 943 ArchDefinePwr4 = 1 << 6, 944 ArchDefinePwr5 = 1 << 7, 945 ArchDefinePwr5x = 1 << 8, 946 ArchDefinePwr6 = 1 << 9, 947 ArchDefinePwr6x = 1 << 10, 948 ArchDefinePwr7 = 1 << 11, 949 ArchDefinePwr8 = 1 << 12, 950 ArchDefinePwr9 = 1 << 13, 951 ArchDefineA2 = 1 << 14, 952 ArchDefineA2q = 1 << 15 953 } ArchDefineTypes; 954 955 // Set the language option for altivec based on our value. 956 void adjust(LangOptions &Opts) override { 957 if (HasAltivec) 958 Opts.AltiVec = 1; 959 TargetInfo::adjust(Opts); 960 } 961 962 // Note: GCC recognizes the following additional cpus: 963 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 964 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 965 // titan, rs64. 966 bool setCPU(const std::string &Name) override { 967 bool CPUKnown = llvm::StringSwitch<bool>(Name) 968 .Case("generic", true) 969 .Case("440", true) 970 .Case("450", true) 971 .Case("601", true) 972 .Case("602", true) 973 .Case("603", true) 974 .Case("603e", true) 975 .Case("603ev", true) 976 .Case("604", true) 977 .Case("604e", true) 978 .Case("620", true) 979 .Case("630", true) 980 .Case("g3", true) 981 .Case("7400", true) 982 .Case("g4", true) 983 .Case("7450", true) 984 .Case("g4+", true) 985 .Case("750", true) 986 .Case("970", true) 987 .Case("g5", true) 988 .Case("a2", true) 989 .Case("a2q", true) 990 .Case("e500mc", true) 991 .Case("e5500", true) 992 .Case("power3", true) 993 .Case("pwr3", true) 994 .Case("power4", true) 995 .Case("pwr4", true) 996 .Case("power5", true) 997 .Case("pwr5", true) 998 .Case("power5x", true) 999 .Case("pwr5x", true) 1000 .Case("power6", true) 1001 .Case("pwr6", true) 1002 .Case("power6x", true) 1003 .Case("pwr6x", true) 1004 .Case("power7", true) 1005 .Case("pwr7", true) 1006 .Case("power8", true) 1007 .Case("pwr8", true) 1008 .Case("power9", true) 1009 .Case("pwr9", true) 1010 .Case("powerpc", true) 1011 .Case("ppc", true) 1012 .Case("powerpc64", true) 1013 .Case("ppc64", true) 1014 .Case("powerpc64le", true) 1015 .Case("ppc64le", true) 1016 .Default(false); 1017 1018 if (CPUKnown) 1019 CPU = Name; 1020 1021 return CPUKnown; 1022 } 1023 1024 1025 StringRef getABI() const override { return ABI; } 1026 1027 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1028 return llvm::makeArrayRef(BuiltinInfo, 1029 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1030 } 1031 1032 bool isCLZForZeroUndef() const override { return false; } 1033 1034 void getTargetDefines(const LangOptions &Opts, 1035 MacroBuilder &Builder) const override; 1036 1037 bool 1038 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1039 StringRef CPU, 1040 const std::vector<std::string> &FeaturesVec) const override; 1041 1042 bool handleTargetFeatures(std::vector<std::string> &Features, 1043 DiagnosticsEngine &Diags) override; 1044 bool hasFeature(StringRef Feature) const override; 1045 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1046 bool Enabled) const override; 1047 1048 ArrayRef<const char *> getGCCRegNames() const override; 1049 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1050 bool validateAsmConstraint(const char *&Name, 1051 TargetInfo::ConstraintInfo &Info) const override { 1052 switch (*Name) { 1053 default: return false; 1054 case 'O': // Zero 1055 break; 1056 case 'b': // Base register 1057 case 'f': // Floating point register 1058 Info.setAllowsRegister(); 1059 break; 1060 // FIXME: The following are added to allow parsing. 1061 // I just took a guess at what the actions should be. 1062 // Also, is more specific checking needed? I.e. specific registers? 1063 case 'd': // Floating point register (containing 64-bit value) 1064 case 'v': // Altivec vector register 1065 Info.setAllowsRegister(); 1066 break; 1067 case 'w': 1068 switch (Name[1]) { 1069 case 'd':// VSX vector register to hold vector double data 1070 case 'f':// VSX vector register to hold vector float data 1071 case 's':// VSX vector register to hold scalar float data 1072 case 'a':// Any VSX register 1073 case 'c':// An individual CR bit 1074 break; 1075 default: 1076 return false; 1077 } 1078 Info.setAllowsRegister(); 1079 Name++; // Skip over 'w'. 1080 break; 1081 case 'h': // `MQ', `CTR', or `LINK' register 1082 case 'q': // `MQ' register 1083 case 'c': // `CTR' register 1084 case 'l': // `LINK' register 1085 case 'x': // `CR' register (condition register) number 0 1086 case 'y': // `CR' register (condition register) 1087 case 'z': // `XER[CA]' carry bit (part of the XER register) 1088 Info.setAllowsRegister(); 1089 break; 1090 case 'I': // Signed 16-bit constant 1091 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1092 // (use `L' instead for SImode constants) 1093 case 'K': // Unsigned 16-bit constant 1094 case 'L': // Signed 16-bit constant shifted left 16 bits 1095 case 'M': // Constant larger than 31 1096 case 'N': // Exact power of 2 1097 case 'P': // Constant whose negation is a signed 16-bit constant 1098 case 'G': // Floating point constant that can be loaded into a 1099 // register with one instruction per word 1100 case 'H': // Integer/Floating point constant that can be loaded 1101 // into a register using three instructions 1102 break; 1103 case 'm': // Memory operand. Note that on PowerPC targets, m can 1104 // include addresses that update the base register. It 1105 // is therefore only safe to use `m' in an asm statement 1106 // if that asm statement accesses the operand exactly once. 1107 // The asm statement must also use `%U<opno>' as a 1108 // placeholder for the "update" flag in the corresponding 1109 // load or store instruction. For example: 1110 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1111 // is correct but: 1112 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1113 // is not. Use es rather than m if you don't want the base 1114 // register to be updated. 1115 case 'e': 1116 if (Name[1] != 's') 1117 return false; 1118 // es: A "stable" memory operand; that is, one which does not 1119 // include any automodification of the base register. Unlike 1120 // `m', this constraint can be used in asm statements that 1121 // might access the operand several times, or that might not 1122 // access it at all. 1123 Info.setAllowsMemory(); 1124 Name++; // Skip over 'e'. 1125 break; 1126 case 'Q': // Memory operand that is an offset from a register (it is 1127 // usually better to use `m' or `es' in asm statements) 1128 case 'Z': // Memory operand that is an indexed or indirect from a 1129 // register (it is usually better to use `m' or `es' in 1130 // asm statements) 1131 Info.setAllowsMemory(); 1132 Info.setAllowsRegister(); 1133 break; 1134 case 'R': // AIX TOC entry 1135 case 'a': // Address operand that is an indexed or indirect from a 1136 // register (`p' is preferable for asm statements) 1137 case 'S': // Constant suitable as a 64-bit mask operand 1138 case 'T': // Constant suitable as a 32-bit mask operand 1139 case 'U': // System V Release 4 small data area reference 1140 case 't': // AND masks that can be performed by two rldic{l, r} 1141 // instructions 1142 case 'W': // Vector constant that does not require memory 1143 case 'j': // Vector constant that is all zeros. 1144 break; 1145 // End FIXME. 1146 } 1147 return true; 1148 } 1149 std::string convertConstraint(const char *&Constraint) const override { 1150 std::string R; 1151 switch (*Constraint) { 1152 case 'e': 1153 case 'w': 1154 // Two-character constraint; add "^" hint for later parsing. 1155 R = std::string("^") + std::string(Constraint, 2); 1156 Constraint++; 1157 break; 1158 default: 1159 return TargetInfo::convertConstraint(Constraint); 1160 } 1161 return R; 1162 } 1163 const char *getClobbers() const override { 1164 return ""; 1165 } 1166 int getEHDataRegisterNumber(unsigned RegNo) const override { 1167 if (RegNo == 0) return 3; 1168 if (RegNo == 1) return 4; 1169 return -1; 1170 } 1171 1172 bool hasSjLjLowering() const override { 1173 return true; 1174 } 1175 1176 bool useFloat128ManglingForLongDouble() const override { 1177 return LongDoubleWidth == 128 && 1178 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1179 getTriple().isOSBinFormatELF(); 1180 } 1181 }; 1182 1183 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1184 #define BUILTIN(ID, TYPE, ATTRS) \ 1185 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1186 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1187 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1188 #include "clang/Basic/BuiltinsPPC.def" 1189 }; 1190 1191 /// handleTargetFeatures - Perform initialization based on the user 1192 /// configured set of features. 1193 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1194 DiagnosticsEngine &Diags) { 1195 for (const auto &Feature : Features) { 1196 if (Feature == "+altivec") { 1197 HasAltivec = true; 1198 } else if (Feature == "+vsx") { 1199 HasVSX = true; 1200 } else if (Feature == "+bpermd") { 1201 HasBPERMD = true; 1202 } else if (Feature == "+extdiv") { 1203 HasExtDiv = true; 1204 } else if (Feature == "+power8-vector") { 1205 HasP8Vector = true; 1206 } else if (Feature == "+crypto") { 1207 HasP8Crypto = true; 1208 } else if (Feature == "+direct-move") { 1209 HasDirectMove = true; 1210 } else if (Feature == "+qpx") { 1211 HasQPX = true; 1212 } else if (Feature == "+htm") { 1213 HasHTM = true; 1214 } else if (Feature == "+float128") { 1215 HasFloat128 = true; 1216 } else if (Feature == "+power9-vector") { 1217 HasP9Vector = true; 1218 } 1219 // TODO: Finish this list and add an assert that we've handled them 1220 // all. 1221 } 1222 1223 return true; 1224 } 1225 1226 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1227 /// #defines that are not tied to a specific subtarget. 1228 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1229 MacroBuilder &Builder) const { 1230 // Target identification. 1231 Builder.defineMacro("__ppc__"); 1232 Builder.defineMacro("__PPC__"); 1233 Builder.defineMacro("_ARCH_PPC"); 1234 Builder.defineMacro("__powerpc__"); 1235 Builder.defineMacro("__POWERPC__"); 1236 if (PointerWidth == 64) { 1237 Builder.defineMacro("_ARCH_PPC64"); 1238 Builder.defineMacro("__powerpc64__"); 1239 Builder.defineMacro("__ppc64__"); 1240 Builder.defineMacro("__PPC64__"); 1241 } 1242 1243 // Target properties. 1244 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1245 Builder.defineMacro("_LITTLE_ENDIAN"); 1246 } else { 1247 if (getTriple().getOS() != llvm::Triple::NetBSD && 1248 getTriple().getOS() != llvm::Triple::OpenBSD) 1249 Builder.defineMacro("_BIG_ENDIAN"); 1250 } 1251 1252 // ABI options. 1253 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1254 Builder.defineMacro("_CALL_ELF", "1"); 1255 if (ABI == "elfv2") 1256 Builder.defineMacro("_CALL_ELF", "2"); 1257 1258 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1259 // our suppport post-dates this and it should work on all 64-bit ppc linux 1260 // platforms. It is guaranteed to work on all elfv2 platforms. 1261 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1262 Builder.defineMacro("_CALL_LINUX", "1"); 1263 1264 // Subtarget options. 1265 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1266 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1267 1268 // FIXME: Should be controlled by command line option. 1269 if (LongDoubleWidth == 128) { 1270 Builder.defineMacro("__LONG_DOUBLE_128__"); 1271 Builder.defineMacro("__LONGDOUBLE128"); 1272 } 1273 1274 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1275 if (ABI == "elfv2" || 1276 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1277 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1278 1279 // CPU identification. 1280 ArchDefineTypes defs = 1281 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1282 .Case("440", ArchDefineName) 1283 .Case("450", ArchDefineName | ArchDefine440) 1284 .Case("601", ArchDefineName) 1285 .Case("602", ArchDefineName | ArchDefinePpcgr) 1286 .Case("603", ArchDefineName | ArchDefinePpcgr) 1287 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1288 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1289 .Case("604", ArchDefineName | ArchDefinePpcgr) 1290 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1291 .Case("620", ArchDefineName | ArchDefinePpcgr) 1292 .Case("630", ArchDefineName | ArchDefinePpcgr) 1293 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1294 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1295 .Case("750", ArchDefineName | ArchDefinePpcgr) 1296 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1297 ArchDefinePpcsq) 1298 .Case("a2", ArchDefineA2) 1299 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1300 .Case("pwr3", ArchDefinePpcgr) 1301 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1302 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1303 ArchDefinePpcsq) 1304 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1305 ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1307 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1308 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1309 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1310 ArchDefinePpcsq) 1311 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1312 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1313 ArchDefinePpcgr | ArchDefinePpcsq) 1314 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1315 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1316 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1317 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1318 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1319 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1320 ArchDefinePpcsq) 1321 .Case("power3", ArchDefinePpcgr) 1322 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1323 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1324 ArchDefinePpcsq) 1325 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1326 ArchDefinePpcgr | ArchDefinePpcsq) 1327 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1328 ArchDefinePwr4 | ArchDefinePpcgr | 1329 ArchDefinePpcsq) 1330 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1331 ArchDefinePwr5 | ArchDefinePwr4 | 1332 ArchDefinePpcgr | ArchDefinePpcsq) 1333 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1334 ArchDefinePwr5x | ArchDefinePwr5 | 1335 ArchDefinePwr4 | ArchDefinePpcgr | 1336 ArchDefinePpcsq) 1337 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1338 ArchDefinePwr6 | ArchDefinePwr5x | 1339 ArchDefinePwr5 | ArchDefinePwr4 | 1340 ArchDefinePpcgr | ArchDefinePpcsq) 1341 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1342 ArchDefinePwr6x | ArchDefinePwr6 | 1343 ArchDefinePwr5x | ArchDefinePwr5 | 1344 ArchDefinePwr4 | ArchDefinePpcgr | 1345 ArchDefinePpcsq) 1346 // powerpc64le automatically defaults to at least power8. 1347 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1348 ArchDefinePwr6 | ArchDefinePwr5x | 1349 ArchDefinePwr5 | ArchDefinePwr4 | 1350 ArchDefinePpcgr | ArchDefinePpcsq) 1351 .Default(ArchDefineNone); 1352 1353 if (defs & ArchDefineName) 1354 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1355 if (defs & ArchDefinePpcgr) 1356 Builder.defineMacro("_ARCH_PPCGR"); 1357 if (defs & ArchDefinePpcsq) 1358 Builder.defineMacro("_ARCH_PPCSQ"); 1359 if (defs & ArchDefine440) 1360 Builder.defineMacro("_ARCH_440"); 1361 if (defs & ArchDefine603) 1362 Builder.defineMacro("_ARCH_603"); 1363 if (defs & ArchDefine604) 1364 Builder.defineMacro("_ARCH_604"); 1365 if (defs & ArchDefinePwr4) 1366 Builder.defineMacro("_ARCH_PWR4"); 1367 if (defs & ArchDefinePwr5) 1368 Builder.defineMacro("_ARCH_PWR5"); 1369 if (defs & ArchDefinePwr5x) 1370 Builder.defineMacro("_ARCH_PWR5X"); 1371 if (defs & ArchDefinePwr6) 1372 Builder.defineMacro("_ARCH_PWR6"); 1373 if (defs & ArchDefinePwr6x) 1374 Builder.defineMacro("_ARCH_PWR6X"); 1375 if (defs & ArchDefinePwr7) 1376 Builder.defineMacro("_ARCH_PWR7"); 1377 if (defs & ArchDefinePwr8) 1378 Builder.defineMacro("_ARCH_PWR8"); 1379 if (defs & ArchDefinePwr9) 1380 Builder.defineMacro("_ARCH_PWR9"); 1381 if (defs & ArchDefineA2) 1382 Builder.defineMacro("_ARCH_A2"); 1383 if (defs & ArchDefineA2q) { 1384 Builder.defineMacro("_ARCH_A2Q"); 1385 Builder.defineMacro("_ARCH_QP"); 1386 } 1387 1388 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1389 Builder.defineMacro("__bg__"); 1390 Builder.defineMacro("__THW_BLUEGENE__"); 1391 Builder.defineMacro("__bgq__"); 1392 Builder.defineMacro("__TOS_BGQ__"); 1393 } 1394 1395 if (HasAltivec) { 1396 Builder.defineMacro("__VEC__", "10206"); 1397 Builder.defineMacro("__ALTIVEC__"); 1398 } 1399 if (HasVSX) 1400 Builder.defineMacro("__VSX__"); 1401 if (HasP8Vector) 1402 Builder.defineMacro("__POWER8_VECTOR__"); 1403 if (HasP8Crypto) 1404 Builder.defineMacro("__CRYPTO__"); 1405 if (HasHTM) 1406 Builder.defineMacro("__HTM__"); 1407 if (HasFloat128) 1408 Builder.defineMacro("__FLOAT128__"); 1409 if (HasP9Vector) 1410 Builder.defineMacro("__POWER9_VECTOR__"); 1411 1412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1413 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1415 if (PointerWidth == 64) 1416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1417 1418 // We have support for the bswap intrinsics so we can define this. 1419 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1420 1421 // FIXME: The following are not yet generated here by Clang, but are 1422 // generated by GCC: 1423 // 1424 // _SOFT_FLOAT_ 1425 // __RECIP_PRECISION__ 1426 // __APPLE_ALTIVEC__ 1427 // __RECIP__ 1428 // __RECIPF__ 1429 // __RSQRTE__ 1430 // __RSQRTEF__ 1431 // _SOFT_DOUBLE_ 1432 // __NO_LWSYNC__ 1433 // __CMODEL_MEDIUM__ 1434 // __CMODEL_LARGE__ 1435 // _CALL_SYSV 1436 // _CALL_DARWIN 1437 // __NO_FPRS__ 1438 } 1439 1440 // Handle explicit options being passed to the compiler here: if we've 1441 // explicitly turned off vsx and turned on any of: 1442 // - power8-vector 1443 // - direct-move 1444 // - float128 1445 // - power9-vector 1446 // then go ahead and error since the customer has expressed an incompatible 1447 // set of options. 1448 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1449 const std::vector<std::string> &FeaturesVec) { 1450 1451 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1452 FeaturesVec.end()) { 1453 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1454 FeaturesVec.end()) { 1455 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1456 << "-mno-vsx"; 1457 return false; 1458 } 1459 1460 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1461 FeaturesVec.end()) { 1462 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1463 << "-mno-vsx"; 1464 return false; 1465 } 1466 1467 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1468 FeaturesVec.end()) { 1469 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1470 << "-mno-vsx"; 1471 return false; 1472 } 1473 1474 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1475 FeaturesVec.end()) { 1476 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1477 << "-mno-vsx"; 1478 return false; 1479 } 1480 } 1481 1482 return true; 1483 } 1484 1485 bool PPCTargetInfo::initFeatureMap( 1486 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1487 const std::vector<std::string> &FeaturesVec) const { 1488 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1489 .Case("7400", true) 1490 .Case("g4", true) 1491 .Case("7450", true) 1492 .Case("g4+", true) 1493 .Case("970", true) 1494 .Case("g5", true) 1495 .Case("pwr6", true) 1496 .Case("pwr7", true) 1497 .Case("pwr8", true) 1498 .Case("pwr9", true) 1499 .Case("ppc64", true) 1500 .Case("ppc64le", true) 1501 .Default(false); 1502 1503 Features["qpx"] = (CPU == "a2q"); 1504 Features["power9-vector"] = (CPU == "pwr9"); 1505 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1506 .Case("ppc64le", true) 1507 .Case("pwr9", true) 1508 .Case("pwr8", true) 1509 .Default(false); 1510 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1511 .Case("ppc64le", true) 1512 .Case("pwr9", true) 1513 .Case("pwr8", true) 1514 .Default(false); 1515 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1516 .Case("ppc64le", true) 1517 .Case("pwr9", true) 1518 .Case("pwr8", true) 1519 .Case("pwr7", true) 1520 .Default(false); 1521 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1522 .Case("ppc64le", true) 1523 .Case("pwr9", true) 1524 .Case("pwr8", true) 1525 .Case("pwr7", true) 1526 .Default(false); 1527 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1528 .Case("ppc64le", true) 1529 .Case("pwr9", true) 1530 .Case("pwr8", true) 1531 .Default(false); 1532 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1533 .Case("ppc64le", true) 1534 .Case("pwr9", true) 1535 .Case("pwr8", true) 1536 .Case("pwr7", true) 1537 .Default(false); 1538 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1539 .Case("ppc64le", true) 1540 .Case("pwr9", true) 1541 .Case("pwr8", true) 1542 .Default(false); 1543 1544 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1545 return false; 1546 1547 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1548 } 1549 1550 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1551 return llvm::StringSwitch<bool>(Feature) 1552 .Case("powerpc", true) 1553 .Case("altivec", HasAltivec) 1554 .Case("vsx", HasVSX) 1555 .Case("power8-vector", HasP8Vector) 1556 .Case("crypto", HasP8Crypto) 1557 .Case("direct-move", HasDirectMove) 1558 .Case("qpx", HasQPX) 1559 .Case("htm", HasHTM) 1560 .Case("bpermd", HasBPERMD) 1561 .Case("extdiv", HasExtDiv) 1562 .Case("float128", HasFloat128) 1563 .Case("power9-vector", HasP9Vector) 1564 .Default(false); 1565 } 1566 1567 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1568 StringRef Name, bool Enabled) const { 1569 if (Enabled) { 1570 // If we're enabling any of the vsx based features then enable vsx and 1571 // altivec. We'll diagnose any problems later. 1572 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1573 .Case("vsx", true) 1574 .Case("direct-move", true) 1575 .Case("power8-vector", true) 1576 .Case("power9-vector", true) 1577 .Case("float128", true) 1578 .Default(false); 1579 if (FeatureHasVSX) 1580 Features["vsx"] = Features["altivec"] = true; 1581 if (Name == "power9-vector") 1582 Features["power8-vector"] = true; 1583 Features[Name] = true; 1584 } else { 1585 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1586 // features. 1587 if ((Name == "altivec") || (Name == "vsx")) 1588 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1589 Features["float128"] = Features["power9-vector"] = false; 1590 if (Name == "power8-vector") 1591 Features["power9-vector"] = false; 1592 Features[Name] = false; 1593 } 1594 } 1595 1596 const char * const PPCTargetInfo::GCCRegNames[] = { 1597 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1598 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1599 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1600 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1601 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1602 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1603 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1604 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1605 "mq", "lr", "ctr", "ap", 1606 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1607 "xer", 1608 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1609 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1610 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1611 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1612 "vrsave", "vscr", 1613 "spe_acc", "spefscr", 1614 "sfp" 1615 }; 1616 1617 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1618 return llvm::makeArrayRef(GCCRegNames); 1619 } 1620 1621 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1622 // While some of these aliases do map to different registers 1623 // they still share the same register name. 1624 { { "0" }, "r0" }, 1625 { { "1"}, "r1" }, 1626 { { "2" }, "r2" }, 1627 { { "3" }, "r3" }, 1628 { { "4" }, "r4" }, 1629 { { "5" }, "r5" }, 1630 { { "6" }, "r6" }, 1631 { { "7" }, "r7" }, 1632 { { "8" }, "r8" }, 1633 { { "9" }, "r9" }, 1634 { { "10" }, "r10" }, 1635 { { "11" }, "r11" }, 1636 { { "12" }, "r12" }, 1637 { { "13" }, "r13" }, 1638 { { "14" }, "r14" }, 1639 { { "15" }, "r15" }, 1640 { { "16" }, "r16" }, 1641 { { "17" }, "r17" }, 1642 { { "18" }, "r18" }, 1643 { { "19" }, "r19" }, 1644 { { "20" }, "r20" }, 1645 { { "21" }, "r21" }, 1646 { { "22" }, "r22" }, 1647 { { "23" }, "r23" }, 1648 { { "24" }, "r24" }, 1649 { { "25" }, "r25" }, 1650 { { "26" }, "r26" }, 1651 { { "27" }, "r27" }, 1652 { { "28" }, "r28" }, 1653 { { "29" }, "r29" }, 1654 { { "30" }, "r30" }, 1655 { { "31" }, "r31" }, 1656 { { "fr0" }, "f0" }, 1657 { { "fr1" }, "f1" }, 1658 { { "fr2" }, "f2" }, 1659 { { "fr3" }, "f3" }, 1660 { { "fr4" }, "f4" }, 1661 { { "fr5" }, "f5" }, 1662 { { "fr6" }, "f6" }, 1663 { { "fr7" }, "f7" }, 1664 { { "fr8" }, "f8" }, 1665 { { "fr9" }, "f9" }, 1666 { { "fr10" }, "f10" }, 1667 { { "fr11" }, "f11" }, 1668 { { "fr12" }, "f12" }, 1669 { { "fr13" }, "f13" }, 1670 { { "fr14" }, "f14" }, 1671 { { "fr15" }, "f15" }, 1672 { { "fr16" }, "f16" }, 1673 { { "fr17" }, "f17" }, 1674 { { "fr18" }, "f18" }, 1675 { { "fr19" }, "f19" }, 1676 { { "fr20" }, "f20" }, 1677 { { "fr21" }, "f21" }, 1678 { { "fr22" }, "f22" }, 1679 { { "fr23" }, "f23" }, 1680 { { "fr24" }, "f24" }, 1681 { { "fr25" }, "f25" }, 1682 { { "fr26" }, "f26" }, 1683 { { "fr27" }, "f27" }, 1684 { { "fr28" }, "f28" }, 1685 { { "fr29" }, "f29" }, 1686 { { "fr30" }, "f30" }, 1687 { { "fr31" }, "f31" }, 1688 { { "cc" }, "cr0" }, 1689 }; 1690 1691 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1692 return llvm::makeArrayRef(GCCRegAliases); 1693 } 1694 1695 class PPC32TargetInfo : public PPCTargetInfo { 1696 public: 1697 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1698 : PPCTargetInfo(Triple, Opts) { 1699 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1700 1701 switch (getTriple().getOS()) { 1702 case llvm::Triple::Linux: 1703 case llvm::Triple::FreeBSD: 1704 case llvm::Triple::NetBSD: 1705 SizeType = UnsignedInt; 1706 PtrDiffType = SignedInt; 1707 IntPtrType = SignedInt; 1708 break; 1709 default: 1710 break; 1711 } 1712 1713 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1714 LongDoubleWidth = LongDoubleAlign = 64; 1715 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1716 } 1717 1718 // PPC32 supports atomics up to 4 bytes. 1719 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1720 } 1721 1722 BuiltinVaListKind getBuiltinVaListKind() const override { 1723 // This is the ELF definition, and is overridden by the Darwin sub-target 1724 return TargetInfo::PowerABIBuiltinVaList; 1725 } 1726 }; 1727 1728 // Note: ABI differences may eventually require us to have a separate 1729 // TargetInfo for little endian. 1730 class PPC64TargetInfo : public PPCTargetInfo { 1731 public: 1732 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1733 : PPCTargetInfo(Triple, Opts) { 1734 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1735 IntMaxType = SignedLong; 1736 Int64Type = SignedLong; 1737 1738 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1739 resetDataLayout("e-m:e-i64:64-n32:64"); 1740 ABI = "elfv2"; 1741 } else { 1742 resetDataLayout("E-m:e-i64:64-n32:64"); 1743 ABI = "elfv1"; 1744 } 1745 1746 switch (getTriple().getOS()) { 1747 case llvm::Triple::FreeBSD: 1748 LongDoubleWidth = LongDoubleAlign = 64; 1749 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1750 break; 1751 case llvm::Triple::NetBSD: 1752 IntMaxType = SignedLongLong; 1753 Int64Type = SignedLongLong; 1754 break; 1755 default: 1756 break; 1757 } 1758 1759 // PPC64 supports atomics up to 8 bytes. 1760 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1761 } 1762 BuiltinVaListKind getBuiltinVaListKind() const override { 1763 return TargetInfo::CharPtrBuiltinVaList; 1764 } 1765 // PPC64 Linux-specific ABI options. 1766 bool setABI(const std::string &Name) override { 1767 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1768 ABI = Name; 1769 return true; 1770 } 1771 return false; 1772 } 1773 }; 1774 1775 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1776 public: 1777 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1778 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1779 HasAlignMac68kSupport = true; 1780 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1781 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1782 LongLongAlign = 32; 1783 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1784 } 1785 BuiltinVaListKind getBuiltinVaListKind() const override { 1786 return TargetInfo::CharPtrBuiltinVaList; 1787 } 1788 }; 1789 1790 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1791 public: 1792 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1793 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1794 HasAlignMac68kSupport = true; 1795 resetDataLayout("E-m:o-i64:64-n32:64"); 1796 } 1797 }; 1798 1799 static const unsigned NVPTXAddrSpaceMap[] = { 1800 0, // Default 1801 1, // opencl_global 1802 3, // opencl_local 1803 4, // opencl_constant 1804 // FIXME: generic has to be added to the target 1805 0, // opencl_generic 1806 1, // cuda_device 1807 4, // cuda_constant 1808 3, // cuda_shared 1809 }; 1810 1811 class NVPTXTargetInfo : public TargetInfo { 1812 static const char *const GCCRegNames[]; 1813 static const Builtin::Info BuiltinInfo[]; 1814 CudaArch GPU; 1815 std::unique_ptr<TargetInfo> HostTarget; 1816 1817 public: 1818 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1819 unsigned TargetPointerWidth) 1820 : TargetInfo(Triple) { 1821 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1822 "NVPTX only supports 32- and 64-bit modes."); 1823 1824 TLSSupported = false; 1825 AddrSpaceMap = &NVPTXAddrSpaceMap; 1826 UseAddrSpaceMapMangling = true; 1827 1828 // Define available target features 1829 // These must be defined in sorted order! 1830 NoAsmVariants = true; 1831 GPU = CudaArch::SM_20; 1832 1833 if (TargetPointerWidth == 32) 1834 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1835 else 1836 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1837 1838 // If possible, get a TargetInfo for our host triple, so we can match its 1839 // types. 1840 llvm::Triple HostTriple(Opts.HostTriple); 1841 if (!HostTriple.isNVPTX()) 1842 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1843 1844 // If no host target, make some guesses about the data layout and return. 1845 if (!HostTarget) { 1846 LongWidth = LongAlign = TargetPointerWidth; 1847 PointerWidth = PointerAlign = TargetPointerWidth; 1848 switch (TargetPointerWidth) { 1849 case 32: 1850 SizeType = TargetInfo::UnsignedInt; 1851 PtrDiffType = TargetInfo::SignedInt; 1852 IntPtrType = TargetInfo::SignedInt; 1853 break; 1854 case 64: 1855 SizeType = TargetInfo::UnsignedLong; 1856 PtrDiffType = TargetInfo::SignedLong; 1857 IntPtrType = TargetInfo::SignedLong; 1858 break; 1859 default: 1860 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1861 } 1862 return; 1863 } 1864 1865 // Copy properties from host target. 1866 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1867 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1868 BoolWidth = HostTarget->getBoolWidth(); 1869 BoolAlign = HostTarget->getBoolAlign(); 1870 IntWidth = HostTarget->getIntWidth(); 1871 IntAlign = HostTarget->getIntAlign(); 1872 HalfWidth = HostTarget->getHalfWidth(); 1873 HalfAlign = HostTarget->getHalfAlign(); 1874 FloatWidth = HostTarget->getFloatWidth(); 1875 FloatAlign = HostTarget->getFloatAlign(); 1876 DoubleWidth = HostTarget->getDoubleWidth(); 1877 DoubleAlign = HostTarget->getDoubleAlign(); 1878 LongWidth = HostTarget->getLongWidth(); 1879 LongAlign = HostTarget->getLongAlign(); 1880 LongLongWidth = HostTarget->getLongLongWidth(); 1881 LongLongAlign = HostTarget->getLongLongAlign(); 1882 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1883 NewAlign = HostTarget->getNewAlign(); 1884 DefaultAlignForAttributeAligned = 1885 HostTarget->getDefaultAlignForAttributeAligned(); 1886 SizeType = HostTarget->getSizeType(); 1887 IntMaxType = HostTarget->getIntMaxType(); 1888 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1889 IntPtrType = HostTarget->getIntPtrType(); 1890 WCharType = HostTarget->getWCharType(); 1891 WIntType = HostTarget->getWIntType(); 1892 Char16Type = HostTarget->getChar16Type(); 1893 Char32Type = HostTarget->getChar32Type(); 1894 Int64Type = HostTarget->getInt64Type(); 1895 SigAtomicType = HostTarget->getSigAtomicType(); 1896 ProcessIDType = HostTarget->getProcessIDType(); 1897 1898 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1899 UseZeroLengthBitfieldAlignment = 1900 HostTarget->useZeroLengthBitfieldAlignment(); 1901 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1902 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1903 1904 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1905 // we need those macros to be identical on host and device, because (among 1906 // other things) they affect which standard library classes are defined, and 1907 // we need all classes to be defined on both the host and device. 1908 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1909 1910 // Properties intentionally not copied from host: 1911 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1912 // host/device boundary. 1913 // - SuitableAlign: Not visible across the host/device boundary, and may 1914 // correctly be different on host/device, e.g. if host has wider vector 1915 // types than device. 1916 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1917 // as its double type, but that's not necessarily true on the host. 1918 // TODO: nvcc emits a warning when using long double on device; we should 1919 // do the same. 1920 } 1921 void getTargetDefines(const LangOptions &Opts, 1922 MacroBuilder &Builder) const override { 1923 Builder.defineMacro("__PTX__"); 1924 Builder.defineMacro("__NVPTX__"); 1925 if (Opts.CUDAIsDevice) { 1926 // Set __CUDA_ARCH__ for the GPU specified. 1927 std::string CUDAArchCode = [this] { 1928 switch (GPU) { 1929 case CudaArch::UNKNOWN: 1930 assert(false && "No GPU arch when compiling CUDA device code."); 1931 return ""; 1932 case CudaArch::SM_20: 1933 return "200"; 1934 case CudaArch::SM_21: 1935 return "210"; 1936 case CudaArch::SM_30: 1937 return "300"; 1938 case CudaArch::SM_32: 1939 return "320"; 1940 case CudaArch::SM_35: 1941 return "350"; 1942 case CudaArch::SM_37: 1943 return "370"; 1944 case CudaArch::SM_50: 1945 return "500"; 1946 case CudaArch::SM_52: 1947 return "520"; 1948 case CudaArch::SM_53: 1949 return "530"; 1950 case CudaArch::SM_60: 1951 return "600"; 1952 case CudaArch::SM_61: 1953 return "610"; 1954 case CudaArch::SM_62: 1955 return "620"; 1956 } 1957 llvm_unreachable("unhandled CudaArch"); 1958 }(); 1959 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1960 } 1961 } 1962 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1963 return llvm::makeArrayRef(BuiltinInfo, 1964 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1965 } 1966 bool 1967 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1968 StringRef CPU, 1969 const std::vector<std::string> &FeaturesVec) const override { 1970 Features["satom"] = GPU >= CudaArch::SM_60; 1971 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1972 } 1973 1974 bool hasFeature(StringRef Feature) const override { 1975 return llvm::StringSwitch<bool>(Feature) 1976 .Cases("ptx", "nvptx", true) 1977 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1978 .Default(false); 1979 } 1980 1981 ArrayRef<const char *> getGCCRegNames() const override; 1982 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1983 // No aliases. 1984 return None; 1985 } 1986 bool validateAsmConstraint(const char *&Name, 1987 TargetInfo::ConstraintInfo &Info) const override { 1988 switch (*Name) { 1989 default: 1990 return false; 1991 case 'c': 1992 case 'h': 1993 case 'r': 1994 case 'l': 1995 case 'f': 1996 case 'd': 1997 Info.setAllowsRegister(); 1998 return true; 1999 } 2000 } 2001 const char *getClobbers() const override { 2002 // FIXME: Is this really right? 2003 return ""; 2004 } 2005 BuiltinVaListKind getBuiltinVaListKind() const override { 2006 // FIXME: implement 2007 return TargetInfo::CharPtrBuiltinVaList; 2008 } 2009 bool setCPU(const std::string &Name) override { 2010 GPU = StringToCudaArch(Name); 2011 return GPU != CudaArch::UNKNOWN; 2012 } 2013 void setSupportedOpenCLOpts() override { 2014 auto &Opts = getSupportedOpenCLOpts(); 2015 Opts.support("cl_clang_storage_class_specifiers"); 2016 Opts.support("cl_khr_gl_sharing"); 2017 Opts.support("cl_khr_icd"); 2018 2019 Opts.support("cl_khr_fp64"); 2020 Opts.support("cl_khr_byte_addressable_store"); 2021 Opts.support("cl_khr_global_int32_base_atomics"); 2022 Opts.support("cl_khr_global_int32_extended_atomics"); 2023 Opts.support("cl_khr_local_int32_base_atomics"); 2024 Opts.support("cl_khr_local_int32_extended_atomics"); 2025 } 2026 2027 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2028 // CUDA compilations support all of the host's calling conventions. 2029 // 2030 // TODO: We should warn if you apply a non-default CC to anything other than 2031 // a host function. 2032 if (HostTarget) 2033 return HostTarget->checkCallingConvention(CC); 2034 return CCCR_Warning; 2035 } 2036 }; 2037 2038 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2039 #define BUILTIN(ID, TYPE, ATTRS) \ 2040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2041 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2042 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2043 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2044 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2045 #include "clang/Basic/BuiltinsNVPTX.def" 2046 }; 2047 2048 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2049 2050 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2051 return llvm::makeArrayRef(GCCRegNames); 2052 } 2053 2054 static const LangAS::Map AMDGPUPrivIsZeroDefIsGenMap = { 2055 4, // Default 2056 1, // opencl_global 2057 3, // opencl_local 2058 2, // opencl_constant 2059 4, // opencl_generic 2060 1, // cuda_device 2061 2, // cuda_constant 2062 3 // cuda_shared 2063 }; 2064 static const LangAS::Map AMDGPUGenIsZeroDefIsGenMap = { 2065 0, // Default 2066 1, // opencl_global 2067 3, // opencl_local 2068 2, // opencl_constant 2069 0, // opencl_generic 2070 1, // cuda_device 2071 2, // cuda_constant 2072 3 // cuda_shared 2073 }; 2074 static const LangAS::Map AMDGPUPrivIsZeroDefIsPrivMap = { 2075 0, // Default 2076 1, // opencl_global 2077 3, // opencl_local 2078 2, // opencl_constant 2079 4, // opencl_generic 2080 1, // cuda_device 2081 2, // cuda_constant 2082 3 // cuda_shared 2083 }; 2084 static const LangAS::Map AMDGPUGenIsZeroDefIsPrivMap = { 2085 5, // Default 2086 1, // opencl_global 2087 3, // opencl_local 2088 2, // opencl_constant 2089 0, // opencl_generic 2090 1, // cuda_device 2091 2, // cuda_constant 2092 3 // cuda_shared 2093 }; 2094 2095 // If you edit the description strings, make sure you update 2096 // getPointerWidthV(). 2097 2098 static const char *const DataLayoutStringR600 = 2099 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2100 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2101 2102 static const char *const DataLayoutStringSIPrivateIsZero = 2103 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2104 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2105 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2106 2107 static const char *const DataLayoutStringSIGenericIsZero = 2108 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2109 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2110 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2111 2112 class AMDGPUTargetInfo final : public TargetInfo { 2113 static const Builtin::Info BuiltinInfo[]; 2114 static const char * const GCCRegNames[]; 2115 2116 struct AddrSpace { 2117 unsigned Generic, Global, Local, Constant, Private; 2118 AddrSpace(bool IsGenericZero_ = false){ 2119 if (IsGenericZero_) { 2120 Generic = 0; 2121 Global = 1; 2122 Local = 3; 2123 Constant = 2; 2124 Private = 5; 2125 } else { 2126 Generic = 4; 2127 Global = 1; 2128 Local = 3; 2129 Constant = 2; 2130 Private = 0; 2131 } 2132 } 2133 }; 2134 2135 /// \brief The GPU profiles supported by the AMDGPU target. 2136 enum GPUKind { 2137 GK_NONE, 2138 GK_R600, 2139 GK_R600_DOUBLE_OPS, 2140 GK_R700, 2141 GK_R700_DOUBLE_OPS, 2142 GK_EVERGREEN, 2143 GK_EVERGREEN_DOUBLE_OPS, 2144 GK_NORTHERN_ISLANDS, 2145 GK_CAYMAN, 2146 GK_GFX6, 2147 GK_GFX7, 2148 GK_GFX8, 2149 GK_GFX9 2150 } GPU; 2151 2152 bool hasFP64:1; 2153 bool hasFMAF:1; 2154 bool hasLDEXPF:1; 2155 const AddrSpace AS; 2156 2157 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2158 return parseAMDGCNName(GPUName) >= GK_GFX9; 2159 } 2160 2161 static bool isAMDGCN(const llvm::Triple &TT) { 2162 return TT.getArch() == llvm::Triple::amdgcn; 2163 } 2164 2165 static bool isGenericZero(const llvm::Triple &TT) { 2166 return TT.getEnvironmentName() == "amdgiz" || 2167 TT.getEnvironmentName() == "amdgizcl"; 2168 } 2169 public: 2170 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2171 : TargetInfo(Triple) , 2172 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2173 hasFP64(false), 2174 hasFMAF(false), 2175 hasLDEXPF(false), 2176 AS(isGenericZero(Triple)){ 2177 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2178 hasFP64 = true; 2179 hasFMAF = true; 2180 hasLDEXPF = true; 2181 } 2182 auto IsGenericZero = isGenericZero(Triple); 2183 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2184 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2185 DataLayoutStringSIPrivateIsZero) 2186 : DataLayoutStringR600); 2187 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2188 2189 setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D || 2190 Triple.getEnvironment() == llvm::Triple::OpenCL || 2191 Triple.getEnvironmentName() == "amdgizcl" || 2192 !isAMDGCN(Triple)); 2193 UseAddrSpaceMapMangling = true; 2194 2195 // Set pointer width and alignment for target address space 0. 2196 PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits(); 2197 if (getMaxPointerWidth() == 64) { 2198 LongWidth = LongAlign = 64; 2199 SizeType = UnsignedLong; 2200 PtrDiffType = SignedLong; 2201 IntPtrType = SignedLong; 2202 } 2203 } 2204 2205 void setAddressSpaceMap(bool DefaultIsPrivate) { 2206 if (isGenericZero(getTriple())) { 2207 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap 2208 : &AMDGPUGenIsZeroDefIsGenMap; 2209 } else { 2210 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap 2211 : &AMDGPUPrivIsZeroDefIsGenMap; 2212 } 2213 } 2214 2215 void adjust(LangOptions &Opts) override { 2216 TargetInfo::adjust(Opts); 2217 setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple())); 2218 } 2219 2220 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2221 if (GPU <= GK_CAYMAN) 2222 return 32; 2223 2224 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2225 return 32; 2226 } 2227 return 64; 2228 } 2229 2230 uint64_t getPointerAlignV(unsigned AddrSpace) const override { 2231 return getPointerWidthV(AddrSpace); 2232 } 2233 2234 uint64_t getMaxPointerWidth() const override { 2235 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2236 } 2237 2238 const char * getClobbers() const override { 2239 return ""; 2240 } 2241 2242 ArrayRef<const char *> getGCCRegNames() const override; 2243 2244 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2245 return None; 2246 } 2247 2248 bool validateAsmConstraint(const char *&Name, 2249 TargetInfo::ConstraintInfo &Info) const override { 2250 switch (*Name) { 2251 default: break; 2252 case 'v': // vgpr 2253 case 's': // sgpr 2254 Info.setAllowsRegister(); 2255 return true; 2256 } 2257 return false; 2258 } 2259 2260 bool initFeatureMap(llvm::StringMap<bool> &Features, 2261 DiagnosticsEngine &Diags, StringRef CPU, 2262 const std::vector<std::string> &FeatureVec) const override; 2263 2264 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2265 TargetOptions &TargetOpts) const override { 2266 bool hasFP32Denormals = false; 2267 bool hasFP64Denormals = false; 2268 for (auto &I : TargetOpts.FeaturesAsWritten) { 2269 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2270 hasFP32Denormals = true; 2271 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2272 hasFP64Denormals = true; 2273 } 2274 if (!hasFP32Denormals) 2275 TargetOpts.Features.push_back( 2276 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2277 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2278 // Always do not flush fp64 or fp16 denorms. 2279 if (!hasFP64Denormals && hasFP64) 2280 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2281 } 2282 2283 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2284 return llvm::makeArrayRef(BuiltinInfo, 2285 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2286 } 2287 2288 void getTargetDefines(const LangOptions &Opts, 2289 MacroBuilder &Builder) const override { 2290 if (getTriple().getArch() == llvm::Triple::amdgcn) 2291 Builder.defineMacro("__AMDGCN__"); 2292 else 2293 Builder.defineMacro("__R600__"); 2294 2295 if (hasFMAF) 2296 Builder.defineMacro("__HAS_FMAF__"); 2297 if (hasLDEXPF) 2298 Builder.defineMacro("__HAS_LDEXPF__"); 2299 if (hasFP64) 2300 Builder.defineMacro("__HAS_FP64__"); 2301 } 2302 2303 BuiltinVaListKind getBuiltinVaListKind() const override { 2304 return TargetInfo::CharPtrBuiltinVaList; 2305 } 2306 2307 static GPUKind parseR600Name(StringRef Name) { 2308 return llvm::StringSwitch<GPUKind>(Name) 2309 .Case("r600" , GK_R600) 2310 .Case("rv610", GK_R600) 2311 .Case("rv620", GK_R600) 2312 .Case("rv630", GK_R600) 2313 .Case("rv635", GK_R600) 2314 .Case("rs780", GK_R600) 2315 .Case("rs880", GK_R600) 2316 .Case("rv670", GK_R600_DOUBLE_OPS) 2317 .Case("rv710", GK_R700) 2318 .Case("rv730", GK_R700) 2319 .Case("rv740", GK_R700_DOUBLE_OPS) 2320 .Case("rv770", GK_R700_DOUBLE_OPS) 2321 .Case("palm", GK_EVERGREEN) 2322 .Case("cedar", GK_EVERGREEN) 2323 .Case("sumo", GK_EVERGREEN) 2324 .Case("sumo2", GK_EVERGREEN) 2325 .Case("redwood", GK_EVERGREEN) 2326 .Case("juniper", GK_EVERGREEN) 2327 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2328 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2329 .Case("barts", GK_NORTHERN_ISLANDS) 2330 .Case("turks", GK_NORTHERN_ISLANDS) 2331 .Case("caicos", GK_NORTHERN_ISLANDS) 2332 .Case("cayman", GK_CAYMAN) 2333 .Case("aruba", GK_CAYMAN) 2334 .Default(GK_NONE); 2335 } 2336 2337 static GPUKind parseAMDGCNName(StringRef Name) { 2338 return llvm::StringSwitch<GPUKind>(Name) 2339 .Case("tahiti", GK_GFX6) 2340 .Case("pitcairn", GK_GFX6) 2341 .Case("verde", GK_GFX6) 2342 .Case("oland", GK_GFX6) 2343 .Case("hainan", GK_GFX6) 2344 .Case("bonaire", GK_GFX7) 2345 .Case("kabini", GK_GFX7) 2346 .Case("kaveri", GK_GFX7) 2347 .Case("hawaii", GK_GFX7) 2348 .Case("mullins", GK_GFX7) 2349 .Case("gfx700", GK_GFX7) 2350 .Case("gfx701", GK_GFX7) 2351 .Case("gfx702", GK_GFX7) 2352 .Case("tonga", GK_GFX8) 2353 .Case("iceland", GK_GFX8) 2354 .Case("carrizo", GK_GFX8) 2355 .Case("fiji", GK_GFX8) 2356 .Case("stoney", GK_GFX8) 2357 .Case("polaris10", GK_GFX8) 2358 .Case("polaris11", GK_GFX8) 2359 .Case("gfx800", GK_GFX8) 2360 .Case("gfx801", GK_GFX8) 2361 .Case("gfx802", GK_GFX8) 2362 .Case("gfx803", GK_GFX8) 2363 .Case("gfx804", GK_GFX8) 2364 .Case("gfx810", GK_GFX8) 2365 .Case("gfx900", GK_GFX9) 2366 .Case("gfx901", GK_GFX9) 2367 .Default(GK_NONE); 2368 } 2369 2370 bool setCPU(const std::string &Name) override { 2371 if (getTriple().getArch() == llvm::Triple::amdgcn) 2372 GPU = parseAMDGCNName(Name); 2373 else 2374 GPU = parseR600Name(Name); 2375 2376 return GPU != GK_NONE; 2377 } 2378 2379 void setSupportedOpenCLOpts() override { 2380 auto &Opts = getSupportedOpenCLOpts(); 2381 Opts.support("cl_clang_storage_class_specifiers"); 2382 Opts.support("cl_khr_icd"); 2383 2384 if (hasFP64) 2385 Opts.support("cl_khr_fp64"); 2386 if (GPU >= GK_EVERGREEN) { 2387 Opts.support("cl_khr_byte_addressable_store"); 2388 Opts.support("cl_khr_global_int32_base_atomics"); 2389 Opts.support("cl_khr_global_int32_extended_atomics"); 2390 Opts.support("cl_khr_local_int32_base_atomics"); 2391 Opts.support("cl_khr_local_int32_extended_atomics"); 2392 } 2393 if (GPU >= GK_GFX6) { 2394 Opts.support("cl_khr_fp16"); 2395 Opts.support("cl_khr_int64_base_atomics"); 2396 Opts.support("cl_khr_int64_extended_atomics"); 2397 Opts.support("cl_khr_mipmap_image"); 2398 Opts.support("cl_khr_subgroups"); 2399 Opts.support("cl_khr_3d_image_writes"); 2400 Opts.support("cl_amd_media_ops"); 2401 Opts.support("cl_amd_media_ops2"); 2402 } 2403 } 2404 2405 LangAS::ID getOpenCLImageAddrSpace() const override { 2406 return LangAS::opencl_constant; 2407 } 2408 2409 llvm::Optional<unsigned> getConstantAddressSpace() const override { 2410 return LangAS::FirstTargetAddressSpace + AS.Constant; 2411 } 2412 2413 /// \returns Target specific vtbl ptr address space. 2414 unsigned getVtblPtrAddressSpace() const override { return AS.Constant; } 2415 2416 /// \returns If a target requires an address within a target specific address 2417 /// space \p AddressSpace to be converted in order to be used, then return the 2418 /// corresponding target specific DWARF address space. 2419 /// 2420 /// \returns Otherwise return None and no conversion will be emitted in the 2421 /// DWARF. 2422 Optional<unsigned> getDWARFAddressSpace( 2423 unsigned AddressSpace) const override { 2424 const unsigned DWARF_Private = 1; 2425 const unsigned DWARF_Local = 2; 2426 if (AddressSpace == AS.Private) { 2427 return DWARF_Private; 2428 } else if (AddressSpace == AS.Local) { 2429 return DWARF_Local; 2430 } else { 2431 return None; 2432 } 2433 } 2434 2435 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2436 switch (CC) { 2437 default: 2438 return CCCR_Warning; 2439 case CC_C: 2440 case CC_OpenCLKernel: 2441 return CCCR_OK; 2442 } 2443 } 2444 2445 // In amdgcn target the null pointer in global, constant, and generic 2446 // address space has value 0 but in private and local address space has 2447 // value ~0. 2448 uint64_t getNullPointerValue(unsigned AS) const override { 2449 return AS == LangAS::opencl_local ? ~0 : 0; 2450 } 2451 }; 2452 2453 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2454 #define BUILTIN(ID, TYPE, ATTRS) \ 2455 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2456 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2457 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2458 #include "clang/Basic/BuiltinsAMDGPU.def" 2459 }; 2460 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2461 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2462 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2463 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2464 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2465 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2466 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2467 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2468 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2469 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2470 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2471 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2472 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2473 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2474 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2475 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2476 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2477 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2478 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2479 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2480 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2481 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2482 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2483 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2484 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2485 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2486 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2487 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2488 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2489 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2490 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2491 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2492 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2493 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2494 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2495 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2496 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2497 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2498 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2499 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2500 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2501 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2502 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2503 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2504 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2505 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2506 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2507 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2508 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2509 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2510 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2511 }; 2512 2513 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2514 return llvm::makeArrayRef(GCCRegNames); 2515 } 2516 2517 bool AMDGPUTargetInfo::initFeatureMap( 2518 llvm::StringMap<bool> &Features, 2519 DiagnosticsEngine &Diags, StringRef CPU, 2520 const std::vector<std::string> &FeatureVec) const { 2521 2522 // XXX - What does the member GPU mean if device name string passed here? 2523 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2524 if (CPU.empty()) 2525 CPU = "tahiti"; 2526 2527 switch (parseAMDGCNName(CPU)) { 2528 case GK_GFX6: 2529 case GK_GFX7: 2530 break; 2531 2532 case GK_GFX9: 2533 Features["gfx9-insts"] = true; 2534 LLVM_FALLTHROUGH; 2535 case GK_GFX8: 2536 Features["s-memrealtime"] = true; 2537 Features["16-bit-insts"] = true; 2538 Features["dpp"] = true; 2539 break; 2540 2541 case GK_NONE: 2542 return false; 2543 default: 2544 llvm_unreachable("unhandled subtarget"); 2545 } 2546 } else { 2547 if (CPU.empty()) 2548 CPU = "r600"; 2549 2550 switch (parseR600Name(CPU)) { 2551 case GK_R600: 2552 case GK_R700: 2553 case GK_EVERGREEN: 2554 case GK_NORTHERN_ISLANDS: 2555 break; 2556 case GK_R600_DOUBLE_OPS: 2557 case GK_R700_DOUBLE_OPS: 2558 case GK_EVERGREEN_DOUBLE_OPS: 2559 case GK_CAYMAN: 2560 Features["fp64"] = true; 2561 break; 2562 case GK_NONE: 2563 return false; 2564 default: 2565 llvm_unreachable("unhandled subtarget"); 2566 } 2567 } 2568 2569 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2570 } 2571 2572 const Builtin::Info BuiltinInfoX86[] = { 2573 #define BUILTIN(ID, TYPE, ATTRS) \ 2574 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2575 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2576 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2577 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2578 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2579 #include "clang/Basic/BuiltinsX86.def" 2580 2581 #define BUILTIN(ID, TYPE, ATTRS) \ 2582 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2583 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2584 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2585 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2586 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2587 #include "clang/Basic/BuiltinsX86_64.def" 2588 }; 2589 2590 2591 static const char* const GCCRegNames[] = { 2592 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2593 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2594 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2595 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2596 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2597 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2598 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2599 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2600 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2601 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2602 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2603 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2604 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2605 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2606 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2607 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2608 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2609 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2610 }; 2611 2612 const TargetInfo::AddlRegName AddlRegNames[] = { 2613 { { "al", "ah", "eax", "rax" }, 0 }, 2614 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2615 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2616 { { "dl", "dh", "edx", "rdx" }, 1 }, 2617 { { "esi", "rsi" }, 4 }, 2618 { { "edi", "rdi" }, 5 }, 2619 { { "esp", "rsp" }, 7 }, 2620 { { "ebp", "rbp" }, 6 }, 2621 { { "r8d", "r8w", "r8b" }, 38 }, 2622 { { "r9d", "r9w", "r9b" }, 39 }, 2623 { { "r10d", "r10w", "r10b" }, 40 }, 2624 { { "r11d", "r11w", "r11b" }, 41 }, 2625 { { "r12d", "r12w", "r12b" }, 42 }, 2626 { { "r13d", "r13w", "r13b" }, 43 }, 2627 { { "r14d", "r14w", "r14b" }, 44 }, 2628 { { "r15d", "r15w", "r15b" }, 45 }, 2629 }; 2630 2631 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2632 // most of the implementation can be shared. 2633 class X86TargetInfo : public TargetInfo { 2634 enum X86SSEEnum { 2635 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2636 } SSELevel = NoSSE; 2637 enum MMX3DNowEnum { 2638 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2639 } MMX3DNowLevel = NoMMX3DNow; 2640 enum XOPEnum { 2641 NoXOP, 2642 SSE4A, 2643 FMA4, 2644 XOP 2645 } XOPLevel = NoXOP; 2646 2647 bool HasAES = false; 2648 bool HasPCLMUL = false; 2649 bool HasLZCNT = false; 2650 bool HasRDRND = false; 2651 bool HasFSGSBASE = false; 2652 bool HasBMI = false; 2653 bool HasBMI2 = false; 2654 bool HasPOPCNT = false; 2655 bool HasRTM = false; 2656 bool HasPRFCHW = false; 2657 bool HasRDSEED = false; 2658 bool HasADX = false; 2659 bool HasTBM = false; 2660 bool HasLWP = false; 2661 bool HasFMA = false; 2662 bool HasF16C = false; 2663 bool HasAVX512CD = false; 2664 bool HasAVX512VPOPCNTDQ = false; 2665 bool HasAVX512ER = false; 2666 bool HasAVX512PF = false; 2667 bool HasAVX512DQ = false; 2668 bool HasAVX512BW = false; 2669 bool HasAVX512VL = false; 2670 bool HasAVX512VBMI = false; 2671 bool HasAVX512IFMA = false; 2672 bool HasSHA = false; 2673 bool HasMPX = false; 2674 bool HasSGX = false; 2675 bool HasCX16 = false; 2676 bool HasFXSR = false; 2677 bool HasXSAVE = false; 2678 bool HasXSAVEOPT = false; 2679 bool HasXSAVEC = false; 2680 bool HasXSAVES = false; 2681 bool HasMWAITX = false; 2682 bool HasCLZERO = false; 2683 bool HasPKU = false; 2684 bool HasCLFLUSHOPT = false; 2685 bool HasCLWB = false; 2686 bool HasMOVBE = false; 2687 bool HasPREFETCHWT1 = false; 2688 2689 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2690 /// 2691 /// Each enumeration represents a particular CPU supported by Clang. These 2692 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2693 enum CPUKind { 2694 CK_Generic, 2695 2696 /// \name i386 2697 /// i386-generation processors. 2698 //@{ 2699 CK_i386, 2700 //@} 2701 2702 /// \name i486 2703 /// i486-generation processors. 2704 //@{ 2705 CK_i486, 2706 CK_WinChipC6, 2707 CK_WinChip2, 2708 CK_C3, 2709 //@} 2710 2711 /// \name i586 2712 /// i586-generation processors, P5 microarchitecture based. 2713 //@{ 2714 CK_i586, 2715 CK_Pentium, 2716 CK_PentiumMMX, 2717 //@} 2718 2719 /// \name i686 2720 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2721 //@{ 2722 CK_i686, 2723 CK_PentiumPro, 2724 CK_Pentium2, 2725 CK_Pentium3, 2726 CK_Pentium3M, 2727 CK_PentiumM, 2728 CK_C3_2, 2729 2730 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2731 /// Clang however has some logic to support this. 2732 // FIXME: Warn, deprecate, and potentially remove this. 2733 CK_Yonah, 2734 //@} 2735 2736 /// \name Netburst 2737 /// Netburst microarchitecture based processors. 2738 //@{ 2739 CK_Pentium4, 2740 CK_Pentium4M, 2741 CK_Prescott, 2742 CK_Nocona, 2743 //@} 2744 2745 /// \name Core 2746 /// Core microarchitecture based processors. 2747 //@{ 2748 CK_Core2, 2749 2750 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2751 /// codename which GCC no longer accepts as an option to -march, but Clang 2752 /// has some logic for recognizing it. 2753 // FIXME: Warn, deprecate, and potentially remove this. 2754 CK_Penryn, 2755 //@} 2756 2757 /// \name Atom 2758 /// Atom processors 2759 //@{ 2760 CK_Bonnell, 2761 CK_Silvermont, 2762 CK_Goldmont, 2763 //@} 2764 2765 /// \name Nehalem 2766 /// Nehalem microarchitecture based processors. 2767 CK_Nehalem, 2768 2769 /// \name Westmere 2770 /// Westmere microarchitecture based processors. 2771 CK_Westmere, 2772 2773 /// \name Sandy Bridge 2774 /// Sandy Bridge microarchitecture based processors. 2775 CK_SandyBridge, 2776 2777 /// \name Ivy Bridge 2778 /// Ivy Bridge microarchitecture based processors. 2779 CK_IvyBridge, 2780 2781 /// \name Haswell 2782 /// Haswell microarchitecture based processors. 2783 CK_Haswell, 2784 2785 /// \name Broadwell 2786 /// Broadwell microarchitecture based processors. 2787 CK_Broadwell, 2788 2789 /// \name Skylake Client 2790 /// Skylake client microarchitecture based processors. 2791 CK_SkylakeClient, 2792 2793 /// \name Skylake Server 2794 /// Skylake server microarchitecture based processors. 2795 CK_SkylakeServer, 2796 2797 /// \name Cannonlake Client 2798 /// Cannonlake client microarchitecture based processors. 2799 CK_Cannonlake, 2800 2801 /// \name Knights Landing 2802 /// Knights Landing processor. 2803 CK_KNL, 2804 2805 /// \name Lakemont 2806 /// Lakemont microarchitecture based processors. 2807 CK_Lakemont, 2808 2809 /// \name K6 2810 /// K6 architecture processors. 2811 //@{ 2812 CK_K6, 2813 CK_K6_2, 2814 CK_K6_3, 2815 //@} 2816 2817 /// \name K7 2818 /// K7 architecture processors. 2819 //@{ 2820 CK_Athlon, 2821 CK_AthlonThunderbird, 2822 CK_Athlon4, 2823 CK_AthlonXP, 2824 CK_AthlonMP, 2825 //@} 2826 2827 /// \name K8 2828 /// K8 architecture processors. 2829 //@{ 2830 CK_Athlon64, 2831 CK_Athlon64SSE3, 2832 CK_AthlonFX, 2833 CK_K8, 2834 CK_K8SSE3, 2835 CK_Opteron, 2836 CK_OpteronSSE3, 2837 CK_AMDFAM10, 2838 //@} 2839 2840 /// \name Bobcat 2841 /// Bobcat architecture processors. 2842 //@{ 2843 CK_BTVER1, 2844 CK_BTVER2, 2845 //@} 2846 2847 /// \name Bulldozer 2848 /// Bulldozer architecture processors. 2849 //@{ 2850 CK_BDVER1, 2851 CK_BDVER2, 2852 CK_BDVER3, 2853 CK_BDVER4, 2854 //@} 2855 2856 /// \name zen 2857 /// Zen architecture processors. 2858 //@{ 2859 CK_ZNVER1, 2860 //@} 2861 2862 /// This specification is deprecated and will be removed in the future. 2863 /// Users should prefer \see CK_K8. 2864 // FIXME: Warn on this when the CPU is set to it. 2865 //@{ 2866 CK_x86_64, 2867 //@} 2868 2869 /// \name Geode 2870 /// Geode processors. 2871 //@{ 2872 CK_Geode 2873 //@} 2874 } CPU = CK_Generic; 2875 2876 CPUKind getCPUKind(StringRef CPU) const { 2877 return llvm::StringSwitch<CPUKind>(CPU) 2878 .Case("i386", CK_i386) 2879 .Case("i486", CK_i486) 2880 .Case("winchip-c6", CK_WinChipC6) 2881 .Case("winchip2", CK_WinChip2) 2882 .Case("c3", CK_C3) 2883 .Case("i586", CK_i586) 2884 .Case("pentium", CK_Pentium) 2885 .Case("pentium-mmx", CK_PentiumMMX) 2886 .Case("i686", CK_i686) 2887 .Case("pentiumpro", CK_PentiumPro) 2888 .Case("pentium2", CK_Pentium2) 2889 .Case("pentium3", CK_Pentium3) 2890 .Case("pentium3m", CK_Pentium3M) 2891 .Case("pentium-m", CK_PentiumM) 2892 .Case("c3-2", CK_C3_2) 2893 .Case("yonah", CK_Yonah) 2894 .Case("pentium4", CK_Pentium4) 2895 .Case("pentium4m", CK_Pentium4M) 2896 .Case("prescott", CK_Prescott) 2897 .Case("nocona", CK_Nocona) 2898 .Case("core2", CK_Core2) 2899 .Case("penryn", CK_Penryn) 2900 .Case("bonnell", CK_Bonnell) 2901 .Case("atom", CK_Bonnell) // Legacy name. 2902 .Case("silvermont", CK_Silvermont) 2903 .Case("slm", CK_Silvermont) // Legacy name. 2904 .Case("goldmont", CK_Goldmont) 2905 .Case("nehalem", CK_Nehalem) 2906 .Case("corei7", CK_Nehalem) // Legacy name. 2907 .Case("westmere", CK_Westmere) 2908 .Case("sandybridge", CK_SandyBridge) 2909 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2910 .Case("ivybridge", CK_IvyBridge) 2911 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2912 .Case("haswell", CK_Haswell) 2913 .Case("core-avx2", CK_Haswell) // Legacy name. 2914 .Case("broadwell", CK_Broadwell) 2915 .Case("skylake", CK_SkylakeClient) 2916 .Case("skylake-avx512", CK_SkylakeServer) 2917 .Case("skx", CK_SkylakeServer) // Legacy name. 2918 .Case("cannonlake", CK_Cannonlake) 2919 .Case("knl", CK_KNL) 2920 .Case("lakemont", CK_Lakemont) 2921 .Case("k6", CK_K6) 2922 .Case("k6-2", CK_K6_2) 2923 .Case("k6-3", CK_K6_3) 2924 .Case("athlon", CK_Athlon) 2925 .Case("athlon-tbird", CK_AthlonThunderbird) 2926 .Case("athlon-4", CK_Athlon4) 2927 .Case("athlon-xp", CK_AthlonXP) 2928 .Case("athlon-mp", CK_AthlonMP) 2929 .Case("athlon64", CK_Athlon64) 2930 .Case("athlon64-sse3", CK_Athlon64SSE3) 2931 .Case("athlon-fx", CK_AthlonFX) 2932 .Case("k8", CK_K8) 2933 .Case("k8-sse3", CK_K8SSE3) 2934 .Case("opteron", CK_Opteron) 2935 .Case("opteron-sse3", CK_OpteronSSE3) 2936 .Case("barcelona", CK_AMDFAM10) 2937 .Case("amdfam10", CK_AMDFAM10) 2938 .Case("btver1", CK_BTVER1) 2939 .Case("btver2", CK_BTVER2) 2940 .Case("bdver1", CK_BDVER1) 2941 .Case("bdver2", CK_BDVER2) 2942 .Case("bdver3", CK_BDVER3) 2943 .Case("bdver4", CK_BDVER4) 2944 .Case("znver1", CK_ZNVER1) 2945 .Case("x86-64", CK_x86_64) 2946 .Case("geode", CK_Geode) 2947 .Default(CK_Generic); 2948 } 2949 2950 enum FPMathKind { 2951 FP_Default, 2952 FP_SSE, 2953 FP_387 2954 } FPMath = FP_Default; 2955 2956 public: 2957 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2958 : TargetInfo(Triple) { 2959 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2960 } 2961 unsigned getFloatEvalMethod() const override { 2962 // X87 evaluates with 80 bits "long double" precision. 2963 return SSELevel == NoSSE ? 2 : 0; 2964 } 2965 ArrayRef<const char *> getGCCRegNames() const override { 2966 return llvm::makeArrayRef(GCCRegNames); 2967 } 2968 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2969 return None; 2970 } 2971 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2972 return llvm::makeArrayRef(AddlRegNames); 2973 } 2974 bool validateCpuSupports(StringRef Name) const override; 2975 bool validateAsmConstraint(const char *&Name, 2976 TargetInfo::ConstraintInfo &info) const override; 2977 2978 bool validateGlobalRegisterVariable(StringRef RegName, 2979 unsigned RegSize, 2980 bool &HasSizeMismatch) const override { 2981 // esp and ebp are the only 32-bit registers the x86 backend can currently 2982 // handle. 2983 if (RegName.equals("esp") || RegName.equals("ebp")) { 2984 // Check that the register size is 32-bit. 2985 HasSizeMismatch = RegSize != 32; 2986 return true; 2987 } 2988 2989 return false; 2990 } 2991 2992 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2993 2994 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2995 2996 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2997 2998 std::string convertConstraint(const char *&Constraint) const override; 2999 const char *getClobbers() const override { 3000 return "~{dirflag},~{fpsr},~{flags}"; 3001 } 3002 3003 StringRef getConstraintRegister(const StringRef &Constraint, 3004 const StringRef &Expression) const override { 3005 StringRef::iterator I, E; 3006 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 3007 if (isalpha(*I)) 3008 break; 3009 } 3010 if (I == E) 3011 return ""; 3012 switch (*I) { 3013 // For the register constraints, return the matching register name 3014 case 'a': 3015 return "ax"; 3016 case 'b': 3017 return "bx"; 3018 case 'c': 3019 return "cx"; 3020 case 'd': 3021 return "dx"; 3022 case 'S': 3023 return "si"; 3024 case 'D': 3025 return "di"; 3026 // In case the constraint is 'r' we need to return Expression 3027 case 'r': 3028 return Expression; 3029 default: 3030 // Default value if there is no constraint for the register 3031 return ""; 3032 } 3033 return ""; 3034 } 3035 3036 void getTargetDefines(const LangOptions &Opts, 3037 MacroBuilder &Builder) const override; 3038 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3039 bool Enabled); 3040 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3041 bool Enabled); 3042 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3043 bool Enabled); 3044 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3045 StringRef Name, bool Enabled) const override { 3046 setFeatureEnabledImpl(Features, Name, Enabled); 3047 } 3048 // This exists purely to cut down on the number of virtual calls in 3049 // initFeatureMap which calls this repeatedly. 3050 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3051 StringRef Name, bool Enabled); 3052 bool 3053 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3054 StringRef CPU, 3055 const std::vector<std::string> &FeaturesVec) const override; 3056 bool hasFeature(StringRef Feature) const override; 3057 bool handleTargetFeatures(std::vector<std::string> &Features, 3058 DiagnosticsEngine &Diags) override; 3059 StringRef getABI() const override { 3060 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3061 return "avx512"; 3062 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3063 return "avx"; 3064 if (getTriple().getArch() == llvm::Triple::x86 && 3065 MMX3DNowLevel == NoMMX3DNow) 3066 return "no-mmx"; 3067 return ""; 3068 } 3069 bool setCPU(const std::string &Name) override { 3070 CPU = getCPUKind(Name); 3071 3072 // Perform any per-CPU checks necessary to determine if this CPU is 3073 // acceptable. 3074 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3075 // invalid without explaining *why*. 3076 switch (CPU) { 3077 case CK_Generic: 3078 // No processor selected! 3079 return false; 3080 3081 case CK_i386: 3082 case CK_i486: 3083 case CK_WinChipC6: 3084 case CK_WinChip2: 3085 case CK_C3: 3086 case CK_i586: 3087 case CK_Pentium: 3088 case CK_PentiumMMX: 3089 case CK_i686: 3090 case CK_PentiumPro: 3091 case CK_Pentium2: 3092 case CK_Pentium3: 3093 case CK_Pentium3M: 3094 case CK_PentiumM: 3095 case CK_Yonah: 3096 case CK_C3_2: 3097 case CK_Pentium4: 3098 case CK_Pentium4M: 3099 case CK_Lakemont: 3100 case CK_Prescott: 3101 case CK_K6: 3102 case CK_K6_2: 3103 case CK_K6_3: 3104 case CK_Athlon: 3105 case CK_AthlonThunderbird: 3106 case CK_Athlon4: 3107 case CK_AthlonXP: 3108 case CK_AthlonMP: 3109 case CK_Geode: 3110 // Only accept certain architectures when compiling in 32-bit mode. 3111 if (getTriple().getArch() != llvm::Triple::x86) 3112 return false; 3113 3114 // Fallthrough 3115 case CK_Nocona: 3116 case CK_Core2: 3117 case CK_Penryn: 3118 case CK_Bonnell: 3119 case CK_Silvermont: 3120 case CK_Goldmont: 3121 case CK_Nehalem: 3122 case CK_Westmere: 3123 case CK_SandyBridge: 3124 case CK_IvyBridge: 3125 case CK_Haswell: 3126 case CK_Broadwell: 3127 case CK_SkylakeClient: 3128 case CK_SkylakeServer: 3129 case CK_Cannonlake: 3130 case CK_KNL: 3131 case CK_Athlon64: 3132 case CK_Athlon64SSE3: 3133 case CK_AthlonFX: 3134 case CK_K8: 3135 case CK_K8SSE3: 3136 case CK_Opteron: 3137 case CK_OpteronSSE3: 3138 case CK_AMDFAM10: 3139 case CK_BTVER1: 3140 case CK_BTVER2: 3141 case CK_BDVER1: 3142 case CK_BDVER2: 3143 case CK_BDVER3: 3144 case CK_BDVER4: 3145 case CK_ZNVER1: 3146 case CK_x86_64: 3147 return true; 3148 } 3149 llvm_unreachable("Unhandled CPU kind"); 3150 } 3151 3152 bool setFPMath(StringRef Name) override; 3153 3154 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3155 // Most of the non-ARM calling conventions are i386 conventions. 3156 switch (CC) { 3157 case CC_X86ThisCall: 3158 case CC_X86FastCall: 3159 case CC_X86StdCall: 3160 case CC_X86VectorCall: 3161 case CC_X86RegCall: 3162 case CC_C: 3163 case CC_Swift: 3164 case CC_X86Pascal: 3165 case CC_IntelOclBicc: 3166 case CC_OpenCLKernel: 3167 return CCCR_OK; 3168 default: 3169 return CCCR_Warning; 3170 } 3171 } 3172 3173 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3174 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3175 } 3176 3177 bool hasSjLjLowering() const override { 3178 return true; 3179 } 3180 3181 void setSupportedOpenCLOpts() override { 3182 getSupportedOpenCLOpts().supportAll(); 3183 } 3184 }; 3185 3186 bool X86TargetInfo::setFPMath(StringRef Name) { 3187 if (Name == "387") { 3188 FPMath = FP_387; 3189 return true; 3190 } 3191 if (Name == "sse") { 3192 FPMath = FP_SSE; 3193 return true; 3194 } 3195 return false; 3196 } 3197 3198 bool X86TargetInfo::initFeatureMap( 3199 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3200 const std::vector<std::string> &FeaturesVec) const { 3201 // FIXME: This *really* should not be here. 3202 // X86_64 always has SSE2. 3203 if (getTriple().getArch() == llvm::Triple::x86_64) 3204 setFeatureEnabledImpl(Features, "sse2", true); 3205 3206 const CPUKind Kind = getCPUKind(CPU); 3207 3208 // Enable X87 for all X86 processors but Lakemont. 3209 if (Kind != CK_Lakemont) 3210 setFeatureEnabledImpl(Features, "x87", true); 3211 3212 switch (Kind) { 3213 case CK_Generic: 3214 case CK_i386: 3215 case CK_i486: 3216 case CK_i586: 3217 case CK_Pentium: 3218 case CK_i686: 3219 case CK_PentiumPro: 3220 case CK_Lakemont: 3221 break; 3222 case CK_PentiumMMX: 3223 case CK_Pentium2: 3224 case CK_K6: 3225 case CK_WinChipC6: 3226 setFeatureEnabledImpl(Features, "mmx", true); 3227 break; 3228 case CK_Pentium3: 3229 case CK_Pentium3M: 3230 case CK_C3_2: 3231 setFeatureEnabledImpl(Features, "sse", true); 3232 setFeatureEnabledImpl(Features, "fxsr", true); 3233 break; 3234 case CK_PentiumM: 3235 case CK_Pentium4: 3236 case CK_Pentium4M: 3237 case CK_x86_64: 3238 setFeatureEnabledImpl(Features, "sse2", true); 3239 setFeatureEnabledImpl(Features, "fxsr", true); 3240 break; 3241 case CK_Yonah: 3242 case CK_Prescott: 3243 case CK_Nocona: 3244 setFeatureEnabledImpl(Features, "sse3", true); 3245 setFeatureEnabledImpl(Features, "fxsr", true); 3246 setFeatureEnabledImpl(Features, "cx16", true); 3247 break; 3248 case CK_Core2: 3249 setFeatureEnabledImpl(Features, "ssse3", true); 3250 setFeatureEnabledImpl(Features, "fxsr", true); 3251 setFeatureEnabledImpl(Features, "cx16", true); 3252 break; 3253 case CK_Penryn: 3254 setFeatureEnabledImpl(Features, "sse4.1", true); 3255 setFeatureEnabledImpl(Features, "fxsr", true); 3256 setFeatureEnabledImpl(Features, "cx16", true); 3257 break; 3258 case CK_Cannonlake: 3259 setFeatureEnabledImpl(Features, "avx512ifma", true); 3260 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3261 setFeatureEnabledImpl(Features, "sha", true); 3262 LLVM_FALLTHROUGH; 3263 case CK_SkylakeServer: 3264 setFeatureEnabledImpl(Features, "avx512f", true); 3265 setFeatureEnabledImpl(Features, "avx512cd", true); 3266 setFeatureEnabledImpl(Features, "avx512dq", true); 3267 setFeatureEnabledImpl(Features, "avx512bw", true); 3268 setFeatureEnabledImpl(Features, "avx512vl", true); 3269 setFeatureEnabledImpl(Features, "pku", true); 3270 setFeatureEnabledImpl(Features, "clwb", true); 3271 LLVM_FALLTHROUGH; 3272 case CK_SkylakeClient: 3273 setFeatureEnabledImpl(Features, "xsavec", true); 3274 setFeatureEnabledImpl(Features, "xsaves", true); 3275 setFeatureEnabledImpl(Features, "mpx", true); 3276 setFeatureEnabledImpl(Features, "sgx", true); 3277 setFeatureEnabledImpl(Features, "clflushopt", true); 3278 setFeatureEnabledImpl(Features, "rtm", true); 3279 LLVM_FALLTHROUGH; 3280 case CK_Broadwell: 3281 setFeatureEnabledImpl(Features, "rdseed", true); 3282 setFeatureEnabledImpl(Features, "adx", true); 3283 LLVM_FALLTHROUGH; 3284 case CK_Haswell: 3285 setFeatureEnabledImpl(Features, "avx2", true); 3286 setFeatureEnabledImpl(Features, "lzcnt", true); 3287 setFeatureEnabledImpl(Features, "bmi", true); 3288 setFeatureEnabledImpl(Features, "bmi2", true); 3289 setFeatureEnabledImpl(Features, "fma", true); 3290 setFeatureEnabledImpl(Features, "movbe", true); 3291 LLVM_FALLTHROUGH; 3292 case CK_IvyBridge: 3293 setFeatureEnabledImpl(Features, "rdrnd", true); 3294 setFeatureEnabledImpl(Features, "f16c", true); 3295 setFeatureEnabledImpl(Features, "fsgsbase", true); 3296 LLVM_FALLTHROUGH; 3297 case CK_SandyBridge: 3298 setFeatureEnabledImpl(Features, "avx", true); 3299 setFeatureEnabledImpl(Features, "xsave", true); 3300 setFeatureEnabledImpl(Features, "xsaveopt", true); 3301 LLVM_FALLTHROUGH; 3302 case CK_Westmere: 3303 setFeatureEnabledImpl(Features, "aes", true); 3304 setFeatureEnabledImpl(Features, "pclmul", true); 3305 LLVM_FALLTHROUGH; 3306 case CK_Nehalem: 3307 setFeatureEnabledImpl(Features, "sse4.2", true); 3308 setFeatureEnabledImpl(Features, "fxsr", true); 3309 setFeatureEnabledImpl(Features, "cx16", true); 3310 break; 3311 case CK_Goldmont: 3312 setFeatureEnabledImpl(Features, "sha", true); 3313 setFeatureEnabledImpl(Features, "rdrnd", true); 3314 setFeatureEnabledImpl(Features, "rdseed", true); 3315 setFeatureEnabledImpl(Features, "xsave", true); 3316 setFeatureEnabledImpl(Features, "xsaveopt", true); 3317 setFeatureEnabledImpl(Features, "xsavec", true); 3318 setFeatureEnabledImpl(Features, "xsaves", true); 3319 setFeatureEnabledImpl(Features, "clflushopt", true); 3320 setFeatureEnabledImpl(Features, "mpx", true); 3321 LLVM_FALLTHROUGH; 3322 case CK_Silvermont: 3323 setFeatureEnabledImpl(Features, "aes", true); 3324 setFeatureEnabledImpl(Features, "pclmul", true); 3325 setFeatureEnabledImpl(Features, "sse4.2", true); 3326 LLVM_FALLTHROUGH; 3327 case CK_Bonnell: 3328 setFeatureEnabledImpl(Features, "movbe", true); 3329 setFeatureEnabledImpl(Features, "ssse3", true); 3330 setFeatureEnabledImpl(Features, "fxsr", true); 3331 setFeatureEnabledImpl(Features, "cx16", true); 3332 break; 3333 case CK_KNL: 3334 setFeatureEnabledImpl(Features, "avx512f", true); 3335 setFeatureEnabledImpl(Features, "avx512cd", true); 3336 setFeatureEnabledImpl(Features, "avx512er", true); 3337 setFeatureEnabledImpl(Features, "avx512pf", true); 3338 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3339 setFeatureEnabledImpl(Features, "fxsr", true); 3340 setFeatureEnabledImpl(Features, "rdseed", true); 3341 setFeatureEnabledImpl(Features, "adx", true); 3342 setFeatureEnabledImpl(Features, "lzcnt", true); 3343 setFeatureEnabledImpl(Features, "bmi", true); 3344 setFeatureEnabledImpl(Features, "bmi2", true); 3345 setFeatureEnabledImpl(Features, "rtm", true); 3346 setFeatureEnabledImpl(Features, "fma", true); 3347 setFeatureEnabledImpl(Features, "rdrnd", true); 3348 setFeatureEnabledImpl(Features, "f16c", true); 3349 setFeatureEnabledImpl(Features, "fsgsbase", true); 3350 setFeatureEnabledImpl(Features, "aes", true); 3351 setFeatureEnabledImpl(Features, "pclmul", true); 3352 setFeatureEnabledImpl(Features, "cx16", true); 3353 setFeatureEnabledImpl(Features, "xsaveopt", true); 3354 setFeatureEnabledImpl(Features, "xsave", true); 3355 setFeatureEnabledImpl(Features, "movbe", true); 3356 break; 3357 case CK_K6_2: 3358 case CK_K6_3: 3359 case CK_WinChip2: 3360 case CK_C3: 3361 setFeatureEnabledImpl(Features, "3dnow", true); 3362 break; 3363 case CK_Athlon: 3364 case CK_AthlonThunderbird: 3365 case CK_Geode: 3366 setFeatureEnabledImpl(Features, "3dnowa", true); 3367 break; 3368 case CK_Athlon4: 3369 case CK_AthlonXP: 3370 case CK_AthlonMP: 3371 setFeatureEnabledImpl(Features, "sse", true); 3372 setFeatureEnabledImpl(Features, "3dnowa", true); 3373 setFeatureEnabledImpl(Features, "fxsr", true); 3374 break; 3375 case CK_K8: 3376 case CK_Opteron: 3377 case CK_Athlon64: 3378 case CK_AthlonFX: 3379 setFeatureEnabledImpl(Features, "sse2", true); 3380 setFeatureEnabledImpl(Features, "3dnowa", true); 3381 setFeatureEnabledImpl(Features, "fxsr", true); 3382 break; 3383 case CK_AMDFAM10: 3384 setFeatureEnabledImpl(Features, "sse4a", true); 3385 setFeatureEnabledImpl(Features, "lzcnt", true); 3386 setFeatureEnabledImpl(Features, "popcnt", true); 3387 LLVM_FALLTHROUGH; 3388 case CK_K8SSE3: 3389 case CK_OpteronSSE3: 3390 case CK_Athlon64SSE3: 3391 setFeatureEnabledImpl(Features, "sse3", true); 3392 setFeatureEnabledImpl(Features, "3dnowa", true); 3393 setFeatureEnabledImpl(Features, "fxsr", true); 3394 break; 3395 case CK_BTVER2: 3396 setFeatureEnabledImpl(Features, "avx", true); 3397 setFeatureEnabledImpl(Features, "aes", true); 3398 setFeatureEnabledImpl(Features, "pclmul", true); 3399 setFeatureEnabledImpl(Features, "bmi", true); 3400 setFeatureEnabledImpl(Features, "f16c", true); 3401 setFeatureEnabledImpl(Features, "xsaveopt", true); 3402 setFeatureEnabledImpl(Features, "movbe", true); 3403 LLVM_FALLTHROUGH; 3404 case CK_BTVER1: 3405 setFeatureEnabledImpl(Features, "ssse3", true); 3406 setFeatureEnabledImpl(Features, "sse4a", true); 3407 setFeatureEnabledImpl(Features, "lzcnt", true); 3408 setFeatureEnabledImpl(Features, "popcnt", true); 3409 setFeatureEnabledImpl(Features, "prfchw", true); 3410 setFeatureEnabledImpl(Features, "cx16", true); 3411 setFeatureEnabledImpl(Features, "fxsr", true); 3412 break; 3413 case CK_ZNVER1: 3414 setFeatureEnabledImpl(Features, "adx", true); 3415 setFeatureEnabledImpl(Features, "aes", true); 3416 setFeatureEnabledImpl(Features, "avx2", true); 3417 setFeatureEnabledImpl(Features, "bmi", true); 3418 setFeatureEnabledImpl(Features, "bmi2", true); 3419 setFeatureEnabledImpl(Features, "clflushopt", true); 3420 setFeatureEnabledImpl(Features, "clzero", true); 3421 setFeatureEnabledImpl(Features, "cx16", true); 3422 setFeatureEnabledImpl(Features, "f16c", true); 3423 setFeatureEnabledImpl(Features, "fma", true); 3424 setFeatureEnabledImpl(Features, "fsgsbase", true); 3425 setFeatureEnabledImpl(Features, "fxsr", true); 3426 setFeatureEnabledImpl(Features, "lzcnt", true); 3427 setFeatureEnabledImpl(Features, "mwaitx", true); 3428 setFeatureEnabledImpl(Features, "movbe", true); 3429 setFeatureEnabledImpl(Features, "pclmul", true); 3430 setFeatureEnabledImpl(Features, "popcnt", true); 3431 setFeatureEnabledImpl(Features, "prfchw", true); 3432 setFeatureEnabledImpl(Features, "rdrnd", true); 3433 setFeatureEnabledImpl(Features, "rdseed", true); 3434 setFeatureEnabledImpl(Features, "sha", true); 3435 setFeatureEnabledImpl(Features, "sse4a", true); 3436 setFeatureEnabledImpl(Features, "xsave", true); 3437 setFeatureEnabledImpl(Features, "xsavec", true); 3438 setFeatureEnabledImpl(Features, "xsaveopt", true); 3439 setFeatureEnabledImpl(Features, "xsaves", true); 3440 break; 3441 case CK_BDVER4: 3442 setFeatureEnabledImpl(Features, "avx2", true); 3443 setFeatureEnabledImpl(Features, "bmi2", true); 3444 setFeatureEnabledImpl(Features, "mwaitx", true); 3445 LLVM_FALLTHROUGH; 3446 case CK_BDVER3: 3447 setFeatureEnabledImpl(Features, "fsgsbase", true); 3448 setFeatureEnabledImpl(Features, "xsaveopt", true); 3449 LLVM_FALLTHROUGH; 3450 case CK_BDVER2: 3451 setFeatureEnabledImpl(Features, "bmi", true); 3452 setFeatureEnabledImpl(Features, "fma", true); 3453 setFeatureEnabledImpl(Features, "f16c", true); 3454 setFeatureEnabledImpl(Features, "tbm", true); 3455 LLVM_FALLTHROUGH; 3456 case CK_BDVER1: 3457 // xop implies avx, sse4a and fma4. 3458 setFeatureEnabledImpl(Features, "xop", true); 3459 setFeatureEnabledImpl(Features, "lwp", true); 3460 setFeatureEnabledImpl(Features, "lzcnt", true); 3461 setFeatureEnabledImpl(Features, "aes", true); 3462 setFeatureEnabledImpl(Features, "pclmul", true); 3463 setFeatureEnabledImpl(Features, "prfchw", true); 3464 setFeatureEnabledImpl(Features, "cx16", true); 3465 setFeatureEnabledImpl(Features, "fxsr", true); 3466 setFeatureEnabledImpl(Features, "xsave", true); 3467 break; 3468 } 3469 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3470 return false; 3471 3472 // Can't do this earlier because we need to be able to explicitly enable 3473 // or disable these features and the things that they depend upon. 3474 3475 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3476 auto I = Features.find("sse4.2"); 3477 if (I != Features.end() && I->getValue() && 3478 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3479 FeaturesVec.end()) 3480 Features["popcnt"] = true; 3481 3482 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3483 I = Features.find("3dnow"); 3484 if (I != Features.end() && I->getValue() && 3485 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3486 FeaturesVec.end()) 3487 Features["prfchw"] = true; 3488 3489 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3490 // then enable MMX. 3491 I = Features.find("sse"); 3492 if (I != Features.end() && I->getValue() && 3493 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3494 FeaturesVec.end()) 3495 Features["mmx"] = true; 3496 3497 return true; 3498 } 3499 3500 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3501 X86SSEEnum Level, bool Enabled) { 3502 if (Enabled) { 3503 switch (Level) { 3504 case AVX512F: 3505 Features["avx512f"] = true; 3506 LLVM_FALLTHROUGH; 3507 case AVX2: 3508 Features["avx2"] = true; 3509 LLVM_FALLTHROUGH; 3510 case AVX: 3511 Features["avx"] = true; 3512 Features["xsave"] = true; 3513 LLVM_FALLTHROUGH; 3514 case SSE42: 3515 Features["sse4.2"] = true; 3516 LLVM_FALLTHROUGH; 3517 case SSE41: 3518 Features["sse4.1"] = true; 3519 LLVM_FALLTHROUGH; 3520 case SSSE3: 3521 Features["ssse3"] = true; 3522 LLVM_FALLTHROUGH; 3523 case SSE3: 3524 Features["sse3"] = true; 3525 LLVM_FALLTHROUGH; 3526 case SSE2: 3527 Features["sse2"] = true; 3528 LLVM_FALLTHROUGH; 3529 case SSE1: 3530 Features["sse"] = true; 3531 LLVM_FALLTHROUGH; 3532 case NoSSE: 3533 break; 3534 } 3535 return; 3536 } 3537 3538 switch (Level) { 3539 case NoSSE: 3540 case SSE1: 3541 Features["sse"] = false; 3542 LLVM_FALLTHROUGH; 3543 case SSE2: 3544 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3545 Features["sha"] = false; 3546 LLVM_FALLTHROUGH; 3547 case SSE3: 3548 Features["sse3"] = false; 3549 setXOPLevel(Features, NoXOP, false); 3550 LLVM_FALLTHROUGH; 3551 case SSSE3: 3552 Features["ssse3"] = false; 3553 LLVM_FALLTHROUGH; 3554 case SSE41: 3555 Features["sse4.1"] = false; 3556 LLVM_FALLTHROUGH; 3557 case SSE42: 3558 Features["sse4.2"] = false; 3559 LLVM_FALLTHROUGH; 3560 case AVX: 3561 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3562 Features["xsaveopt"] = false; 3563 setXOPLevel(Features, FMA4, false); 3564 LLVM_FALLTHROUGH; 3565 case AVX2: 3566 Features["avx2"] = false; 3567 LLVM_FALLTHROUGH; 3568 case AVX512F: 3569 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3570 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3571 Features["avx512vl"] = Features["avx512vbmi"] = 3572 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3573 break; 3574 } 3575 } 3576 3577 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3578 MMX3DNowEnum Level, bool Enabled) { 3579 if (Enabled) { 3580 switch (Level) { 3581 case AMD3DNowAthlon: 3582 Features["3dnowa"] = true; 3583 LLVM_FALLTHROUGH; 3584 case AMD3DNow: 3585 Features["3dnow"] = true; 3586 LLVM_FALLTHROUGH; 3587 case MMX: 3588 Features["mmx"] = true; 3589 LLVM_FALLTHROUGH; 3590 case NoMMX3DNow: 3591 break; 3592 } 3593 return; 3594 } 3595 3596 switch (Level) { 3597 case NoMMX3DNow: 3598 case MMX: 3599 Features["mmx"] = false; 3600 LLVM_FALLTHROUGH; 3601 case AMD3DNow: 3602 Features["3dnow"] = false; 3603 LLVM_FALLTHROUGH; 3604 case AMD3DNowAthlon: 3605 Features["3dnowa"] = false; 3606 break; 3607 } 3608 } 3609 3610 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3611 bool Enabled) { 3612 if (Enabled) { 3613 switch (Level) { 3614 case XOP: 3615 Features["xop"] = true; 3616 LLVM_FALLTHROUGH; 3617 case FMA4: 3618 Features["fma4"] = true; 3619 setSSELevel(Features, AVX, true); 3620 LLVM_FALLTHROUGH; 3621 case SSE4A: 3622 Features["sse4a"] = true; 3623 setSSELevel(Features, SSE3, true); 3624 LLVM_FALLTHROUGH; 3625 case NoXOP: 3626 break; 3627 } 3628 return; 3629 } 3630 3631 switch (Level) { 3632 case NoXOP: 3633 case SSE4A: 3634 Features["sse4a"] = false; 3635 LLVM_FALLTHROUGH; 3636 case FMA4: 3637 Features["fma4"] = false; 3638 LLVM_FALLTHROUGH; 3639 case XOP: 3640 Features["xop"] = false; 3641 break; 3642 } 3643 } 3644 3645 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3646 StringRef Name, bool Enabled) { 3647 // This is a bit of a hack to deal with the sse4 target feature when used 3648 // as part of the target attribute. We handle sse4 correctly everywhere 3649 // else. See below for more information on how we handle the sse4 options. 3650 if (Name != "sse4") 3651 Features[Name] = Enabled; 3652 3653 if (Name == "mmx") { 3654 setMMXLevel(Features, MMX, Enabled); 3655 } else if (Name == "sse") { 3656 setSSELevel(Features, SSE1, Enabled); 3657 } else if (Name == "sse2") { 3658 setSSELevel(Features, SSE2, Enabled); 3659 } else if (Name == "sse3") { 3660 setSSELevel(Features, SSE3, Enabled); 3661 } else if (Name == "ssse3") { 3662 setSSELevel(Features, SSSE3, Enabled); 3663 } else if (Name == "sse4.2") { 3664 setSSELevel(Features, SSE42, Enabled); 3665 } else if (Name == "sse4.1") { 3666 setSSELevel(Features, SSE41, Enabled); 3667 } else if (Name == "3dnow") { 3668 setMMXLevel(Features, AMD3DNow, Enabled); 3669 } else if (Name == "3dnowa") { 3670 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3671 } else if (Name == "aes") { 3672 if (Enabled) 3673 setSSELevel(Features, SSE2, Enabled); 3674 } else if (Name == "pclmul") { 3675 if (Enabled) 3676 setSSELevel(Features, SSE2, Enabled); 3677 } else if (Name == "avx") { 3678 setSSELevel(Features, AVX, Enabled); 3679 } else if (Name == "avx2") { 3680 setSSELevel(Features, AVX2, Enabled); 3681 } else if (Name == "avx512f") { 3682 setSSELevel(Features, AVX512F, Enabled); 3683 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3684 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3685 Name == "avx512vbmi" || Name == "avx512ifma" || 3686 Name == "avx512vpopcntdq") { 3687 if (Enabled) 3688 setSSELevel(Features, AVX512F, Enabled); 3689 // Enable BWI instruction if VBMI is being enabled. 3690 if (Name == "avx512vbmi" && Enabled) 3691 Features["avx512bw"] = true; 3692 // Also disable VBMI if BWI is being disabled. 3693 if (Name == "avx512bw" && !Enabled) 3694 Features["avx512vbmi"] = false; 3695 } else if (Name == "fma") { 3696 if (Enabled) 3697 setSSELevel(Features, AVX, Enabled); 3698 } else if (Name == "fma4") { 3699 setXOPLevel(Features, FMA4, Enabled); 3700 } else if (Name == "xop") { 3701 setXOPLevel(Features, XOP, Enabled); 3702 } else if (Name == "sse4a") { 3703 setXOPLevel(Features, SSE4A, Enabled); 3704 } else if (Name == "f16c") { 3705 if (Enabled) 3706 setSSELevel(Features, AVX, Enabled); 3707 } else if (Name == "sha") { 3708 if (Enabled) 3709 setSSELevel(Features, SSE2, Enabled); 3710 } else if (Name == "sse4") { 3711 // We can get here via the __target__ attribute since that's not controlled 3712 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3713 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3714 // disabled. 3715 if (Enabled) 3716 setSSELevel(Features, SSE42, Enabled); 3717 else 3718 setSSELevel(Features, SSE41, Enabled); 3719 } else if (Name == "xsave") { 3720 if (!Enabled) 3721 Features["xsaveopt"] = false; 3722 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3723 if (Enabled) 3724 Features["xsave"] = true; 3725 } 3726 } 3727 3728 /// handleTargetFeatures - Perform initialization based on the user 3729 /// configured set of features. 3730 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3731 DiagnosticsEngine &Diags) { 3732 for (const auto &Feature : Features) { 3733 if (Feature[0] != '+') 3734 continue; 3735 3736 if (Feature == "+aes") { 3737 HasAES = true; 3738 } else if (Feature == "+pclmul") { 3739 HasPCLMUL = true; 3740 } else if (Feature == "+lzcnt") { 3741 HasLZCNT = true; 3742 } else if (Feature == "+rdrnd") { 3743 HasRDRND = true; 3744 } else if (Feature == "+fsgsbase") { 3745 HasFSGSBASE = true; 3746 } else if (Feature == "+bmi") { 3747 HasBMI = true; 3748 } else if (Feature == "+bmi2") { 3749 HasBMI2 = true; 3750 } else if (Feature == "+popcnt") { 3751 HasPOPCNT = true; 3752 } else if (Feature == "+rtm") { 3753 HasRTM = true; 3754 } else if (Feature == "+prfchw") { 3755 HasPRFCHW = true; 3756 } else if (Feature == "+rdseed") { 3757 HasRDSEED = true; 3758 } else if (Feature == "+adx") { 3759 HasADX = true; 3760 } else if (Feature == "+tbm") { 3761 HasTBM = true; 3762 } else if (Feature == "+lwp") { 3763 HasLWP = true; 3764 } else if (Feature == "+fma") { 3765 HasFMA = true; 3766 } else if (Feature == "+f16c") { 3767 HasF16C = true; 3768 } else if (Feature == "+avx512cd") { 3769 HasAVX512CD = true; 3770 } else if (Feature == "+avx512vpopcntdq") { 3771 HasAVX512VPOPCNTDQ = true; 3772 } else if (Feature == "+avx512er") { 3773 HasAVX512ER = true; 3774 } else if (Feature == "+avx512pf") { 3775 HasAVX512PF = true; 3776 } else if (Feature == "+avx512dq") { 3777 HasAVX512DQ = true; 3778 } else if (Feature == "+avx512bw") { 3779 HasAVX512BW = true; 3780 } else if (Feature == "+avx512vl") { 3781 HasAVX512VL = true; 3782 } else if (Feature == "+avx512vbmi") { 3783 HasAVX512VBMI = true; 3784 } else if (Feature == "+avx512ifma") { 3785 HasAVX512IFMA = true; 3786 } else if (Feature == "+sha") { 3787 HasSHA = true; 3788 } else if (Feature == "+mpx") { 3789 HasMPX = true; 3790 } else if (Feature == "+movbe") { 3791 HasMOVBE = true; 3792 } else if (Feature == "+sgx") { 3793 HasSGX = true; 3794 } else if (Feature == "+cx16") { 3795 HasCX16 = true; 3796 } else if (Feature == "+fxsr") { 3797 HasFXSR = true; 3798 } else if (Feature == "+xsave") { 3799 HasXSAVE = true; 3800 } else if (Feature == "+xsaveopt") { 3801 HasXSAVEOPT = true; 3802 } else if (Feature == "+xsavec") { 3803 HasXSAVEC = true; 3804 } else if (Feature == "+xsaves") { 3805 HasXSAVES = true; 3806 } else if (Feature == "+mwaitx") { 3807 HasMWAITX = true; 3808 } else if (Feature == "+pku") { 3809 HasPKU = true; 3810 } else if (Feature == "+clflushopt") { 3811 HasCLFLUSHOPT = true; 3812 } else if (Feature == "+clwb") { 3813 HasCLWB = true; 3814 } else if (Feature == "+prefetchwt1") { 3815 HasPREFETCHWT1 = true; 3816 } else if (Feature == "+clzero") { 3817 HasCLZERO = true; 3818 } 3819 3820 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3821 .Case("+avx512f", AVX512F) 3822 .Case("+avx2", AVX2) 3823 .Case("+avx", AVX) 3824 .Case("+sse4.2", SSE42) 3825 .Case("+sse4.1", SSE41) 3826 .Case("+ssse3", SSSE3) 3827 .Case("+sse3", SSE3) 3828 .Case("+sse2", SSE2) 3829 .Case("+sse", SSE1) 3830 .Default(NoSSE); 3831 SSELevel = std::max(SSELevel, Level); 3832 3833 MMX3DNowEnum ThreeDNowLevel = 3834 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3835 .Case("+3dnowa", AMD3DNowAthlon) 3836 .Case("+3dnow", AMD3DNow) 3837 .Case("+mmx", MMX) 3838 .Default(NoMMX3DNow); 3839 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3840 3841 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3842 .Case("+xop", XOP) 3843 .Case("+fma4", FMA4) 3844 .Case("+sse4a", SSE4A) 3845 .Default(NoXOP); 3846 XOPLevel = std::max(XOPLevel, XLevel); 3847 } 3848 3849 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3850 // matches the selected sse level. 3851 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3852 (FPMath == FP_387 && SSELevel >= SSE1)) { 3853 Diags.Report(diag::err_target_unsupported_fpmath) << 3854 (FPMath == FP_SSE ? "sse" : "387"); 3855 return false; 3856 } 3857 3858 SimdDefaultAlign = 3859 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3860 return true; 3861 } 3862 3863 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3864 /// definitions for this particular subtarget. 3865 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3866 MacroBuilder &Builder) const { 3867 // Target identification. 3868 if (getTriple().getArch() == llvm::Triple::x86_64) { 3869 Builder.defineMacro("__amd64__"); 3870 Builder.defineMacro("__amd64"); 3871 Builder.defineMacro("__x86_64"); 3872 Builder.defineMacro("__x86_64__"); 3873 if (getTriple().getArchName() == "x86_64h") { 3874 Builder.defineMacro("__x86_64h"); 3875 Builder.defineMacro("__x86_64h__"); 3876 } 3877 } else { 3878 DefineStd(Builder, "i386", Opts); 3879 } 3880 3881 // Subtarget options. 3882 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3883 // truly should be based on -mtune options. 3884 switch (CPU) { 3885 case CK_Generic: 3886 break; 3887 case CK_i386: 3888 // The rest are coming from the i386 define above. 3889 Builder.defineMacro("__tune_i386__"); 3890 break; 3891 case CK_i486: 3892 case CK_WinChipC6: 3893 case CK_WinChip2: 3894 case CK_C3: 3895 defineCPUMacros(Builder, "i486"); 3896 break; 3897 case CK_PentiumMMX: 3898 Builder.defineMacro("__pentium_mmx__"); 3899 Builder.defineMacro("__tune_pentium_mmx__"); 3900 LLVM_FALLTHROUGH; 3901 case CK_i586: 3902 case CK_Pentium: 3903 defineCPUMacros(Builder, "i586"); 3904 defineCPUMacros(Builder, "pentium"); 3905 break; 3906 case CK_Pentium3: 3907 case CK_Pentium3M: 3908 case CK_PentiumM: 3909 Builder.defineMacro("__tune_pentium3__"); 3910 LLVM_FALLTHROUGH; 3911 case CK_Pentium2: 3912 case CK_C3_2: 3913 Builder.defineMacro("__tune_pentium2__"); 3914 LLVM_FALLTHROUGH; 3915 case CK_PentiumPro: 3916 Builder.defineMacro("__tune_i686__"); 3917 Builder.defineMacro("__tune_pentiumpro__"); 3918 LLVM_FALLTHROUGH; 3919 case CK_i686: 3920 Builder.defineMacro("__i686"); 3921 Builder.defineMacro("__i686__"); 3922 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3923 Builder.defineMacro("__pentiumpro"); 3924 Builder.defineMacro("__pentiumpro__"); 3925 break; 3926 case CK_Pentium4: 3927 case CK_Pentium4M: 3928 defineCPUMacros(Builder, "pentium4"); 3929 break; 3930 case CK_Yonah: 3931 case CK_Prescott: 3932 case CK_Nocona: 3933 defineCPUMacros(Builder, "nocona"); 3934 break; 3935 case CK_Core2: 3936 case CK_Penryn: 3937 defineCPUMacros(Builder, "core2"); 3938 break; 3939 case CK_Bonnell: 3940 defineCPUMacros(Builder, "atom"); 3941 break; 3942 case CK_Silvermont: 3943 defineCPUMacros(Builder, "slm"); 3944 break; 3945 case CK_Goldmont: 3946 defineCPUMacros(Builder, "goldmont"); 3947 break; 3948 case CK_Nehalem: 3949 case CK_Westmere: 3950 case CK_SandyBridge: 3951 case CK_IvyBridge: 3952 case CK_Haswell: 3953 case CK_Broadwell: 3954 case CK_SkylakeClient: 3955 // FIXME: Historically, we defined this legacy name, it would be nice to 3956 // remove it at some point. We've never exposed fine-grained names for 3957 // recent primary x86 CPUs, and we should keep it that way. 3958 defineCPUMacros(Builder, "corei7"); 3959 break; 3960 case CK_SkylakeServer: 3961 defineCPUMacros(Builder, "skx"); 3962 break; 3963 case CK_Cannonlake: 3964 break; 3965 case CK_KNL: 3966 defineCPUMacros(Builder, "knl"); 3967 break; 3968 case CK_Lakemont: 3969 Builder.defineMacro("__tune_lakemont__"); 3970 break; 3971 case CK_K6_2: 3972 Builder.defineMacro("__k6_2__"); 3973 Builder.defineMacro("__tune_k6_2__"); 3974 LLVM_FALLTHROUGH; 3975 case CK_K6_3: 3976 if (CPU != CK_K6_2) { // In case of fallthrough 3977 // FIXME: GCC may be enabling these in cases where some other k6 3978 // architecture is specified but -m3dnow is explicitly provided. The 3979 // exact semantics need to be determined and emulated here. 3980 Builder.defineMacro("__k6_3__"); 3981 Builder.defineMacro("__tune_k6_3__"); 3982 } 3983 LLVM_FALLTHROUGH; 3984 case CK_K6: 3985 defineCPUMacros(Builder, "k6"); 3986 break; 3987 case CK_Athlon: 3988 case CK_AthlonThunderbird: 3989 case CK_Athlon4: 3990 case CK_AthlonXP: 3991 case CK_AthlonMP: 3992 defineCPUMacros(Builder, "athlon"); 3993 if (SSELevel != NoSSE) { 3994 Builder.defineMacro("__athlon_sse__"); 3995 Builder.defineMacro("__tune_athlon_sse__"); 3996 } 3997 break; 3998 case CK_K8: 3999 case CK_K8SSE3: 4000 case CK_x86_64: 4001 case CK_Opteron: 4002 case CK_OpteronSSE3: 4003 case CK_Athlon64: 4004 case CK_Athlon64SSE3: 4005 case CK_AthlonFX: 4006 defineCPUMacros(Builder, "k8"); 4007 break; 4008 case CK_AMDFAM10: 4009 defineCPUMacros(Builder, "amdfam10"); 4010 break; 4011 case CK_BTVER1: 4012 defineCPUMacros(Builder, "btver1"); 4013 break; 4014 case CK_BTVER2: 4015 defineCPUMacros(Builder, "btver2"); 4016 break; 4017 case CK_BDVER1: 4018 defineCPUMacros(Builder, "bdver1"); 4019 break; 4020 case CK_BDVER2: 4021 defineCPUMacros(Builder, "bdver2"); 4022 break; 4023 case CK_BDVER3: 4024 defineCPUMacros(Builder, "bdver3"); 4025 break; 4026 case CK_BDVER4: 4027 defineCPUMacros(Builder, "bdver4"); 4028 break; 4029 case CK_ZNVER1: 4030 defineCPUMacros(Builder, "znver1"); 4031 break; 4032 case CK_Geode: 4033 defineCPUMacros(Builder, "geode"); 4034 break; 4035 } 4036 4037 // Target properties. 4038 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4039 4040 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 4041 // functions in glibc header files that use FP Stack inline asm which the 4042 // backend can't deal with (PR879). 4043 Builder.defineMacro("__NO_MATH_INLINES"); 4044 4045 if (HasAES) 4046 Builder.defineMacro("__AES__"); 4047 4048 if (HasPCLMUL) 4049 Builder.defineMacro("__PCLMUL__"); 4050 4051 if (HasLZCNT) 4052 Builder.defineMacro("__LZCNT__"); 4053 4054 if (HasRDRND) 4055 Builder.defineMacro("__RDRND__"); 4056 4057 if (HasFSGSBASE) 4058 Builder.defineMacro("__FSGSBASE__"); 4059 4060 if (HasBMI) 4061 Builder.defineMacro("__BMI__"); 4062 4063 if (HasBMI2) 4064 Builder.defineMacro("__BMI2__"); 4065 4066 if (HasPOPCNT) 4067 Builder.defineMacro("__POPCNT__"); 4068 4069 if (HasRTM) 4070 Builder.defineMacro("__RTM__"); 4071 4072 if (HasPRFCHW) 4073 Builder.defineMacro("__PRFCHW__"); 4074 4075 if (HasRDSEED) 4076 Builder.defineMacro("__RDSEED__"); 4077 4078 if (HasADX) 4079 Builder.defineMacro("__ADX__"); 4080 4081 if (HasTBM) 4082 Builder.defineMacro("__TBM__"); 4083 4084 if (HasLWP) 4085 Builder.defineMacro("__LWP__"); 4086 4087 if (HasMWAITX) 4088 Builder.defineMacro("__MWAITX__"); 4089 4090 switch (XOPLevel) { 4091 case XOP: 4092 Builder.defineMacro("__XOP__"); 4093 LLVM_FALLTHROUGH; 4094 case FMA4: 4095 Builder.defineMacro("__FMA4__"); 4096 LLVM_FALLTHROUGH; 4097 case SSE4A: 4098 Builder.defineMacro("__SSE4A__"); 4099 LLVM_FALLTHROUGH; 4100 case NoXOP: 4101 break; 4102 } 4103 4104 if (HasFMA) 4105 Builder.defineMacro("__FMA__"); 4106 4107 if (HasF16C) 4108 Builder.defineMacro("__F16C__"); 4109 4110 if (HasAVX512CD) 4111 Builder.defineMacro("__AVX512CD__"); 4112 if (HasAVX512VPOPCNTDQ) 4113 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4114 if (HasAVX512ER) 4115 Builder.defineMacro("__AVX512ER__"); 4116 if (HasAVX512PF) 4117 Builder.defineMacro("__AVX512PF__"); 4118 if (HasAVX512DQ) 4119 Builder.defineMacro("__AVX512DQ__"); 4120 if (HasAVX512BW) 4121 Builder.defineMacro("__AVX512BW__"); 4122 if (HasAVX512VL) 4123 Builder.defineMacro("__AVX512VL__"); 4124 if (HasAVX512VBMI) 4125 Builder.defineMacro("__AVX512VBMI__"); 4126 if (HasAVX512IFMA) 4127 Builder.defineMacro("__AVX512IFMA__"); 4128 4129 if (HasSHA) 4130 Builder.defineMacro("__SHA__"); 4131 4132 if (HasFXSR) 4133 Builder.defineMacro("__FXSR__"); 4134 if (HasXSAVE) 4135 Builder.defineMacro("__XSAVE__"); 4136 if (HasXSAVEOPT) 4137 Builder.defineMacro("__XSAVEOPT__"); 4138 if (HasXSAVEC) 4139 Builder.defineMacro("__XSAVEC__"); 4140 if (HasXSAVES) 4141 Builder.defineMacro("__XSAVES__"); 4142 if (HasPKU) 4143 Builder.defineMacro("__PKU__"); 4144 if (HasCX16) 4145 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4146 if (HasCLFLUSHOPT) 4147 Builder.defineMacro("__CLFLUSHOPT__"); 4148 if (HasCLWB) 4149 Builder.defineMacro("__CLWB__"); 4150 if (HasMPX) 4151 Builder.defineMacro("__MPX__"); 4152 if (HasSGX) 4153 Builder.defineMacro("__SGX__"); 4154 if (HasPREFETCHWT1) 4155 Builder.defineMacro("__PREFETCHWT1__"); 4156 if (HasCLZERO) 4157 Builder.defineMacro("__CLZERO__"); 4158 4159 // Each case falls through to the previous one here. 4160 switch (SSELevel) { 4161 case AVX512F: 4162 Builder.defineMacro("__AVX512F__"); 4163 LLVM_FALLTHROUGH; 4164 case AVX2: 4165 Builder.defineMacro("__AVX2__"); 4166 LLVM_FALLTHROUGH; 4167 case AVX: 4168 Builder.defineMacro("__AVX__"); 4169 LLVM_FALLTHROUGH; 4170 case SSE42: 4171 Builder.defineMacro("__SSE4_2__"); 4172 LLVM_FALLTHROUGH; 4173 case SSE41: 4174 Builder.defineMacro("__SSE4_1__"); 4175 LLVM_FALLTHROUGH; 4176 case SSSE3: 4177 Builder.defineMacro("__SSSE3__"); 4178 LLVM_FALLTHROUGH; 4179 case SSE3: 4180 Builder.defineMacro("__SSE3__"); 4181 LLVM_FALLTHROUGH; 4182 case SSE2: 4183 Builder.defineMacro("__SSE2__"); 4184 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4185 LLVM_FALLTHROUGH; 4186 case SSE1: 4187 Builder.defineMacro("__SSE__"); 4188 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4189 LLVM_FALLTHROUGH; 4190 case NoSSE: 4191 break; 4192 } 4193 4194 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4195 switch (SSELevel) { 4196 case AVX512F: 4197 case AVX2: 4198 case AVX: 4199 case SSE42: 4200 case SSE41: 4201 case SSSE3: 4202 case SSE3: 4203 case SSE2: 4204 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4205 break; 4206 case SSE1: 4207 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4208 break; 4209 default: 4210 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4211 break; 4212 } 4213 } 4214 4215 // Each case falls through to the previous one here. 4216 switch (MMX3DNowLevel) { 4217 case AMD3DNowAthlon: 4218 Builder.defineMacro("__3dNOW_A__"); 4219 LLVM_FALLTHROUGH; 4220 case AMD3DNow: 4221 Builder.defineMacro("__3dNOW__"); 4222 LLVM_FALLTHROUGH; 4223 case MMX: 4224 Builder.defineMacro("__MMX__"); 4225 LLVM_FALLTHROUGH; 4226 case NoMMX3DNow: 4227 break; 4228 } 4229 4230 if (CPU >= CK_i486) { 4231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4233 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4234 } 4235 if (CPU >= CK_i586) 4236 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4237 4238 if (HasFloat128) 4239 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4240 } 4241 4242 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4243 return llvm::StringSwitch<bool>(Feature) 4244 .Case("aes", HasAES) 4245 .Case("avx", SSELevel >= AVX) 4246 .Case("avx2", SSELevel >= AVX2) 4247 .Case("avx512f", SSELevel >= AVX512F) 4248 .Case("avx512cd", HasAVX512CD) 4249 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4250 .Case("avx512er", HasAVX512ER) 4251 .Case("avx512pf", HasAVX512PF) 4252 .Case("avx512dq", HasAVX512DQ) 4253 .Case("avx512bw", HasAVX512BW) 4254 .Case("avx512vl", HasAVX512VL) 4255 .Case("avx512vbmi", HasAVX512VBMI) 4256 .Case("avx512ifma", HasAVX512IFMA) 4257 .Case("bmi", HasBMI) 4258 .Case("bmi2", HasBMI2) 4259 .Case("clflushopt", HasCLFLUSHOPT) 4260 .Case("clwb", HasCLWB) 4261 .Case("clzero", HasCLZERO) 4262 .Case("cx16", HasCX16) 4263 .Case("f16c", HasF16C) 4264 .Case("fma", HasFMA) 4265 .Case("fma4", XOPLevel >= FMA4) 4266 .Case("fsgsbase", HasFSGSBASE) 4267 .Case("fxsr", HasFXSR) 4268 .Case("lzcnt", HasLZCNT) 4269 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4270 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4271 .Case("mmx", MMX3DNowLevel >= MMX) 4272 .Case("movbe", HasMOVBE) 4273 .Case("mpx", HasMPX) 4274 .Case("pclmul", HasPCLMUL) 4275 .Case("pku", HasPKU) 4276 .Case("popcnt", HasPOPCNT) 4277 .Case("prefetchwt1", HasPREFETCHWT1) 4278 .Case("prfchw", HasPRFCHW) 4279 .Case("rdrnd", HasRDRND) 4280 .Case("rdseed", HasRDSEED) 4281 .Case("rtm", HasRTM) 4282 .Case("sgx", HasSGX) 4283 .Case("sha", HasSHA) 4284 .Case("sse", SSELevel >= SSE1) 4285 .Case("sse2", SSELevel >= SSE2) 4286 .Case("sse3", SSELevel >= SSE3) 4287 .Case("ssse3", SSELevel >= SSSE3) 4288 .Case("sse4.1", SSELevel >= SSE41) 4289 .Case("sse4.2", SSELevel >= SSE42) 4290 .Case("sse4a", XOPLevel >= SSE4A) 4291 .Case("tbm", HasTBM) 4292 .Case("lwp", HasLWP) 4293 .Case("x86", true) 4294 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4295 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4296 .Case("xop", XOPLevel >= XOP) 4297 .Case("xsave", HasXSAVE) 4298 .Case("xsavec", HasXSAVEC) 4299 .Case("xsaves", HasXSAVES) 4300 .Case("xsaveopt", HasXSAVEOPT) 4301 .Default(false); 4302 } 4303 4304 // We can't use a generic validation scheme for the features accepted here 4305 // versus subtarget features accepted in the target attribute because the 4306 // bitfield structure that's initialized in the runtime only supports the 4307 // below currently rather than the full range of subtarget features. (See 4308 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4309 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4310 return llvm::StringSwitch<bool>(FeatureStr) 4311 .Case("cmov", true) 4312 .Case("mmx", true) 4313 .Case("popcnt", true) 4314 .Case("sse", true) 4315 .Case("sse2", true) 4316 .Case("sse3", true) 4317 .Case("ssse3", true) 4318 .Case("sse4.1", true) 4319 .Case("sse4.2", true) 4320 .Case("avx", true) 4321 .Case("avx2", true) 4322 .Case("sse4a", true) 4323 .Case("fma4", true) 4324 .Case("xop", true) 4325 .Case("fma", true) 4326 .Case("avx512f", true) 4327 .Case("bmi", true) 4328 .Case("bmi2", true) 4329 .Case("aes", true) 4330 .Case("pclmul", true) 4331 .Case("avx512vl", true) 4332 .Case("avx512bw", true) 4333 .Case("avx512dq", true) 4334 .Case("avx512cd", true) 4335 .Case("avx512vpopcntdq", true) 4336 .Case("avx512er", true) 4337 .Case("avx512pf", true) 4338 .Case("avx512vbmi", true) 4339 .Case("avx512ifma", true) 4340 .Default(false); 4341 } 4342 4343 bool 4344 X86TargetInfo::validateAsmConstraint(const char *&Name, 4345 TargetInfo::ConstraintInfo &Info) const { 4346 switch (*Name) { 4347 default: return false; 4348 // Constant constraints. 4349 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4350 // instructions. 4351 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4352 // x86_64 instructions. 4353 case 's': 4354 Info.setRequiresImmediate(); 4355 return true; 4356 case 'I': 4357 Info.setRequiresImmediate(0, 31); 4358 return true; 4359 case 'J': 4360 Info.setRequiresImmediate(0, 63); 4361 return true; 4362 case 'K': 4363 Info.setRequiresImmediate(-128, 127); 4364 return true; 4365 case 'L': 4366 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4367 return true; 4368 case 'M': 4369 Info.setRequiresImmediate(0, 3); 4370 return true; 4371 case 'N': 4372 Info.setRequiresImmediate(0, 255); 4373 return true; 4374 case 'O': 4375 Info.setRequiresImmediate(0, 127); 4376 return true; 4377 // Register constraints. 4378 case 'Y': // 'Y' is the first character for several 2-character constraints. 4379 // Shift the pointer to the second character of the constraint. 4380 Name++; 4381 switch (*Name) { 4382 default: 4383 return false; 4384 case '0': // First SSE register. 4385 case 't': // Any SSE register, when SSE2 is enabled. 4386 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4387 case 'm': // Any MMX register, when inter-unit moves enabled. 4388 case 'k': // AVX512 arch mask registers: k1-k7. 4389 Info.setAllowsRegister(); 4390 return true; 4391 } 4392 case 'f': // Any x87 floating point stack register. 4393 // Constraint 'f' cannot be used for output operands. 4394 if (Info.ConstraintStr[0] == '=') 4395 return false; 4396 Info.setAllowsRegister(); 4397 return true; 4398 case 'a': // eax. 4399 case 'b': // ebx. 4400 case 'c': // ecx. 4401 case 'd': // edx. 4402 case 'S': // esi. 4403 case 'D': // edi. 4404 case 'A': // edx:eax. 4405 case 't': // Top of floating point stack. 4406 case 'u': // Second from top of floating point stack. 4407 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4408 case 'y': // Any MMX register. 4409 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4410 case 'x': // Any SSE register. 4411 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4412 // for intermideate k reg operations). 4413 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4414 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4415 case 'l': // "Index" registers: any general register that can be used as an 4416 // index in a base+index memory access. 4417 Info.setAllowsRegister(); 4418 return true; 4419 // Floating point constant constraints. 4420 case 'C': // SSE floating point constant. 4421 case 'G': // x87 floating point constant. 4422 return true; 4423 } 4424 } 4425 4426 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4427 unsigned Size) const { 4428 // Strip off constraint modifiers. 4429 while (Constraint[0] == '=' || 4430 Constraint[0] == '+' || 4431 Constraint[0] == '&') 4432 Constraint = Constraint.substr(1); 4433 4434 return validateOperandSize(Constraint, Size); 4435 } 4436 4437 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4438 unsigned Size) const { 4439 return validateOperandSize(Constraint, Size); 4440 } 4441 4442 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4443 unsigned Size) const { 4444 switch (Constraint[0]) { 4445 default: break; 4446 case 'k': 4447 // Registers k0-k7 (AVX512) size limit is 64 bit. 4448 case 'y': 4449 return Size <= 64; 4450 case 'f': 4451 case 't': 4452 case 'u': 4453 return Size <= 128; 4454 case 'v': 4455 case 'x': 4456 if (SSELevel >= AVX512F) 4457 // 512-bit zmm registers can be used if target supports AVX512F. 4458 return Size <= 512U; 4459 else if (SSELevel >= AVX) 4460 // 256-bit ymm registers can be used if target supports AVX. 4461 return Size <= 256U; 4462 return Size <= 128U; 4463 case 'Y': 4464 // 'Y' is the first character for several 2-character constraints. 4465 switch (Constraint[1]) { 4466 default: break; 4467 case 'm': 4468 // 'Ym' is synonymous with 'y'. 4469 case 'k': 4470 return Size <= 64; 4471 case 'i': 4472 case 't': 4473 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4474 if (SSELevel >= AVX512F) 4475 return Size <= 512U; 4476 else if (SSELevel >= AVX) 4477 return Size <= 256U; 4478 return SSELevel >= SSE2 && Size <= 128U; 4479 } 4480 4481 } 4482 4483 return true; 4484 } 4485 4486 std::string 4487 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4488 switch (*Constraint) { 4489 case 'a': return std::string("{ax}"); 4490 case 'b': return std::string("{bx}"); 4491 case 'c': return std::string("{cx}"); 4492 case 'd': return std::string("{dx}"); 4493 case 'S': return std::string("{si}"); 4494 case 'D': return std::string("{di}"); 4495 case 'p': // address 4496 return std::string("im"); 4497 case 't': // top of floating point stack. 4498 return std::string("{st}"); 4499 case 'u': // second from top of floating point stack. 4500 return std::string("{st(1)}"); // second from top of floating point stack. 4501 case 'Y': 4502 switch (Constraint[1]) { 4503 default: 4504 // Break from inner switch and fall through (copy single char), 4505 // continue parsing after copying the current constraint into 4506 // the return string. 4507 break; 4508 case 'k': 4509 // "^" hints llvm that this is a 2 letter constraint. 4510 // "Constraint++" is used to promote the string iterator 4511 // to the next constraint. 4512 return std::string("^") + std::string(Constraint++, 2); 4513 } 4514 LLVM_FALLTHROUGH; 4515 default: 4516 return std::string(1, *Constraint); 4517 } 4518 } 4519 4520 // X86-32 generic target 4521 class X86_32TargetInfo : public X86TargetInfo { 4522 public: 4523 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4524 : X86TargetInfo(Triple, Opts) { 4525 DoubleAlign = LongLongAlign = 32; 4526 LongDoubleWidth = 96; 4527 LongDoubleAlign = 32; 4528 SuitableAlign = 128; 4529 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4530 SizeType = UnsignedInt; 4531 PtrDiffType = SignedInt; 4532 IntPtrType = SignedInt; 4533 RegParmMax = 3; 4534 4535 // Use fpret for all types. 4536 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4537 (1 << TargetInfo::Double) | 4538 (1 << TargetInfo::LongDouble)); 4539 4540 // x86-32 has atomics up to 8 bytes 4541 // FIXME: Check that we actually have cmpxchg8b before setting 4542 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4543 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4544 } 4545 BuiltinVaListKind getBuiltinVaListKind() const override { 4546 return TargetInfo::CharPtrBuiltinVaList; 4547 } 4548 4549 int getEHDataRegisterNumber(unsigned RegNo) const override { 4550 if (RegNo == 0) return 0; 4551 if (RegNo == 1) return 2; 4552 return -1; 4553 } 4554 bool validateOperandSize(StringRef Constraint, 4555 unsigned Size) const override { 4556 switch (Constraint[0]) { 4557 default: break; 4558 case 'R': 4559 case 'q': 4560 case 'Q': 4561 case 'a': 4562 case 'b': 4563 case 'c': 4564 case 'd': 4565 case 'S': 4566 case 'D': 4567 return Size <= 32; 4568 case 'A': 4569 return Size <= 64; 4570 } 4571 4572 return X86TargetInfo::validateOperandSize(Constraint, Size); 4573 } 4574 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4575 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4576 Builtin::FirstTSBuiltin + 1); 4577 } 4578 }; 4579 4580 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4581 public: 4582 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4583 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4584 4585 unsigned getFloatEvalMethod() const override { 4586 unsigned Major, Minor, Micro; 4587 getTriple().getOSVersion(Major, Minor, Micro); 4588 // New NetBSD uses the default rounding mode. 4589 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4590 return X86_32TargetInfo::getFloatEvalMethod(); 4591 // NetBSD before 6.99.26 defaults to "double" rounding. 4592 return 1; 4593 } 4594 }; 4595 4596 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4597 public: 4598 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4599 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4600 SizeType = UnsignedLong; 4601 IntPtrType = SignedLong; 4602 PtrDiffType = SignedLong; 4603 } 4604 }; 4605 4606 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4607 public: 4608 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4609 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4610 SizeType = UnsignedLong; 4611 IntPtrType = SignedLong; 4612 PtrDiffType = SignedLong; 4613 } 4614 }; 4615 4616 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4617 public: 4618 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4619 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4620 LongDoubleWidth = 128; 4621 LongDoubleAlign = 128; 4622 SuitableAlign = 128; 4623 MaxVectorAlign = 256; 4624 // The watchOS simulator uses the builtin bool type for Objective-C. 4625 llvm::Triple T = llvm::Triple(Triple); 4626 if (T.isWatchOS()) 4627 UseSignedCharForObjCBool = false; 4628 SizeType = UnsignedLong; 4629 IntPtrType = SignedLong; 4630 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4631 HasAlignMac68kSupport = true; 4632 } 4633 4634 bool handleTargetFeatures(std::vector<std::string> &Features, 4635 DiagnosticsEngine &Diags) override { 4636 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4637 Diags)) 4638 return false; 4639 // We now know the features we have: we can decide how to align vectors. 4640 MaxVectorAlign = 4641 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4642 return true; 4643 } 4644 }; 4645 4646 // x86-32 Windows target 4647 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4648 public: 4649 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4650 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4651 WCharType = UnsignedShort; 4652 DoubleAlign = LongLongAlign = 64; 4653 bool IsWinCOFF = 4654 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4655 resetDataLayout(IsWinCOFF 4656 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4657 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4658 } 4659 void getTargetDefines(const LangOptions &Opts, 4660 MacroBuilder &Builder) const override { 4661 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4662 } 4663 }; 4664 4665 // x86-32 Windows Visual Studio target 4666 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4667 public: 4668 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4669 const TargetOptions &Opts) 4670 : WindowsX86_32TargetInfo(Triple, Opts) { 4671 LongDoubleWidth = LongDoubleAlign = 64; 4672 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4673 } 4674 void getTargetDefines(const LangOptions &Opts, 4675 MacroBuilder &Builder) const override { 4676 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4677 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4678 // The value of the following reflects processor type. 4679 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4680 // We lost the original triple, so we use the default. 4681 Builder.defineMacro("_M_IX86", "600"); 4682 } 4683 }; 4684 4685 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4686 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4687 // supports __declspec natively under -fms-extensions, but we define a no-op 4688 // __declspec macro anyway for pre-processor compatibility. 4689 if (Opts.MicrosoftExt) 4690 Builder.defineMacro("__declspec", "__declspec"); 4691 else 4692 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4693 4694 if (!Opts.MicrosoftExt) { 4695 // Provide macros for all the calling convention keywords. Provide both 4696 // single and double underscore prefixed variants. These are available on 4697 // x64 as well as x86, even though they have no effect. 4698 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4699 for (const char *CC : CCs) { 4700 std::string GCCSpelling = "__attribute__((__"; 4701 GCCSpelling += CC; 4702 GCCSpelling += "__))"; 4703 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4704 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4705 } 4706 } 4707 } 4708 4709 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4710 Builder.defineMacro("__MSVCRT__"); 4711 Builder.defineMacro("__MINGW32__"); 4712 addCygMingDefines(Opts, Builder); 4713 } 4714 4715 // x86-32 MinGW target 4716 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4717 public: 4718 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4719 : WindowsX86_32TargetInfo(Triple, Opts) { 4720 HasFloat128 = true; 4721 } 4722 void getTargetDefines(const LangOptions &Opts, 4723 MacroBuilder &Builder) const override { 4724 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4725 DefineStd(Builder, "WIN32", Opts); 4726 DefineStd(Builder, "WINNT", Opts); 4727 Builder.defineMacro("_X86_"); 4728 addMinGWDefines(Opts, Builder); 4729 } 4730 }; 4731 4732 // x86-32 Cygwin target 4733 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4734 public: 4735 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4736 : X86_32TargetInfo(Triple, Opts) { 4737 WCharType = UnsignedShort; 4738 DoubleAlign = LongLongAlign = 64; 4739 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4740 } 4741 void getTargetDefines(const LangOptions &Opts, 4742 MacroBuilder &Builder) const override { 4743 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4744 Builder.defineMacro("_X86_"); 4745 Builder.defineMacro("__CYGWIN__"); 4746 Builder.defineMacro("__CYGWIN32__"); 4747 addCygMingDefines(Opts, Builder); 4748 DefineStd(Builder, "unix", Opts); 4749 if (Opts.CPlusPlus) 4750 Builder.defineMacro("_GNU_SOURCE"); 4751 } 4752 }; 4753 4754 // x86-32 Haiku target 4755 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4756 public: 4757 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4758 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4759 } 4760 void getTargetDefines(const LangOptions &Opts, 4761 MacroBuilder &Builder) const override { 4762 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4763 Builder.defineMacro("__INTEL__"); 4764 } 4765 }; 4766 4767 // X86-32 MCU target 4768 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4769 public: 4770 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4771 : X86_32TargetInfo(Triple, Opts) { 4772 LongDoubleWidth = 64; 4773 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4774 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4775 WIntType = UnsignedInt; 4776 } 4777 4778 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4779 // On MCU we support only C calling convention. 4780 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4781 } 4782 4783 void getTargetDefines(const LangOptions &Opts, 4784 MacroBuilder &Builder) const override { 4785 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4786 Builder.defineMacro("__iamcu"); 4787 Builder.defineMacro("__iamcu__"); 4788 } 4789 4790 bool allowsLargerPreferedTypeAlignment() const override { 4791 return false; 4792 } 4793 }; 4794 4795 // RTEMS Target 4796 template<typename Target> 4797 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4798 protected: 4799 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4800 MacroBuilder &Builder) const override { 4801 // RTEMS defines; list based off of gcc output 4802 4803 Builder.defineMacro("__rtems__"); 4804 Builder.defineMacro("__ELF__"); 4805 } 4806 4807 public: 4808 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4809 : OSTargetInfo<Target>(Triple, Opts) { 4810 switch (Triple.getArch()) { 4811 default: 4812 case llvm::Triple::x86: 4813 // this->MCountName = ".mcount"; 4814 break; 4815 case llvm::Triple::mips: 4816 case llvm::Triple::mipsel: 4817 case llvm::Triple::ppc: 4818 case llvm::Triple::ppc64: 4819 case llvm::Triple::ppc64le: 4820 // this->MCountName = "_mcount"; 4821 break; 4822 case llvm::Triple::arm: 4823 // this->MCountName = "__mcount"; 4824 break; 4825 } 4826 } 4827 }; 4828 4829 // x86-32 RTEMS target 4830 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4831 public: 4832 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4833 : X86_32TargetInfo(Triple, Opts) { 4834 SizeType = UnsignedLong; 4835 IntPtrType = SignedLong; 4836 PtrDiffType = SignedLong; 4837 } 4838 void getTargetDefines(const LangOptions &Opts, 4839 MacroBuilder &Builder) const override { 4840 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4841 Builder.defineMacro("__INTEL__"); 4842 Builder.defineMacro("__rtems__"); 4843 } 4844 }; 4845 4846 // x86-64 generic target 4847 class X86_64TargetInfo : public X86TargetInfo { 4848 public: 4849 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4850 : X86TargetInfo(Triple, Opts) { 4851 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4852 bool IsWinCOFF = 4853 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4854 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4855 LongDoubleWidth = 128; 4856 LongDoubleAlign = 128; 4857 LargeArrayMinWidth = 128; 4858 LargeArrayAlign = 128; 4859 SuitableAlign = 128; 4860 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4861 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4862 IntPtrType = IsX32 ? SignedInt : SignedLong; 4863 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4864 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4865 RegParmMax = 6; 4866 4867 // Pointers are 32-bit in x32. 4868 resetDataLayout(IsX32 4869 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4870 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4871 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4872 4873 // Use fpret only for long double. 4874 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4875 4876 // Use fp2ret for _Complex long double. 4877 ComplexLongDoubleUsesFP2Ret = true; 4878 4879 // Make __builtin_ms_va_list available. 4880 HasBuiltinMSVaList = true; 4881 4882 // x86-64 has atomics up to 16 bytes. 4883 MaxAtomicPromoteWidth = 128; 4884 MaxAtomicInlineWidth = 128; 4885 } 4886 BuiltinVaListKind getBuiltinVaListKind() const override { 4887 return TargetInfo::X86_64ABIBuiltinVaList; 4888 } 4889 4890 int getEHDataRegisterNumber(unsigned RegNo) const override { 4891 if (RegNo == 0) return 0; 4892 if (RegNo == 1) return 1; 4893 return -1; 4894 } 4895 4896 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4897 switch (CC) { 4898 case CC_C: 4899 case CC_Swift: 4900 case CC_X86VectorCall: 4901 case CC_IntelOclBicc: 4902 case CC_Win64: 4903 case CC_PreserveMost: 4904 case CC_PreserveAll: 4905 case CC_X86RegCall: 4906 case CC_OpenCLKernel: 4907 return CCCR_OK; 4908 default: 4909 return CCCR_Warning; 4910 } 4911 } 4912 4913 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4914 return CC_C; 4915 } 4916 4917 // for x32 we need it here explicitly 4918 bool hasInt128Type() const override { return true; } 4919 unsigned getUnwindWordWidth() const override { return 64; } 4920 unsigned getRegisterWidth() const override { return 64; } 4921 4922 bool validateGlobalRegisterVariable(StringRef RegName, 4923 unsigned RegSize, 4924 bool &HasSizeMismatch) const override { 4925 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4926 // handle. 4927 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4928 // Check that the register size is 64-bit. 4929 HasSizeMismatch = RegSize != 64; 4930 return true; 4931 } 4932 4933 // Check if the register is a 32-bit register the backend can handle. 4934 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4935 HasSizeMismatch); 4936 } 4937 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4938 return llvm::makeArrayRef(BuiltinInfoX86, 4939 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4940 } 4941 }; 4942 4943 // x86-64 Windows target 4944 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4945 public: 4946 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4947 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4948 WCharType = UnsignedShort; 4949 LongWidth = LongAlign = 32; 4950 DoubleAlign = LongLongAlign = 64; 4951 IntMaxType = SignedLongLong; 4952 Int64Type = SignedLongLong; 4953 SizeType = UnsignedLongLong; 4954 PtrDiffType = SignedLongLong; 4955 IntPtrType = SignedLongLong; 4956 } 4957 4958 void getTargetDefines(const LangOptions &Opts, 4959 MacroBuilder &Builder) const override { 4960 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4961 Builder.defineMacro("_WIN64"); 4962 } 4963 4964 BuiltinVaListKind getBuiltinVaListKind() const override { 4965 return TargetInfo::CharPtrBuiltinVaList; 4966 } 4967 4968 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4969 switch (CC) { 4970 case CC_X86StdCall: 4971 case CC_X86ThisCall: 4972 case CC_X86FastCall: 4973 return CCCR_Ignore; 4974 case CC_C: 4975 case CC_X86VectorCall: 4976 case CC_IntelOclBicc: 4977 case CC_X86_64SysV: 4978 case CC_Swift: 4979 case CC_X86RegCall: 4980 case CC_OpenCLKernel: 4981 return CCCR_OK; 4982 default: 4983 return CCCR_Warning; 4984 } 4985 } 4986 }; 4987 4988 // x86-64 Windows Visual Studio target 4989 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4990 public: 4991 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4992 const TargetOptions &Opts) 4993 : WindowsX86_64TargetInfo(Triple, Opts) { 4994 LongDoubleWidth = LongDoubleAlign = 64; 4995 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4996 } 4997 void getTargetDefines(const LangOptions &Opts, 4998 MacroBuilder &Builder) const override { 4999 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 5000 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 5001 Builder.defineMacro("_M_X64", "100"); 5002 Builder.defineMacro("_M_AMD64", "100"); 5003 } 5004 }; 5005 5006 // x86-64 MinGW target 5007 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 5008 public: 5009 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5010 : WindowsX86_64TargetInfo(Triple, Opts) { 5011 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 5012 // with x86 FP ops. Weird. 5013 LongDoubleWidth = LongDoubleAlign = 128; 5014 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 5015 HasFloat128 = true; 5016 } 5017 5018 void getTargetDefines(const LangOptions &Opts, 5019 MacroBuilder &Builder) const override { 5020 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 5021 DefineStd(Builder, "WIN64", Opts); 5022 Builder.defineMacro("__MINGW64__"); 5023 addMinGWDefines(Opts, Builder); 5024 5025 // GCC defines this macro when it is using __gxx_personality_seh0. 5026 if (!Opts.SjLjExceptions) 5027 Builder.defineMacro("__SEH__"); 5028 } 5029 }; 5030 5031 // x86-64 Cygwin target 5032 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 5033 public: 5034 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5035 : X86_64TargetInfo(Triple, Opts) { 5036 TLSSupported = false; 5037 WCharType = UnsignedShort; 5038 } 5039 void getTargetDefines(const LangOptions &Opts, 5040 MacroBuilder &Builder) const override { 5041 X86_64TargetInfo::getTargetDefines(Opts, Builder); 5042 Builder.defineMacro("__x86_64__"); 5043 Builder.defineMacro("__CYGWIN__"); 5044 Builder.defineMacro("__CYGWIN64__"); 5045 addCygMingDefines(Opts, Builder); 5046 DefineStd(Builder, "unix", Opts); 5047 if (Opts.CPlusPlus) 5048 Builder.defineMacro("_GNU_SOURCE"); 5049 5050 // GCC defines this macro when it is using __gxx_personality_seh0. 5051 if (!Opts.SjLjExceptions) 5052 Builder.defineMacro("__SEH__"); 5053 } 5054 }; 5055 5056 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 5057 public: 5058 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5059 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5060 Int64Type = SignedLongLong; 5061 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 5062 llvm::Triple T = llvm::Triple(Triple); 5063 if (T.isiOS()) 5064 UseSignedCharForObjCBool = false; 5065 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 5066 } 5067 5068 bool handleTargetFeatures(std::vector<std::string> &Features, 5069 DiagnosticsEngine &Diags) override { 5070 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5071 Diags)) 5072 return false; 5073 // We now know the features we have: we can decide how to align vectors. 5074 MaxVectorAlign = 5075 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5076 return true; 5077 } 5078 }; 5079 5080 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5081 public: 5082 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5083 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5084 IntMaxType = SignedLongLong; 5085 Int64Type = SignedLongLong; 5086 } 5087 }; 5088 5089 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5090 public: 5091 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5092 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5093 IntMaxType = SignedLongLong; 5094 Int64Type = SignedLongLong; 5095 } 5096 }; 5097 5098 class ARMTargetInfo : public TargetInfo { 5099 // Possible FPU choices. 5100 enum FPUMode { 5101 VFP2FPU = (1 << 0), 5102 VFP3FPU = (1 << 1), 5103 VFP4FPU = (1 << 2), 5104 NeonFPU = (1 << 3), 5105 FPARMV8 = (1 << 4) 5106 }; 5107 5108 // Possible HWDiv features. 5109 enum HWDivMode { 5110 HWDivThumb = (1 << 0), 5111 HWDivARM = (1 << 1) 5112 }; 5113 5114 static bool FPUModeIsVFP(FPUMode Mode) { 5115 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5116 } 5117 5118 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5119 static const char * const GCCRegNames[]; 5120 5121 std::string ABI, CPU; 5122 5123 StringRef CPUProfile; 5124 StringRef CPUAttr; 5125 5126 enum { 5127 FP_Default, 5128 FP_VFP, 5129 FP_Neon 5130 } FPMath; 5131 5132 unsigned ArchISA; 5133 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5134 unsigned ArchProfile; 5135 unsigned ArchVersion; 5136 5137 unsigned FPU : 5; 5138 5139 unsigned IsAAPCS : 1; 5140 unsigned HWDiv : 2; 5141 5142 // Initialized via features. 5143 unsigned SoftFloat : 1; 5144 unsigned SoftFloatABI : 1; 5145 5146 unsigned CRC : 1; 5147 unsigned Crypto : 1; 5148 unsigned DSP : 1; 5149 unsigned Unaligned : 1; 5150 5151 enum { 5152 LDREX_B = (1 << 0), /// byte (8-bit) 5153 LDREX_H = (1 << 1), /// half (16-bit) 5154 LDREX_W = (1 << 2), /// word (32-bit) 5155 LDREX_D = (1 << 3), /// double (64-bit) 5156 }; 5157 5158 uint32_t LDREX; 5159 5160 // ACLE 6.5.1 Hardware floating point 5161 enum { 5162 HW_FP_HP = (1 << 1), /// half (16-bit) 5163 HW_FP_SP = (1 << 2), /// single (32-bit) 5164 HW_FP_DP = (1 << 3), /// double (64-bit) 5165 }; 5166 uint32_t HW_FP; 5167 5168 static const Builtin::Info BuiltinInfo[]; 5169 5170 void setABIAAPCS() { 5171 IsAAPCS = true; 5172 5173 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5174 const llvm::Triple &T = getTriple(); 5175 5176 // size_t is unsigned long on MachO-derived environments, NetBSD, 5177 // OpenBSD and Bitrig. 5178 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5179 T.getOS() == llvm::Triple::OpenBSD || 5180 T.getOS() == llvm::Triple::Bitrig) 5181 SizeType = UnsignedLong; 5182 else 5183 SizeType = UnsignedInt; 5184 5185 switch (T.getOS()) { 5186 case llvm::Triple::NetBSD: 5187 case llvm::Triple::OpenBSD: 5188 WCharType = SignedInt; 5189 break; 5190 case llvm::Triple::Win32: 5191 WCharType = UnsignedShort; 5192 break; 5193 case llvm::Triple::Linux: 5194 default: 5195 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5196 WCharType = UnsignedInt; 5197 break; 5198 } 5199 5200 UseBitFieldTypeAlignment = true; 5201 5202 ZeroLengthBitfieldBoundary = 0; 5203 5204 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5205 // so set preferred for small types to 32. 5206 if (T.isOSBinFormatMachO()) { 5207 resetDataLayout(BigEndian 5208 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5209 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5210 } else if (T.isOSWindows()) { 5211 assert(!BigEndian && "Windows on ARM does not support big endian"); 5212 resetDataLayout("e" 5213 "-m:w" 5214 "-p:32:32" 5215 "-i64:64" 5216 "-v128:64:128" 5217 "-a:0:32" 5218 "-n32" 5219 "-S64"); 5220 } else if (T.isOSNaCl()) { 5221 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5222 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5223 } else { 5224 resetDataLayout(BigEndian 5225 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5226 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5227 } 5228 5229 // FIXME: Enumerated types are variable width in straight AAPCS. 5230 } 5231 5232 void setABIAPCS(bool IsAAPCS16) { 5233 const llvm::Triple &T = getTriple(); 5234 5235 IsAAPCS = false; 5236 5237 if (IsAAPCS16) 5238 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5239 else 5240 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5241 5242 // size_t is unsigned int on FreeBSD. 5243 if (T.getOS() == llvm::Triple::FreeBSD) 5244 SizeType = UnsignedInt; 5245 else 5246 SizeType = UnsignedLong; 5247 5248 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5249 WCharType = SignedInt; 5250 5251 // Do not respect the alignment of bit-field types when laying out 5252 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5253 UseBitFieldTypeAlignment = false; 5254 5255 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5256 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5257 /// gcc. 5258 ZeroLengthBitfieldBoundary = 32; 5259 5260 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5261 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5262 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5263 } else if (T.isOSBinFormatMachO()) 5264 resetDataLayout( 5265 BigEndian 5266 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5267 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5268 else 5269 resetDataLayout( 5270 BigEndian 5271 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5272 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5273 5274 // FIXME: Override "preferred align" for double and long long. 5275 } 5276 5277 void setArchInfo() { 5278 StringRef ArchName = getTriple().getArchName(); 5279 5280 ArchISA = llvm::ARM::parseArchISA(ArchName); 5281 CPU = llvm::ARM::getDefaultCPU(ArchName); 5282 unsigned AK = llvm::ARM::parseArch(ArchName); 5283 if (AK != llvm::ARM::AK_INVALID) 5284 ArchKind = AK; 5285 setArchInfo(ArchKind); 5286 } 5287 5288 void setArchInfo(unsigned Kind) { 5289 StringRef SubArch; 5290 5291 // cache TargetParser info 5292 ArchKind = Kind; 5293 SubArch = llvm::ARM::getSubArch(ArchKind); 5294 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5295 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5296 5297 // cache CPU related strings 5298 CPUAttr = getCPUAttr(); 5299 CPUProfile = getCPUProfile(); 5300 } 5301 5302 void setAtomic() { 5303 // when triple does not specify a sub arch, 5304 // then we are not using inline atomics 5305 bool ShouldUseInlineAtomic = 5306 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5307 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5308 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5309 if (ArchProfile == llvm::ARM::PK_M) { 5310 MaxAtomicPromoteWidth = 32; 5311 if (ShouldUseInlineAtomic) 5312 MaxAtomicInlineWidth = 32; 5313 } 5314 else { 5315 MaxAtomicPromoteWidth = 64; 5316 if (ShouldUseInlineAtomic) 5317 MaxAtomicInlineWidth = 64; 5318 } 5319 } 5320 5321 bool isThumb() const { 5322 return (ArchISA == llvm::ARM::IK_THUMB); 5323 } 5324 5325 bool supportsThumb() const { 5326 return CPUAttr.count('T') || ArchVersion >= 6; 5327 } 5328 5329 bool supportsThumb2() const { 5330 return CPUAttr.equals("6T2") || 5331 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5332 } 5333 5334 StringRef getCPUAttr() const { 5335 // For most sub-arches, the build attribute CPU name is enough. 5336 // For Cortex variants, it's slightly different. 5337 switch(ArchKind) { 5338 default: 5339 return llvm::ARM::getCPUAttr(ArchKind); 5340 case llvm::ARM::AK_ARMV6M: 5341 return "6M"; 5342 case llvm::ARM::AK_ARMV7S: 5343 return "7S"; 5344 case llvm::ARM::AK_ARMV7A: 5345 return "7A"; 5346 case llvm::ARM::AK_ARMV7R: 5347 return "7R"; 5348 case llvm::ARM::AK_ARMV7M: 5349 return "7M"; 5350 case llvm::ARM::AK_ARMV7EM: 5351 return "7EM"; 5352 case llvm::ARM::AK_ARMV7VE: 5353 return "7VE"; 5354 case llvm::ARM::AK_ARMV8A: 5355 return "8A"; 5356 case llvm::ARM::AK_ARMV8_1A: 5357 return "8_1A"; 5358 case llvm::ARM::AK_ARMV8_2A: 5359 return "8_2A"; 5360 case llvm::ARM::AK_ARMV8MBaseline: 5361 return "8M_BASE"; 5362 case llvm::ARM::AK_ARMV8MMainline: 5363 return "8M_MAIN"; 5364 case llvm::ARM::AK_ARMV8R: 5365 return "8R"; 5366 } 5367 } 5368 5369 StringRef getCPUProfile() const { 5370 switch(ArchProfile) { 5371 case llvm::ARM::PK_A: 5372 return "A"; 5373 case llvm::ARM::PK_R: 5374 return "R"; 5375 case llvm::ARM::PK_M: 5376 return "M"; 5377 default: 5378 return ""; 5379 } 5380 } 5381 5382 public: 5383 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5384 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5385 HW_FP(0) { 5386 5387 switch (getTriple().getOS()) { 5388 case llvm::Triple::NetBSD: 5389 case llvm::Triple::OpenBSD: 5390 PtrDiffType = SignedLong; 5391 break; 5392 default: 5393 PtrDiffType = SignedInt; 5394 break; 5395 } 5396 5397 // Cache arch related info. 5398 setArchInfo(); 5399 5400 // {} in inline assembly are neon specifiers, not assembly variant 5401 // specifiers. 5402 NoAsmVariants = true; 5403 5404 // FIXME: This duplicates code from the driver that sets the -target-abi 5405 // option - this code is used if -target-abi isn't passed and should 5406 // be unified in some way. 5407 if (Triple.isOSBinFormatMachO()) { 5408 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5409 // the frontend matches that. 5410 if (Triple.getEnvironment() == llvm::Triple::EABI || 5411 Triple.getOS() == llvm::Triple::UnknownOS || 5412 ArchProfile == llvm::ARM::PK_M) { 5413 setABI("aapcs"); 5414 } else if (Triple.isWatchABI()) { 5415 setABI("aapcs16"); 5416 } else { 5417 setABI("apcs-gnu"); 5418 } 5419 } else if (Triple.isOSWindows()) { 5420 // FIXME: this is invalid for WindowsCE 5421 setABI("aapcs"); 5422 } else { 5423 // Select the default based on the platform. 5424 switch (Triple.getEnvironment()) { 5425 case llvm::Triple::Android: 5426 case llvm::Triple::GNUEABI: 5427 case llvm::Triple::GNUEABIHF: 5428 case llvm::Triple::MuslEABI: 5429 case llvm::Triple::MuslEABIHF: 5430 setABI("aapcs-linux"); 5431 break; 5432 case llvm::Triple::EABIHF: 5433 case llvm::Triple::EABI: 5434 setABI("aapcs"); 5435 break; 5436 case llvm::Triple::GNU: 5437 setABI("apcs-gnu"); 5438 break; 5439 default: 5440 if (Triple.getOS() == llvm::Triple::NetBSD) 5441 setABI("apcs-gnu"); 5442 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5443 setABI("aapcs-linux"); 5444 else 5445 setABI("aapcs"); 5446 break; 5447 } 5448 } 5449 5450 // ARM targets default to using the ARM C++ ABI. 5451 TheCXXABI.set(TargetCXXABI::GenericARM); 5452 5453 // ARM has atomics up to 8 bytes 5454 setAtomic(); 5455 5456 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) 5457 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) 5458 MaxVectorAlign = 64; 5459 5460 // Do force alignment of members that follow zero length bitfields. If 5461 // the alignment of the zero-length bitfield is greater than the member 5462 // that follows it, `bar', `bar' will be aligned as the type of the 5463 // zero length bitfield. 5464 UseZeroLengthBitfieldAlignment = true; 5465 5466 if (Triple.getOS() == llvm::Triple::Linux || 5467 Triple.getOS() == llvm::Triple::UnknownOS) 5468 this->MCountName = 5469 Opts.EABIVersion == llvm::EABI::GNU ? "\01__gnu_mcount_nc" : "\01mcount"; 5470 } 5471 5472 StringRef getABI() const override { return ABI; } 5473 5474 bool setABI(const std::string &Name) override { 5475 ABI = Name; 5476 5477 // The defaults (above) are for AAPCS, check if we need to change them. 5478 // 5479 // FIXME: We need support for -meabi... we could just mangle it into the 5480 // name. 5481 if (Name == "apcs-gnu" || Name == "aapcs16") { 5482 setABIAPCS(Name == "aapcs16"); 5483 return true; 5484 } 5485 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5486 setABIAAPCS(); 5487 return true; 5488 } 5489 return false; 5490 } 5491 5492 // FIXME: This should be based on Arch attributes, not CPU names. 5493 bool 5494 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5495 StringRef CPU, 5496 const std::vector<std::string> &FeaturesVec) const override { 5497 5498 std::vector<StringRef> TargetFeatures; 5499 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5500 5501 // get default FPU features 5502 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5503 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5504 5505 // get default Extension features 5506 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5507 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5508 5509 for (auto Feature : TargetFeatures) 5510 if (Feature[0] == '+') 5511 Features[Feature.drop_front(1)] = true; 5512 5513 // Enable or disable thumb-mode explicitly per function to enable mixed 5514 // ARM and Thumb code generation. 5515 if (isThumb()) 5516 Features["thumb-mode"] = true; 5517 else 5518 Features["thumb-mode"] = false; 5519 5520 // Convert user-provided arm and thumb GNU target attributes to 5521 // [-|+]thumb-mode target features respectively. 5522 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); 5523 for (auto &Feature : UpdatedFeaturesVec) { 5524 if (Feature.compare("+arm") == 0) 5525 Feature = "-thumb-mode"; 5526 else if (Feature.compare("+thumb") == 0) 5527 Feature = "+thumb-mode"; 5528 } 5529 5530 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); 5531 } 5532 5533 bool handleTargetFeatures(std::vector<std::string> &Features, 5534 DiagnosticsEngine &Diags) override { 5535 FPU = 0; 5536 CRC = 0; 5537 Crypto = 0; 5538 DSP = 0; 5539 Unaligned = 1; 5540 SoftFloat = SoftFloatABI = false; 5541 HWDiv = 0; 5542 5543 // This does not diagnose illegal cases like having both 5544 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5545 uint32_t HW_FP_remove = 0; 5546 for (const auto &Feature : Features) { 5547 if (Feature == "+soft-float") { 5548 SoftFloat = true; 5549 } else if (Feature == "+soft-float-abi") { 5550 SoftFloatABI = true; 5551 } else if (Feature == "+vfp2") { 5552 FPU |= VFP2FPU; 5553 HW_FP |= HW_FP_SP | HW_FP_DP; 5554 } else if (Feature == "+vfp3") { 5555 FPU |= VFP3FPU; 5556 HW_FP |= HW_FP_SP | HW_FP_DP; 5557 } else if (Feature == "+vfp4") { 5558 FPU |= VFP4FPU; 5559 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5560 } else if (Feature == "+fp-armv8") { 5561 FPU |= FPARMV8; 5562 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5563 } else if (Feature == "+neon") { 5564 FPU |= NeonFPU; 5565 HW_FP |= HW_FP_SP | HW_FP_DP; 5566 } else if (Feature == "+hwdiv") { 5567 HWDiv |= HWDivThumb; 5568 } else if (Feature == "+hwdiv-arm") { 5569 HWDiv |= HWDivARM; 5570 } else if (Feature == "+crc") { 5571 CRC = 1; 5572 } else if (Feature == "+crypto") { 5573 Crypto = 1; 5574 } else if (Feature == "+dsp") { 5575 DSP = 1; 5576 } else if (Feature == "+fp-only-sp") { 5577 HW_FP_remove |= HW_FP_DP; 5578 } else if (Feature == "+strict-align") { 5579 Unaligned = 0; 5580 } else if (Feature == "+fp16") { 5581 HW_FP |= HW_FP_HP; 5582 } 5583 } 5584 HW_FP &= ~HW_FP_remove; 5585 5586 switch (ArchVersion) { 5587 case 6: 5588 if (ArchProfile == llvm::ARM::PK_M) 5589 LDREX = 0; 5590 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5591 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5592 else 5593 LDREX = LDREX_W; 5594 break; 5595 case 7: 5596 if (ArchProfile == llvm::ARM::PK_M) 5597 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5598 else 5599 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5600 break; 5601 case 8: 5602 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5603 } 5604 5605 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5606 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5607 return false; 5608 } 5609 5610 if (FPMath == FP_Neon) 5611 Features.push_back("+neonfp"); 5612 else if (FPMath == FP_VFP) 5613 Features.push_back("-neonfp"); 5614 5615 // Remove front-end specific options which the backend handles differently. 5616 auto Feature = 5617 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5618 if (Feature != Features.end()) 5619 Features.erase(Feature); 5620 5621 return true; 5622 } 5623 5624 bool hasFeature(StringRef Feature) const override { 5625 return llvm::StringSwitch<bool>(Feature) 5626 .Case("arm", true) 5627 .Case("aarch32", true) 5628 .Case("softfloat", SoftFloat) 5629 .Case("thumb", isThumb()) 5630 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5631 .Case("vfp", FPU && !SoftFloat) 5632 .Case("hwdiv", HWDiv & HWDivThumb) 5633 .Case("hwdiv-arm", HWDiv & HWDivARM) 5634 .Default(false); 5635 } 5636 5637 bool setCPU(const std::string &Name) override { 5638 if (Name != "generic") 5639 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5640 5641 if (ArchKind == llvm::ARM::AK_INVALID) 5642 return false; 5643 setAtomic(); 5644 CPU = Name; 5645 return true; 5646 } 5647 5648 bool setFPMath(StringRef Name) override; 5649 5650 void getTargetDefinesARMV81A(const LangOptions &Opts, 5651 MacroBuilder &Builder) const { 5652 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5653 } 5654 5655 void getTargetDefinesARMV82A(const LangOptions &Opts, 5656 MacroBuilder &Builder) const { 5657 // Also include the ARMv8.1-A defines 5658 getTargetDefinesARMV81A(Opts, Builder); 5659 } 5660 5661 void getTargetDefines(const LangOptions &Opts, 5662 MacroBuilder &Builder) const override { 5663 // Target identification. 5664 Builder.defineMacro("__arm"); 5665 Builder.defineMacro("__arm__"); 5666 // For bare-metal none-eabi. 5667 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5668 (getTriple().getEnvironment() == llvm::Triple::EABI || 5669 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5670 Builder.defineMacro("__ELF__"); 5671 5672 5673 // Target properties. 5674 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5675 5676 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5677 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5678 if (getTriple().isWatchABI()) 5679 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5680 5681 if (!CPUAttr.empty()) 5682 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5683 5684 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5685 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5686 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5687 5688 if (ArchVersion >= 8) { 5689 // ACLE 6.5.7 Crypto Extension 5690 if (Crypto) 5691 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5692 // ACLE 6.5.8 CRC32 Extension 5693 if (CRC) 5694 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5695 // ACLE 6.5.10 Numeric Maximum and Minimum 5696 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5697 // ACLE 6.5.9 Directed Rounding 5698 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5699 } 5700 5701 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5702 // is not defined for the M-profile. 5703 // NOTE that the default profile is assumed to be 'A' 5704 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5705 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5706 5707 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5708 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5709 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5710 // v7 and v8 architectures excluding v8-M Baseline. 5711 if (supportsThumb2()) 5712 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5713 else if (supportsThumb()) 5714 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5715 5716 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5717 // instruction set such as ARM or Thumb. 5718 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5719 5720 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5721 5722 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5723 if (!CPUProfile.empty()) 5724 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5725 5726 // ACLE 6.4.3 Unaligned access supported in hardware 5727 if (Unaligned) 5728 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5729 5730 // ACLE 6.4.4 LDREX/STREX 5731 if (LDREX) 5732 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5733 5734 // ACLE 6.4.5 CLZ 5735 if (ArchVersion == 5 || 5736 (ArchVersion == 6 && CPUProfile != "M") || 5737 ArchVersion > 6) 5738 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5739 5740 // ACLE 6.5.1 Hardware Floating Point 5741 if (HW_FP) 5742 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5743 5744 // ACLE predefines. 5745 Builder.defineMacro("__ARM_ACLE", "200"); 5746 5747 // FP16 support (we currently only support IEEE format). 5748 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5749 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5750 5751 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5752 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5753 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5754 5755 // Subtarget options. 5756 5757 // FIXME: It's more complicated than this and we don't really support 5758 // interworking. 5759 // Windows on ARM does not "support" interworking 5760 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5761 Builder.defineMacro("__THUMB_INTERWORK__"); 5762 5763 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5764 // Embedded targets on Darwin follow AAPCS, but not EABI. 5765 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5766 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5767 Builder.defineMacro("__ARM_EABI__"); 5768 Builder.defineMacro("__ARM_PCS", "1"); 5769 } 5770 5771 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5772 ABI == "aapcs16") 5773 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5774 5775 if (SoftFloat) 5776 Builder.defineMacro("__SOFTFP__"); 5777 5778 if (ArchKind == llvm::ARM::AK_XSCALE) 5779 Builder.defineMacro("__XSCALE__"); 5780 5781 if (isThumb()) { 5782 Builder.defineMacro("__THUMBEL__"); 5783 Builder.defineMacro("__thumb__"); 5784 if (supportsThumb2()) 5785 Builder.defineMacro("__thumb2__"); 5786 } 5787 5788 // ACLE 6.4.9 32-bit SIMD instructions 5789 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5790 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5791 5792 // ACLE 6.4.10 Hardware Integer Divide 5793 if (((HWDiv & HWDivThumb) && isThumb()) || 5794 ((HWDiv & HWDivARM) && !isThumb())) { 5795 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5796 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5797 } 5798 5799 // Note, this is always on in gcc, even though it doesn't make sense. 5800 Builder.defineMacro("__APCS_32__"); 5801 5802 if (FPUModeIsVFP((FPUMode) FPU)) { 5803 Builder.defineMacro("__VFP_FP__"); 5804 if (FPU & VFP2FPU) 5805 Builder.defineMacro("__ARM_VFPV2__"); 5806 if (FPU & VFP3FPU) 5807 Builder.defineMacro("__ARM_VFPV3__"); 5808 if (FPU & VFP4FPU) 5809 Builder.defineMacro("__ARM_VFPV4__"); 5810 if (FPU & FPARMV8) 5811 Builder.defineMacro("__ARM_FPV5__"); 5812 } 5813 5814 // This only gets set when Neon instructions are actually available, unlike 5815 // the VFP define, hence the soft float and arch check. This is subtly 5816 // different from gcc, we follow the intent which was that it should be set 5817 // when Neon instructions are actually available. 5818 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5819 Builder.defineMacro("__ARM_NEON", "1"); 5820 Builder.defineMacro("__ARM_NEON__"); 5821 // current AArch32 NEON implementations do not support double-precision 5822 // floating-point even when it is present in VFP. 5823 Builder.defineMacro("__ARM_NEON_FP", 5824 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5825 } 5826 5827 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5828 Opts.ShortWChar ? "2" : "4"); 5829 5830 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5831 Opts.ShortEnums ? "1" : "4"); 5832 5833 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5834 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5835 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5836 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5837 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5838 } 5839 5840 // ACLE 6.4.7 DSP instructions 5841 if (DSP) { 5842 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5843 } 5844 5845 // ACLE 6.4.8 Saturation instructions 5846 bool SAT = false; 5847 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5848 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5849 SAT = true; 5850 } 5851 5852 // ACLE 6.4.6 Q (saturation) flag 5853 if (DSP || SAT) 5854 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5855 5856 if (Opts.UnsafeFPMath) 5857 Builder.defineMacro("__ARM_FP_FAST", "1"); 5858 5859 switch(ArchKind) { 5860 default: break; 5861 case llvm::ARM::AK_ARMV8_1A: 5862 getTargetDefinesARMV81A(Opts, Builder); 5863 break; 5864 case llvm::ARM::AK_ARMV8_2A: 5865 getTargetDefinesARMV82A(Opts, Builder); 5866 break; 5867 } 5868 } 5869 5870 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5871 return llvm::makeArrayRef(BuiltinInfo, 5872 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5873 } 5874 bool isCLZForZeroUndef() const override { return false; } 5875 BuiltinVaListKind getBuiltinVaListKind() const override { 5876 return IsAAPCS 5877 ? AAPCSABIBuiltinVaList 5878 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5879 : TargetInfo::VoidPtrBuiltinVaList); 5880 } 5881 ArrayRef<const char *> getGCCRegNames() const override; 5882 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5883 bool validateAsmConstraint(const char *&Name, 5884 TargetInfo::ConstraintInfo &Info) const override { 5885 switch (*Name) { 5886 default: break; 5887 case 'l': // r0-r7 5888 case 'h': // r8-r15 5889 case 't': // VFP Floating point register single precision 5890 case 'w': // VFP Floating point register double precision 5891 Info.setAllowsRegister(); 5892 return true; 5893 case 'I': 5894 case 'J': 5895 case 'K': 5896 case 'L': 5897 case 'M': 5898 // FIXME 5899 return true; 5900 case 'Q': // A memory address that is a single base register. 5901 Info.setAllowsMemory(); 5902 return true; 5903 case 'U': // a memory reference... 5904 switch (Name[1]) { 5905 case 'q': // ...ARMV4 ldrsb 5906 case 'v': // ...VFP load/store (reg+constant offset) 5907 case 'y': // ...iWMMXt load/store 5908 case 't': // address valid for load/store opaque types wider 5909 // than 128-bits 5910 case 'n': // valid address for Neon doubleword vector load/store 5911 case 'm': // valid address for Neon element and structure load/store 5912 case 's': // valid address for non-offset loads/stores of quad-word 5913 // values in four ARM registers 5914 Info.setAllowsMemory(); 5915 Name++; 5916 return true; 5917 } 5918 } 5919 return false; 5920 } 5921 std::string convertConstraint(const char *&Constraint) const override { 5922 std::string R; 5923 switch (*Constraint) { 5924 case 'U': // Two-character constraint; add "^" hint for later parsing. 5925 R = std::string("^") + std::string(Constraint, 2); 5926 Constraint++; 5927 break; 5928 case 'p': // 'p' should be translated to 'r' by default. 5929 R = std::string("r"); 5930 break; 5931 default: 5932 return std::string(1, *Constraint); 5933 } 5934 return R; 5935 } 5936 bool 5937 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5938 std::string &SuggestedModifier) const override { 5939 bool isOutput = (Constraint[0] == '='); 5940 bool isInOut = (Constraint[0] == '+'); 5941 5942 // Strip off constraint modifiers. 5943 while (Constraint[0] == '=' || 5944 Constraint[0] == '+' || 5945 Constraint[0] == '&') 5946 Constraint = Constraint.substr(1); 5947 5948 switch (Constraint[0]) { 5949 default: break; 5950 case 'r': { 5951 switch (Modifier) { 5952 default: 5953 return (isInOut || isOutput || Size <= 64); 5954 case 'q': 5955 // A register of size 32 cannot fit a vector type. 5956 return false; 5957 } 5958 } 5959 } 5960 5961 return true; 5962 } 5963 const char *getClobbers() const override { 5964 // FIXME: Is this really right? 5965 return ""; 5966 } 5967 5968 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5969 switch (CC) { 5970 case CC_AAPCS: 5971 case CC_AAPCS_VFP: 5972 case CC_Swift: 5973 case CC_OpenCLKernel: 5974 return CCCR_OK; 5975 default: 5976 return CCCR_Warning; 5977 } 5978 } 5979 5980 int getEHDataRegisterNumber(unsigned RegNo) const override { 5981 if (RegNo == 0) return 0; 5982 if (RegNo == 1) return 1; 5983 return -1; 5984 } 5985 5986 bool hasSjLjLowering() const override { 5987 return true; 5988 } 5989 }; 5990 5991 bool ARMTargetInfo::setFPMath(StringRef Name) { 5992 if (Name == "neon") { 5993 FPMath = FP_Neon; 5994 return true; 5995 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5996 Name == "vfp4") { 5997 FPMath = FP_VFP; 5998 return true; 5999 } 6000 return false; 6001 } 6002 6003 const char * const ARMTargetInfo::GCCRegNames[] = { 6004 // Integer registers 6005 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6006 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 6007 6008 // Float registers 6009 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 6010 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 6011 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 6012 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6013 6014 // Double registers 6015 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 6016 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 6017 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 6018 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6019 6020 // Quad registers 6021 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 6022 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 6023 }; 6024 6025 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 6026 return llvm::makeArrayRef(GCCRegNames); 6027 } 6028 6029 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 6030 { { "a1" }, "r0" }, 6031 { { "a2" }, "r1" }, 6032 { { "a3" }, "r2" }, 6033 { { "a4" }, "r3" }, 6034 { { "v1" }, "r4" }, 6035 { { "v2" }, "r5" }, 6036 { { "v3" }, "r6" }, 6037 { { "v4" }, "r7" }, 6038 { { "v5" }, "r8" }, 6039 { { "v6", "rfp" }, "r9" }, 6040 { { "sl" }, "r10" }, 6041 { { "fp" }, "r11" }, 6042 { { "ip" }, "r12" }, 6043 { { "r13" }, "sp" }, 6044 { { "r14" }, "lr" }, 6045 { { "r15" }, "pc" }, 6046 // The S, D and Q registers overlap, but aren't really aliases; we 6047 // don't want to substitute one of these for a different-sized one. 6048 }; 6049 6050 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 6051 return llvm::makeArrayRef(GCCRegAliases); 6052 } 6053 6054 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 6055 #define BUILTIN(ID, TYPE, ATTRS) \ 6056 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6057 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6058 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6059 #include "clang/Basic/BuiltinsNEON.def" 6060 6061 #define BUILTIN(ID, TYPE, ATTRS) \ 6062 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6063 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 6064 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 6065 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6066 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6067 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 6068 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 6069 #include "clang/Basic/BuiltinsARM.def" 6070 }; 6071 6072 class ARMleTargetInfo : public ARMTargetInfo { 6073 public: 6074 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6075 : ARMTargetInfo(Triple, Opts) {} 6076 void getTargetDefines(const LangOptions &Opts, 6077 MacroBuilder &Builder) const override { 6078 Builder.defineMacro("__ARMEL__"); 6079 ARMTargetInfo::getTargetDefines(Opts, Builder); 6080 } 6081 }; 6082 6083 class ARMbeTargetInfo : public ARMTargetInfo { 6084 public: 6085 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6086 : ARMTargetInfo(Triple, Opts) {} 6087 void getTargetDefines(const LangOptions &Opts, 6088 MacroBuilder &Builder) const override { 6089 Builder.defineMacro("__ARMEB__"); 6090 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6091 ARMTargetInfo::getTargetDefines(Opts, Builder); 6092 } 6093 }; 6094 6095 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 6096 const llvm::Triple Triple; 6097 public: 6098 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6099 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 6100 WCharType = UnsignedShort; 6101 SizeType = UnsignedInt; 6102 } 6103 void getVisualStudioDefines(const LangOptions &Opts, 6104 MacroBuilder &Builder) const { 6105 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 6106 6107 // FIXME: this is invalid for WindowsCE 6108 Builder.defineMacro("_M_ARM_NT", "1"); 6109 Builder.defineMacro("_M_ARMT", "_M_ARM"); 6110 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6111 6112 assert((Triple.getArch() == llvm::Triple::arm || 6113 Triple.getArch() == llvm::Triple::thumb) && 6114 "invalid architecture for Windows ARM target info"); 6115 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6116 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6117 6118 // TODO map the complete set of values 6119 // 31: VFPv3 40: VFPv4 6120 Builder.defineMacro("_M_ARM_FP", "31"); 6121 } 6122 BuiltinVaListKind getBuiltinVaListKind() const override { 6123 return TargetInfo::CharPtrBuiltinVaList; 6124 } 6125 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6126 switch (CC) { 6127 case CC_X86StdCall: 6128 case CC_X86ThisCall: 6129 case CC_X86FastCall: 6130 case CC_X86VectorCall: 6131 return CCCR_Ignore; 6132 case CC_C: 6133 case CC_OpenCLKernel: 6134 return CCCR_OK; 6135 default: 6136 return CCCR_Warning; 6137 } 6138 } 6139 }; 6140 6141 // Windows ARM + Itanium C++ ABI Target 6142 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6143 public: 6144 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6145 const TargetOptions &Opts) 6146 : WindowsARMTargetInfo(Triple, Opts) { 6147 TheCXXABI.set(TargetCXXABI::GenericARM); 6148 } 6149 6150 void getTargetDefines(const LangOptions &Opts, 6151 MacroBuilder &Builder) const override { 6152 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6153 6154 if (Opts.MSVCCompat) 6155 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6156 } 6157 }; 6158 6159 // Windows ARM, MS (C++) ABI 6160 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6161 public: 6162 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6163 const TargetOptions &Opts) 6164 : WindowsARMTargetInfo(Triple, Opts) { 6165 TheCXXABI.set(TargetCXXABI::Microsoft); 6166 } 6167 6168 void getTargetDefines(const LangOptions &Opts, 6169 MacroBuilder &Builder) const override { 6170 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6171 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6172 } 6173 }; 6174 6175 // ARM MinGW target 6176 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6177 public: 6178 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6179 : WindowsARMTargetInfo(Triple, Opts) { 6180 TheCXXABI.set(TargetCXXABI::GenericARM); 6181 } 6182 6183 void getTargetDefines(const LangOptions &Opts, 6184 MacroBuilder &Builder) const override { 6185 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6186 DefineStd(Builder, "WIN32", Opts); 6187 DefineStd(Builder, "WINNT", Opts); 6188 Builder.defineMacro("_ARM_"); 6189 addMinGWDefines(Opts, Builder); 6190 } 6191 }; 6192 6193 // ARM Cygwin target 6194 class CygwinARMTargetInfo : public ARMleTargetInfo { 6195 public: 6196 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6197 : ARMleTargetInfo(Triple, Opts) { 6198 TLSSupported = false; 6199 WCharType = UnsignedShort; 6200 DoubleAlign = LongLongAlign = 64; 6201 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6202 } 6203 void getTargetDefines(const LangOptions &Opts, 6204 MacroBuilder &Builder) const override { 6205 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6206 Builder.defineMacro("_ARM_"); 6207 Builder.defineMacro("__CYGWIN__"); 6208 Builder.defineMacro("__CYGWIN32__"); 6209 DefineStd(Builder, "unix", Opts); 6210 if (Opts.CPlusPlus) 6211 Builder.defineMacro("_GNU_SOURCE"); 6212 } 6213 }; 6214 6215 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6216 protected: 6217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6218 MacroBuilder &Builder) const override { 6219 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6220 } 6221 6222 public: 6223 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6224 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6225 HasAlignMac68kSupport = true; 6226 // iOS always has 64-bit atomic instructions. 6227 // FIXME: This should be based off of the target features in 6228 // ARMleTargetInfo. 6229 MaxAtomicInlineWidth = 64; 6230 6231 if (Triple.isWatchABI()) { 6232 // Darwin on iOS uses a variant of the ARM C++ ABI. 6233 TheCXXABI.set(TargetCXXABI::WatchOS); 6234 6235 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6236 // size_t is long, it's a bit weird for it to be int. 6237 PtrDiffType = SignedLong; 6238 6239 // BOOL should be a real boolean on the new ABI 6240 UseSignedCharForObjCBool = false; 6241 } else 6242 TheCXXABI.set(TargetCXXABI::iOS); 6243 } 6244 }; 6245 6246 class AArch64TargetInfo : public TargetInfo { 6247 virtual void setDataLayout() = 0; 6248 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6249 static const char *const GCCRegNames[]; 6250 6251 enum FPUModeEnum { 6252 FPUMode, 6253 NeonMode = (1 << 0), 6254 SveMode = (1 << 1) 6255 }; 6256 6257 unsigned FPU; 6258 unsigned CRC; 6259 unsigned Crypto; 6260 unsigned Unaligned; 6261 unsigned HasFullFP16; 6262 llvm::AArch64::ArchKind ArchKind; 6263 6264 static const Builtin::Info BuiltinInfo[]; 6265 6266 std::string ABI; 6267 6268 public: 6269 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6270 : TargetInfo(Triple), ABI("aapcs") { 6271 if (getTriple().getOS() == llvm::Triple::NetBSD || 6272 getTriple().getOS() == llvm::Triple::OpenBSD) { 6273 WCharType = SignedInt; 6274 6275 // NetBSD apparently prefers consistency across ARM targets to consistency 6276 // across 64-bit targets. 6277 Int64Type = SignedLongLong; 6278 IntMaxType = SignedLongLong; 6279 } else { 6280 WCharType = UnsignedInt; 6281 Int64Type = SignedLong; 6282 IntMaxType = SignedLong; 6283 } 6284 6285 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6286 MaxVectorAlign = 128; 6287 MaxAtomicInlineWidth = 128; 6288 MaxAtomicPromoteWidth = 128; 6289 6290 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6291 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6292 6293 // Make __builtin_ms_va_list available. 6294 HasBuiltinMSVaList = true; 6295 6296 // {} in inline assembly are neon specifiers, not assembly variant 6297 // specifiers. 6298 NoAsmVariants = true; 6299 6300 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6301 // contributes to the alignment of the containing aggregate in the same way 6302 // a plain (non bit-field) member of that type would, without exception for 6303 // zero-sized or anonymous bit-fields." 6304 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6305 UseZeroLengthBitfieldAlignment = true; 6306 6307 // AArch64 targets default to using the ARM C++ ABI. 6308 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6309 6310 if (Triple.getOS() == llvm::Triple::Linux) 6311 this->MCountName = "\01_mcount"; 6312 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6313 this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount"; 6314 } 6315 6316 StringRef getABI() const override { return ABI; } 6317 bool setABI(const std::string &Name) override { 6318 if (Name != "aapcs" && Name != "darwinpcs") 6319 return false; 6320 6321 ABI = Name; 6322 return true; 6323 } 6324 6325 bool setCPU(const std::string &Name) override { 6326 return Name == "generic" || 6327 llvm::AArch64::parseCPUArch(Name) != 6328 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6329 } 6330 6331 void getTargetDefinesARMV81A(const LangOptions &Opts, 6332 MacroBuilder &Builder) const { 6333 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6334 } 6335 6336 void getTargetDefinesARMV82A(const LangOptions &Opts, 6337 MacroBuilder &Builder) const { 6338 // Also include the ARMv8.1 defines 6339 getTargetDefinesARMV81A(Opts, Builder); 6340 } 6341 6342 void getTargetDefines(const LangOptions &Opts, 6343 MacroBuilder &Builder) const override { 6344 // Target identification. 6345 Builder.defineMacro("__aarch64__"); 6346 // For bare-metal none-eabi. 6347 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6348 (getTriple().getEnvironment() == llvm::Triple::EABI || 6349 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6350 Builder.defineMacro("__ELF__"); 6351 6352 // Target properties. 6353 Builder.defineMacro("_LP64"); 6354 Builder.defineMacro("__LP64__"); 6355 6356 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6357 Builder.defineMacro("__ARM_ACLE", "200"); 6358 Builder.defineMacro("__ARM_ARCH", "8"); 6359 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6360 6361 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6362 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6363 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6364 6365 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6366 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6367 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6368 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6369 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6370 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6371 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6372 6373 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6374 6375 // 0xe implies support for half, single and double precision operations. 6376 Builder.defineMacro("__ARM_FP", "0xE"); 6377 6378 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6379 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6380 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6381 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6382 6383 if (Opts.UnsafeFPMath) 6384 Builder.defineMacro("__ARM_FP_FAST", "1"); 6385 6386 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6387 6388 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6389 Opts.ShortEnums ? "1" : "4"); 6390 6391 if (FPU & NeonMode) { 6392 Builder.defineMacro("__ARM_NEON", "1"); 6393 // 64-bit NEON supports half, single and double precision operations. 6394 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6395 } 6396 6397 if (FPU & SveMode) 6398 Builder.defineMacro("__ARM_FEATURE_SVE", "1"); 6399 6400 if (CRC) 6401 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6402 6403 if (Crypto) 6404 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6405 6406 if (Unaligned) 6407 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6408 6409 switch(ArchKind) { 6410 default: break; 6411 case llvm::AArch64::ArchKind::AK_ARMV8_1A: 6412 getTargetDefinesARMV81A(Opts, Builder); 6413 break; 6414 case llvm::AArch64::ArchKind::AK_ARMV8_2A: 6415 getTargetDefinesARMV82A(Opts, Builder); 6416 break; 6417 } 6418 6419 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6420 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6421 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6422 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6423 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6424 } 6425 6426 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6427 return llvm::makeArrayRef(BuiltinInfo, 6428 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6429 } 6430 6431 bool hasFeature(StringRef Feature) const override { 6432 return Feature == "aarch64" || 6433 Feature == "arm64" || 6434 Feature == "arm" || 6435 (Feature == "neon" && (FPU & NeonMode)) || 6436 (Feature == "sve" && (FPU & SveMode)); 6437 } 6438 6439 bool handleTargetFeatures(std::vector<std::string> &Features, 6440 DiagnosticsEngine &Diags) override { 6441 FPU = FPUMode; 6442 CRC = 0; 6443 Crypto = 0; 6444 Unaligned = 1; 6445 HasFullFP16 = 0; 6446 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A; 6447 6448 for (const auto &Feature : Features) { 6449 if (Feature == "+neon") 6450 FPU |= NeonMode; 6451 if (Feature == "+sve") 6452 FPU |= SveMode; 6453 if (Feature == "+crc") 6454 CRC = 1; 6455 if (Feature == "+crypto") 6456 Crypto = 1; 6457 if (Feature == "+strict-align") 6458 Unaligned = 0; 6459 if (Feature == "+v8.1a") 6460 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A; 6461 if (Feature == "+v8.2a") 6462 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A; 6463 if (Feature == "+fullfp16") 6464 HasFullFP16 = 1; 6465 } 6466 6467 setDataLayout(); 6468 6469 return true; 6470 } 6471 6472 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6473 switch (CC) { 6474 case CC_C: 6475 case CC_Swift: 6476 case CC_PreserveMost: 6477 case CC_PreserveAll: 6478 case CC_OpenCLKernel: 6479 case CC_Win64: 6480 return CCCR_OK; 6481 default: 6482 return CCCR_Warning; 6483 } 6484 } 6485 6486 bool isCLZForZeroUndef() const override { return false; } 6487 6488 BuiltinVaListKind getBuiltinVaListKind() const override { 6489 return TargetInfo::AArch64ABIBuiltinVaList; 6490 } 6491 6492 ArrayRef<const char *> getGCCRegNames() const override; 6493 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6494 6495 bool validateAsmConstraint(const char *&Name, 6496 TargetInfo::ConstraintInfo &Info) const override { 6497 switch (*Name) { 6498 default: 6499 return false; 6500 case 'w': // Floating point and SIMD registers (V0-V31) 6501 Info.setAllowsRegister(); 6502 return true; 6503 case 'I': // Constant that can be used with an ADD instruction 6504 case 'J': // Constant that can be used with a SUB instruction 6505 case 'K': // Constant that can be used with a 32-bit logical instruction 6506 case 'L': // Constant that can be used with a 64-bit logical instruction 6507 case 'M': // Constant that can be used as a 32-bit MOV immediate 6508 case 'N': // Constant that can be used as a 64-bit MOV immediate 6509 case 'Y': // Floating point constant zero 6510 case 'Z': // Integer constant zero 6511 return true; 6512 case 'Q': // A memory reference with base register and no offset 6513 Info.setAllowsMemory(); 6514 return true; 6515 case 'S': // A symbolic address 6516 Info.setAllowsRegister(); 6517 return true; 6518 case 'U': 6519 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6520 // Utf: A memory address suitable for ldp/stp in TF mode. 6521 // Usa: An absolute symbolic address. 6522 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6523 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6524 case 'z': // Zero register, wzr or xzr 6525 Info.setAllowsRegister(); 6526 return true; 6527 case 'x': // Floating point and SIMD registers (V0-V15) 6528 Info.setAllowsRegister(); 6529 return true; 6530 } 6531 return false; 6532 } 6533 6534 bool 6535 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6536 std::string &SuggestedModifier) const override { 6537 // Strip off constraint modifiers. 6538 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6539 Constraint = Constraint.substr(1); 6540 6541 switch (Constraint[0]) { 6542 default: 6543 return true; 6544 case 'z': 6545 case 'r': { 6546 switch (Modifier) { 6547 case 'x': 6548 case 'w': 6549 // For now assume that the person knows what they're 6550 // doing with the modifier. 6551 return true; 6552 default: 6553 // By default an 'r' constraint will be in the 'x' 6554 // registers. 6555 if (Size == 64) 6556 return true; 6557 6558 SuggestedModifier = "w"; 6559 return false; 6560 } 6561 } 6562 } 6563 } 6564 6565 const char *getClobbers() const override { return ""; } 6566 6567 int getEHDataRegisterNumber(unsigned RegNo) const override { 6568 if (RegNo == 0) 6569 return 0; 6570 if (RegNo == 1) 6571 return 1; 6572 return -1; 6573 } 6574 }; 6575 6576 const char *const AArch64TargetInfo::GCCRegNames[] = { 6577 // 32-bit Integer registers 6578 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6579 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6580 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6581 6582 // 64-bit Integer registers 6583 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6584 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6585 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6586 6587 // 32-bit floating point regsisters 6588 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6589 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6590 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6591 6592 // 64-bit floating point regsisters 6593 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6594 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6595 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6596 6597 // Vector registers 6598 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6599 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6600 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6601 }; 6602 6603 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6604 return llvm::makeArrayRef(GCCRegNames); 6605 } 6606 6607 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6608 { { "w31" }, "wsp" }, 6609 { { "x29" }, "fp" }, 6610 { { "x30" }, "lr" }, 6611 { { "x31" }, "sp" }, 6612 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6613 // don't want to substitute one of these for a different-sized one. 6614 }; 6615 6616 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6617 return llvm::makeArrayRef(GCCRegAliases); 6618 } 6619 6620 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6621 #define BUILTIN(ID, TYPE, ATTRS) \ 6622 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6623 #include "clang/Basic/BuiltinsNEON.def" 6624 6625 #define BUILTIN(ID, TYPE, ATTRS) \ 6626 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6627 #include "clang/Basic/BuiltinsAArch64.def" 6628 }; 6629 6630 class AArch64leTargetInfo : public AArch64TargetInfo { 6631 void setDataLayout() override { 6632 if (getTriple().isOSBinFormatMachO()) 6633 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6634 else 6635 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6636 } 6637 6638 public: 6639 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6640 : AArch64TargetInfo(Triple, Opts) { 6641 } 6642 void getTargetDefines(const LangOptions &Opts, 6643 MacroBuilder &Builder) const override { 6644 Builder.defineMacro("__AARCH64EL__"); 6645 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6646 } 6647 }; 6648 6649 class MicrosoftARM64TargetInfo 6650 : public WindowsTargetInfo<AArch64leTargetInfo> { 6651 const llvm::Triple Triple; 6652 6653 public: 6654 MicrosoftARM64TargetInfo(const llvm::Triple &Triple, 6655 const TargetOptions &Opts) 6656 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) { 6657 6658 // This is an LLP64 platform. 6659 // int:4, long:4, long long:8, long double:8. 6660 WCharType = UnsignedShort; 6661 IntWidth = IntAlign = 32; 6662 LongWidth = LongAlign = 32; 6663 DoubleAlign = LongLongAlign = 64; 6664 LongDoubleWidth = LongDoubleAlign = 64; 6665 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6666 IntMaxType = SignedLongLong; 6667 Int64Type = SignedLongLong; 6668 SizeType = UnsignedLongLong; 6669 PtrDiffType = SignedLongLong; 6670 IntPtrType = SignedLongLong; 6671 6672 TheCXXABI.set(TargetCXXABI::Microsoft); 6673 } 6674 6675 void setDataLayout() override { 6676 resetDataLayout("e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"); 6677 } 6678 6679 void getVisualStudioDefines(const LangOptions &Opts, 6680 MacroBuilder &Builder) const { 6681 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, 6682 Builder); 6683 Builder.defineMacro("_WIN32", "1"); 6684 Builder.defineMacro("_WIN64", "1"); 6685 Builder.defineMacro("_M_ARM64", "1"); 6686 } 6687 6688 void getTargetDefines(const LangOptions &Opts, 6689 MacroBuilder &Builder) const override { 6690 WindowsTargetInfo::getTargetDefines(Opts, Builder); 6691 getVisualStudioDefines(Opts, Builder); 6692 } 6693 6694 BuiltinVaListKind getBuiltinVaListKind() const override { 6695 return TargetInfo::CharPtrBuiltinVaList; 6696 } 6697 }; 6698 6699 class AArch64beTargetInfo : public AArch64TargetInfo { 6700 void setDataLayout() override { 6701 assert(!getTriple().isOSBinFormatMachO()); 6702 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6703 } 6704 6705 public: 6706 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6707 : AArch64TargetInfo(Triple, Opts) {} 6708 void getTargetDefines(const LangOptions &Opts, 6709 MacroBuilder &Builder) const override { 6710 Builder.defineMacro("__AARCH64EB__"); 6711 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6712 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6713 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6714 } 6715 }; 6716 6717 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6718 protected: 6719 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6720 MacroBuilder &Builder) const override { 6721 Builder.defineMacro("__AARCH64_SIMD__"); 6722 Builder.defineMacro("__ARM64_ARCH_8__"); 6723 Builder.defineMacro("__ARM_NEON__"); 6724 Builder.defineMacro("__LITTLE_ENDIAN__"); 6725 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6726 Builder.defineMacro("__arm64", "1"); 6727 Builder.defineMacro("__arm64__", "1"); 6728 6729 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6730 } 6731 6732 public: 6733 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6734 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6735 Int64Type = SignedLongLong; 6736 WCharType = SignedInt; 6737 UseSignedCharForObjCBool = false; 6738 6739 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6740 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6741 6742 TheCXXABI.set(TargetCXXABI::iOS64); 6743 } 6744 6745 BuiltinVaListKind getBuiltinVaListKind() const override { 6746 return TargetInfo::CharPtrBuiltinVaList; 6747 } 6748 }; 6749 6750 // Hexagon abstract base class 6751 class HexagonTargetInfo : public TargetInfo { 6752 static const Builtin::Info BuiltinInfo[]; 6753 static const char * const GCCRegNames[]; 6754 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6755 std::string CPU; 6756 bool HasHVX, HasHVXDouble; 6757 bool UseLongCalls; 6758 6759 public: 6760 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6761 : TargetInfo(Triple) { 6762 // Specify the vector alignment explicitly. For v512x1, the calculated 6763 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6764 // the required minimum of 64 bytes. 6765 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6766 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6767 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6768 SizeType = UnsignedInt; 6769 PtrDiffType = SignedInt; 6770 IntPtrType = SignedInt; 6771 6772 // {} in inline assembly are packet specifiers, not assembly variant 6773 // specifiers. 6774 NoAsmVariants = true; 6775 6776 LargeArrayMinWidth = 64; 6777 LargeArrayAlign = 64; 6778 UseBitFieldTypeAlignment = true; 6779 ZeroLengthBitfieldBoundary = 32; 6780 HasHVX = HasHVXDouble = false; 6781 UseLongCalls = false; 6782 } 6783 6784 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6785 return llvm::makeArrayRef(BuiltinInfo, 6786 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6787 } 6788 6789 bool validateAsmConstraint(const char *&Name, 6790 TargetInfo::ConstraintInfo &Info) const override { 6791 switch (*Name) { 6792 case 'v': 6793 case 'q': 6794 if (HasHVX) { 6795 Info.setAllowsRegister(); 6796 return true; 6797 } 6798 break; 6799 case 's': 6800 // Relocatable constant. 6801 return true; 6802 } 6803 return false; 6804 } 6805 6806 void getTargetDefines(const LangOptions &Opts, 6807 MacroBuilder &Builder) const override; 6808 6809 bool isCLZForZeroUndef() const override { return false; } 6810 6811 bool hasFeature(StringRef Feature) const override { 6812 return llvm::StringSwitch<bool>(Feature) 6813 .Case("hexagon", true) 6814 .Case("hvx", HasHVX) 6815 .Case("hvx-double", HasHVXDouble) 6816 .Case("long-calls", UseLongCalls) 6817 .Default(false); 6818 } 6819 6820 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6821 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6822 const override; 6823 6824 bool handleTargetFeatures(std::vector<std::string> &Features, 6825 DiagnosticsEngine &Diags) override; 6826 6827 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6828 bool Enabled) const override; 6829 6830 BuiltinVaListKind getBuiltinVaListKind() const override { 6831 return TargetInfo::CharPtrBuiltinVaList; 6832 } 6833 ArrayRef<const char *> getGCCRegNames() const override; 6834 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6835 const char *getClobbers() const override { 6836 return ""; 6837 } 6838 6839 static const char *getHexagonCPUSuffix(StringRef Name) { 6840 return llvm::StringSwitch<const char*>(Name) 6841 .Case("hexagonv4", "4") 6842 .Case("hexagonv5", "5") 6843 .Case("hexagonv55", "55") 6844 .Case("hexagonv60", "60") 6845 .Case("hexagonv62", "62") 6846 .Default(nullptr); 6847 } 6848 6849 bool setCPU(const std::string &Name) override { 6850 if (!getHexagonCPUSuffix(Name)) 6851 return false; 6852 CPU = Name; 6853 return true; 6854 } 6855 6856 int getEHDataRegisterNumber(unsigned RegNo) const override { 6857 return RegNo < 2 ? RegNo : -1; 6858 } 6859 }; 6860 6861 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6862 MacroBuilder &Builder) const { 6863 Builder.defineMacro("__qdsp6__", "1"); 6864 Builder.defineMacro("__hexagon__", "1"); 6865 6866 if (CPU == "hexagonv4") { 6867 Builder.defineMacro("__HEXAGON_V4__"); 6868 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6869 if (Opts.HexagonQdsp6Compat) { 6870 Builder.defineMacro("__QDSP6_V4__"); 6871 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6872 } 6873 } else if (CPU == "hexagonv5") { 6874 Builder.defineMacro("__HEXAGON_V5__"); 6875 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6876 if(Opts.HexagonQdsp6Compat) { 6877 Builder.defineMacro("__QDSP6_V5__"); 6878 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6879 } 6880 } else if (CPU == "hexagonv55") { 6881 Builder.defineMacro("__HEXAGON_V55__"); 6882 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6883 Builder.defineMacro("__QDSP6_V55__"); 6884 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6885 } else if (CPU == "hexagonv60") { 6886 Builder.defineMacro("__HEXAGON_V60__"); 6887 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6888 Builder.defineMacro("__QDSP6_V60__"); 6889 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6890 } else if (CPU == "hexagonv62") { 6891 Builder.defineMacro("__HEXAGON_V62__"); 6892 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6893 } 6894 6895 if (hasFeature("hvx")) { 6896 Builder.defineMacro("__HVX__"); 6897 if (hasFeature("hvx-double")) 6898 Builder.defineMacro("__HVXDBL__"); 6899 } 6900 } 6901 6902 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6903 DiagnosticsEngine &Diags, StringRef CPU, 6904 const std::vector<std::string> &FeaturesVec) const { 6905 // Default for v60: -hvx, -hvx-double. 6906 Features["hvx"] = false; 6907 Features["hvx-double"] = false; 6908 Features["long-calls"] = false; 6909 6910 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6911 } 6912 6913 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6914 DiagnosticsEngine &Diags) { 6915 for (auto &F : Features) { 6916 if (F == "+hvx") 6917 HasHVX = true; 6918 else if (F == "-hvx") 6919 HasHVX = HasHVXDouble = false; 6920 else if (F == "+hvx-double") 6921 HasHVX = HasHVXDouble = true; 6922 else if (F == "-hvx-double") 6923 HasHVXDouble = false; 6924 6925 if (F == "+long-calls") 6926 UseLongCalls = true; 6927 else if (F == "-long-calls") 6928 UseLongCalls = false; 6929 } 6930 return true; 6931 } 6932 6933 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6934 StringRef Name, bool Enabled) const { 6935 if (Enabled) { 6936 if (Name == "hvx-double") 6937 Features["hvx"] = true; 6938 } else { 6939 if (Name == "hvx") 6940 Features["hvx-double"] = false; 6941 } 6942 Features[Name] = Enabled; 6943 } 6944 6945 const char *const HexagonTargetInfo::GCCRegNames[] = { 6946 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6947 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6948 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6949 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6950 "p0", "p1", "p2", "p3", 6951 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6952 }; 6953 6954 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6955 return llvm::makeArrayRef(GCCRegNames); 6956 } 6957 6958 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6959 { { "sp" }, "r29" }, 6960 { { "fp" }, "r30" }, 6961 { { "lr" }, "r31" }, 6962 }; 6963 6964 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6965 return llvm::makeArrayRef(GCCRegAliases); 6966 } 6967 6968 6969 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6970 #define BUILTIN(ID, TYPE, ATTRS) \ 6971 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6972 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6973 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6974 #include "clang/Basic/BuiltinsHexagon.def" 6975 }; 6976 6977 class LanaiTargetInfo : public TargetInfo { 6978 // Class for Lanai (32-bit). 6979 // The CPU profiles supported by the Lanai backend 6980 enum CPUKind { 6981 CK_NONE, 6982 CK_V11, 6983 } CPU; 6984 6985 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6986 static const char *const GCCRegNames[]; 6987 6988 public: 6989 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6990 : TargetInfo(Triple) { 6991 // Description string has to be kept in sync with backend. 6992 resetDataLayout("E" // Big endian 6993 "-m:e" // ELF name manging 6994 "-p:32:32" // 32 bit pointers, 32 bit aligned 6995 "-i64:64" // 64 bit integers, 64 bit aligned 6996 "-a:0:32" // 32 bit alignment of objects of aggregate type 6997 "-n32" // 32 bit native integer width 6998 "-S64" // 64 bit natural stack alignment 6999 ); 7000 7001 // Setting RegParmMax equal to what mregparm was set to in the old 7002 // toolchain 7003 RegParmMax = 4; 7004 7005 // Set the default CPU to V11 7006 CPU = CK_V11; 7007 7008 // Temporary approach to make everything at least word-aligned and allow for 7009 // safely casting between pointers with different alignment requirements. 7010 // TODO: Remove this when there are no more cast align warnings on the 7011 // firmware. 7012 MinGlobalAlign = 32; 7013 } 7014 7015 void getTargetDefines(const LangOptions &Opts, 7016 MacroBuilder &Builder) const override { 7017 // Define __lanai__ when building for target lanai. 7018 Builder.defineMacro("__lanai__"); 7019 7020 // Set define for the CPU specified. 7021 switch (CPU) { 7022 case CK_V11: 7023 Builder.defineMacro("__LANAI_V11__"); 7024 break; 7025 case CK_NONE: 7026 llvm_unreachable("Unhandled target CPU"); 7027 } 7028 } 7029 7030 bool setCPU(const std::string &Name) override { 7031 CPU = llvm::StringSwitch<CPUKind>(Name) 7032 .Case("v11", CK_V11) 7033 .Default(CK_NONE); 7034 7035 return CPU != CK_NONE; 7036 } 7037 7038 bool hasFeature(StringRef Feature) const override { 7039 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 7040 } 7041 7042 ArrayRef<const char *> getGCCRegNames() const override; 7043 7044 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7045 7046 BuiltinVaListKind getBuiltinVaListKind() const override { 7047 return TargetInfo::VoidPtrBuiltinVaList; 7048 } 7049 7050 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7051 7052 bool validateAsmConstraint(const char *&Name, 7053 TargetInfo::ConstraintInfo &info) const override { 7054 return false; 7055 } 7056 7057 const char *getClobbers() const override { return ""; } 7058 }; 7059 7060 const char *const LanaiTargetInfo::GCCRegNames[] = { 7061 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7062 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 7063 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 7064 7065 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 7066 return llvm::makeArrayRef(GCCRegNames); 7067 } 7068 7069 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 7070 {{"pc"}, "r2"}, 7071 {{"sp"}, "r4"}, 7072 {{"fp"}, "r5"}, 7073 {{"rv"}, "r8"}, 7074 {{"rr1"}, "r10"}, 7075 {{"rr2"}, "r11"}, 7076 {{"rca"}, "r15"}, 7077 }; 7078 7079 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 7080 return llvm::makeArrayRef(GCCRegAliases); 7081 } 7082 7083 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 7084 class SparcTargetInfo : public TargetInfo { 7085 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 7086 static const char * const GCCRegNames[]; 7087 bool SoftFloat; 7088 public: 7089 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7090 : TargetInfo(Triple), SoftFloat(false) {} 7091 7092 int getEHDataRegisterNumber(unsigned RegNo) const override { 7093 if (RegNo == 0) return 24; 7094 if (RegNo == 1) return 25; 7095 return -1; 7096 } 7097 7098 bool handleTargetFeatures(std::vector<std::string> &Features, 7099 DiagnosticsEngine &Diags) override { 7100 // Check if software floating point is enabled 7101 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 7102 if (Feature != Features.end()) { 7103 SoftFloat = true; 7104 } 7105 return true; 7106 } 7107 void getTargetDefines(const LangOptions &Opts, 7108 MacroBuilder &Builder) const override { 7109 DefineStd(Builder, "sparc", Opts); 7110 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7111 7112 if (SoftFloat) 7113 Builder.defineMacro("SOFT_FLOAT", "1"); 7114 } 7115 7116 bool hasFeature(StringRef Feature) const override { 7117 return llvm::StringSwitch<bool>(Feature) 7118 .Case("softfloat", SoftFloat) 7119 .Case("sparc", true) 7120 .Default(false); 7121 } 7122 7123 bool hasSjLjLowering() const override { 7124 return true; 7125 } 7126 7127 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7128 // FIXME: Implement! 7129 return None; 7130 } 7131 BuiltinVaListKind getBuiltinVaListKind() const override { 7132 return TargetInfo::VoidPtrBuiltinVaList; 7133 } 7134 ArrayRef<const char *> getGCCRegNames() const override; 7135 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7136 bool validateAsmConstraint(const char *&Name, 7137 TargetInfo::ConstraintInfo &info) const override { 7138 // FIXME: Implement! 7139 switch (*Name) { 7140 case 'I': // Signed 13-bit constant 7141 case 'J': // Zero 7142 case 'K': // 32-bit constant with the low 12 bits clear 7143 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 7144 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 7145 case 'N': // Same as 'K' but zext (required for SIMode) 7146 case 'O': // The constant 4096 7147 return true; 7148 7149 case 'f': 7150 case 'e': 7151 info.setAllowsRegister(); 7152 return true; 7153 } 7154 return false; 7155 } 7156 const char *getClobbers() const override { 7157 // FIXME: Implement! 7158 return ""; 7159 } 7160 7161 // No Sparc V7 for now, the backend doesn't support it anyway. 7162 enum CPUKind { 7163 CK_GENERIC, 7164 CK_V8, 7165 CK_SUPERSPARC, 7166 CK_SPARCLITE, 7167 CK_F934, 7168 CK_HYPERSPARC, 7169 CK_SPARCLITE86X, 7170 CK_SPARCLET, 7171 CK_TSC701, 7172 CK_V9, 7173 CK_ULTRASPARC, 7174 CK_ULTRASPARC3, 7175 CK_NIAGARA, 7176 CK_NIAGARA2, 7177 CK_NIAGARA3, 7178 CK_NIAGARA4, 7179 CK_MYRIAD2100, 7180 CK_MYRIAD2150, 7181 CK_MYRIAD2450, 7182 CK_LEON2, 7183 CK_LEON2_AT697E, 7184 CK_LEON2_AT697F, 7185 CK_LEON3, 7186 CK_LEON3_UT699, 7187 CK_LEON3_GR712RC, 7188 CK_LEON4, 7189 CK_LEON4_GR740 7190 } CPU = CK_GENERIC; 7191 7192 enum CPUGeneration { 7193 CG_V8, 7194 CG_V9, 7195 }; 7196 7197 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7198 switch (Kind) { 7199 case CK_GENERIC: 7200 case CK_V8: 7201 case CK_SUPERSPARC: 7202 case CK_SPARCLITE: 7203 case CK_F934: 7204 case CK_HYPERSPARC: 7205 case CK_SPARCLITE86X: 7206 case CK_SPARCLET: 7207 case CK_TSC701: 7208 case CK_MYRIAD2100: 7209 case CK_MYRIAD2150: 7210 case CK_MYRIAD2450: 7211 case CK_LEON2: 7212 case CK_LEON2_AT697E: 7213 case CK_LEON2_AT697F: 7214 case CK_LEON3: 7215 case CK_LEON3_UT699: 7216 case CK_LEON3_GR712RC: 7217 case CK_LEON4: 7218 case CK_LEON4_GR740: 7219 return CG_V8; 7220 case CK_V9: 7221 case CK_ULTRASPARC: 7222 case CK_ULTRASPARC3: 7223 case CK_NIAGARA: 7224 case CK_NIAGARA2: 7225 case CK_NIAGARA3: 7226 case CK_NIAGARA4: 7227 return CG_V9; 7228 } 7229 llvm_unreachable("Unexpected CPU kind"); 7230 } 7231 7232 CPUKind getCPUKind(StringRef Name) const { 7233 return llvm::StringSwitch<CPUKind>(Name) 7234 .Case("v8", CK_V8) 7235 .Case("supersparc", CK_SUPERSPARC) 7236 .Case("sparclite", CK_SPARCLITE) 7237 .Case("f934", CK_F934) 7238 .Case("hypersparc", CK_HYPERSPARC) 7239 .Case("sparclite86x", CK_SPARCLITE86X) 7240 .Case("sparclet", CK_SPARCLET) 7241 .Case("tsc701", CK_TSC701) 7242 .Case("v9", CK_V9) 7243 .Case("ultrasparc", CK_ULTRASPARC) 7244 .Case("ultrasparc3", CK_ULTRASPARC3) 7245 .Case("niagara", CK_NIAGARA) 7246 .Case("niagara2", CK_NIAGARA2) 7247 .Case("niagara3", CK_NIAGARA3) 7248 .Case("niagara4", CK_NIAGARA4) 7249 .Case("ma2100", CK_MYRIAD2100) 7250 .Case("ma2150", CK_MYRIAD2150) 7251 .Case("ma2450", CK_MYRIAD2450) 7252 // FIXME: the myriad2[.n] spellings are obsolete, 7253 // but a grace period is needed to allow updating dependent builds. 7254 .Case("myriad2", CK_MYRIAD2100) 7255 .Case("myriad2.1", CK_MYRIAD2100) 7256 .Case("myriad2.2", CK_MYRIAD2150) 7257 .Case("leon2", CK_LEON2) 7258 .Case("at697e", CK_LEON2_AT697E) 7259 .Case("at697f", CK_LEON2_AT697F) 7260 .Case("leon3", CK_LEON3) 7261 .Case("ut699", CK_LEON3_UT699) 7262 .Case("gr712rc", CK_LEON3_GR712RC) 7263 .Case("leon4", CK_LEON4) 7264 .Case("gr740", CK_LEON4_GR740) 7265 .Default(CK_GENERIC); 7266 } 7267 7268 bool setCPU(const std::string &Name) override { 7269 CPU = getCPUKind(Name); 7270 return CPU != CK_GENERIC; 7271 } 7272 }; 7273 7274 const char * const SparcTargetInfo::GCCRegNames[] = { 7275 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7276 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7277 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7278 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7279 }; 7280 7281 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7282 return llvm::makeArrayRef(GCCRegNames); 7283 } 7284 7285 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7286 { { "g0" }, "r0" }, 7287 { { "g1" }, "r1" }, 7288 { { "g2" }, "r2" }, 7289 { { "g3" }, "r3" }, 7290 { { "g4" }, "r4" }, 7291 { { "g5" }, "r5" }, 7292 { { "g6" }, "r6" }, 7293 { { "g7" }, "r7" }, 7294 { { "o0" }, "r8" }, 7295 { { "o1" }, "r9" }, 7296 { { "o2" }, "r10" }, 7297 { { "o3" }, "r11" }, 7298 { { "o4" }, "r12" }, 7299 { { "o5" }, "r13" }, 7300 { { "o6", "sp" }, "r14" }, 7301 { { "o7" }, "r15" }, 7302 { { "l0" }, "r16" }, 7303 { { "l1" }, "r17" }, 7304 { { "l2" }, "r18" }, 7305 { { "l3" }, "r19" }, 7306 { { "l4" }, "r20" }, 7307 { { "l5" }, "r21" }, 7308 { { "l6" }, "r22" }, 7309 { { "l7" }, "r23" }, 7310 { { "i0" }, "r24" }, 7311 { { "i1" }, "r25" }, 7312 { { "i2" }, "r26" }, 7313 { { "i3" }, "r27" }, 7314 { { "i4" }, "r28" }, 7315 { { "i5" }, "r29" }, 7316 { { "i6", "fp" }, "r30" }, 7317 { { "i7" }, "r31" }, 7318 }; 7319 7320 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7321 return llvm::makeArrayRef(GCCRegAliases); 7322 } 7323 7324 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7325 class SparcV8TargetInfo : public SparcTargetInfo { 7326 public: 7327 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7328 : SparcTargetInfo(Triple, Opts) { 7329 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7330 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7331 switch (getTriple().getOS()) { 7332 default: 7333 SizeType = UnsignedInt; 7334 IntPtrType = SignedInt; 7335 PtrDiffType = SignedInt; 7336 break; 7337 case llvm::Triple::NetBSD: 7338 case llvm::Triple::OpenBSD: 7339 SizeType = UnsignedLong; 7340 IntPtrType = SignedLong; 7341 PtrDiffType = SignedLong; 7342 break; 7343 } 7344 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7345 // on up to 64 bits. 7346 MaxAtomicPromoteWidth = 64; 7347 MaxAtomicInlineWidth = 32; 7348 } 7349 7350 void getTargetDefines(const LangOptions &Opts, 7351 MacroBuilder &Builder) const override { 7352 SparcTargetInfo::getTargetDefines(Opts, Builder); 7353 switch (getCPUGeneration(CPU)) { 7354 case CG_V8: 7355 Builder.defineMacro("__sparcv8"); 7356 if (getTriple().getOS() != llvm::Triple::Solaris) 7357 Builder.defineMacro("__sparcv8__"); 7358 break; 7359 case CG_V9: 7360 Builder.defineMacro("__sparcv9"); 7361 if (getTriple().getOS() != llvm::Triple::Solaris) { 7362 Builder.defineMacro("__sparcv9__"); 7363 Builder.defineMacro("__sparc_v9__"); 7364 } 7365 break; 7366 } 7367 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7368 std::string MyriadArchValue, Myriad2Value; 7369 Builder.defineMacro("__sparc_v8__"); 7370 Builder.defineMacro("__leon__"); 7371 switch (CPU) { 7372 case CK_MYRIAD2150: 7373 MyriadArchValue = "__ma2150"; 7374 Myriad2Value = "2"; 7375 break; 7376 case CK_MYRIAD2450: 7377 MyriadArchValue = "__ma2450"; 7378 Myriad2Value = "2"; 7379 break; 7380 default: 7381 MyriadArchValue = "__ma2100"; 7382 Myriad2Value = "1"; 7383 break; 7384 } 7385 Builder.defineMacro(MyriadArchValue, "1"); 7386 Builder.defineMacro(MyriadArchValue+"__", "1"); 7387 Builder.defineMacro("__myriad2__", Myriad2Value); 7388 Builder.defineMacro("__myriad2", Myriad2Value); 7389 } 7390 } 7391 7392 bool hasSjLjLowering() const override { 7393 return true; 7394 } 7395 }; 7396 7397 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7398 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7399 public: 7400 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7401 : SparcV8TargetInfo(Triple, Opts) { 7402 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7403 } 7404 }; 7405 7406 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7407 class SparcV9TargetInfo : public SparcTargetInfo { 7408 public: 7409 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7410 : SparcTargetInfo(Triple, Opts) { 7411 // FIXME: Support Sparc quad-precision long double? 7412 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7413 // This is an LP64 platform. 7414 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7415 7416 // OpenBSD uses long long for int64_t and intmax_t. 7417 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7418 IntMaxType = SignedLongLong; 7419 else 7420 IntMaxType = SignedLong; 7421 Int64Type = IntMaxType; 7422 7423 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7424 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7425 LongDoubleWidth = 128; 7426 LongDoubleAlign = 128; 7427 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7428 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7429 } 7430 7431 void getTargetDefines(const LangOptions &Opts, 7432 MacroBuilder &Builder) const override { 7433 SparcTargetInfo::getTargetDefines(Opts, Builder); 7434 Builder.defineMacro("__sparcv9"); 7435 Builder.defineMacro("__arch64__"); 7436 // Solaris doesn't need these variants, but the BSDs do. 7437 if (getTriple().getOS() != llvm::Triple::Solaris) { 7438 Builder.defineMacro("__sparc64__"); 7439 Builder.defineMacro("__sparc_v9__"); 7440 Builder.defineMacro("__sparcv9__"); 7441 } 7442 } 7443 7444 bool setCPU(const std::string &Name) override { 7445 if (!SparcTargetInfo::setCPU(Name)) 7446 return false; 7447 return getCPUGeneration(CPU) == CG_V9; 7448 } 7449 }; 7450 7451 class SystemZTargetInfo : public TargetInfo { 7452 static const Builtin::Info BuiltinInfo[]; 7453 static const char *const GCCRegNames[]; 7454 std::string CPU; 7455 int ISARevision; 7456 bool HasTransactionalExecution; 7457 bool HasVector; 7458 7459 public: 7460 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7461 : TargetInfo(Triple), CPU("z10"), ISARevision(8), 7462 HasTransactionalExecution(false), HasVector(false) { 7463 IntMaxType = SignedLong; 7464 Int64Type = SignedLong; 7465 TLSSupported = true; 7466 IntWidth = IntAlign = 32; 7467 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7468 PointerWidth = PointerAlign = 64; 7469 LongDoubleWidth = 128; 7470 LongDoubleAlign = 64; 7471 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7472 DefaultAlignForAttributeAligned = 64; 7473 MinGlobalAlign = 16; 7474 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7475 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7476 } 7477 void getTargetDefines(const LangOptions &Opts, 7478 MacroBuilder &Builder) const override { 7479 Builder.defineMacro("__s390__"); 7480 Builder.defineMacro("__s390x__"); 7481 Builder.defineMacro("__zarch__"); 7482 Builder.defineMacro("__LONG_DOUBLE_128__"); 7483 7484 Builder.defineMacro("__ARCH__", Twine(ISARevision)); 7485 7486 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7487 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7488 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7489 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7490 7491 if (HasTransactionalExecution) 7492 Builder.defineMacro("__HTM__"); 7493 if (HasVector) 7494 Builder.defineMacro("__VX__"); 7495 if (Opts.ZVector) 7496 Builder.defineMacro("__VEC__", "10302"); 7497 } 7498 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7499 return llvm::makeArrayRef(BuiltinInfo, 7500 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7501 } 7502 7503 ArrayRef<const char *> getGCCRegNames() const override; 7504 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7505 // No aliases. 7506 return None; 7507 } 7508 bool validateAsmConstraint(const char *&Name, 7509 TargetInfo::ConstraintInfo &info) const override; 7510 const char *getClobbers() const override { 7511 // FIXME: Is this really right? 7512 return ""; 7513 } 7514 BuiltinVaListKind getBuiltinVaListKind() const override { 7515 return TargetInfo::SystemZBuiltinVaList; 7516 } 7517 int getISARevision(const StringRef &Name) const { 7518 return llvm::StringSwitch<int>(Name) 7519 .Cases("arch8", "z10", 8) 7520 .Cases("arch9", "z196", 9) 7521 .Cases("arch10", "zEC12", 10) 7522 .Cases("arch11", "z13", 11) 7523 .Cases("arch12", "z14", 12) 7524 .Default(-1); 7525 } 7526 bool setCPU(const std::string &Name) override { 7527 CPU = Name; 7528 ISARevision = getISARevision(CPU); 7529 return ISARevision != -1; 7530 } 7531 bool 7532 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7533 StringRef CPU, 7534 const std::vector<std::string> &FeaturesVec) const override { 7535 int ISARevision = getISARevision(CPU); 7536 if (ISARevision >= 10) 7537 Features["transactional-execution"] = true; 7538 if (ISARevision >= 11) 7539 Features["vector"] = true; 7540 if (ISARevision >= 12) 7541 Features["vector-enhancements-1"] = true; 7542 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7543 } 7544 7545 bool handleTargetFeatures(std::vector<std::string> &Features, 7546 DiagnosticsEngine &Diags) override { 7547 HasTransactionalExecution = false; 7548 HasVector = false; 7549 for (const auto &Feature : Features) { 7550 if (Feature == "+transactional-execution") 7551 HasTransactionalExecution = true; 7552 else if (Feature == "+vector") 7553 HasVector = true; 7554 } 7555 // If we use the vector ABI, vector types are 64-bit aligned. 7556 if (HasVector) { 7557 MaxVectorAlign = 64; 7558 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7559 "-v128:64-a:8:16-n32:64"); 7560 } 7561 return true; 7562 } 7563 7564 bool hasFeature(StringRef Feature) const override { 7565 return llvm::StringSwitch<bool>(Feature) 7566 .Case("systemz", true) 7567 .Case("arch8", ISARevision >= 8) 7568 .Case("arch9", ISARevision >= 9) 7569 .Case("arch10", ISARevision >= 10) 7570 .Case("arch11", ISARevision >= 11) 7571 .Case("arch12", ISARevision >= 12) 7572 .Case("htm", HasTransactionalExecution) 7573 .Case("vx", HasVector) 7574 .Default(false); 7575 } 7576 7577 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7578 switch (CC) { 7579 case CC_C: 7580 case CC_Swift: 7581 case CC_OpenCLKernel: 7582 return CCCR_OK; 7583 default: 7584 return CCCR_Warning; 7585 } 7586 } 7587 7588 StringRef getABI() const override { 7589 if (HasVector) 7590 return "vector"; 7591 return ""; 7592 } 7593 7594 bool useFloat128ManglingForLongDouble() const override { 7595 return true; 7596 } 7597 }; 7598 7599 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7600 #define BUILTIN(ID, TYPE, ATTRS) \ 7601 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7602 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7603 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7604 #include "clang/Basic/BuiltinsSystemZ.def" 7605 }; 7606 7607 const char *const SystemZTargetInfo::GCCRegNames[] = { 7608 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7609 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7610 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7611 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7612 }; 7613 7614 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7615 return llvm::makeArrayRef(GCCRegNames); 7616 } 7617 7618 bool SystemZTargetInfo:: 7619 validateAsmConstraint(const char *&Name, 7620 TargetInfo::ConstraintInfo &Info) const { 7621 switch (*Name) { 7622 default: 7623 return false; 7624 7625 case 'a': // Address register 7626 case 'd': // Data register (equivalent to 'r') 7627 case 'f': // Floating-point register 7628 Info.setAllowsRegister(); 7629 return true; 7630 7631 case 'I': // Unsigned 8-bit constant 7632 case 'J': // Unsigned 12-bit constant 7633 case 'K': // Signed 16-bit constant 7634 case 'L': // Signed 20-bit displacement (on all targets we support) 7635 case 'M': // 0x7fffffff 7636 return true; 7637 7638 case 'Q': // Memory with base and unsigned 12-bit displacement 7639 case 'R': // Likewise, plus an index 7640 case 'S': // Memory with base and signed 20-bit displacement 7641 case 'T': // Likewise, plus an index 7642 Info.setAllowsMemory(); 7643 return true; 7644 } 7645 } 7646 7647 class MSP430TargetInfo : public TargetInfo { 7648 static const char *const GCCRegNames[]; 7649 7650 public: 7651 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7652 : TargetInfo(Triple) { 7653 TLSSupported = false; 7654 IntWidth = 16; 7655 IntAlign = 16; 7656 LongWidth = 32; 7657 LongLongWidth = 64; 7658 LongAlign = LongLongAlign = 16; 7659 PointerWidth = 16; 7660 PointerAlign = 16; 7661 SuitableAlign = 16; 7662 SizeType = UnsignedInt; 7663 IntMaxType = SignedLongLong; 7664 IntPtrType = SignedInt; 7665 PtrDiffType = SignedInt; 7666 SigAtomicType = SignedLong; 7667 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"); 7668 } 7669 void getTargetDefines(const LangOptions &Opts, 7670 MacroBuilder &Builder) const override { 7671 Builder.defineMacro("MSP430"); 7672 Builder.defineMacro("__MSP430__"); 7673 // FIXME: defines for different 'flavours' of MCU 7674 } 7675 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7676 // FIXME: Implement. 7677 return None; 7678 } 7679 bool hasFeature(StringRef Feature) const override { 7680 return Feature == "msp430"; 7681 } 7682 ArrayRef<const char *> getGCCRegNames() const override; 7683 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7684 // No aliases. 7685 return None; 7686 } 7687 bool validateAsmConstraint(const char *&Name, 7688 TargetInfo::ConstraintInfo &info) const override { 7689 // FIXME: implement 7690 switch (*Name) { 7691 case 'K': // the constant 1 7692 case 'L': // constant -1^20 .. 1^19 7693 case 'M': // constant 1-4: 7694 return true; 7695 } 7696 // No target constraints for now. 7697 return false; 7698 } 7699 const char *getClobbers() const override { 7700 // FIXME: Is this really right? 7701 return ""; 7702 } 7703 BuiltinVaListKind getBuiltinVaListKind() const override { 7704 // FIXME: implement 7705 return TargetInfo::CharPtrBuiltinVaList; 7706 } 7707 }; 7708 7709 const char *const MSP430TargetInfo::GCCRegNames[] = { 7710 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7711 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7712 7713 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7714 return llvm::makeArrayRef(GCCRegNames); 7715 } 7716 7717 // LLVM and Clang cannot be used directly to output native binaries for 7718 // target, but is used to compile C code to llvm bitcode with correct 7719 // type and alignment information. 7720 // 7721 // TCE uses the llvm bitcode as input and uses it for generating customized 7722 // target processor and program binary. TCE co-design environment is 7723 // publicly available in http://tce.cs.tut.fi 7724 7725 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7726 0, // Default 7727 3, // opencl_global 7728 4, // opencl_local 7729 5, // opencl_constant 7730 // FIXME: generic has to be added to the target 7731 0, // opencl_generic 7732 0, // cuda_device 7733 0, // cuda_constant 7734 0 // cuda_shared 7735 }; 7736 7737 class TCETargetInfo : public TargetInfo { 7738 public: 7739 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7740 : TargetInfo(Triple) { 7741 TLSSupported = false; 7742 IntWidth = 32; 7743 LongWidth = LongLongWidth = 32; 7744 PointerWidth = 32; 7745 IntAlign = 32; 7746 LongAlign = LongLongAlign = 32; 7747 PointerAlign = 32; 7748 SuitableAlign = 32; 7749 SizeType = UnsignedInt; 7750 IntMaxType = SignedLong; 7751 IntPtrType = SignedInt; 7752 PtrDiffType = SignedInt; 7753 FloatWidth = 32; 7754 FloatAlign = 32; 7755 DoubleWidth = 32; 7756 DoubleAlign = 32; 7757 LongDoubleWidth = 32; 7758 LongDoubleAlign = 32; 7759 FloatFormat = &llvm::APFloat::IEEEsingle(); 7760 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7761 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7762 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7763 "i16:16:32-i32:32:32-i64:32:32-" 7764 "f32:32:32-f64:32:32-v64:32:32-" 7765 "v128:32:32-v256:32:32-v512:32:32-" 7766 "v1024:32:32-a0:0:32-n32"); 7767 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7768 UseAddrSpaceMapMangling = true; 7769 } 7770 7771 void getTargetDefines(const LangOptions &Opts, 7772 MacroBuilder &Builder) const override { 7773 DefineStd(Builder, "tce", Opts); 7774 Builder.defineMacro("__TCE__"); 7775 Builder.defineMacro("__TCE_V1__"); 7776 } 7777 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7778 7779 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7780 const char *getClobbers() const override { return ""; } 7781 BuiltinVaListKind getBuiltinVaListKind() const override { 7782 return TargetInfo::VoidPtrBuiltinVaList; 7783 } 7784 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7785 bool validateAsmConstraint(const char *&Name, 7786 TargetInfo::ConstraintInfo &info) const override { 7787 return true; 7788 } 7789 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7790 return None; 7791 } 7792 }; 7793 7794 class TCELETargetInfo : public TCETargetInfo { 7795 public: 7796 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7797 : TCETargetInfo(Triple, Opts) { 7798 BigEndian = false; 7799 7800 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7801 "i16:16:32-i32:32:32-i64:32:32-" 7802 "f32:32:32-f64:32:32-v64:32:32-" 7803 "v128:32:32-v256:32:32-v512:32:32-" 7804 "v1024:32:32-a0:0:32-n32"); 7805 7806 } 7807 7808 virtual void getTargetDefines(const LangOptions &Opts, 7809 MacroBuilder &Builder) const { 7810 DefineStd(Builder, "tcele", Opts); 7811 Builder.defineMacro("__TCE__"); 7812 Builder.defineMacro("__TCE_V1__"); 7813 Builder.defineMacro("__TCELE__"); 7814 Builder.defineMacro("__TCELE_V1__"); 7815 } 7816 7817 }; 7818 7819 class BPFTargetInfo : public TargetInfo { 7820 public: 7821 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7822 : TargetInfo(Triple) { 7823 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7824 SizeType = UnsignedLong; 7825 PtrDiffType = SignedLong; 7826 IntPtrType = SignedLong; 7827 IntMaxType = SignedLong; 7828 Int64Type = SignedLong; 7829 RegParmMax = 5; 7830 if (Triple.getArch() == llvm::Triple::bpfeb) { 7831 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7832 } else { 7833 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7834 } 7835 MaxAtomicPromoteWidth = 64; 7836 MaxAtomicInlineWidth = 64; 7837 TLSSupported = false; 7838 } 7839 void getTargetDefines(const LangOptions &Opts, 7840 MacroBuilder &Builder) const override { 7841 DefineStd(Builder, "bpf", Opts); 7842 Builder.defineMacro("__BPF__"); 7843 } 7844 bool hasFeature(StringRef Feature) const override { 7845 return Feature == "bpf"; 7846 } 7847 7848 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7849 const char *getClobbers() const override { 7850 return ""; 7851 } 7852 BuiltinVaListKind getBuiltinVaListKind() const override { 7853 return TargetInfo::VoidPtrBuiltinVaList; 7854 } 7855 ArrayRef<const char *> getGCCRegNames() const override { 7856 return None; 7857 } 7858 bool validateAsmConstraint(const char *&Name, 7859 TargetInfo::ConstraintInfo &info) const override { 7860 return true; 7861 } 7862 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7863 return None; 7864 } 7865 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7866 switch (CC) { 7867 default: 7868 return CCCR_Warning; 7869 case CC_C: 7870 case CC_OpenCLKernel: 7871 return CCCR_OK; 7872 } 7873 } 7874 }; 7875 7876 class Nios2TargetInfo : public TargetInfo { 7877 void setDataLayout() { 7878 if (BigEndian) 7879 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32"); 7880 else 7881 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32"); 7882 } 7883 7884 static const Builtin::Info BuiltinInfo[]; 7885 std::string CPU; 7886 std::string ABI; 7887 7888 public: 7889 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts) 7890 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) { 7891 SizeType = UnsignedInt; 7892 PtrDiffType = SignedInt; 7893 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7894 setDataLayout(); 7895 } 7896 7897 StringRef getABI() const override { return ABI; } 7898 bool setABI(const std::string &Name) override { 7899 if (Name == "o32" || Name == "eabi") { 7900 ABI = Name; 7901 return true; 7902 } 7903 return false; 7904 } 7905 7906 bool setCPU(const std::string &Name) override { 7907 if (Name == "nios2r1" || Name == "nios2r2") { 7908 CPU = Name; 7909 return true; 7910 } 7911 return false; 7912 } 7913 7914 void getTargetDefines(const LangOptions &Opts, 7915 MacroBuilder &Builder) const override { 7916 DefineStd(Builder, "nios2", Opts); 7917 DefineStd(Builder, "NIOS2", Opts); 7918 7919 Builder.defineMacro("__nios2"); 7920 Builder.defineMacro("__NIOS2"); 7921 Builder.defineMacro("__nios2__"); 7922 Builder.defineMacro("__NIOS2__"); 7923 } 7924 7925 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7926 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin - 7927 Builtin::FirstTSBuiltin); 7928 } 7929 7930 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const { 7931 const bool isR2 = CPU == "nios2r2"; 7932 return llvm::StringSwitch<bool>(Feature) 7933 .Case("nios2r2mandatory", isR2) 7934 .Case("nios2r2bmx", isR2) 7935 .Case("nios2r2mpx", isR2) 7936 .Case("nios2r2cdx", isR2) 7937 .Default(false); 7938 } 7939 7940 bool initFeatureMap(llvm::StringMap<bool> &Features, 7941 DiagnosticsEngine &Diags, StringRef CPU, 7942 const std::vector<std::string> &FeatureVec) const override { 7943 static const char *allFeatures[] = { 7944 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx" 7945 }; 7946 for (const char *feature : allFeatures) { 7947 Features[feature] = isFeatureSupportedByCPU(feature, CPU); 7948 } 7949 return true; 7950 } 7951 7952 bool hasFeature(StringRef Feature) const override { 7953 return isFeatureSupportedByCPU(Feature, CPU); 7954 } 7955 7956 BuiltinVaListKind getBuiltinVaListKind() const override { 7957 return TargetInfo::VoidPtrBuiltinVaList; 7958 } 7959 7960 ArrayRef<const char *> getGCCRegNames() const override { 7961 static const char *const GCCRegNames[] = { 7962 // CPU register names 7963 // Must match second column of GCCRegAliases 7964 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7965 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", 7966 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", 7967 "r31", 7968 // Floating point register names 7969 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8", 7970 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15" 7971 }; 7972 return llvm::makeArrayRef(GCCRegNames); 7973 } 7974 7975 bool validateAsmConstraint(const char *&Name, 7976 TargetInfo::ConstraintInfo &Info) const override { 7977 switch (*Name) { 7978 default: 7979 return false; 7980 7981 case 'r': // CPU registers. 7982 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7983 case 'y': // Equivalent to "r", backwards compatibility only. 7984 case 'f': // floating-point registers. 7985 case 'c': // $25 for indirect jumps 7986 case 'l': // lo register 7987 case 'x': // hilo register pair 7988 Info.setAllowsRegister(); 7989 return true; 7990 } 7991 } 7992 7993 const char *getClobbers() const override { return ""; } 7994 7995 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7996 static const TargetInfo::GCCRegAlias aliases[] = { 7997 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"}, 7998 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"}, 7999 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"}, 8000 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"}, 8001 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"}, 8002 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"}, 8003 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"}, 8004 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"}, 8005 }; 8006 return llvm::makeArrayRef(aliases); 8007 } 8008 }; 8009 8010 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = { 8011 #define BUILTIN(ID, TYPE, ATTRS) \ 8012 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 8013 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 8014 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 8015 #include "clang/Basic/BuiltinsNios2.def" 8016 }; 8017 8018 class MipsTargetInfo : public TargetInfo { 8019 void setDataLayout() { 8020 StringRef Layout; 8021 8022 if (ABI == "o32") 8023 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 8024 else if (ABI == "n32") 8025 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 8026 else if (ABI == "n64") 8027 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 8028 else 8029 llvm_unreachable("Invalid ABI"); 8030 8031 if (BigEndian) 8032 resetDataLayout(("E-" + Layout).str()); 8033 else 8034 resetDataLayout(("e-" + Layout).str()); 8035 } 8036 8037 8038 static const Builtin::Info BuiltinInfo[]; 8039 std::string CPU; 8040 bool IsMips16; 8041 bool IsMicromips; 8042 bool IsNan2008; 8043 bool IsSingleFloat; 8044 bool IsNoABICalls; 8045 bool CanUseBSDABICalls; 8046 enum MipsFloatABI { 8047 HardFloat, SoftFloat 8048 } FloatABI; 8049 enum DspRevEnum { 8050 NoDSP, DSP1, DSP2 8051 } DspRev; 8052 bool HasMSA; 8053 8054 protected: 8055 bool HasFP64; 8056 std::string ABI; 8057 8058 public: 8059 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8060 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 8061 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 8062 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 8063 HasMSA(false), HasFP64(false) { 8064 TheCXXABI.set(TargetCXXABI::GenericMIPS); 8065 8066 setABI((getTriple().getArch() == llvm::Triple::mips || 8067 getTriple().getArch() == llvm::Triple::mipsel) 8068 ? "o32" 8069 : "n64"); 8070 8071 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 8072 8073 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 8074 Triple.getOS() == llvm::Triple::OpenBSD; 8075 } 8076 8077 bool isNaN2008Default() const { 8078 return CPU == "mips32r6" || CPU == "mips64r6"; 8079 } 8080 8081 bool isFP64Default() const { 8082 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 8083 } 8084 8085 bool isNan2008() const override { 8086 return IsNan2008; 8087 } 8088 8089 bool processorSupportsGPR64() const { 8090 return llvm::StringSwitch<bool>(CPU) 8091 .Case("mips3", true) 8092 .Case("mips4", true) 8093 .Case("mips5", true) 8094 .Case("mips64", true) 8095 .Case("mips64r2", true) 8096 .Case("mips64r3", true) 8097 .Case("mips64r5", true) 8098 .Case("mips64r6", true) 8099 .Case("octeon", true) 8100 .Default(false); 8101 return false; 8102 } 8103 8104 StringRef getABI() const override { return ABI; } 8105 bool setABI(const std::string &Name) override { 8106 if (Name == "o32") { 8107 setO32ABITypes(); 8108 ABI = Name; 8109 return true; 8110 } 8111 8112 if (Name == "n32") { 8113 setN32ABITypes(); 8114 ABI = Name; 8115 return true; 8116 } 8117 if (Name == "n64") { 8118 setN64ABITypes(); 8119 ABI = Name; 8120 return true; 8121 } 8122 return false; 8123 } 8124 8125 void setO32ABITypes() { 8126 Int64Type = SignedLongLong; 8127 IntMaxType = Int64Type; 8128 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8129 LongDoubleWidth = LongDoubleAlign = 64; 8130 LongWidth = LongAlign = 32; 8131 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8132 PointerWidth = PointerAlign = 32; 8133 PtrDiffType = SignedInt; 8134 SizeType = UnsignedInt; 8135 SuitableAlign = 64; 8136 } 8137 8138 void setN32N64ABITypes() { 8139 LongDoubleWidth = LongDoubleAlign = 128; 8140 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8141 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 8142 LongDoubleWidth = LongDoubleAlign = 64; 8143 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8144 } 8145 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8146 SuitableAlign = 128; 8147 } 8148 8149 void setN64ABITypes() { 8150 setN32N64ABITypes(); 8151 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 8152 Int64Type = SignedLongLong; 8153 } else { 8154 Int64Type = SignedLong; 8155 } 8156 IntMaxType = Int64Type; 8157 LongWidth = LongAlign = 64; 8158 PointerWidth = PointerAlign = 64; 8159 PtrDiffType = SignedLong; 8160 SizeType = UnsignedLong; 8161 } 8162 8163 void setN32ABITypes() { 8164 setN32N64ABITypes(); 8165 Int64Type = SignedLongLong; 8166 IntMaxType = Int64Type; 8167 LongWidth = LongAlign = 32; 8168 PointerWidth = PointerAlign = 32; 8169 PtrDiffType = SignedInt; 8170 SizeType = UnsignedInt; 8171 } 8172 8173 bool setCPU(const std::string &Name) override { 8174 CPU = Name; 8175 return llvm::StringSwitch<bool>(Name) 8176 .Case("mips1", true) 8177 .Case("mips2", true) 8178 .Case("mips3", true) 8179 .Case("mips4", true) 8180 .Case("mips5", true) 8181 .Case("mips32", true) 8182 .Case("mips32r2", true) 8183 .Case("mips32r3", true) 8184 .Case("mips32r5", true) 8185 .Case("mips32r6", true) 8186 .Case("mips64", true) 8187 .Case("mips64r2", true) 8188 .Case("mips64r3", true) 8189 .Case("mips64r5", true) 8190 .Case("mips64r6", true) 8191 .Case("octeon", true) 8192 .Case("p5600", true) 8193 .Default(false); 8194 } 8195 const std::string& getCPU() const { return CPU; } 8196 bool 8197 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8198 StringRef CPU, 8199 const std::vector<std::string> &FeaturesVec) const override { 8200 if (CPU.empty()) 8201 CPU = getCPU(); 8202 if (CPU == "octeon") 8203 Features["mips64r2"] = Features["cnmips"] = true; 8204 else 8205 Features[CPU] = true; 8206 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8207 } 8208 8209 void getTargetDefines(const LangOptions &Opts, 8210 MacroBuilder &Builder) const override { 8211 if (BigEndian) { 8212 DefineStd(Builder, "MIPSEB", Opts); 8213 Builder.defineMacro("_MIPSEB"); 8214 } else { 8215 DefineStd(Builder, "MIPSEL", Opts); 8216 Builder.defineMacro("_MIPSEL"); 8217 } 8218 8219 Builder.defineMacro("__mips__"); 8220 Builder.defineMacro("_mips"); 8221 if (Opts.GNUMode) 8222 Builder.defineMacro("mips"); 8223 8224 if (ABI == "o32") { 8225 Builder.defineMacro("__mips", "32"); 8226 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 8227 } else { 8228 Builder.defineMacro("__mips", "64"); 8229 Builder.defineMacro("__mips64"); 8230 Builder.defineMacro("__mips64__"); 8231 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 8232 } 8233 8234 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 8235 .Cases("mips32", "mips64", "1") 8236 .Cases("mips32r2", "mips64r2", "2") 8237 .Cases("mips32r3", "mips64r3", "3") 8238 .Cases("mips32r5", "mips64r5", "5") 8239 .Cases("mips32r6", "mips64r6", "6") 8240 .Default(""); 8241 if (!ISARev.empty()) 8242 Builder.defineMacro("__mips_isa_rev", ISARev); 8243 8244 if (ABI == "o32") { 8245 Builder.defineMacro("__mips_o32"); 8246 Builder.defineMacro("_ABIO32", "1"); 8247 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 8248 } else if (ABI == "n32") { 8249 Builder.defineMacro("__mips_n32"); 8250 Builder.defineMacro("_ABIN32", "2"); 8251 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 8252 } else if (ABI == "n64") { 8253 Builder.defineMacro("__mips_n64"); 8254 Builder.defineMacro("_ABI64", "3"); 8255 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 8256 } else 8257 llvm_unreachable("Invalid ABI."); 8258 8259 if (!IsNoABICalls) { 8260 Builder.defineMacro("__mips_abicalls"); 8261 if (CanUseBSDABICalls) 8262 Builder.defineMacro("__ABICALLS__"); 8263 } 8264 8265 Builder.defineMacro("__REGISTER_PREFIX__", ""); 8266 8267 switch (FloatABI) { 8268 case HardFloat: 8269 Builder.defineMacro("__mips_hard_float", Twine(1)); 8270 break; 8271 case SoftFloat: 8272 Builder.defineMacro("__mips_soft_float", Twine(1)); 8273 break; 8274 } 8275 8276 if (IsSingleFloat) 8277 Builder.defineMacro("__mips_single_float", Twine(1)); 8278 8279 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 8280 Builder.defineMacro("_MIPS_FPSET", 8281 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 8282 8283 if (IsMips16) 8284 Builder.defineMacro("__mips16", Twine(1)); 8285 8286 if (IsMicromips) 8287 Builder.defineMacro("__mips_micromips", Twine(1)); 8288 8289 if (IsNan2008) 8290 Builder.defineMacro("__mips_nan2008", Twine(1)); 8291 8292 switch (DspRev) { 8293 default: 8294 break; 8295 case DSP1: 8296 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 8297 Builder.defineMacro("__mips_dsp", Twine(1)); 8298 break; 8299 case DSP2: 8300 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 8301 Builder.defineMacro("__mips_dspr2", Twine(1)); 8302 Builder.defineMacro("__mips_dsp", Twine(1)); 8303 break; 8304 } 8305 8306 if (HasMSA) 8307 Builder.defineMacro("__mips_msa", Twine(1)); 8308 8309 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 8310 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 8311 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 8312 8313 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 8314 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 8315 8316 // These shouldn't be defined for MIPS-I but there's no need to check 8317 // for that since MIPS-I isn't supported. 8318 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 8319 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 8320 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 8321 8322 // 32-bit MIPS processors don't have the necessary lld/scd instructions 8323 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 8324 // the instructions exist but using them violates the ABI since they 8325 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 8326 if (ABI == "n32" || ABI == "n64") 8327 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 8328 } 8329 8330 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8331 return llvm::makeArrayRef(BuiltinInfo, 8332 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 8333 } 8334 bool hasFeature(StringRef Feature) const override { 8335 return llvm::StringSwitch<bool>(Feature) 8336 .Case("mips", true) 8337 .Case("fp64", HasFP64) 8338 .Default(false); 8339 } 8340 BuiltinVaListKind getBuiltinVaListKind() const override { 8341 return TargetInfo::VoidPtrBuiltinVaList; 8342 } 8343 ArrayRef<const char *> getGCCRegNames() const override { 8344 static const char *const GCCRegNames[] = { 8345 // CPU register names 8346 // Must match second column of GCCRegAliases 8347 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 8348 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 8349 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8350 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8351 // Floating point register names 8352 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8353 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8354 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8355 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8356 // Hi/lo and condition register names 8357 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8358 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8359 "$ac3hi","$ac3lo", 8360 // MSA register names 8361 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8362 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8363 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8364 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8365 // MSA control register names 8366 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8367 "$msarequest", "$msamap", "$msaunmap" 8368 }; 8369 return llvm::makeArrayRef(GCCRegNames); 8370 } 8371 bool validateAsmConstraint(const char *&Name, 8372 TargetInfo::ConstraintInfo &Info) const override { 8373 switch (*Name) { 8374 default: 8375 return false; 8376 case 'r': // CPU registers. 8377 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8378 case 'y': // Equivalent to "r", backward compatibility only. 8379 case 'f': // floating-point registers. 8380 case 'c': // $25 for indirect jumps 8381 case 'l': // lo register 8382 case 'x': // hilo register pair 8383 Info.setAllowsRegister(); 8384 return true; 8385 case 'I': // Signed 16-bit constant 8386 case 'J': // Integer 0 8387 case 'K': // Unsigned 16-bit constant 8388 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8389 case 'M': // Constants not loadable via lui, addiu, or ori 8390 case 'N': // Constant -1 to -65535 8391 case 'O': // A signed 15-bit constant 8392 case 'P': // A constant between 1 go 65535 8393 return true; 8394 case 'R': // An address that can be used in a non-macro load or store 8395 Info.setAllowsMemory(); 8396 return true; 8397 case 'Z': 8398 if (Name[1] == 'C') { // An address usable by ll, and sc. 8399 Info.setAllowsMemory(); 8400 Name++; // Skip over 'Z'. 8401 return true; 8402 } 8403 return false; 8404 } 8405 } 8406 8407 std::string convertConstraint(const char *&Constraint) const override { 8408 std::string R; 8409 switch (*Constraint) { 8410 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8411 if (Constraint[1] == 'C') { 8412 R = std::string("^") + std::string(Constraint, 2); 8413 Constraint++; 8414 return R; 8415 } 8416 break; 8417 } 8418 return TargetInfo::convertConstraint(Constraint); 8419 } 8420 8421 const char *getClobbers() const override { 8422 // In GCC, $1 is not widely used in generated code (it's used only in a few 8423 // specific situations), so there is no real need for users to add it to 8424 // the clobbers list if they want to use it in their inline assembly code. 8425 // 8426 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8427 // code generation, so using it in inline assembly without adding it to the 8428 // clobbers list can cause conflicts between the inline assembly code and 8429 // the surrounding generated code. 8430 // 8431 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8432 // operands, which will conflict with the ".set at" assembler option (which 8433 // we use only for inline assembly, in order to maintain compatibility with 8434 // GCC) and will also conflict with the user's usage of $1. 8435 // 8436 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8437 // register for generated code is to automatically clobber $1 for all inline 8438 // assembly code. 8439 // 8440 // FIXME: We should automatically clobber $1 only for inline assembly code 8441 // which actually uses it. This would allow LLVM to use $1 for inline 8442 // assembly operands if the user's assembly code doesn't use it. 8443 return "~{$1}"; 8444 } 8445 8446 bool handleTargetFeatures(std::vector<std::string> &Features, 8447 DiagnosticsEngine &Diags) override { 8448 IsMips16 = false; 8449 IsMicromips = false; 8450 IsNan2008 = isNaN2008Default(); 8451 IsSingleFloat = false; 8452 FloatABI = HardFloat; 8453 DspRev = NoDSP; 8454 HasFP64 = isFP64Default(); 8455 8456 for (const auto &Feature : Features) { 8457 if (Feature == "+single-float") 8458 IsSingleFloat = true; 8459 else if (Feature == "+soft-float") 8460 FloatABI = SoftFloat; 8461 else if (Feature == "+mips16") 8462 IsMips16 = true; 8463 else if (Feature == "+micromips") 8464 IsMicromips = true; 8465 else if (Feature == "+dsp") 8466 DspRev = std::max(DspRev, DSP1); 8467 else if (Feature == "+dspr2") 8468 DspRev = std::max(DspRev, DSP2); 8469 else if (Feature == "+msa") 8470 HasMSA = true; 8471 else if (Feature == "+fp64") 8472 HasFP64 = true; 8473 else if (Feature == "-fp64") 8474 HasFP64 = false; 8475 else if (Feature == "+nan2008") 8476 IsNan2008 = true; 8477 else if (Feature == "-nan2008") 8478 IsNan2008 = false; 8479 else if (Feature == "+noabicalls") 8480 IsNoABICalls = true; 8481 } 8482 8483 setDataLayout(); 8484 8485 return true; 8486 } 8487 8488 int getEHDataRegisterNumber(unsigned RegNo) const override { 8489 if (RegNo == 0) return 4; 8490 if (RegNo == 1) return 5; 8491 return -1; 8492 } 8493 8494 bool isCLZForZeroUndef() const override { return false; } 8495 8496 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8497 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8498 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8499 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8500 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8501 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8502 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8503 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8504 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8505 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8506 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8507 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8508 {{"ra"}, "$31"}}; 8509 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8510 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8511 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8512 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8513 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8514 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8515 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8516 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8517 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8518 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8519 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8520 {{"ra"}, "$31"}}; 8521 if (ABI == "o32") 8522 return llvm::makeArrayRef(O32RegAliases); 8523 return llvm::makeArrayRef(NewABIRegAliases); 8524 } 8525 8526 bool hasInt128Type() const override { 8527 return ABI == "n32" || ABI == "n64"; 8528 } 8529 8530 bool validateTarget(DiagnosticsEngine &Diags) const override { 8531 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8532 // this yet. It's better to fail here than on the backend assertion. 8533 if (processorSupportsGPR64() && ABI == "o32") { 8534 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8535 return false; 8536 } 8537 8538 // 64-bit ABI's require 64-bit CPU's. 8539 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8540 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8541 return false; 8542 } 8543 8544 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8545 // can't handle this yet. It's better to fail here than on the 8546 // backend assertion. 8547 if ((getTriple().getArch() == llvm::Triple::mips64 || 8548 getTriple().getArch() == llvm::Triple::mips64el) && 8549 ABI == "o32") { 8550 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8551 << ABI << getTriple().str(); 8552 return false; 8553 } 8554 8555 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8556 // can't handle this yet. It's better to fail here than on the 8557 // backend assertion. 8558 if ((getTriple().getArch() == llvm::Triple::mips || 8559 getTriple().getArch() == llvm::Triple::mipsel) && 8560 (ABI == "n32" || ABI == "n64")) { 8561 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8562 << ABI << getTriple().str(); 8563 return false; 8564 } 8565 8566 return true; 8567 } 8568 }; 8569 8570 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8571 #define BUILTIN(ID, TYPE, ATTRS) \ 8572 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8573 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8574 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8575 #include "clang/Basic/BuiltinsMips.def" 8576 }; 8577 8578 class PNaClTargetInfo : public TargetInfo { 8579 public: 8580 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8581 : TargetInfo(Triple) { 8582 this->LongAlign = 32; 8583 this->LongWidth = 32; 8584 this->PointerAlign = 32; 8585 this->PointerWidth = 32; 8586 this->IntMaxType = TargetInfo::SignedLongLong; 8587 this->Int64Type = TargetInfo::SignedLongLong; 8588 this->DoubleAlign = 64; 8589 this->LongDoubleWidth = 64; 8590 this->LongDoubleAlign = 64; 8591 this->SizeType = TargetInfo::UnsignedInt; 8592 this->PtrDiffType = TargetInfo::SignedInt; 8593 this->IntPtrType = TargetInfo::SignedInt; 8594 this->RegParmMax = 0; // Disallow regparm 8595 } 8596 8597 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8598 Builder.defineMacro("__le32__"); 8599 Builder.defineMacro("__pnacl__"); 8600 } 8601 void getTargetDefines(const LangOptions &Opts, 8602 MacroBuilder &Builder) const override { 8603 getArchDefines(Opts, Builder); 8604 } 8605 bool hasFeature(StringRef Feature) const override { 8606 return Feature == "pnacl"; 8607 } 8608 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8609 BuiltinVaListKind getBuiltinVaListKind() const override { 8610 return TargetInfo::PNaClABIBuiltinVaList; 8611 } 8612 ArrayRef<const char *> getGCCRegNames() const override; 8613 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8614 bool validateAsmConstraint(const char *&Name, 8615 TargetInfo::ConstraintInfo &Info) const override { 8616 return false; 8617 } 8618 8619 const char *getClobbers() const override { 8620 return ""; 8621 } 8622 }; 8623 8624 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8625 return None; 8626 } 8627 8628 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8629 return None; 8630 } 8631 8632 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8633 class NaClMips32TargetInfo : public MipsTargetInfo { 8634 public: 8635 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8636 : MipsTargetInfo(Triple, Opts) {} 8637 8638 BuiltinVaListKind getBuiltinVaListKind() const override { 8639 return TargetInfo::PNaClABIBuiltinVaList; 8640 } 8641 }; 8642 8643 class Le64TargetInfo : public TargetInfo { 8644 static const Builtin::Info BuiltinInfo[]; 8645 8646 public: 8647 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8648 : TargetInfo(Triple) { 8649 NoAsmVariants = true; 8650 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8651 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8652 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8653 } 8654 8655 void getTargetDefines(const LangOptions &Opts, 8656 MacroBuilder &Builder) const override { 8657 DefineStd(Builder, "unix", Opts); 8658 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8659 Builder.defineMacro("__ELF__"); 8660 } 8661 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8662 return llvm::makeArrayRef(BuiltinInfo, 8663 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8664 } 8665 BuiltinVaListKind getBuiltinVaListKind() const override { 8666 return TargetInfo::PNaClABIBuiltinVaList; 8667 } 8668 const char *getClobbers() const override { return ""; } 8669 ArrayRef<const char *> getGCCRegNames() const override { 8670 return None; 8671 } 8672 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8673 return None; 8674 } 8675 bool validateAsmConstraint(const char *&Name, 8676 TargetInfo::ConstraintInfo &Info) const override { 8677 return false; 8678 } 8679 8680 bool hasProtectedVisibility() const override { return false; } 8681 }; 8682 8683 class WebAssemblyTargetInfo : public TargetInfo { 8684 static const Builtin::Info BuiltinInfo[]; 8685 8686 enum SIMDEnum { 8687 NoSIMD, 8688 SIMD128, 8689 } SIMDLevel; 8690 8691 public: 8692 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8693 : TargetInfo(T), SIMDLevel(NoSIMD) { 8694 NoAsmVariants = true; 8695 SuitableAlign = 128; 8696 LargeArrayMinWidth = 128; 8697 LargeArrayAlign = 128; 8698 SimdDefaultAlign = 128; 8699 SigAtomicType = SignedLong; 8700 LongDoubleWidth = LongDoubleAlign = 128; 8701 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8702 SizeType = UnsignedInt; 8703 PtrDiffType = SignedInt; 8704 IntPtrType = SignedInt; 8705 } 8706 8707 protected: 8708 void getTargetDefines(const LangOptions &Opts, 8709 MacroBuilder &Builder) const override { 8710 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8711 if (SIMDLevel >= SIMD128) 8712 Builder.defineMacro("__wasm_simd128__"); 8713 } 8714 8715 private: 8716 bool 8717 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8718 StringRef CPU, 8719 const std::vector<std::string> &FeaturesVec) const override { 8720 if (CPU == "bleeding-edge") 8721 Features["simd128"] = true; 8722 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8723 } 8724 bool hasFeature(StringRef Feature) const final { 8725 return llvm::StringSwitch<bool>(Feature) 8726 .Case("simd128", SIMDLevel >= SIMD128) 8727 .Default(false); 8728 } 8729 bool handleTargetFeatures(std::vector<std::string> &Features, 8730 DiagnosticsEngine &Diags) final { 8731 for (const auto &Feature : Features) { 8732 if (Feature == "+simd128") { 8733 SIMDLevel = std::max(SIMDLevel, SIMD128); 8734 continue; 8735 } 8736 if (Feature == "-simd128") { 8737 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8738 continue; 8739 } 8740 8741 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8742 << "-target-feature"; 8743 return false; 8744 } 8745 return true; 8746 } 8747 bool setCPU(const std::string &Name) final { 8748 return llvm::StringSwitch<bool>(Name) 8749 .Case("mvp", true) 8750 .Case("bleeding-edge", true) 8751 .Case("generic", true) 8752 .Default(false); 8753 } 8754 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8755 return llvm::makeArrayRef(BuiltinInfo, 8756 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8757 } 8758 BuiltinVaListKind getBuiltinVaListKind() const final { 8759 return VoidPtrBuiltinVaList; 8760 } 8761 ArrayRef<const char *> getGCCRegNames() const final { 8762 return None; 8763 } 8764 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8765 return None; 8766 } 8767 bool 8768 validateAsmConstraint(const char *&Name, 8769 TargetInfo::ConstraintInfo &Info) const final { 8770 return false; 8771 } 8772 const char *getClobbers() const final { return ""; } 8773 bool isCLZForZeroUndef() const final { return false; } 8774 bool hasInt128Type() const final { return true; } 8775 IntType getIntTypeByWidth(unsigned BitWidth, 8776 bool IsSigned) const final { 8777 // WebAssembly prefers long long for explicitly 64-bit integers. 8778 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8779 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8780 } 8781 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8782 bool IsSigned) const final { 8783 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8784 return BitWidth == 64 8785 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8786 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8787 } 8788 }; 8789 8790 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8791 #define BUILTIN(ID, TYPE, ATTRS) \ 8792 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8793 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8794 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8795 #include "clang/Basic/BuiltinsWebAssembly.def" 8796 }; 8797 8798 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8799 public: 8800 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8801 const TargetOptions &Opts) 8802 : WebAssemblyTargetInfo(T, Opts) { 8803 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8804 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8805 } 8806 8807 protected: 8808 void getTargetDefines(const LangOptions &Opts, 8809 MacroBuilder &Builder) const override { 8810 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8811 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8812 } 8813 }; 8814 8815 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8816 public: 8817 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8818 const TargetOptions &Opts) 8819 : WebAssemblyTargetInfo(T, Opts) { 8820 LongAlign = LongWidth = 64; 8821 PointerAlign = PointerWidth = 64; 8822 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8823 SizeType = UnsignedLong; 8824 PtrDiffType = SignedLong; 8825 IntPtrType = SignedLong; 8826 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8827 } 8828 8829 protected: 8830 void getTargetDefines(const LangOptions &Opts, 8831 MacroBuilder &Builder) const override { 8832 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8833 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8834 } 8835 }; 8836 8837 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8838 #define BUILTIN(ID, TYPE, ATTRS) \ 8839 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8840 #include "clang/Basic/BuiltinsLe64.def" 8841 }; 8842 8843 static const unsigned SPIRAddrSpaceMap[] = { 8844 0, // Default 8845 1, // opencl_global 8846 3, // opencl_local 8847 2, // opencl_constant 8848 4, // opencl_generic 8849 0, // cuda_device 8850 0, // cuda_constant 8851 0 // cuda_shared 8852 }; 8853 class SPIRTargetInfo : public TargetInfo { 8854 public: 8855 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8856 : TargetInfo(Triple) { 8857 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8858 "SPIR target must use unknown OS"); 8859 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8860 "SPIR target must use unknown environment type"); 8861 TLSSupported = false; 8862 LongWidth = LongAlign = 64; 8863 AddrSpaceMap = &SPIRAddrSpaceMap; 8864 UseAddrSpaceMapMangling = true; 8865 // Define available target features 8866 // These must be defined in sorted order! 8867 NoAsmVariants = true; 8868 } 8869 void getTargetDefines(const LangOptions &Opts, 8870 MacroBuilder &Builder) const override { 8871 DefineStd(Builder, "SPIR", Opts); 8872 } 8873 bool hasFeature(StringRef Feature) const override { 8874 return Feature == "spir"; 8875 } 8876 8877 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8878 const char *getClobbers() const override { return ""; } 8879 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8880 bool validateAsmConstraint(const char *&Name, 8881 TargetInfo::ConstraintInfo &info) const override { 8882 return true; 8883 } 8884 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8885 return None; 8886 } 8887 BuiltinVaListKind getBuiltinVaListKind() const override { 8888 return TargetInfo::VoidPtrBuiltinVaList; 8889 } 8890 8891 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8892 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8893 : CCCR_Warning; 8894 } 8895 8896 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8897 return CC_SpirFunction; 8898 } 8899 8900 void setSupportedOpenCLOpts() override { 8901 // Assume all OpenCL extensions and optional core features are supported 8902 // for SPIR since it is a generic target. 8903 getSupportedOpenCLOpts().supportAll(); 8904 } 8905 }; 8906 8907 class SPIR32TargetInfo : public SPIRTargetInfo { 8908 public: 8909 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8910 : SPIRTargetInfo(Triple, Opts) { 8911 PointerWidth = PointerAlign = 32; 8912 SizeType = TargetInfo::UnsignedInt; 8913 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8914 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8915 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8916 } 8917 void getTargetDefines(const LangOptions &Opts, 8918 MacroBuilder &Builder) const override { 8919 DefineStd(Builder, "SPIR32", Opts); 8920 } 8921 }; 8922 8923 class SPIR64TargetInfo : public SPIRTargetInfo { 8924 public: 8925 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8926 : SPIRTargetInfo(Triple, Opts) { 8927 PointerWidth = PointerAlign = 64; 8928 SizeType = TargetInfo::UnsignedLong; 8929 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8930 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8931 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8932 } 8933 void getTargetDefines(const LangOptions &Opts, 8934 MacroBuilder &Builder) const override { 8935 DefineStd(Builder, "SPIR64", Opts); 8936 } 8937 }; 8938 8939 class XCoreTargetInfo : public TargetInfo { 8940 static const Builtin::Info BuiltinInfo[]; 8941 public: 8942 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8943 : TargetInfo(Triple) { 8944 NoAsmVariants = true; 8945 LongLongAlign = 32; 8946 SuitableAlign = 32; 8947 DoubleAlign = LongDoubleAlign = 32; 8948 SizeType = UnsignedInt; 8949 PtrDiffType = SignedInt; 8950 IntPtrType = SignedInt; 8951 WCharType = UnsignedChar; 8952 WIntType = UnsignedInt; 8953 UseZeroLengthBitfieldAlignment = true; 8954 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8955 "-f64:32-a:0:32-n32"); 8956 } 8957 void getTargetDefines(const LangOptions &Opts, 8958 MacroBuilder &Builder) const override { 8959 Builder.defineMacro("__XS1B__"); 8960 } 8961 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8962 return llvm::makeArrayRef(BuiltinInfo, 8963 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8964 } 8965 BuiltinVaListKind getBuiltinVaListKind() const override { 8966 return TargetInfo::VoidPtrBuiltinVaList; 8967 } 8968 const char *getClobbers() const override { 8969 return ""; 8970 } 8971 ArrayRef<const char *> getGCCRegNames() const override { 8972 static const char * const GCCRegNames[] = { 8973 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8974 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8975 }; 8976 return llvm::makeArrayRef(GCCRegNames); 8977 } 8978 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8979 return None; 8980 } 8981 bool validateAsmConstraint(const char *&Name, 8982 TargetInfo::ConstraintInfo &Info) const override { 8983 return false; 8984 } 8985 int getEHDataRegisterNumber(unsigned RegNo) const override { 8986 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8987 return (RegNo < 2)? RegNo : -1; 8988 } 8989 bool allowsLargerPreferedTypeAlignment() const override { 8990 return false; 8991 } 8992 }; 8993 8994 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8995 #define BUILTIN(ID, TYPE, ATTRS) \ 8996 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8997 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8998 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8999 #include "clang/Basic/BuiltinsXCore.def" 9000 }; 9001 9002 // x86_32 Android target 9003 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 9004 public: 9005 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 9006 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 9007 SuitableAlign = 32; 9008 LongDoubleWidth = 64; 9009 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 9010 } 9011 }; 9012 9013 // x86_64 Android target 9014 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 9015 public: 9016 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 9017 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 9018 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 9019 } 9020 9021 bool useFloat128ManglingForLongDouble() const override { 9022 return true; 9023 } 9024 }; 9025 9026 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 9027 class RenderScript32TargetInfo : public ARMleTargetInfo { 9028 public: 9029 RenderScript32TargetInfo(const llvm::Triple &Triple, 9030 const TargetOptions &Opts) 9031 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 9032 Triple.getOSName(), 9033 Triple.getEnvironmentName()), 9034 Opts) { 9035 IsRenderScriptTarget = true; 9036 LongWidth = LongAlign = 64; 9037 } 9038 void getTargetDefines(const LangOptions &Opts, 9039 MacroBuilder &Builder) const override { 9040 Builder.defineMacro("__RENDERSCRIPT__"); 9041 ARMleTargetInfo::getTargetDefines(Opts, Builder); 9042 } 9043 }; 9044 9045 // 64-bit RenderScript is aarch64 9046 class RenderScript64TargetInfo : public AArch64leTargetInfo { 9047 public: 9048 RenderScript64TargetInfo(const llvm::Triple &Triple, 9049 const TargetOptions &Opts) 9050 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 9051 Triple.getOSName(), 9052 Triple.getEnvironmentName()), 9053 Opts) { 9054 IsRenderScriptTarget = true; 9055 } 9056 9057 void getTargetDefines(const LangOptions &Opts, 9058 MacroBuilder &Builder) const override { 9059 Builder.defineMacro("__RENDERSCRIPT__"); 9060 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 9061 } 9062 }; 9063 9064 /// Information about a specific microcontroller. 9065 struct MCUInfo { 9066 const char *Name; 9067 const char *DefineName; 9068 }; 9069 9070 // This list should be kept up-to-date with AVRDevices.td in LLVM. 9071 static ArrayRef<MCUInfo> AVRMcus = { 9072 { "at90s1200", "__AVR_AT90S1200__" }, 9073 { "attiny11", "__AVR_ATtiny11__" }, 9074 { "attiny12", "__AVR_ATtiny12__" }, 9075 { "attiny15", "__AVR_ATtiny15__" }, 9076 { "attiny28", "__AVR_ATtiny28__" }, 9077 { "at90s2313", "__AVR_AT90S2313__" }, 9078 { "at90s2323", "__AVR_AT90S2323__" }, 9079 { "at90s2333", "__AVR_AT90S2333__" }, 9080 { "at90s2343", "__AVR_AT90S2343__" }, 9081 { "attiny22", "__AVR_ATtiny22__" }, 9082 { "attiny26", "__AVR_ATtiny26__" }, 9083 { "at86rf401", "__AVR_AT86RF401__" }, 9084 { "at90s4414", "__AVR_AT90S4414__" }, 9085 { "at90s4433", "__AVR_AT90S4433__" }, 9086 { "at90s4434", "__AVR_AT90S4434__" }, 9087 { "at90s8515", "__AVR_AT90S8515__" }, 9088 { "at90c8534", "__AVR_AT90c8534__" }, 9089 { "at90s8535", "__AVR_AT90S8535__" }, 9090 { "ata5272", "__AVR_ATA5272__" }, 9091 { "attiny13", "__AVR_ATtiny13__" }, 9092 { "attiny13a", "__AVR_ATtiny13A__" }, 9093 { "attiny2313", "__AVR_ATtiny2313__" }, 9094 { "attiny2313a", "__AVR_ATtiny2313A__" }, 9095 { "attiny24", "__AVR_ATtiny24__" }, 9096 { "attiny24a", "__AVR_ATtiny24A__" }, 9097 { "attiny4313", "__AVR_ATtiny4313__" }, 9098 { "attiny44", "__AVR_ATtiny44__" }, 9099 { "attiny44a", "__AVR_ATtiny44A__" }, 9100 { "attiny84", "__AVR_ATtiny84__" }, 9101 { "attiny84a", "__AVR_ATtiny84A__" }, 9102 { "attiny25", "__AVR_ATtiny25__" }, 9103 { "attiny45", "__AVR_ATtiny45__" }, 9104 { "attiny85", "__AVR_ATtiny85__" }, 9105 { "attiny261", "__AVR_ATtiny261__" }, 9106 { "attiny261a", "__AVR_ATtiny261A__" }, 9107 { "attiny461", "__AVR_ATtiny461__" }, 9108 { "attiny461a", "__AVR_ATtiny461A__" }, 9109 { "attiny861", "__AVR_ATtiny861__" }, 9110 { "attiny861a", "__AVR_ATtiny861A__" }, 9111 { "attiny87", "__AVR_ATtiny87__" }, 9112 { "attiny43u", "__AVR_ATtiny43U__" }, 9113 { "attiny48", "__AVR_ATtiny48__" }, 9114 { "attiny88", "__AVR_ATtiny88__" }, 9115 { "attiny828", "__AVR_ATtiny828__" }, 9116 { "at43usb355", "__AVR_AT43USB355__" }, 9117 { "at76c711", "__AVR_AT76C711__" }, 9118 { "atmega103", "__AVR_ATmega103__" }, 9119 { "at43usb320", "__AVR_AT43USB320__" }, 9120 { "attiny167", "__AVR_ATtiny167__" }, 9121 { "at90usb82", "__AVR_AT90USB82__" }, 9122 { "at90usb162", "__AVR_AT90USB162__" }, 9123 { "ata5505", "__AVR_ATA5505__" }, 9124 { "atmega8u2", "__AVR_ATmega8U2__" }, 9125 { "atmega16u2", "__AVR_ATmega16U2__" }, 9126 { "atmega32u2", "__AVR_ATmega32U2__" }, 9127 { "attiny1634", "__AVR_ATtiny1634__" }, 9128 { "atmega8", "__AVR_ATmega8__" }, 9129 { "ata6289", "__AVR_ATA6289__" }, 9130 { "atmega8a", "__AVR_ATmega8A__" }, 9131 { "ata6285", "__AVR_ATA6285__" }, 9132 { "ata6286", "__AVR_ATA6286__" }, 9133 { "atmega48", "__AVR_ATmega48__" }, 9134 { "atmega48a", "__AVR_ATmega48A__" }, 9135 { "atmega48pa", "__AVR_ATmega48PA__" }, 9136 { "atmega48p", "__AVR_ATmega48P__" }, 9137 { "atmega88", "__AVR_ATmega88__" }, 9138 { "atmega88a", "__AVR_ATmega88A__" }, 9139 { "atmega88p", "__AVR_ATmega88P__" }, 9140 { "atmega88pa", "__AVR_ATmega88PA__" }, 9141 { "atmega8515", "__AVR_ATmega8515__" }, 9142 { "atmega8535", "__AVR_ATmega8535__" }, 9143 { "atmega8hva", "__AVR_ATmega8HVA__" }, 9144 { "at90pwm1", "__AVR_AT90PWM1__" }, 9145 { "at90pwm2", "__AVR_AT90PWM2__" }, 9146 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 9147 { "at90pwm3", "__AVR_AT90PWM3__" }, 9148 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 9149 { "at90pwm81", "__AVR_AT90PWM81__" }, 9150 { "ata5790", "__AVR_ATA5790__" }, 9151 { "ata5795", "__AVR_ATA5795__" }, 9152 { "atmega16", "__AVR_ATmega16__" }, 9153 { "atmega16a", "__AVR_ATmega16A__" }, 9154 { "atmega161", "__AVR_ATmega161__" }, 9155 { "atmega162", "__AVR_ATmega162__" }, 9156 { "atmega163", "__AVR_ATmega163__" }, 9157 { "atmega164a", "__AVR_ATmega164A__" }, 9158 { "atmega164p", "__AVR_ATmega164P__" }, 9159 { "atmega164pa", "__AVR_ATmega164PA__" }, 9160 { "atmega165", "__AVR_ATmega165__" }, 9161 { "atmega165a", "__AVR_ATmega165A__" }, 9162 { "atmega165p", "__AVR_ATmega165P__" }, 9163 { "atmega165pa", "__AVR_ATmega165PA__" }, 9164 { "atmega168", "__AVR_ATmega168__" }, 9165 { "atmega168a", "__AVR_ATmega168A__" }, 9166 { "atmega168p", "__AVR_ATmega168P__" }, 9167 { "atmega168pa", "__AVR_ATmega168PA__" }, 9168 { "atmega169", "__AVR_ATmega169__" }, 9169 { "atmega169a", "__AVR_ATmega169A__" }, 9170 { "atmega169p", "__AVR_ATmega169P__" }, 9171 { "atmega169pa", "__AVR_ATmega169PA__" }, 9172 { "atmega32", "__AVR_ATmega32__" }, 9173 { "atmega32a", "__AVR_ATmega32A__" }, 9174 { "atmega323", "__AVR_ATmega323__" }, 9175 { "atmega324a", "__AVR_ATmega324A__" }, 9176 { "atmega324p", "__AVR_ATmega324P__" }, 9177 { "atmega324pa", "__AVR_ATmega324PA__" }, 9178 { "atmega325", "__AVR_ATmega325__" }, 9179 { "atmega325a", "__AVR_ATmega325A__" }, 9180 { "atmega325p", "__AVR_ATmega325P__" }, 9181 { "atmega325pa", "__AVR_ATmega325PA__" }, 9182 { "atmega3250", "__AVR_ATmega3250__" }, 9183 { "atmega3250a", "__AVR_ATmega3250A__" }, 9184 { "atmega3250p", "__AVR_ATmega3250P__" }, 9185 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 9186 { "atmega328", "__AVR_ATmega328__" }, 9187 { "atmega328p", "__AVR_ATmega328P__" }, 9188 { "atmega329", "__AVR_ATmega329__" }, 9189 { "atmega329a", "__AVR_ATmega329A__" }, 9190 { "atmega329p", "__AVR_ATmega329P__" }, 9191 { "atmega329pa", "__AVR_ATmega329PA__" }, 9192 { "atmega3290", "__AVR_ATmega3290__" }, 9193 { "atmega3290a", "__AVR_ATmega3290A__" }, 9194 { "atmega3290p", "__AVR_ATmega3290P__" }, 9195 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 9196 { "atmega406", "__AVR_ATmega406__" }, 9197 { "atmega64", "__AVR_ATmega64__" }, 9198 { "atmega64a", "__AVR_ATmega64A__" }, 9199 { "atmega640", "__AVR_ATmega640__" }, 9200 { "atmega644", "__AVR_ATmega644__" }, 9201 { "atmega644a", "__AVR_ATmega644A__" }, 9202 { "atmega644p", "__AVR_ATmega644P__" }, 9203 { "atmega644pa", "__AVR_ATmega644PA__" }, 9204 { "atmega645", "__AVR_ATmega645__" }, 9205 { "atmega645a", "__AVR_ATmega645A__" }, 9206 { "atmega645p", "__AVR_ATmega645P__" }, 9207 { "atmega649", "__AVR_ATmega649__" }, 9208 { "atmega649a", "__AVR_ATmega649A__" }, 9209 { "atmega649p", "__AVR_ATmega649P__" }, 9210 { "atmega6450", "__AVR_ATmega6450__" }, 9211 { "atmega6450a", "__AVR_ATmega6450A__" }, 9212 { "atmega6450p", "__AVR_ATmega6450P__" }, 9213 { "atmega6490", "__AVR_ATmega6490__" }, 9214 { "atmega6490a", "__AVR_ATmega6490A__" }, 9215 { "atmega6490p", "__AVR_ATmega6490P__" }, 9216 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 9217 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 9218 { "atmega16hva", "__AVR_ATmega16HVA__" }, 9219 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 9220 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 9221 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 9222 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 9223 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 9224 { "atmega64hve", "__AVR_ATmega64HVE__" }, 9225 { "at90can32", "__AVR_AT90CAN32__" }, 9226 { "at90can64", "__AVR_AT90CAN64__" }, 9227 { "at90pwm161", "__AVR_AT90PWM161__" }, 9228 { "at90pwm216", "__AVR_AT90PWM216__" }, 9229 { "at90pwm316", "__AVR_AT90PWM316__" }, 9230 { "atmega32c1", "__AVR_ATmega32C1__" }, 9231 { "atmega64c1", "__AVR_ATmega64C1__" }, 9232 { "atmega16m1", "__AVR_ATmega16M1__" }, 9233 { "atmega32m1", "__AVR_ATmega32M1__" }, 9234 { "atmega64m1", "__AVR_ATmega64M1__" }, 9235 { "atmega16u4", "__AVR_ATmega16U4__" }, 9236 { "atmega32u4", "__AVR_ATmega32U4__" }, 9237 { "atmega32u6", "__AVR_ATmega32U6__" }, 9238 { "at90usb646", "__AVR_AT90USB646__" }, 9239 { "at90usb647", "__AVR_AT90USB647__" }, 9240 { "at90scr100", "__AVR_AT90SCR100__" }, 9241 { "at94k", "__AVR_AT94K__" }, 9242 { "m3000", "__AVR_AT000__" }, 9243 { "atmega128", "__AVR_ATmega128__" }, 9244 { "atmega128a", "__AVR_ATmega128A__" }, 9245 { "atmega1280", "__AVR_ATmega1280__" }, 9246 { "atmega1281", "__AVR_ATmega1281__" }, 9247 { "atmega1284", "__AVR_ATmega1284__" }, 9248 { "atmega1284p", "__AVR_ATmega1284P__" }, 9249 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 9250 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 9251 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 9252 { "at90can128", "__AVR_AT90CAN128__" }, 9253 { "at90usb1286", "__AVR_AT90USB1286__" }, 9254 { "at90usb1287", "__AVR_AT90USB1287__" }, 9255 { "atmega2560", "__AVR_ATmega2560__" }, 9256 { "atmega2561", "__AVR_ATmega2561__" }, 9257 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 9258 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 9259 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 9260 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 9261 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 9262 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 9263 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 9264 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 9265 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 9266 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 9267 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 9268 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 9269 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 9270 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 9271 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 9272 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 9273 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 9274 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 9275 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 9276 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 9277 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 9278 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 9279 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 9280 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 9281 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 9282 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 9283 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 9284 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 9285 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 9286 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 9287 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 9288 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 9289 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 9290 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 9291 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 9292 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 9293 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 9294 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 9295 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 9296 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 9297 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 9298 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 9299 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 9300 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 9301 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 9302 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 9303 { "attiny4", "__AVR_ATtiny4__" }, 9304 { "attiny5", "__AVR_ATtiny5__" }, 9305 { "attiny9", "__AVR_ATtiny9__" }, 9306 { "attiny10", "__AVR_ATtiny10__" }, 9307 { "attiny20", "__AVR_ATtiny20__" }, 9308 { "attiny40", "__AVR_ATtiny40__" }, 9309 { "attiny102", "__AVR_ATtiny102__" }, 9310 { "attiny104", "__AVR_ATtiny104__" }, 9311 }; 9312 9313 // AVR Target 9314 class AVRTargetInfo : public TargetInfo { 9315 public: 9316 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9317 : TargetInfo(Triple) { 9318 TLSSupported = false; 9319 PointerWidth = 16; 9320 PointerAlign = 8; 9321 IntWidth = 16; 9322 IntAlign = 8; 9323 LongWidth = 32; 9324 LongAlign = 8; 9325 LongLongWidth = 64; 9326 LongLongAlign = 8; 9327 SuitableAlign = 8; 9328 DefaultAlignForAttributeAligned = 8; 9329 HalfWidth = 16; 9330 HalfAlign = 8; 9331 FloatWidth = 32; 9332 FloatAlign = 8; 9333 DoubleWidth = 32; 9334 DoubleAlign = 8; 9335 DoubleFormat = &llvm::APFloat::IEEEsingle(); 9336 LongDoubleWidth = 32; 9337 LongDoubleAlign = 8; 9338 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 9339 SizeType = UnsignedInt; 9340 PtrDiffType = SignedInt; 9341 IntPtrType = SignedInt; 9342 Char16Type = UnsignedInt; 9343 WCharType = SignedInt; 9344 WIntType = SignedInt; 9345 Char32Type = UnsignedLong; 9346 SigAtomicType = SignedChar; 9347 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 9348 "-f32:32:32-f64:64:64-n8"); 9349 } 9350 9351 void getTargetDefines(const LangOptions &Opts, 9352 MacroBuilder &Builder) const override { 9353 Builder.defineMacro("AVR"); 9354 Builder.defineMacro("__AVR"); 9355 Builder.defineMacro("__AVR__"); 9356 9357 if (!this->CPU.empty()) { 9358 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9359 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9360 9361 if (It != AVRMcus.end()) 9362 Builder.defineMacro(It->DefineName); 9363 } 9364 } 9365 9366 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9367 return None; 9368 } 9369 9370 BuiltinVaListKind getBuiltinVaListKind() const override { 9371 return TargetInfo::VoidPtrBuiltinVaList; 9372 } 9373 9374 const char *getClobbers() const override { 9375 return ""; 9376 } 9377 9378 ArrayRef<const char *> getGCCRegNames() const override { 9379 static const char * const GCCRegNames[] = { 9380 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9381 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9382 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9383 "r24", "r25", "X", "Y", "Z", "SP" 9384 }; 9385 return llvm::makeArrayRef(GCCRegNames); 9386 } 9387 9388 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9389 return None; 9390 } 9391 9392 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9393 static const TargetInfo::AddlRegName AddlRegNames[] = { 9394 { { "r26", "r27"}, 26 }, 9395 { { "r28", "r29"}, 27 }, 9396 { { "r30", "r31"}, 28 }, 9397 { { "SPL", "SPH"}, 29 }, 9398 }; 9399 return llvm::makeArrayRef(AddlRegNames); 9400 } 9401 9402 bool validateAsmConstraint(const char *&Name, 9403 TargetInfo::ConstraintInfo &Info) const override { 9404 // There aren't any multi-character AVR specific constraints. 9405 if (StringRef(Name).size() > 1) return false; 9406 9407 switch (*Name) { 9408 default: return false; 9409 case 'a': // Simple upper registers 9410 case 'b': // Base pointer registers pairs 9411 case 'd': // Upper register 9412 case 'l': // Lower registers 9413 case 'e': // Pointer register pairs 9414 case 'q': // Stack pointer register 9415 case 'r': // Any register 9416 case 'w': // Special upper register pairs 9417 case 't': // Temporary register 9418 case 'x': case 'X': // Pointer register pair X 9419 case 'y': case 'Y': // Pointer register pair Y 9420 case 'z': case 'Z': // Pointer register pair Z 9421 Info.setAllowsRegister(); 9422 return true; 9423 case 'I': // 6-bit positive integer constant 9424 Info.setRequiresImmediate(0, 63); 9425 return true; 9426 case 'J': // 6-bit negative integer constant 9427 Info.setRequiresImmediate(-63, 0); 9428 return true; 9429 case 'K': // Integer constant (Range: 2) 9430 Info.setRequiresImmediate(2); 9431 return true; 9432 case 'L': // Integer constant (Range: 0) 9433 Info.setRequiresImmediate(0); 9434 return true; 9435 case 'M': // 8-bit integer constant 9436 Info.setRequiresImmediate(0, 0xff); 9437 return true; 9438 case 'N': // Integer constant (Range: -1) 9439 Info.setRequiresImmediate(-1); 9440 return true; 9441 case 'O': // Integer constant (Range: 8, 16, 24) 9442 Info.setRequiresImmediate({8, 16, 24}); 9443 return true; 9444 case 'P': // Integer constant (Range: 1) 9445 Info.setRequiresImmediate(1); 9446 return true; 9447 case 'R': // Integer constant (Range: -6 to 5) 9448 Info.setRequiresImmediate(-6, 5); 9449 return true; 9450 case 'G': // Floating point constant 9451 case 'Q': // A memory address based on Y or Z pointer with displacement. 9452 return true; 9453 } 9454 9455 return false; 9456 } 9457 9458 IntType getIntTypeByWidth(unsigned BitWidth, 9459 bool IsSigned) const final { 9460 // AVR prefers int for 16-bit integers. 9461 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9462 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9463 } 9464 9465 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9466 bool IsSigned) const final { 9467 // AVR uses int for int_least16_t and int_fast16_t. 9468 return BitWidth == 16 9469 ? (IsSigned ? SignedInt : UnsignedInt) 9470 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9471 } 9472 9473 bool setCPU(const std::string &Name) override { 9474 bool IsFamily = llvm::StringSwitch<bool>(Name) 9475 .Case("avr1", true) 9476 .Case("avr2", true) 9477 .Case("avr25", true) 9478 .Case("avr3", true) 9479 .Case("avr31", true) 9480 .Case("avr35", true) 9481 .Case("avr4", true) 9482 .Case("avr5", true) 9483 .Case("avr51", true) 9484 .Case("avr6", true) 9485 .Case("avrxmega1", true) 9486 .Case("avrxmega2", true) 9487 .Case("avrxmega3", true) 9488 .Case("avrxmega4", true) 9489 .Case("avrxmega5", true) 9490 .Case("avrxmega6", true) 9491 .Case("avrxmega7", true) 9492 .Case("avrtiny", true) 9493 .Default(false); 9494 9495 if (IsFamily) this->CPU = Name; 9496 9497 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9498 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9499 9500 if (IsMCU) this->CPU = Name; 9501 9502 return IsFamily || IsMCU; 9503 } 9504 9505 protected: 9506 std::string CPU; 9507 }; 9508 9509 } // end anonymous namespace 9510 9511 //===----------------------------------------------------------------------===// 9512 // Driver code 9513 //===----------------------------------------------------------------------===// 9514 9515 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9516 const TargetOptions &Opts) { 9517 llvm::Triple::OSType os = Triple.getOS(); 9518 9519 switch (Triple.getArch()) { 9520 default: 9521 return nullptr; 9522 9523 case llvm::Triple::xcore: 9524 return new XCoreTargetInfo(Triple, Opts); 9525 9526 case llvm::Triple::hexagon: 9527 return new HexagonTargetInfo(Triple, Opts); 9528 9529 case llvm::Triple::lanai: 9530 return new LanaiTargetInfo(Triple, Opts); 9531 9532 case llvm::Triple::aarch64: 9533 if (Triple.isOSDarwin()) 9534 return new DarwinAArch64TargetInfo(Triple, Opts); 9535 9536 switch (os) { 9537 case llvm::Triple::CloudABI: 9538 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9539 case llvm::Triple::FreeBSD: 9540 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9541 case llvm::Triple::Fuchsia: 9542 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9543 case llvm::Triple::Linux: 9544 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9545 case llvm::Triple::NetBSD: 9546 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9547 case llvm::Triple::OpenBSD: 9548 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9549 case llvm::Triple::Win32: 9550 return new MicrosoftARM64TargetInfo(Triple, Opts); 9551 default: 9552 return new AArch64leTargetInfo(Triple, Opts); 9553 } 9554 9555 case llvm::Triple::aarch64_be: 9556 switch (os) { 9557 case llvm::Triple::FreeBSD: 9558 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9559 case llvm::Triple::Fuchsia: 9560 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9561 case llvm::Triple::Linux: 9562 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9563 case llvm::Triple::NetBSD: 9564 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9565 default: 9566 return new AArch64beTargetInfo(Triple, Opts); 9567 } 9568 9569 case llvm::Triple::arm: 9570 case llvm::Triple::thumb: 9571 if (Triple.isOSBinFormatMachO()) 9572 return new DarwinARMTargetInfo(Triple, Opts); 9573 9574 switch (os) { 9575 case llvm::Triple::CloudABI: 9576 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9577 case llvm::Triple::Linux: 9578 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9579 case llvm::Triple::FreeBSD: 9580 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9581 case llvm::Triple::NetBSD: 9582 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9583 case llvm::Triple::OpenBSD: 9584 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9585 case llvm::Triple::Bitrig: 9586 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9587 case llvm::Triple::RTEMS: 9588 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9589 case llvm::Triple::NaCl: 9590 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9591 case llvm::Triple::Win32: 9592 switch (Triple.getEnvironment()) { 9593 case llvm::Triple::Cygnus: 9594 return new CygwinARMTargetInfo(Triple, Opts); 9595 case llvm::Triple::GNU: 9596 return new MinGWARMTargetInfo(Triple, Opts); 9597 case llvm::Triple::Itanium: 9598 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9599 case llvm::Triple::MSVC: 9600 default: // Assume MSVC for unknown environments 9601 return new MicrosoftARMleTargetInfo(Triple, Opts); 9602 } 9603 default: 9604 return new ARMleTargetInfo(Triple, Opts); 9605 } 9606 9607 case llvm::Triple::armeb: 9608 case llvm::Triple::thumbeb: 9609 if (Triple.isOSDarwin()) 9610 return new DarwinARMTargetInfo(Triple, Opts); 9611 9612 switch (os) { 9613 case llvm::Triple::Linux: 9614 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9615 case llvm::Triple::FreeBSD: 9616 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9617 case llvm::Triple::NetBSD: 9618 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9619 case llvm::Triple::OpenBSD: 9620 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9621 case llvm::Triple::Bitrig: 9622 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9623 case llvm::Triple::RTEMS: 9624 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9625 case llvm::Triple::NaCl: 9626 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9627 default: 9628 return new ARMbeTargetInfo(Triple, Opts); 9629 } 9630 9631 case llvm::Triple::avr: 9632 return new AVRTargetInfo(Triple, Opts); 9633 case llvm::Triple::bpfeb: 9634 case llvm::Triple::bpfel: 9635 return new BPFTargetInfo(Triple, Opts); 9636 9637 case llvm::Triple::msp430: 9638 return new MSP430TargetInfo(Triple, Opts); 9639 9640 case llvm::Triple::nios2: 9641 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts); 9642 9643 case llvm::Triple::mips: 9644 switch (os) { 9645 case llvm::Triple::Linux: 9646 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9647 case llvm::Triple::RTEMS: 9648 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9649 case llvm::Triple::FreeBSD: 9650 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9651 case llvm::Triple::NetBSD: 9652 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9653 default: 9654 return new MipsTargetInfo(Triple, Opts); 9655 } 9656 9657 case llvm::Triple::mipsel: 9658 switch (os) { 9659 case llvm::Triple::Linux: 9660 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9661 case llvm::Triple::RTEMS: 9662 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9663 case llvm::Triple::FreeBSD: 9664 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9665 case llvm::Triple::NetBSD: 9666 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9667 case llvm::Triple::NaCl: 9668 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9669 default: 9670 return new MipsTargetInfo(Triple, Opts); 9671 } 9672 9673 case llvm::Triple::mips64: 9674 switch (os) { 9675 case llvm::Triple::Linux: 9676 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9677 case llvm::Triple::RTEMS: 9678 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9679 case llvm::Triple::FreeBSD: 9680 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9681 case llvm::Triple::NetBSD: 9682 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9683 case llvm::Triple::OpenBSD: 9684 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9685 default: 9686 return new MipsTargetInfo(Triple, Opts); 9687 } 9688 9689 case llvm::Triple::mips64el: 9690 switch (os) { 9691 case llvm::Triple::Linux: 9692 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9693 case llvm::Triple::RTEMS: 9694 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9695 case llvm::Triple::FreeBSD: 9696 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9697 case llvm::Triple::NetBSD: 9698 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9699 case llvm::Triple::OpenBSD: 9700 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9701 default: 9702 return new MipsTargetInfo(Triple, Opts); 9703 } 9704 9705 case llvm::Triple::le32: 9706 switch (os) { 9707 case llvm::Triple::NaCl: 9708 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9709 default: 9710 return nullptr; 9711 } 9712 9713 case llvm::Triple::le64: 9714 return new Le64TargetInfo(Triple, Opts); 9715 9716 case llvm::Triple::ppc: 9717 if (Triple.isOSDarwin()) 9718 return new DarwinPPC32TargetInfo(Triple, Opts); 9719 switch (os) { 9720 case llvm::Triple::Linux: 9721 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9722 case llvm::Triple::FreeBSD: 9723 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9724 case llvm::Triple::NetBSD: 9725 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9726 case llvm::Triple::OpenBSD: 9727 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9728 case llvm::Triple::RTEMS: 9729 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9730 default: 9731 return new PPC32TargetInfo(Triple, Opts); 9732 } 9733 9734 case llvm::Triple::ppc64: 9735 if (Triple.isOSDarwin()) 9736 return new DarwinPPC64TargetInfo(Triple, Opts); 9737 switch (os) { 9738 case llvm::Triple::Linux: 9739 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9740 case llvm::Triple::Lv2: 9741 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9742 case llvm::Triple::FreeBSD: 9743 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9744 case llvm::Triple::NetBSD: 9745 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9746 default: 9747 return new PPC64TargetInfo(Triple, Opts); 9748 } 9749 9750 case llvm::Triple::ppc64le: 9751 switch (os) { 9752 case llvm::Triple::Linux: 9753 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9754 case llvm::Triple::NetBSD: 9755 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9756 default: 9757 return new PPC64TargetInfo(Triple, Opts); 9758 } 9759 9760 case llvm::Triple::nvptx: 9761 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9762 case llvm::Triple::nvptx64: 9763 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9764 9765 case llvm::Triple::amdgcn: 9766 case llvm::Triple::r600: 9767 return new AMDGPUTargetInfo(Triple, Opts); 9768 9769 case llvm::Triple::sparc: 9770 switch (os) { 9771 case llvm::Triple::Linux: 9772 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9773 case llvm::Triple::Solaris: 9774 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9775 case llvm::Triple::NetBSD: 9776 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9777 case llvm::Triple::OpenBSD: 9778 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9779 case llvm::Triple::RTEMS: 9780 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9781 default: 9782 return new SparcV8TargetInfo(Triple, Opts); 9783 } 9784 9785 // The 'sparcel' architecture copies all the above cases except for Solaris. 9786 case llvm::Triple::sparcel: 9787 switch (os) { 9788 case llvm::Triple::Linux: 9789 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9790 case llvm::Triple::NetBSD: 9791 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9792 case llvm::Triple::OpenBSD: 9793 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9794 case llvm::Triple::RTEMS: 9795 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9796 default: 9797 return new SparcV8elTargetInfo(Triple, Opts); 9798 } 9799 9800 case llvm::Triple::sparcv9: 9801 switch (os) { 9802 case llvm::Triple::Linux: 9803 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9804 case llvm::Triple::Solaris: 9805 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9806 case llvm::Triple::NetBSD: 9807 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9808 case llvm::Triple::OpenBSD: 9809 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9810 case llvm::Triple::FreeBSD: 9811 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9812 default: 9813 return new SparcV9TargetInfo(Triple, Opts); 9814 } 9815 9816 case llvm::Triple::systemz: 9817 switch (os) { 9818 case llvm::Triple::Linux: 9819 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9820 default: 9821 return new SystemZTargetInfo(Triple, Opts); 9822 } 9823 9824 case llvm::Triple::tce: 9825 return new TCETargetInfo(Triple, Opts); 9826 9827 case llvm::Triple::tcele: 9828 return new TCELETargetInfo(Triple, Opts); 9829 9830 case llvm::Triple::x86: 9831 if (Triple.isOSDarwin()) 9832 return new DarwinI386TargetInfo(Triple, Opts); 9833 9834 switch (os) { 9835 case llvm::Triple::Ananas: 9836 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts); 9837 case llvm::Triple::CloudABI: 9838 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9839 case llvm::Triple::Linux: { 9840 switch (Triple.getEnvironment()) { 9841 default: 9842 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9843 case llvm::Triple::Android: 9844 return new AndroidX86_32TargetInfo(Triple, Opts); 9845 } 9846 } 9847 case llvm::Triple::DragonFly: 9848 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9849 case llvm::Triple::NetBSD: 9850 return new NetBSDI386TargetInfo(Triple, Opts); 9851 case llvm::Triple::OpenBSD: 9852 return new OpenBSDI386TargetInfo(Triple, Opts); 9853 case llvm::Triple::Bitrig: 9854 return new BitrigI386TargetInfo(Triple, Opts); 9855 case llvm::Triple::FreeBSD: 9856 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9857 case llvm::Triple::KFreeBSD: 9858 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9859 case llvm::Triple::Minix: 9860 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9861 case llvm::Triple::Solaris: 9862 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9863 case llvm::Triple::Win32: { 9864 switch (Triple.getEnvironment()) { 9865 case llvm::Triple::Cygnus: 9866 return new CygwinX86_32TargetInfo(Triple, Opts); 9867 case llvm::Triple::GNU: 9868 return new MinGWX86_32TargetInfo(Triple, Opts); 9869 case llvm::Triple::Itanium: 9870 case llvm::Triple::MSVC: 9871 default: // Assume MSVC for unknown environments 9872 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9873 } 9874 } 9875 case llvm::Triple::Haiku: 9876 return new HaikuX86_32TargetInfo(Triple, Opts); 9877 case llvm::Triple::RTEMS: 9878 return new RTEMSX86_32TargetInfo(Triple, Opts); 9879 case llvm::Triple::NaCl: 9880 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9881 case llvm::Triple::ELFIAMCU: 9882 return new MCUX86_32TargetInfo(Triple, Opts); 9883 default: 9884 return new X86_32TargetInfo(Triple, Opts); 9885 } 9886 9887 case llvm::Triple::x86_64: 9888 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9889 return new DarwinX86_64TargetInfo(Triple, Opts); 9890 9891 switch (os) { 9892 case llvm::Triple::Ananas: 9893 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts); 9894 case llvm::Triple::CloudABI: 9895 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9896 case llvm::Triple::Linux: { 9897 switch (Triple.getEnvironment()) { 9898 default: 9899 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9900 case llvm::Triple::Android: 9901 return new AndroidX86_64TargetInfo(Triple, Opts); 9902 } 9903 } 9904 case llvm::Triple::DragonFly: 9905 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9906 case llvm::Triple::NetBSD: 9907 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9908 case llvm::Triple::OpenBSD: 9909 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9910 case llvm::Triple::Bitrig: 9911 return new BitrigX86_64TargetInfo(Triple, Opts); 9912 case llvm::Triple::FreeBSD: 9913 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9914 case llvm::Triple::Fuchsia: 9915 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9916 case llvm::Triple::KFreeBSD: 9917 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9918 case llvm::Triple::Solaris: 9919 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9920 case llvm::Triple::Win32: { 9921 switch (Triple.getEnvironment()) { 9922 case llvm::Triple::Cygnus: 9923 return new CygwinX86_64TargetInfo(Triple, Opts); 9924 case llvm::Triple::GNU: 9925 return new MinGWX86_64TargetInfo(Triple, Opts); 9926 case llvm::Triple::MSVC: 9927 default: // Assume MSVC for unknown environments 9928 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9929 } 9930 } 9931 case llvm::Triple::Haiku: 9932 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9933 case llvm::Triple::NaCl: 9934 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9935 case llvm::Triple::PS4: 9936 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9937 default: 9938 return new X86_64TargetInfo(Triple, Opts); 9939 } 9940 9941 case llvm::Triple::spir: { 9942 if (Triple.getOS() != llvm::Triple::UnknownOS || 9943 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9944 return nullptr; 9945 return new SPIR32TargetInfo(Triple, Opts); 9946 } 9947 case llvm::Triple::spir64: { 9948 if (Triple.getOS() != llvm::Triple::UnknownOS || 9949 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9950 return nullptr; 9951 return new SPIR64TargetInfo(Triple, Opts); 9952 } 9953 case llvm::Triple::wasm32: 9954 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9955 Triple.getVendor() != llvm::Triple::UnknownVendor || 9956 Triple.getOS() != llvm::Triple::UnknownOS || 9957 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9958 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9959 return nullptr; 9960 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9961 case llvm::Triple::wasm64: 9962 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9963 Triple.getVendor() != llvm::Triple::UnknownVendor || 9964 Triple.getOS() != llvm::Triple::UnknownOS || 9965 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9966 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9967 return nullptr; 9968 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9969 9970 case llvm::Triple::renderscript32: 9971 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9972 case llvm::Triple::renderscript64: 9973 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9974 } 9975 } 9976 9977 /// CreateTargetInfo - Return the target info object for the specified target 9978 /// options. 9979 TargetInfo * 9980 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9981 const std::shared_ptr<TargetOptions> &Opts) { 9982 llvm::Triple Triple(Opts->Triple); 9983 9984 // Construct the target 9985 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9986 if (!Target) { 9987 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9988 return nullptr; 9989 } 9990 Target->TargetOpts = Opts; 9991 9992 // Set the target CPU if specified. 9993 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9994 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9995 return nullptr; 9996 } 9997 9998 // Set the target ABI if specified. 9999 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 10000 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 10001 return nullptr; 10002 } 10003 10004 // Set the fp math unit. 10005 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 10006 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 10007 return nullptr; 10008 } 10009 10010 // Compute the default target features, we need the target to handle this 10011 // because features may have dependencies on one another. 10012 llvm::StringMap<bool> Features; 10013 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 10014 Opts->FeaturesAsWritten)) 10015 return nullptr; 10016 10017 // Add the features to the compile options. 10018 Opts->Features.clear(); 10019 for (const auto &F : Features) 10020 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 10021 10022 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 10023 return nullptr; 10024 10025 Target->setSupportedOpenCLOpts(); 10026 Target->setOpenCLExtensionOpts(); 10027 10028 if (!Target->validateTarget(Diags)) 10029 return nullptr; 10030 10031 return Target.release(); 10032 } 10033