1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 // By default, no TLS, and we whitelist permitted architecture/OS 227 // combinations. 228 this->TLSSupported = false; 229 230 if (Triple.isMacOSX()) 231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 232 else if (Triple.isiOS()) { 233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 234 if (Triple.getArch() == llvm::Triple::x86_64 || 235 Triple.getArch() == llvm::Triple::aarch64) 236 this->TLSSupported = !Triple.isOSVersionLT(8); 237 else if (Triple.getArch() == llvm::Triple::x86 || 238 Triple.getArch() == llvm::Triple::arm || 239 Triple.getArch() == llvm::Triple::thumb) 240 this->TLSSupported = !Triple.isOSVersionLT(9); 241 } else if (Triple.isWatchOS()) 242 this->TLSSupported = !Triple.isOSVersionLT(2); 243 244 this->MCountName = "\01mcount"; 245 } 246 247 std::string isValidSectionSpecifier(StringRef SR) const override { 248 // Let MCSectionMachO validate this. 249 StringRef Segment, Section; 250 unsigned TAA, StubSize; 251 bool HasTAA; 252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 253 TAA, HasTAA, StubSize); 254 } 255 256 const char *getStaticInitSectionSpecifier() const override { 257 // FIXME: We should return 0 when building kexts. 258 return "__TEXT,__StaticInit,regular,pure_instructions"; 259 } 260 261 /// Darwin does not support protected visibility. Darwin's "default" 262 /// is very similar to ELF's "protected"; Darwin requires a "weak" 263 /// attribute on declarations that can be dynamically replaced. 264 bool hasProtectedVisibility() const override { 265 return false; 266 } 267 }; 268 269 270 // DragonFlyBSD Target 271 template<typename Target> 272 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 273 protected: 274 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 275 MacroBuilder &Builder) const override { 276 // DragonFly defines; list based off of gcc output 277 Builder.defineMacro("__DragonFly__"); 278 Builder.defineMacro("__DragonFly_cc_version", "100001"); 279 Builder.defineMacro("__ELF__"); 280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 281 Builder.defineMacro("__tune_i386__"); 282 DefineStd(Builder, "unix", Opts); 283 } 284 public: 285 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 286 : OSTargetInfo<Target>(Triple) { 287 this->UserLabelPrefix = ""; 288 289 switch (Triple.getArch()) { 290 default: 291 case llvm::Triple::x86: 292 case llvm::Triple::x86_64: 293 this->MCountName = ".mcount"; 294 break; 295 } 296 } 297 }; 298 299 #ifndef FREEBSD_CC_VERSION 300 #define FREEBSD_CC_VERSION 0U 301 #endif 302 303 // FreeBSD Target 304 template<typename Target> 305 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 306 protected: 307 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 308 MacroBuilder &Builder) const override { 309 // FreeBSD defines; list based off of gcc output 310 311 unsigned Release = Triple.getOSMajorVersion(); 312 if (Release == 0U) 313 Release = 8U; 314 unsigned CCVersion = FREEBSD_CC_VERSION; 315 if (CCVersion == 0U) 316 CCVersion = Release * 100000U + 1U; 317 318 Builder.defineMacro("__FreeBSD__", Twine(Release)); 319 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 320 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 321 DefineStd(Builder, "unix", Opts); 322 Builder.defineMacro("__ELF__"); 323 324 // On FreeBSD, wchar_t contains the number of the code point as 325 // used by the character set of the locale. These character sets are 326 // not necessarily a superset of ASCII. 327 // 328 // FIXME: This is wrong; the macro refers to the numerical values 329 // of wchar_t *literals*, which are not locale-dependent. However, 330 // FreeBSD systems apparently depend on us getting this wrong, and 331 // setting this to 1 is conforming even if all the basic source 332 // character literals have the same encoding as char and wchar_t. 333 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 334 } 335 public: 336 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 337 this->UserLabelPrefix = ""; 338 339 switch (Triple.getArch()) { 340 default: 341 case llvm::Triple::x86: 342 case llvm::Triple::x86_64: 343 this->MCountName = ".mcount"; 344 break; 345 case llvm::Triple::mips: 346 case llvm::Triple::mipsel: 347 case llvm::Triple::ppc: 348 case llvm::Triple::ppc64: 349 case llvm::Triple::ppc64le: 350 this->MCountName = "_mcount"; 351 break; 352 case llvm::Triple::arm: 353 this->MCountName = "__mcount"; 354 break; 355 } 356 } 357 }; 358 359 // GNU/kFreeBSD Target 360 template<typename Target> 361 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 362 protected: 363 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 364 MacroBuilder &Builder) const override { 365 // GNU/kFreeBSD defines; list based off of gcc output 366 367 DefineStd(Builder, "unix", Opts); 368 Builder.defineMacro("__FreeBSD_kernel__"); 369 Builder.defineMacro("__GLIBC__"); 370 Builder.defineMacro("__ELF__"); 371 if (Opts.POSIXThreads) 372 Builder.defineMacro("_REENTRANT"); 373 if (Opts.CPlusPlus) 374 Builder.defineMacro("_GNU_SOURCE"); 375 } 376 public: 377 KFreeBSDTargetInfo(const llvm::Triple &Triple) 378 : OSTargetInfo<Target>(Triple) { 379 this->UserLabelPrefix = ""; 380 } 381 }; 382 383 // Minix Target 384 template<typename Target> 385 class MinixTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // Minix defines 390 391 Builder.defineMacro("__minix", "3"); 392 Builder.defineMacro("_EM_WSIZE", "4"); 393 Builder.defineMacro("_EM_PSIZE", "4"); 394 Builder.defineMacro("_EM_SSIZE", "2"); 395 Builder.defineMacro("_EM_LSIZE", "4"); 396 Builder.defineMacro("_EM_FSIZE", "4"); 397 Builder.defineMacro("_EM_DSIZE", "8"); 398 Builder.defineMacro("__ELF__"); 399 DefineStd(Builder, "unix", Opts); 400 } 401 public: 402 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 } 405 }; 406 407 // Linux target 408 template<typename Target> 409 class LinuxTargetInfo : public OSTargetInfo<Target> { 410 protected: 411 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 412 MacroBuilder &Builder) const override { 413 // Linux defines; list based off of gcc output 414 DefineStd(Builder, "unix", Opts); 415 DefineStd(Builder, "linux", Opts); 416 Builder.defineMacro("__gnu_linux__"); 417 Builder.defineMacro("__ELF__"); 418 if (Triple.isAndroid()) { 419 Builder.defineMacro("__ANDROID__", "1"); 420 unsigned Maj, Min, Rev; 421 Triple.getEnvironmentVersion(Maj, Min, Rev); 422 this->PlatformName = "android"; 423 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 424 } 425 if (Opts.POSIXThreads) 426 Builder.defineMacro("_REENTRANT"); 427 if (Opts.CPlusPlus) 428 Builder.defineMacro("_GNU_SOURCE"); 429 } 430 public: 431 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 432 this->UserLabelPrefix = ""; 433 this->WIntType = TargetInfo::UnsignedInt; 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::ppc: 439 case llvm::Triple::ppc64: 440 case llvm::Triple::ppc64le: 441 this->MCountName = "_mcount"; 442 break; 443 } 444 } 445 446 const char *getStaticInitSectionSpecifier() const override { 447 return ".text.startup"; 448 } 449 }; 450 451 // NetBSD Target 452 template<typename Target> 453 class NetBSDTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // NetBSD defines; list based off of gcc output 458 Builder.defineMacro("__NetBSD__"); 459 Builder.defineMacro("__unix__"); 460 Builder.defineMacro("__ELF__"); 461 if (Opts.POSIXThreads) 462 Builder.defineMacro("_POSIX_THREADS"); 463 464 switch (Triple.getArch()) { 465 default: 466 break; 467 case llvm::Triple::arm: 468 case llvm::Triple::armeb: 469 case llvm::Triple::thumb: 470 case llvm::Triple::thumbeb: 471 Builder.defineMacro("__ARM_DWARF_EH__"); 472 break; 473 } 474 } 475 public: 476 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 477 this->UserLabelPrefix = ""; 478 this->MCountName = "_mcount"; 479 } 480 }; 481 482 // OpenBSD Target 483 template<typename Target> 484 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 485 protected: 486 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 487 MacroBuilder &Builder) const override { 488 // OpenBSD defines; list based off of gcc output 489 490 Builder.defineMacro("__OpenBSD__"); 491 DefineStd(Builder, "unix", Opts); 492 Builder.defineMacro("__ELF__"); 493 if (Opts.POSIXThreads) 494 Builder.defineMacro("_REENTRANT"); 495 } 496 public: 497 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 498 this->UserLabelPrefix = ""; 499 this->TLSSupported = false; 500 501 switch (Triple.getArch()) { 502 default: 503 case llvm::Triple::x86: 504 case llvm::Triple::x86_64: 505 case llvm::Triple::arm: 506 case llvm::Triple::sparc: 507 this->MCountName = "__mcount"; 508 break; 509 case llvm::Triple::mips64: 510 case llvm::Triple::mips64el: 511 case llvm::Triple::ppc: 512 case llvm::Triple::sparcv9: 513 this->MCountName = "_mcount"; 514 break; 515 } 516 } 517 }; 518 519 // Bitrig Target 520 template<typename Target> 521 class BitrigTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const override { 525 // Bitrig defines; list based off of gcc output 526 527 Builder.defineMacro("__Bitrig__"); 528 DefineStd(Builder, "unix", Opts); 529 Builder.defineMacro("__ELF__"); 530 if (Opts.POSIXThreads) 531 Builder.defineMacro("_REENTRANT"); 532 533 switch (Triple.getArch()) { 534 default: 535 break; 536 case llvm::Triple::arm: 537 case llvm::Triple::armeb: 538 case llvm::Triple::thumb: 539 case llvm::Triple::thumbeb: 540 Builder.defineMacro("__ARM_DWARF_EH__"); 541 break; 542 } 543 } 544 public: 545 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 546 this->UserLabelPrefix = ""; 547 this->MCountName = "__mcount"; 548 } 549 }; 550 551 // PSP Target 552 template<typename Target> 553 class PSPTargetInfo : public OSTargetInfo<Target> { 554 protected: 555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 556 MacroBuilder &Builder) const override { 557 // PSP defines; list based on the output of the pspdev gcc toolchain. 558 Builder.defineMacro("PSP"); 559 Builder.defineMacro("_PSP"); 560 Builder.defineMacro("__psp__"); 561 Builder.defineMacro("__ELF__"); 562 } 563 public: 564 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 565 this->UserLabelPrefix = ""; 566 } 567 }; 568 569 // PS3 PPU Target 570 template<typename Target> 571 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 572 protected: 573 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 574 MacroBuilder &Builder) const override { 575 // PS3 PPU defines. 576 Builder.defineMacro("__PPC__"); 577 Builder.defineMacro("__PPU__"); 578 Builder.defineMacro("__CELLOS_LV2__"); 579 Builder.defineMacro("__ELF__"); 580 Builder.defineMacro("__LP32__"); 581 Builder.defineMacro("_ARCH_PPC64"); 582 Builder.defineMacro("__powerpc64__"); 583 } 584 public: 585 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 586 this->UserLabelPrefix = ""; 587 this->LongWidth = this->LongAlign = 32; 588 this->PointerWidth = this->PointerAlign = 32; 589 this->IntMaxType = TargetInfo::SignedLongLong; 590 this->Int64Type = TargetInfo::SignedLongLong; 591 this->SizeType = TargetInfo::UnsignedInt; 592 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 593 } 594 }; 595 596 template <typename Target> 597 class PS4OSTargetInfo : public OSTargetInfo<Target> { 598 protected: 599 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 600 MacroBuilder &Builder) const override { 601 Builder.defineMacro("__FreeBSD__", "9"); 602 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 603 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 604 DefineStd(Builder, "unix", Opts); 605 Builder.defineMacro("__ELF__"); 606 Builder.defineMacro("__PS4__"); 607 } 608 public: 609 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 610 this->WCharType = this->UnsignedShort; 611 612 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 613 this->MaxTLSAlign = 256; 614 this->UserLabelPrefix = ""; 615 616 switch (Triple.getArch()) { 617 default: 618 case llvm::Triple::x86_64: 619 this->MCountName = ".mcount"; 620 break; 621 } 622 } 623 }; 624 625 // Solaris target 626 template<typename Target> 627 class SolarisTargetInfo : public OSTargetInfo<Target> { 628 protected: 629 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 630 MacroBuilder &Builder) const override { 631 DefineStd(Builder, "sun", Opts); 632 DefineStd(Builder, "unix", Opts); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__svr4__"); 635 Builder.defineMacro("__SVR4"); 636 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 637 // newer, but to 500 for everything else. feature_test.h has a check to 638 // ensure that you are not using C99 with an old version of X/Open or C89 639 // with a new version. 640 if (Opts.C99) 641 Builder.defineMacro("_XOPEN_SOURCE", "600"); 642 else 643 Builder.defineMacro("_XOPEN_SOURCE", "500"); 644 if (Opts.CPlusPlus) 645 Builder.defineMacro("__C99FEATURES__"); 646 Builder.defineMacro("_LARGEFILE_SOURCE"); 647 Builder.defineMacro("_LARGEFILE64_SOURCE"); 648 Builder.defineMacro("__EXTENSIONS__"); 649 Builder.defineMacro("_REENTRANT"); 650 } 651 public: 652 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 653 this->UserLabelPrefix = ""; 654 this->WCharType = this->SignedInt; 655 // FIXME: WIntType should be SignedLong 656 } 657 }; 658 659 // Windows target 660 template<typename Target> 661 class WindowsTargetInfo : public OSTargetInfo<Target> { 662 protected: 663 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 664 MacroBuilder &Builder) const override { 665 Builder.defineMacro("_WIN32"); 666 } 667 void getVisualStudioDefines(const LangOptions &Opts, 668 MacroBuilder &Builder) const { 669 if (Opts.CPlusPlus) { 670 if (Opts.RTTIData) 671 Builder.defineMacro("_CPPRTTI"); 672 673 if (Opts.CXXExceptions) 674 Builder.defineMacro("_CPPUNWIND"); 675 } 676 677 if (Opts.Bool) 678 Builder.defineMacro("__BOOL_DEFINED"); 679 680 if (!Opts.CharIsSigned) 681 Builder.defineMacro("_CHAR_UNSIGNED"); 682 683 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 684 // but it works for now. 685 if (Opts.POSIXThreads) 686 Builder.defineMacro("_MT"); 687 688 if (Opts.MSCompatibilityVersion) { 689 Builder.defineMacro("_MSC_VER", 690 Twine(Opts.MSCompatibilityVersion / 100000)); 691 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 692 // FIXME We cannot encode the revision information into 32-bits 693 Builder.defineMacro("_MSC_BUILD", Twine(1)); 694 695 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 696 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 697 } 698 699 if (Opts.MicrosoftExt) { 700 Builder.defineMacro("_MSC_EXTENSIONS"); 701 702 if (Opts.CPlusPlus11) { 703 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 704 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 705 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 706 } 707 } 708 709 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 710 } 711 712 public: 713 WindowsTargetInfo(const llvm::Triple &Triple) 714 : OSTargetInfo<Target>(Triple) {} 715 }; 716 717 template <typename Target> 718 class NaClTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 if (Opts.POSIXThreads) 723 Builder.defineMacro("_REENTRANT"); 724 if (Opts.CPlusPlus) 725 Builder.defineMacro("_GNU_SOURCE"); 726 727 DefineStd(Builder, "unix", Opts); 728 Builder.defineMacro("__ELF__"); 729 Builder.defineMacro("__native_client__"); 730 } 731 732 public: 733 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 734 this->UserLabelPrefix = ""; 735 this->LongAlign = 32; 736 this->LongWidth = 32; 737 this->PointerAlign = 32; 738 this->PointerWidth = 32; 739 this->IntMaxType = TargetInfo::SignedLongLong; 740 this->Int64Type = TargetInfo::SignedLongLong; 741 this->DoubleAlign = 64; 742 this->LongDoubleWidth = 64; 743 this->LongDoubleAlign = 64; 744 this->LongLongWidth = 64; 745 this->LongLongAlign = 64; 746 this->SizeType = TargetInfo::UnsignedInt; 747 this->PtrDiffType = TargetInfo::SignedInt; 748 this->IntPtrType = TargetInfo::SignedInt; 749 // RegParmMax is inherited from the underlying architecture 750 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 751 if (Triple.getArch() == llvm::Triple::arm) { 752 // Handled in ARM's setABI(). 753 } else if (Triple.getArch() == llvm::Triple::x86) { 754 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 755 } else if (Triple.getArch() == llvm::Triple::x86_64) { 756 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 757 } else if (Triple.getArch() == llvm::Triple::mipsel) { 758 // Handled on mips' setDataLayoutString. 759 } else { 760 assert(Triple.getArch() == llvm::Triple::le32); 761 this->DataLayoutString = "e-p:32:32-i64:64"; 762 } 763 } 764 }; 765 766 // WebAssembly target 767 template <typename Target> 768 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 769 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 770 MacroBuilder &Builder) const final { 771 // A common platform macro. 772 if (Opts.POSIXThreads) 773 Builder.defineMacro("_REENTRANT"); 774 // Follow g++ convention and predefine _GNU_SOURCE for C++. 775 if (Opts.CPlusPlus) 776 Builder.defineMacro("_GNU_SOURCE"); 777 } 778 779 // As an optimization, group static init code together in a section. 780 const char *getStaticInitSectionSpecifier() const final { 781 return ".text.__startup"; 782 } 783 784 public: 785 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 786 : OSTargetInfo<Target>(Triple) { 787 this->MCountName = "__mcount"; 788 this->UserLabelPrefix = ""; 789 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 790 } 791 }; 792 793 //===----------------------------------------------------------------------===// 794 // Specific target implementations. 795 //===----------------------------------------------------------------------===// 796 797 // PPC abstract base class 798 class PPCTargetInfo : public TargetInfo { 799 static const Builtin::Info BuiltinInfo[]; 800 static const char * const GCCRegNames[]; 801 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 802 std::string CPU; 803 804 // Target cpu features. 805 bool HasVSX; 806 bool HasP8Vector; 807 bool HasP8Crypto; 808 bool HasDirectMove; 809 bool HasQPX; 810 bool HasHTM; 811 bool HasBPERMD; 812 bool HasExtDiv; 813 814 protected: 815 std::string ABI; 816 817 public: 818 PPCTargetInfo(const llvm::Triple &Triple) 819 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 820 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 821 HasBPERMD(false), HasExtDiv(false) { 822 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 823 SimdDefaultAlign = 128; 824 LongDoubleWidth = LongDoubleAlign = 128; 825 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 826 } 827 828 /// \brief Flags for architecture specific defines. 829 typedef enum { 830 ArchDefineNone = 0, 831 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 832 ArchDefinePpcgr = 1 << 1, 833 ArchDefinePpcsq = 1 << 2, 834 ArchDefine440 = 1 << 3, 835 ArchDefine603 = 1 << 4, 836 ArchDefine604 = 1 << 5, 837 ArchDefinePwr4 = 1 << 6, 838 ArchDefinePwr5 = 1 << 7, 839 ArchDefinePwr5x = 1 << 8, 840 ArchDefinePwr6 = 1 << 9, 841 ArchDefinePwr6x = 1 << 10, 842 ArchDefinePwr7 = 1 << 11, 843 ArchDefinePwr8 = 1 << 12, 844 ArchDefineA2 = 1 << 13, 845 ArchDefineA2q = 1 << 14 846 } ArchDefineTypes; 847 848 // Note: GCC recognizes the following additional cpus: 849 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 850 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 851 // titan, rs64. 852 bool setCPU(const std::string &Name) override { 853 bool CPUKnown = llvm::StringSwitch<bool>(Name) 854 .Case("generic", true) 855 .Case("440", true) 856 .Case("450", true) 857 .Case("601", true) 858 .Case("602", true) 859 .Case("603", true) 860 .Case("603e", true) 861 .Case("603ev", true) 862 .Case("604", true) 863 .Case("604e", true) 864 .Case("620", true) 865 .Case("630", true) 866 .Case("g3", true) 867 .Case("7400", true) 868 .Case("g4", true) 869 .Case("7450", true) 870 .Case("g4+", true) 871 .Case("750", true) 872 .Case("970", true) 873 .Case("g5", true) 874 .Case("a2", true) 875 .Case("a2q", true) 876 .Case("e500mc", true) 877 .Case("e5500", true) 878 .Case("power3", true) 879 .Case("pwr3", true) 880 .Case("power4", true) 881 .Case("pwr4", true) 882 .Case("power5", true) 883 .Case("pwr5", true) 884 .Case("power5x", true) 885 .Case("pwr5x", true) 886 .Case("power6", true) 887 .Case("pwr6", true) 888 .Case("power6x", true) 889 .Case("pwr6x", true) 890 .Case("power7", true) 891 .Case("pwr7", true) 892 .Case("power8", true) 893 .Case("pwr8", true) 894 .Case("powerpc", true) 895 .Case("ppc", true) 896 .Case("powerpc64", true) 897 .Case("ppc64", true) 898 .Case("powerpc64le", true) 899 .Case("ppc64le", true) 900 .Default(false); 901 902 if (CPUKnown) 903 CPU = Name; 904 905 return CPUKnown; 906 } 907 908 909 StringRef getABI() const override { return ABI; } 910 911 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 912 return llvm::makeArrayRef(BuiltinInfo, 913 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 914 } 915 916 bool isCLZForZeroUndef() const override { return false; } 917 918 void getTargetDefines(const LangOptions &Opts, 919 MacroBuilder &Builder) const override; 920 921 bool 922 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 923 StringRef CPU, 924 const std::vector<std::string> &FeaturesVec) const override; 925 926 bool handleTargetFeatures(std::vector<std::string> &Features, 927 DiagnosticsEngine &Diags) override; 928 bool hasFeature(StringRef Feature) const override; 929 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 930 bool Enabled) const override; 931 932 ArrayRef<const char *> getGCCRegNames() const override; 933 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 934 bool validateAsmConstraint(const char *&Name, 935 TargetInfo::ConstraintInfo &Info) const override { 936 switch (*Name) { 937 default: return false; 938 case 'O': // Zero 939 break; 940 case 'b': // Base register 941 case 'f': // Floating point register 942 Info.setAllowsRegister(); 943 break; 944 // FIXME: The following are added to allow parsing. 945 // I just took a guess at what the actions should be. 946 // Also, is more specific checking needed? I.e. specific registers? 947 case 'd': // Floating point register (containing 64-bit value) 948 case 'v': // Altivec vector register 949 Info.setAllowsRegister(); 950 break; 951 case 'w': 952 switch (Name[1]) { 953 case 'd':// VSX vector register to hold vector double data 954 case 'f':// VSX vector register to hold vector float data 955 case 's':// VSX vector register to hold scalar float data 956 case 'a':// Any VSX register 957 case 'c':// An individual CR bit 958 break; 959 default: 960 return false; 961 } 962 Info.setAllowsRegister(); 963 Name++; // Skip over 'w'. 964 break; 965 case 'h': // `MQ', `CTR', or `LINK' register 966 case 'q': // `MQ' register 967 case 'c': // `CTR' register 968 case 'l': // `LINK' register 969 case 'x': // `CR' register (condition register) number 0 970 case 'y': // `CR' register (condition register) 971 case 'z': // `XER[CA]' carry bit (part of the XER register) 972 Info.setAllowsRegister(); 973 break; 974 case 'I': // Signed 16-bit constant 975 case 'J': // Unsigned 16-bit constant shifted left 16 bits 976 // (use `L' instead for SImode constants) 977 case 'K': // Unsigned 16-bit constant 978 case 'L': // Signed 16-bit constant shifted left 16 bits 979 case 'M': // Constant larger than 31 980 case 'N': // Exact power of 2 981 case 'P': // Constant whose negation is a signed 16-bit constant 982 case 'G': // Floating point constant that can be loaded into a 983 // register with one instruction per word 984 case 'H': // Integer/Floating point constant that can be loaded 985 // into a register using three instructions 986 break; 987 case 'm': // Memory operand. Note that on PowerPC targets, m can 988 // include addresses that update the base register. It 989 // is therefore only safe to use `m' in an asm statement 990 // if that asm statement accesses the operand exactly once. 991 // The asm statement must also use `%U<opno>' as a 992 // placeholder for the "update" flag in the corresponding 993 // load or store instruction. For example: 994 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 995 // is correct but: 996 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 997 // is not. Use es rather than m if you don't want the base 998 // register to be updated. 999 case 'e': 1000 if (Name[1] != 's') 1001 return false; 1002 // es: A "stable" memory operand; that is, one which does not 1003 // include any automodification of the base register. Unlike 1004 // `m', this constraint can be used in asm statements that 1005 // might access the operand several times, or that might not 1006 // access it at all. 1007 Info.setAllowsMemory(); 1008 Name++; // Skip over 'e'. 1009 break; 1010 case 'Q': // Memory operand that is an offset from a register (it is 1011 // usually better to use `m' or `es' in asm statements) 1012 case 'Z': // Memory operand that is an indexed or indirect from a 1013 // register (it is usually better to use `m' or `es' in 1014 // asm statements) 1015 Info.setAllowsMemory(); 1016 Info.setAllowsRegister(); 1017 break; 1018 case 'R': // AIX TOC entry 1019 case 'a': // Address operand that is an indexed or indirect from a 1020 // register (`p' is preferable for asm statements) 1021 case 'S': // Constant suitable as a 64-bit mask operand 1022 case 'T': // Constant suitable as a 32-bit mask operand 1023 case 'U': // System V Release 4 small data area reference 1024 case 't': // AND masks that can be performed by two rldic{l, r} 1025 // instructions 1026 case 'W': // Vector constant that does not require memory 1027 case 'j': // Vector constant that is all zeros. 1028 break; 1029 // End FIXME. 1030 } 1031 return true; 1032 } 1033 std::string convertConstraint(const char *&Constraint) const override { 1034 std::string R; 1035 switch (*Constraint) { 1036 case 'e': 1037 case 'w': 1038 // Two-character constraint; add "^" hint for later parsing. 1039 R = std::string("^") + std::string(Constraint, 2); 1040 Constraint++; 1041 break; 1042 default: 1043 return TargetInfo::convertConstraint(Constraint); 1044 } 1045 return R; 1046 } 1047 const char *getClobbers() const override { 1048 return ""; 1049 } 1050 int getEHDataRegisterNumber(unsigned RegNo) const override { 1051 if (RegNo == 0) return 3; 1052 if (RegNo == 1) return 4; 1053 return -1; 1054 } 1055 1056 bool hasSjLjLowering() const override { 1057 return true; 1058 } 1059 1060 bool useFloat128ManglingForLongDouble() const override { 1061 return LongDoubleWidth == 128 && 1062 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1063 getTriple().isOSBinFormatELF(); 1064 } 1065 }; 1066 1067 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1068 #define BUILTIN(ID, TYPE, ATTRS) \ 1069 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1070 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1071 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1072 #include "clang/Basic/BuiltinsPPC.def" 1073 }; 1074 1075 /// handleTargetFeatures - Perform initialization based on the user 1076 /// configured set of features. 1077 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1078 DiagnosticsEngine &Diags) { 1079 for (const auto &Feature : Features) { 1080 if (Feature == "+vsx") { 1081 HasVSX = true; 1082 } else if (Feature == "+bpermd") { 1083 HasBPERMD = true; 1084 } else if (Feature == "+extdiv") { 1085 HasExtDiv = true; 1086 } else if (Feature == "+power8-vector") { 1087 HasP8Vector = true; 1088 } else if (Feature == "+crypto") { 1089 HasP8Crypto = true; 1090 } else if (Feature == "+direct-move") { 1091 HasDirectMove = true; 1092 } else if (Feature == "+qpx") { 1093 HasQPX = true; 1094 } else if (Feature == "+htm") { 1095 HasHTM = true; 1096 } 1097 // TODO: Finish this list and add an assert that we've handled them 1098 // all. 1099 } 1100 1101 return true; 1102 } 1103 1104 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1105 /// #defines that are not tied to a specific subtarget. 1106 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1107 MacroBuilder &Builder) const { 1108 // Target identification. 1109 Builder.defineMacro("__ppc__"); 1110 Builder.defineMacro("__PPC__"); 1111 Builder.defineMacro("_ARCH_PPC"); 1112 Builder.defineMacro("__powerpc__"); 1113 Builder.defineMacro("__POWERPC__"); 1114 if (PointerWidth == 64) { 1115 Builder.defineMacro("_ARCH_PPC64"); 1116 Builder.defineMacro("__powerpc64__"); 1117 Builder.defineMacro("__ppc64__"); 1118 Builder.defineMacro("__PPC64__"); 1119 } 1120 1121 // Target properties. 1122 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1123 Builder.defineMacro("_LITTLE_ENDIAN"); 1124 } else { 1125 if (getTriple().getOS() != llvm::Triple::NetBSD && 1126 getTriple().getOS() != llvm::Triple::OpenBSD) 1127 Builder.defineMacro("_BIG_ENDIAN"); 1128 } 1129 1130 // ABI options. 1131 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1132 Builder.defineMacro("_CALL_ELF", "1"); 1133 if (ABI == "elfv2") 1134 Builder.defineMacro("_CALL_ELF", "2"); 1135 1136 // Subtarget options. 1137 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1138 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1139 1140 // FIXME: Should be controlled by command line option. 1141 if (LongDoubleWidth == 128) 1142 Builder.defineMacro("__LONG_DOUBLE_128__"); 1143 1144 if (Opts.AltiVec) { 1145 Builder.defineMacro("__VEC__", "10206"); 1146 Builder.defineMacro("__ALTIVEC__"); 1147 } 1148 1149 // CPU identification. 1150 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1151 .Case("440", ArchDefineName) 1152 .Case("450", ArchDefineName | ArchDefine440) 1153 .Case("601", ArchDefineName) 1154 .Case("602", ArchDefineName | ArchDefinePpcgr) 1155 .Case("603", ArchDefineName | ArchDefinePpcgr) 1156 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1157 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1158 .Case("604", ArchDefineName | ArchDefinePpcgr) 1159 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1160 .Case("620", ArchDefineName | ArchDefinePpcgr) 1161 .Case("630", ArchDefineName | ArchDefinePpcgr) 1162 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1163 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1164 .Case("750", ArchDefineName | ArchDefinePpcgr) 1165 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1166 | ArchDefinePpcsq) 1167 .Case("a2", ArchDefineA2) 1168 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1169 .Case("pwr3", ArchDefinePpcgr) 1170 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1171 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1174 | ArchDefinePpcgr | ArchDefinePpcsq) 1175 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1176 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1177 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1178 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1179 | ArchDefinePpcsq) 1180 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1181 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1182 | ArchDefinePpcgr | ArchDefinePpcsq) 1183 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1184 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1185 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1186 .Case("power3", ArchDefinePpcgr) 1187 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1188 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1189 | ArchDefinePpcsq) 1190 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1191 | ArchDefinePpcgr | ArchDefinePpcsq) 1192 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1193 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1194 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1195 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1196 | ArchDefinePpcsq) 1197 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1198 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1199 | ArchDefinePpcgr | ArchDefinePpcsq) 1200 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1201 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1202 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1203 .Default(ArchDefineNone); 1204 1205 if (defs & ArchDefineName) 1206 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1207 if (defs & ArchDefinePpcgr) 1208 Builder.defineMacro("_ARCH_PPCGR"); 1209 if (defs & ArchDefinePpcsq) 1210 Builder.defineMacro("_ARCH_PPCSQ"); 1211 if (defs & ArchDefine440) 1212 Builder.defineMacro("_ARCH_440"); 1213 if (defs & ArchDefine603) 1214 Builder.defineMacro("_ARCH_603"); 1215 if (defs & ArchDefine604) 1216 Builder.defineMacro("_ARCH_604"); 1217 if (defs & ArchDefinePwr4) 1218 Builder.defineMacro("_ARCH_PWR4"); 1219 if (defs & ArchDefinePwr5) 1220 Builder.defineMacro("_ARCH_PWR5"); 1221 if (defs & ArchDefinePwr5x) 1222 Builder.defineMacro("_ARCH_PWR5X"); 1223 if (defs & ArchDefinePwr6) 1224 Builder.defineMacro("_ARCH_PWR6"); 1225 if (defs & ArchDefinePwr6x) 1226 Builder.defineMacro("_ARCH_PWR6X"); 1227 if (defs & ArchDefinePwr7) 1228 Builder.defineMacro("_ARCH_PWR7"); 1229 if (defs & ArchDefinePwr8) 1230 Builder.defineMacro("_ARCH_PWR8"); 1231 if (defs & ArchDefineA2) 1232 Builder.defineMacro("_ARCH_A2"); 1233 if (defs & ArchDefineA2q) { 1234 Builder.defineMacro("_ARCH_A2Q"); 1235 Builder.defineMacro("_ARCH_QP"); 1236 } 1237 1238 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1239 Builder.defineMacro("__bg__"); 1240 Builder.defineMacro("__THW_BLUEGENE__"); 1241 Builder.defineMacro("__bgq__"); 1242 Builder.defineMacro("__TOS_BGQ__"); 1243 } 1244 1245 if (HasVSX) 1246 Builder.defineMacro("__VSX__"); 1247 if (HasP8Vector) 1248 Builder.defineMacro("__POWER8_VECTOR__"); 1249 if (HasP8Crypto) 1250 Builder.defineMacro("__CRYPTO__"); 1251 if (HasHTM) 1252 Builder.defineMacro("__HTM__"); 1253 1254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1257 if (PointerWidth == 64) 1258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1259 1260 // FIXME: The following are not yet generated here by Clang, but are 1261 // generated by GCC: 1262 // 1263 // _SOFT_FLOAT_ 1264 // __RECIP_PRECISION__ 1265 // __APPLE_ALTIVEC__ 1266 // __RECIP__ 1267 // __RECIPF__ 1268 // __RSQRTE__ 1269 // __RSQRTEF__ 1270 // _SOFT_DOUBLE_ 1271 // __NO_LWSYNC__ 1272 // __HAVE_BSWAP__ 1273 // __LONGDOUBLE128 1274 // __CMODEL_MEDIUM__ 1275 // __CMODEL_LARGE__ 1276 // _CALL_SYSV 1277 // _CALL_DARWIN 1278 // __NO_FPRS__ 1279 } 1280 1281 // Handle explicit options being passed to the compiler here: if we've 1282 // explicitly turned off vsx and turned on power8-vector or direct-move then 1283 // go ahead and error since the customer has expressed a somewhat incompatible 1284 // set of options. 1285 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1286 const std::vector<std::string> &FeaturesVec) { 1287 1288 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1289 FeaturesVec.end()) { 1290 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1291 FeaturesVec.end()) { 1292 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1293 << "-mno-vsx"; 1294 return false; 1295 } 1296 1297 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1298 FeaturesVec.end()) { 1299 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1300 << "-mno-vsx"; 1301 return false; 1302 } 1303 } 1304 1305 return true; 1306 } 1307 1308 bool PPCTargetInfo::initFeatureMap( 1309 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1310 const std::vector<std::string> &FeaturesVec) const { 1311 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1312 .Case("7400", true) 1313 .Case("g4", true) 1314 .Case("7450", true) 1315 .Case("g4+", true) 1316 .Case("970", true) 1317 .Case("g5", true) 1318 .Case("pwr6", true) 1319 .Case("pwr7", true) 1320 .Case("pwr8", true) 1321 .Case("ppc64", true) 1322 .Case("ppc64le", true) 1323 .Default(false); 1324 1325 Features["qpx"] = (CPU == "a2q"); 1326 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1327 .Case("ppc64le", true) 1328 .Case("pwr8", true) 1329 .Default(false); 1330 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1331 .Case("ppc64le", true) 1332 .Case("pwr8", true) 1333 .Default(false); 1334 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1335 .Case("ppc64le", true) 1336 .Case("pwr8", true) 1337 .Case("pwr7", true) 1338 .Default(false); 1339 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1340 .Case("ppc64le", true) 1341 .Case("pwr8", true) 1342 .Case("pwr7", true) 1343 .Default(false); 1344 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1345 .Case("ppc64le", true) 1346 .Case("pwr8", true) 1347 .Default(false); 1348 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1349 .Case("ppc64le", true) 1350 .Case("pwr8", true) 1351 .Case("pwr7", true) 1352 .Default(false); 1353 1354 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1355 return false; 1356 1357 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1358 } 1359 1360 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1361 return llvm::StringSwitch<bool>(Feature) 1362 .Case("powerpc", true) 1363 .Case("vsx", HasVSX) 1364 .Case("power8-vector", HasP8Vector) 1365 .Case("crypto", HasP8Crypto) 1366 .Case("direct-move", HasDirectMove) 1367 .Case("qpx", HasQPX) 1368 .Case("htm", HasHTM) 1369 .Case("bpermd", HasBPERMD) 1370 .Case("extdiv", HasExtDiv) 1371 .Default(false); 1372 } 1373 1374 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1375 StringRef Name, bool Enabled) const { 1376 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1377 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1378 // incompatible options. 1379 if (Enabled) { 1380 if (Name == "vsx") { 1381 Features[Name] = true; 1382 } else if (Name == "direct-move") { 1383 Features[Name] = Features["vsx"] = true; 1384 } else if (Name == "power8-vector") { 1385 Features[Name] = Features["vsx"] = true; 1386 } else { 1387 Features[Name] = true; 1388 } 1389 } else { 1390 if (Name == "vsx") { 1391 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1392 false; 1393 } else { 1394 Features[Name] = false; 1395 } 1396 } 1397 } 1398 1399 const char * const PPCTargetInfo::GCCRegNames[] = { 1400 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1401 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1402 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1403 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1408 "mq", "lr", "ctr", "ap", 1409 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1410 "xer", 1411 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1412 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1413 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1414 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1415 "vrsave", "vscr", 1416 "spe_acc", "spefscr", 1417 "sfp" 1418 }; 1419 1420 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1421 return llvm::makeArrayRef(GCCRegNames); 1422 } 1423 1424 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1425 // While some of these aliases do map to different registers 1426 // they still share the same register name. 1427 { { "0" }, "r0" }, 1428 { { "1"}, "r1" }, 1429 { { "2" }, "r2" }, 1430 { { "3" }, "r3" }, 1431 { { "4" }, "r4" }, 1432 { { "5" }, "r5" }, 1433 { { "6" }, "r6" }, 1434 { { "7" }, "r7" }, 1435 { { "8" }, "r8" }, 1436 { { "9" }, "r9" }, 1437 { { "10" }, "r10" }, 1438 { { "11" }, "r11" }, 1439 { { "12" }, "r12" }, 1440 { { "13" }, "r13" }, 1441 { { "14" }, "r14" }, 1442 { { "15" }, "r15" }, 1443 { { "16" }, "r16" }, 1444 { { "17" }, "r17" }, 1445 { { "18" }, "r18" }, 1446 { { "19" }, "r19" }, 1447 { { "20" }, "r20" }, 1448 { { "21" }, "r21" }, 1449 { { "22" }, "r22" }, 1450 { { "23" }, "r23" }, 1451 { { "24" }, "r24" }, 1452 { { "25" }, "r25" }, 1453 { { "26" }, "r26" }, 1454 { { "27" }, "r27" }, 1455 { { "28" }, "r28" }, 1456 { { "29" }, "r29" }, 1457 { { "30" }, "r30" }, 1458 { { "31" }, "r31" }, 1459 { { "fr0" }, "f0" }, 1460 { { "fr1" }, "f1" }, 1461 { { "fr2" }, "f2" }, 1462 { { "fr3" }, "f3" }, 1463 { { "fr4" }, "f4" }, 1464 { { "fr5" }, "f5" }, 1465 { { "fr6" }, "f6" }, 1466 { { "fr7" }, "f7" }, 1467 { { "fr8" }, "f8" }, 1468 { { "fr9" }, "f9" }, 1469 { { "fr10" }, "f10" }, 1470 { { "fr11" }, "f11" }, 1471 { { "fr12" }, "f12" }, 1472 { { "fr13" }, "f13" }, 1473 { { "fr14" }, "f14" }, 1474 { { "fr15" }, "f15" }, 1475 { { "fr16" }, "f16" }, 1476 { { "fr17" }, "f17" }, 1477 { { "fr18" }, "f18" }, 1478 { { "fr19" }, "f19" }, 1479 { { "fr20" }, "f20" }, 1480 { { "fr21" }, "f21" }, 1481 { { "fr22" }, "f22" }, 1482 { { "fr23" }, "f23" }, 1483 { { "fr24" }, "f24" }, 1484 { { "fr25" }, "f25" }, 1485 { { "fr26" }, "f26" }, 1486 { { "fr27" }, "f27" }, 1487 { { "fr28" }, "f28" }, 1488 { { "fr29" }, "f29" }, 1489 { { "fr30" }, "f30" }, 1490 { { "fr31" }, "f31" }, 1491 { { "cc" }, "cr0" }, 1492 }; 1493 1494 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1495 return llvm::makeArrayRef(GCCRegAliases); 1496 } 1497 1498 class PPC32TargetInfo : public PPCTargetInfo { 1499 public: 1500 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1501 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1502 1503 switch (getTriple().getOS()) { 1504 case llvm::Triple::Linux: 1505 case llvm::Triple::FreeBSD: 1506 case llvm::Triple::NetBSD: 1507 SizeType = UnsignedInt; 1508 PtrDiffType = SignedInt; 1509 IntPtrType = SignedInt; 1510 break; 1511 default: 1512 break; 1513 } 1514 1515 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1516 LongDoubleWidth = LongDoubleAlign = 64; 1517 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1518 } 1519 1520 // PPC32 supports atomics up to 4 bytes. 1521 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1522 } 1523 1524 BuiltinVaListKind getBuiltinVaListKind() const override { 1525 // This is the ELF definition, and is overridden by the Darwin sub-target 1526 return TargetInfo::PowerABIBuiltinVaList; 1527 } 1528 }; 1529 1530 // Note: ABI differences may eventually require us to have a separate 1531 // TargetInfo for little endian. 1532 class PPC64TargetInfo : public PPCTargetInfo { 1533 public: 1534 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1535 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1536 IntMaxType = SignedLong; 1537 Int64Type = SignedLong; 1538 1539 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1540 DataLayoutString = "e-m:e-i64:64-n32:64"; 1541 ABI = "elfv2"; 1542 } else { 1543 DataLayoutString = "E-m:e-i64:64-n32:64"; 1544 ABI = "elfv1"; 1545 } 1546 1547 switch (getTriple().getOS()) { 1548 case llvm::Triple::FreeBSD: 1549 LongDoubleWidth = LongDoubleAlign = 64; 1550 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1551 break; 1552 case llvm::Triple::NetBSD: 1553 IntMaxType = SignedLongLong; 1554 Int64Type = SignedLongLong; 1555 break; 1556 default: 1557 break; 1558 } 1559 1560 // PPC64 supports atomics up to 8 bytes. 1561 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1562 } 1563 BuiltinVaListKind getBuiltinVaListKind() const override { 1564 return TargetInfo::CharPtrBuiltinVaList; 1565 } 1566 // PPC64 Linux-specific ABI options. 1567 bool setABI(const std::string &Name) override { 1568 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1569 ABI = Name; 1570 return true; 1571 } 1572 return false; 1573 } 1574 }; 1575 1576 class DarwinPPC32TargetInfo : 1577 public DarwinTargetInfo<PPC32TargetInfo> { 1578 public: 1579 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1580 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1581 HasAlignMac68kSupport = true; 1582 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1583 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1584 LongLongAlign = 32; 1585 SuitableAlign = 128; 1586 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1587 } 1588 BuiltinVaListKind getBuiltinVaListKind() const override { 1589 return TargetInfo::CharPtrBuiltinVaList; 1590 } 1591 }; 1592 1593 class DarwinPPC64TargetInfo : 1594 public DarwinTargetInfo<PPC64TargetInfo> { 1595 public: 1596 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1597 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1598 HasAlignMac68kSupport = true; 1599 SuitableAlign = 128; 1600 DataLayoutString = "E-m:o-i64:64-n32:64"; 1601 } 1602 }; 1603 1604 static const unsigned NVPTXAddrSpaceMap[] = { 1605 1, // opencl_global 1606 3, // opencl_local 1607 4, // opencl_constant 1608 // FIXME: generic has to be added to the target 1609 0, // opencl_generic 1610 1, // cuda_device 1611 4, // cuda_constant 1612 3, // cuda_shared 1613 }; 1614 1615 class NVPTXTargetInfo : public TargetInfo { 1616 static const char *const GCCRegNames[]; 1617 static const Builtin::Info BuiltinInfo[]; 1618 1619 // The GPU profiles supported by the NVPTX backend 1620 enum GPUKind { 1621 GK_NONE, 1622 GK_SM20, 1623 GK_SM21, 1624 GK_SM30, 1625 GK_SM35, 1626 GK_SM37, 1627 } GPU; 1628 1629 public: 1630 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1631 BigEndian = false; 1632 TLSSupported = false; 1633 LongWidth = LongAlign = 64; 1634 AddrSpaceMap = &NVPTXAddrSpaceMap; 1635 UseAddrSpaceMapMangling = true; 1636 // Define available target features 1637 // These must be defined in sorted order! 1638 NoAsmVariants = true; 1639 // Set the default GPU to sm20 1640 GPU = GK_SM20; 1641 } 1642 void getTargetDefines(const LangOptions &Opts, 1643 MacroBuilder &Builder) const override { 1644 Builder.defineMacro("__PTX__"); 1645 Builder.defineMacro("__NVPTX__"); 1646 if (Opts.CUDAIsDevice) { 1647 // Set __CUDA_ARCH__ for the GPU specified. 1648 std::string CUDAArchCode; 1649 switch (GPU) { 1650 case GK_SM20: 1651 CUDAArchCode = "200"; 1652 break; 1653 case GK_SM21: 1654 CUDAArchCode = "210"; 1655 break; 1656 case GK_SM30: 1657 CUDAArchCode = "300"; 1658 break; 1659 case GK_SM35: 1660 CUDAArchCode = "350"; 1661 break; 1662 case GK_SM37: 1663 CUDAArchCode = "370"; 1664 break; 1665 default: 1666 llvm_unreachable("Unhandled target CPU"); 1667 } 1668 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1669 } 1670 } 1671 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1672 return llvm::makeArrayRef(BuiltinInfo, 1673 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1674 } 1675 bool hasFeature(StringRef Feature) const override { 1676 return Feature == "ptx" || Feature == "nvptx"; 1677 } 1678 1679 ArrayRef<const char *> getGCCRegNames() const override; 1680 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1681 // No aliases. 1682 return None; 1683 } 1684 bool validateAsmConstraint(const char *&Name, 1685 TargetInfo::ConstraintInfo &Info) const override { 1686 switch (*Name) { 1687 default: 1688 return false; 1689 case 'c': 1690 case 'h': 1691 case 'r': 1692 case 'l': 1693 case 'f': 1694 case 'd': 1695 Info.setAllowsRegister(); 1696 return true; 1697 } 1698 } 1699 const char *getClobbers() const override { 1700 // FIXME: Is this really right? 1701 return ""; 1702 } 1703 BuiltinVaListKind getBuiltinVaListKind() const override { 1704 // FIXME: implement 1705 return TargetInfo::CharPtrBuiltinVaList; 1706 } 1707 bool setCPU(const std::string &Name) override { 1708 GPU = llvm::StringSwitch<GPUKind>(Name) 1709 .Case("sm_20", GK_SM20) 1710 .Case("sm_21", GK_SM21) 1711 .Case("sm_30", GK_SM30) 1712 .Case("sm_35", GK_SM35) 1713 .Case("sm_37", GK_SM37) 1714 .Default(GK_NONE); 1715 1716 return GPU != GK_NONE; 1717 } 1718 }; 1719 1720 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1721 #define BUILTIN(ID, TYPE, ATTRS) \ 1722 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1723 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1724 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1725 #include "clang/Basic/BuiltinsNVPTX.def" 1726 }; 1727 1728 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1729 1730 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1731 return llvm::makeArrayRef(GCCRegNames); 1732 } 1733 1734 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1735 public: 1736 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1737 LongWidth = LongAlign = 32; 1738 PointerWidth = PointerAlign = 32; 1739 SizeType = TargetInfo::UnsignedInt; 1740 PtrDiffType = TargetInfo::SignedInt; 1741 IntPtrType = TargetInfo::SignedInt; 1742 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1743 } 1744 }; 1745 1746 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1747 public: 1748 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1749 PointerWidth = PointerAlign = 64; 1750 SizeType = TargetInfo::UnsignedLong; 1751 PtrDiffType = TargetInfo::SignedLong; 1752 IntPtrType = TargetInfo::SignedLong; 1753 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1754 } 1755 }; 1756 1757 static const unsigned AMDGPUAddrSpaceMap[] = { 1758 1, // opencl_global 1759 3, // opencl_local 1760 2, // opencl_constant 1761 4, // opencl_generic 1762 1, // cuda_device 1763 2, // cuda_constant 1764 3 // cuda_shared 1765 }; 1766 1767 // If you edit the description strings, make sure you update 1768 // getPointerWidthV(). 1769 1770 static const char *const DataLayoutStringR600 = 1771 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1772 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1773 1774 static const char *const DataLayoutStringR600DoubleOps = 1775 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1776 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1777 1778 static const char *const DataLayoutStringSI = 1779 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1780 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1781 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1782 1783 class AMDGPUTargetInfo : public TargetInfo { 1784 static const Builtin::Info BuiltinInfo[]; 1785 static const char * const GCCRegNames[]; 1786 1787 /// \brief The GPU profiles supported by the AMDGPU target. 1788 enum GPUKind { 1789 GK_NONE, 1790 GK_R600, 1791 GK_R600_DOUBLE_OPS, 1792 GK_R700, 1793 GK_R700_DOUBLE_OPS, 1794 GK_EVERGREEN, 1795 GK_EVERGREEN_DOUBLE_OPS, 1796 GK_NORTHERN_ISLANDS, 1797 GK_CAYMAN, 1798 GK_SOUTHERN_ISLANDS, 1799 GK_SEA_ISLANDS, 1800 GK_VOLCANIC_ISLANDS 1801 } GPU; 1802 1803 bool hasFP64:1; 1804 bool hasFMAF:1; 1805 bool hasLDEXPF:1; 1806 1807 public: 1808 AMDGPUTargetInfo(const llvm::Triple &Triple) 1809 : TargetInfo(Triple) { 1810 1811 if (Triple.getArch() == llvm::Triple::amdgcn) { 1812 DataLayoutString = DataLayoutStringSI; 1813 GPU = GK_SOUTHERN_ISLANDS; 1814 hasFP64 = true; 1815 hasFMAF = true; 1816 hasLDEXPF = true; 1817 } else { 1818 DataLayoutString = DataLayoutStringR600; 1819 GPU = GK_R600; 1820 hasFP64 = false; 1821 hasFMAF = false; 1822 hasLDEXPF = false; 1823 } 1824 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1825 UseAddrSpaceMapMangling = true; 1826 } 1827 1828 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1829 if (GPU <= GK_CAYMAN) 1830 return 32; 1831 1832 switch(AddrSpace) { 1833 default: 1834 return 64; 1835 case 0: 1836 case 3: 1837 case 5: 1838 return 32; 1839 } 1840 } 1841 1842 const char * getClobbers() const override { 1843 return ""; 1844 } 1845 1846 ArrayRef<const char *> getGCCRegNames() const override; 1847 1848 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1849 return None; 1850 } 1851 1852 bool validateAsmConstraint(const char *&Name, 1853 TargetInfo::ConstraintInfo &Info) const override { 1854 switch (*Name) { 1855 default: break; 1856 case 'v': // vgpr 1857 case 's': // sgpr 1858 Info.setAllowsRegister(); 1859 return true; 1860 } 1861 return false; 1862 } 1863 1864 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1865 return llvm::makeArrayRef(BuiltinInfo, 1866 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1867 } 1868 1869 void getTargetDefines(const LangOptions &Opts, 1870 MacroBuilder &Builder) const override { 1871 Builder.defineMacro("__R600__"); 1872 if (hasFMAF) 1873 Builder.defineMacro("__HAS_FMAF__"); 1874 if (hasLDEXPF) 1875 Builder.defineMacro("__HAS_LDEXPF__"); 1876 if (hasFP64 && Opts.OpenCL) 1877 Builder.defineMacro("cl_khr_fp64"); 1878 if (Opts.OpenCL) { 1879 if (GPU >= GK_NORTHERN_ISLANDS) { 1880 Builder.defineMacro("cl_khr_byte_addressable_store"); 1881 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1882 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1883 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1884 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1885 } 1886 } 1887 } 1888 1889 BuiltinVaListKind getBuiltinVaListKind() const override { 1890 return TargetInfo::CharPtrBuiltinVaList; 1891 } 1892 1893 bool setCPU(const std::string &Name) override { 1894 GPU = llvm::StringSwitch<GPUKind>(Name) 1895 .Case("r600" , GK_R600) 1896 .Case("rv610", GK_R600) 1897 .Case("rv620", GK_R600) 1898 .Case("rv630", GK_R600) 1899 .Case("rv635", GK_R600) 1900 .Case("rs780", GK_R600) 1901 .Case("rs880", GK_R600) 1902 .Case("rv670", GK_R600_DOUBLE_OPS) 1903 .Case("rv710", GK_R700) 1904 .Case("rv730", GK_R700) 1905 .Case("rv740", GK_R700_DOUBLE_OPS) 1906 .Case("rv770", GK_R700_DOUBLE_OPS) 1907 .Case("palm", GK_EVERGREEN) 1908 .Case("cedar", GK_EVERGREEN) 1909 .Case("sumo", GK_EVERGREEN) 1910 .Case("sumo2", GK_EVERGREEN) 1911 .Case("redwood", GK_EVERGREEN) 1912 .Case("juniper", GK_EVERGREEN) 1913 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1914 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1915 .Case("barts", GK_NORTHERN_ISLANDS) 1916 .Case("turks", GK_NORTHERN_ISLANDS) 1917 .Case("caicos", GK_NORTHERN_ISLANDS) 1918 .Case("cayman", GK_CAYMAN) 1919 .Case("aruba", GK_CAYMAN) 1920 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1921 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1922 .Case("verde", GK_SOUTHERN_ISLANDS) 1923 .Case("oland", GK_SOUTHERN_ISLANDS) 1924 .Case("hainan", GK_SOUTHERN_ISLANDS) 1925 .Case("bonaire", GK_SEA_ISLANDS) 1926 .Case("kabini", GK_SEA_ISLANDS) 1927 .Case("kaveri", GK_SEA_ISLANDS) 1928 .Case("hawaii", GK_SEA_ISLANDS) 1929 .Case("mullins", GK_SEA_ISLANDS) 1930 .Case("tonga", GK_VOLCANIC_ISLANDS) 1931 .Case("iceland", GK_VOLCANIC_ISLANDS) 1932 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1933 .Default(GK_NONE); 1934 1935 if (GPU == GK_NONE) { 1936 return false; 1937 } 1938 1939 // Set the correct data layout 1940 switch (GPU) { 1941 case GK_NONE: 1942 case GK_R600: 1943 case GK_R700: 1944 case GK_EVERGREEN: 1945 case GK_NORTHERN_ISLANDS: 1946 DataLayoutString = DataLayoutStringR600; 1947 hasFP64 = false; 1948 hasFMAF = false; 1949 hasLDEXPF = false; 1950 break; 1951 case GK_R600_DOUBLE_OPS: 1952 case GK_R700_DOUBLE_OPS: 1953 case GK_EVERGREEN_DOUBLE_OPS: 1954 case GK_CAYMAN: 1955 DataLayoutString = DataLayoutStringR600DoubleOps; 1956 hasFP64 = true; 1957 hasFMAF = true; 1958 hasLDEXPF = false; 1959 break; 1960 case GK_SOUTHERN_ISLANDS: 1961 case GK_SEA_ISLANDS: 1962 case GK_VOLCANIC_ISLANDS: 1963 DataLayoutString = DataLayoutStringSI; 1964 hasFP64 = true; 1965 hasFMAF = true; 1966 hasLDEXPF = true; 1967 break; 1968 } 1969 1970 return true; 1971 } 1972 }; 1973 1974 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1975 #define BUILTIN(ID, TYPE, ATTRS) \ 1976 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1977 #include "clang/Basic/BuiltinsAMDGPU.def" 1978 }; 1979 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1980 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1981 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1982 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1983 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1984 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1985 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1986 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1987 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1988 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1989 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1990 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1991 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1992 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1993 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1994 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1995 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1996 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1997 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1998 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1999 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2000 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2001 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2002 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2003 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2004 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2005 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2006 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2007 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2008 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2009 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2010 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2011 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2012 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2013 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2014 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2015 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2016 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2017 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2018 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2019 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2020 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2021 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2022 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2023 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2024 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2025 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2026 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2027 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2028 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2029 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2030 }; 2031 2032 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2033 return llvm::makeArrayRef(GCCRegNames); 2034 } 2035 2036 // Namespace for x86 abstract base class 2037 const Builtin::Info BuiltinInfo[] = { 2038 #define BUILTIN(ID, TYPE, ATTRS) \ 2039 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2040 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2041 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2042 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2043 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2044 #include "clang/Basic/BuiltinsX86.def" 2045 }; 2046 2047 static const char* const GCCRegNames[] = { 2048 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2049 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2050 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2051 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2052 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2053 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2054 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2055 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2056 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2057 }; 2058 2059 const TargetInfo::AddlRegName AddlRegNames[] = { 2060 { { "al", "ah", "eax", "rax" }, 0 }, 2061 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2062 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2063 { { "dl", "dh", "edx", "rdx" }, 1 }, 2064 { { "esi", "rsi" }, 4 }, 2065 { { "edi", "rdi" }, 5 }, 2066 { { "esp", "rsp" }, 7 }, 2067 { { "ebp", "rbp" }, 6 }, 2068 { { "r8d", "r8w", "r8b" }, 38 }, 2069 { { "r9d", "r9w", "r9b" }, 39 }, 2070 { { "r10d", "r10w", "r10b" }, 40 }, 2071 { { "r11d", "r11w", "r11b" }, 41 }, 2072 { { "r12d", "r12w", "r12b" }, 42 }, 2073 { { "r13d", "r13w", "r13b" }, 43 }, 2074 { { "r14d", "r14w", "r14b" }, 44 }, 2075 { { "r15d", "r15w", "r15b" }, 45 }, 2076 }; 2077 2078 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2079 // most of the implementation can be shared. 2080 class X86TargetInfo : public TargetInfo { 2081 enum X86SSEEnum { 2082 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2083 } SSELevel = NoSSE; 2084 enum MMX3DNowEnum { 2085 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2086 } MMX3DNowLevel = NoMMX3DNow; 2087 enum XOPEnum { 2088 NoXOP, 2089 SSE4A, 2090 FMA4, 2091 XOP 2092 } XOPLevel = NoXOP; 2093 2094 bool HasAES = false; 2095 bool HasPCLMUL = false; 2096 bool HasLZCNT = false; 2097 bool HasRDRND = false; 2098 bool HasFSGSBASE = false; 2099 bool HasBMI = false; 2100 bool HasBMI2 = false; 2101 bool HasPOPCNT = false; 2102 bool HasRTM = false; 2103 bool HasPRFCHW = false; 2104 bool HasRDSEED = false; 2105 bool HasADX = false; 2106 bool HasTBM = false; 2107 bool HasFMA = false; 2108 bool HasF16C = false; 2109 bool HasAVX512CD = false; 2110 bool HasAVX512ER = false; 2111 bool HasAVX512PF = false; 2112 bool HasAVX512DQ = false; 2113 bool HasAVX512BW = false; 2114 bool HasAVX512VL = false; 2115 bool HasSHA = false; 2116 bool HasCX16 = false; 2117 bool HasFXSR = false; 2118 bool HasXSAVE = false; 2119 bool HasXSAVEOPT = false; 2120 bool HasXSAVEC = false; 2121 bool HasXSAVES = false; 2122 bool HasPKU = false; 2123 2124 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2125 /// 2126 /// Each enumeration represents a particular CPU supported by Clang. These 2127 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2128 enum CPUKind { 2129 CK_Generic, 2130 2131 /// \name i386 2132 /// i386-generation processors. 2133 //@{ 2134 CK_i386, 2135 //@} 2136 2137 /// \name i486 2138 /// i486-generation processors. 2139 //@{ 2140 CK_i486, 2141 CK_WinChipC6, 2142 CK_WinChip2, 2143 CK_C3, 2144 //@} 2145 2146 /// \name i586 2147 /// i586-generation processors, P5 microarchitecture based. 2148 //@{ 2149 CK_i586, 2150 CK_Pentium, 2151 CK_PentiumMMX, 2152 //@} 2153 2154 /// \name i686 2155 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2156 //@{ 2157 CK_i686, 2158 CK_PentiumPro, 2159 CK_Pentium2, 2160 CK_Pentium3, 2161 CK_Pentium3M, 2162 CK_PentiumM, 2163 CK_C3_2, 2164 2165 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2166 /// Clang however has some logic to suport this. 2167 // FIXME: Warn, deprecate, and potentially remove this. 2168 CK_Yonah, 2169 //@} 2170 2171 /// \name Netburst 2172 /// Netburst microarchitecture based processors. 2173 //@{ 2174 CK_Pentium4, 2175 CK_Pentium4M, 2176 CK_Prescott, 2177 CK_Nocona, 2178 //@} 2179 2180 /// \name Core 2181 /// Core microarchitecture based processors. 2182 //@{ 2183 CK_Core2, 2184 2185 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2186 /// codename which GCC no longer accepts as an option to -march, but Clang 2187 /// has some logic for recognizing it. 2188 // FIXME: Warn, deprecate, and potentially remove this. 2189 CK_Penryn, 2190 //@} 2191 2192 /// \name Atom 2193 /// Atom processors 2194 //@{ 2195 CK_Bonnell, 2196 CK_Silvermont, 2197 //@} 2198 2199 /// \name Nehalem 2200 /// Nehalem microarchitecture based processors. 2201 CK_Nehalem, 2202 2203 /// \name Westmere 2204 /// Westmere microarchitecture based processors. 2205 CK_Westmere, 2206 2207 /// \name Sandy Bridge 2208 /// Sandy Bridge microarchitecture based processors. 2209 CK_SandyBridge, 2210 2211 /// \name Ivy Bridge 2212 /// Ivy Bridge microarchitecture based processors. 2213 CK_IvyBridge, 2214 2215 /// \name Haswell 2216 /// Haswell microarchitecture based processors. 2217 CK_Haswell, 2218 2219 /// \name Broadwell 2220 /// Broadwell microarchitecture based processors. 2221 CK_Broadwell, 2222 2223 /// \name Skylake 2224 /// Skylake microarchitecture based processors. 2225 CK_Skylake, 2226 2227 /// \name Knights Landing 2228 /// Knights Landing processor. 2229 CK_KNL, 2230 2231 /// \name K6 2232 /// K6 architecture processors. 2233 //@{ 2234 CK_K6, 2235 CK_K6_2, 2236 CK_K6_3, 2237 //@} 2238 2239 /// \name K7 2240 /// K7 architecture processors. 2241 //@{ 2242 CK_Athlon, 2243 CK_AthlonThunderbird, 2244 CK_Athlon4, 2245 CK_AthlonXP, 2246 CK_AthlonMP, 2247 //@} 2248 2249 /// \name K8 2250 /// K8 architecture processors. 2251 //@{ 2252 CK_Athlon64, 2253 CK_Athlon64SSE3, 2254 CK_AthlonFX, 2255 CK_K8, 2256 CK_K8SSE3, 2257 CK_Opteron, 2258 CK_OpteronSSE3, 2259 CK_AMDFAM10, 2260 //@} 2261 2262 /// \name Bobcat 2263 /// Bobcat architecture processors. 2264 //@{ 2265 CK_BTVER1, 2266 CK_BTVER2, 2267 //@} 2268 2269 /// \name Bulldozer 2270 /// Bulldozer architecture processors. 2271 //@{ 2272 CK_BDVER1, 2273 CK_BDVER2, 2274 CK_BDVER3, 2275 CK_BDVER4, 2276 //@} 2277 2278 /// This specification is deprecated and will be removed in the future. 2279 /// Users should prefer \see CK_K8. 2280 // FIXME: Warn on this when the CPU is set to it. 2281 //@{ 2282 CK_x86_64, 2283 //@} 2284 2285 /// \name Geode 2286 /// Geode processors. 2287 //@{ 2288 CK_Geode 2289 //@} 2290 } CPU = CK_Generic; 2291 2292 CPUKind getCPUKind(StringRef CPU) const { 2293 return llvm::StringSwitch<CPUKind>(CPU) 2294 .Case("i386", CK_i386) 2295 .Case("i486", CK_i486) 2296 .Case("winchip-c6", CK_WinChipC6) 2297 .Case("winchip2", CK_WinChip2) 2298 .Case("c3", CK_C3) 2299 .Case("i586", CK_i586) 2300 .Case("pentium", CK_Pentium) 2301 .Case("pentium-mmx", CK_PentiumMMX) 2302 .Case("i686", CK_i686) 2303 .Case("pentiumpro", CK_PentiumPro) 2304 .Case("pentium2", CK_Pentium2) 2305 .Case("pentium3", CK_Pentium3) 2306 .Case("pentium3m", CK_Pentium3M) 2307 .Case("pentium-m", CK_PentiumM) 2308 .Case("c3-2", CK_C3_2) 2309 .Case("yonah", CK_Yonah) 2310 .Case("pentium4", CK_Pentium4) 2311 .Case("pentium4m", CK_Pentium4M) 2312 .Case("prescott", CK_Prescott) 2313 .Case("nocona", CK_Nocona) 2314 .Case("core2", CK_Core2) 2315 .Case("penryn", CK_Penryn) 2316 .Case("bonnell", CK_Bonnell) 2317 .Case("atom", CK_Bonnell) // Legacy name. 2318 .Case("silvermont", CK_Silvermont) 2319 .Case("slm", CK_Silvermont) // Legacy name. 2320 .Case("nehalem", CK_Nehalem) 2321 .Case("corei7", CK_Nehalem) // Legacy name. 2322 .Case("westmere", CK_Westmere) 2323 .Case("sandybridge", CK_SandyBridge) 2324 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2325 .Case("ivybridge", CK_IvyBridge) 2326 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2327 .Case("haswell", CK_Haswell) 2328 .Case("core-avx2", CK_Haswell) // Legacy name. 2329 .Case("broadwell", CK_Broadwell) 2330 .Case("skylake", CK_Skylake) 2331 .Case("skx", CK_Skylake) // Legacy name. 2332 .Case("knl", CK_KNL) 2333 .Case("k6", CK_K6) 2334 .Case("k6-2", CK_K6_2) 2335 .Case("k6-3", CK_K6_3) 2336 .Case("athlon", CK_Athlon) 2337 .Case("athlon-tbird", CK_AthlonThunderbird) 2338 .Case("athlon-4", CK_Athlon4) 2339 .Case("athlon-xp", CK_AthlonXP) 2340 .Case("athlon-mp", CK_AthlonMP) 2341 .Case("athlon64", CK_Athlon64) 2342 .Case("athlon64-sse3", CK_Athlon64SSE3) 2343 .Case("athlon-fx", CK_AthlonFX) 2344 .Case("k8", CK_K8) 2345 .Case("k8-sse3", CK_K8SSE3) 2346 .Case("opteron", CK_Opteron) 2347 .Case("opteron-sse3", CK_OpteronSSE3) 2348 .Case("barcelona", CK_AMDFAM10) 2349 .Case("amdfam10", CK_AMDFAM10) 2350 .Case("btver1", CK_BTVER1) 2351 .Case("btver2", CK_BTVER2) 2352 .Case("bdver1", CK_BDVER1) 2353 .Case("bdver2", CK_BDVER2) 2354 .Case("bdver3", CK_BDVER3) 2355 .Case("bdver4", CK_BDVER4) 2356 .Case("x86-64", CK_x86_64) 2357 .Case("geode", CK_Geode) 2358 .Default(CK_Generic); 2359 } 2360 2361 enum FPMathKind { 2362 FP_Default, 2363 FP_SSE, 2364 FP_387 2365 } FPMath = FP_Default; 2366 2367 public: 2368 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2369 BigEndian = false; 2370 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2371 } 2372 unsigned getFloatEvalMethod() const override { 2373 // X87 evaluates with 80 bits "long double" precision. 2374 return SSELevel == NoSSE ? 2 : 0; 2375 } 2376 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2377 return llvm::makeArrayRef(BuiltinInfo, 2378 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2379 } 2380 ArrayRef<const char *> getGCCRegNames() const override { 2381 return llvm::makeArrayRef(GCCRegNames); 2382 } 2383 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2384 return None; 2385 } 2386 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2387 return llvm::makeArrayRef(AddlRegNames); 2388 } 2389 bool validateCpuSupports(StringRef Name) const override; 2390 bool validateAsmConstraint(const char *&Name, 2391 TargetInfo::ConstraintInfo &info) const override; 2392 2393 bool validateGlobalRegisterVariable(StringRef RegName, 2394 unsigned RegSize, 2395 bool &HasSizeMismatch) const override { 2396 // esp and ebp are the only 32-bit registers the x86 backend can currently 2397 // handle. 2398 if (RegName.equals("esp") || RegName.equals("ebp")) { 2399 // Check that the register size is 32-bit. 2400 HasSizeMismatch = RegSize != 32; 2401 return true; 2402 } 2403 2404 return false; 2405 } 2406 2407 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2408 2409 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2410 2411 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2412 2413 std::string convertConstraint(const char *&Constraint) const override; 2414 const char *getClobbers() const override { 2415 return "~{dirflag},~{fpsr},~{flags}"; 2416 } 2417 void getTargetDefines(const LangOptions &Opts, 2418 MacroBuilder &Builder) const override; 2419 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2420 bool Enabled); 2421 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2422 bool Enabled); 2423 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2424 bool Enabled); 2425 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2426 StringRef Name, bool Enabled) const override { 2427 setFeatureEnabledImpl(Features, Name, Enabled); 2428 } 2429 // This exists purely to cut down on the number of virtual calls in 2430 // initFeatureMap which calls this repeatedly. 2431 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2432 StringRef Name, bool Enabled); 2433 bool 2434 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2435 StringRef CPU, 2436 const std::vector<std::string> &FeaturesVec) const override; 2437 bool hasFeature(StringRef Feature) const override; 2438 bool handleTargetFeatures(std::vector<std::string> &Features, 2439 DiagnosticsEngine &Diags) override; 2440 StringRef getABI() const override { 2441 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2442 return "avx512"; 2443 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2444 return "avx"; 2445 if (getTriple().getArch() == llvm::Triple::x86 && 2446 MMX3DNowLevel == NoMMX3DNow) 2447 return "no-mmx"; 2448 return ""; 2449 } 2450 bool setCPU(const std::string &Name) override { 2451 CPU = getCPUKind(Name); 2452 2453 // Perform any per-CPU checks necessary to determine if this CPU is 2454 // acceptable. 2455 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2456 // invalid without explaining *why*. 2457 switch (CPU) { 2458 case CK_Generic: 2459 // No processor selected! 2460 return false; 2461 2462 case CK_i386: 2463 case CK_i486: 2464 case CK_WinChipC6: 2465 case CK_WinChip2: 2466 case CK_C3: 2467 case CK_i586: 2468 case CK_Pentium: 2469 case CK_PentiumMMX: 2470 case CK_i686: 2471 case CK_PentiumPro: 2472 case CK_Pentium2: 2473 case CK_Pentium3: 2474 case CK_Pentium3M: 2475 case CK_PentiumM: 2476 case CK_Yonah: 2477 case CK_C3_2: 2478 case CK_Pentium4: 2479 case CK_Pentium4M: 2480 case CK_Prescott: 2481 case CK_K6: 2482 case CK_K6_2: 2483 case CK_K6_3: 2484 case CK_Athlon: 2485 case CK_AthlonThunderbird: 2486 case CK_Athlon4: 2487 case CK_AthlonXP: 2488 case CK_AthlonMP: 2489 case CK_Geode: 2490 // Only accept certain architectures when compiling in 32-bit mode. 2491 if (getTriple().getArch() != llvm::Triple::x86) 2492 return false; 2493 2494 // Fallthrough 2495 case CK_Nocona: 2496 case CK_Core2: 2497 case CK_Penryn: 2498 case CK_Bonnell: 2499 case CK_Silvermont: 2500 case CK_Nehalem: 2501 case CK_Westmere: 2502 case CK_SandyBridge: 2503 case CK_IvyBridge: 2504 case CK_Haswell: 2505 case CK_Broadwell: 2506 case CK_Skylake: 2507 case CK_KNL: 2508 case CK_Athlon64: 2509 case CK_Athlon64SSE3: 2510 case CK_AthlonFX: 2511 case CK_K8: 2512 case CK_K8SSE3: 2513 case CK_Opteron: 2514 case CK_OpteronSSE3: 2515 case CK_AMDFAM10: 2516 case CK_BTVER1: 2517 case CK_BTVER2: 2518 case CK_BDVER1: 2519 case CK_BDVER2: 2520 case CK_BDVER3: 2521 case CK_BDVER4: 2522 case CK_x86_64: 2523 return true; 2524 } 2525 llvm_unreachable("Unhandled CPU kind"); 2526 } 2527 2528 bool setFPMath(StringRef Name) override; 2529 2530 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2531 // We accept all non-ARM calling conventions 2532 return (CC == CC_X86ThisCall || 2533 CC == CC_X86FastCall || 2534 CC == CC_X86StdCall || 2535 CC == CC_X86VectorCall || 2536 CC == CC_C || 2537 CC == CC_X86Pascal || 2538 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2539 } 2540 2541 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2542 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2543 } 2544 2545 bool hasSjLjLowering() const override { 2546 return true; 2547 } 2548 }; 2549 2550 bool X86TargetInfo::setFPMath(StringRef Name) { 2551 if (Name == "387") { 2552 FPMath = FP_387; 2553 return true; 2554 } 2555 if (Name == "sse") { 2556 FPMath = FP_SSE; 2557 return true; 2558 } 2559 return false; 2560 } 2561 2562 bool X86TargetInfo::initFeatureMap( 2563 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2564 const std::vector<std::string> &FeaturesVec) const { 2565 // FIXME: This *really* should not be here. 2566 // X86_64 always has SSE2. 2567 if (getTriple().getArch() == llvm::Triple::x86_64) 2568 setFeatureEnabledImpl(Features, "sse2", true); 2569 2570 switch (getCPUKind(CPU)) { 2571 case CK_Generic: 2572 case CK_i386: 2573 case CK_i486: 2574 case CK_i586: 2575 case CK_Pentium: 2576 case CK_i686: 2577 case CK_PentiumPro: 2578 break; 2579 case CK_PentiumMMX: 2580 case CK_Pentium2: 2581 case CK_K6: 2582 case CK_WinChipC6: 2583 setFeatureEnabledImpl(Features, "mmx", true); 2584 break; 2585 case CK_Pentium3: 2586 case CK_Pentium3M: 2587 case CK_C3_2: 2588 setFeatureEnabledImpl(Features, "sse", true); 2589 setFeatureEnabledImpl(Features, "fxsr", true); 2590 break; 2591 case CK_PentiumM: 2592 case CK_Pentium4: 2593 case CK_Pentium4M: 2594 case CK_x86_64: 2595 setFeatureEnabledImpl(Features, "sse2", true); 2596 setFeatureEnabledImpl(Features, "fxsr", true); 2597 break; 2598 case CK_Yonah: 2599 case CK_Prescott: 2600 case CK_Nocona: 2601 setFeatureEnabledImpl(Features, "sse3", true); 2602 setFeatureEnabledImpl(Features, "fxsr", true); 2603 setFeatureEnabledImpl(Features, "cx16", true); 2604 break; 2605 case CK_Core2: 2606 case CK_Bonnell: 2607 setFeatureEnabledImpl(Features, "ssse3", true); 2608 setFeatureEnabledImpl(Features, "fxsr", true); 2609 setFeatureEnabledImpl(Features, "cx16", true); 2610 break; 2611 case CK_Penryn: 2612 setFeatureEnabledImpl(Features, "sse4.1", true); 2613 setFeatureEnabledImpl(Features, "fxsr", true); 2614 setFeatureEnabledImpl(Features, "cx16", true); 2615 break; 2616 case CK_Skylake: 2617 setFeatureEnabledImpl(Features, "avx512f", true); 2618 setFeatureEnabledImpl(Features, "avx512cd", true); 2619 setFeatureEnabledImpl(Features, "avx512dq", true); 2620 setFeatureEnabledImpl(Features, "avx512bw", true); 2621 setFeatureEnabledImpl(Features, "avx512vl", true); 2622 setFeatureEnabledImpl(Features, "xsavec", true); 2623 setFeatureEnabledImpl(Features, "xsaves", true); 2624 setFeatureEnabledImpl(Features, "pku", true); 2625 // FALLTHROUGH 2626 case CK_Broadwell: 2627 setFeatureEnabledImpl(Features, "rdseed", true); 2628 setFeatureEnabledImpl(Features, "adx", true); 2629 // FALLTHROUGH 2630 case CK_Haswell: 2631 setFeatureEnabledImpl(Features, "avx2", true); 2632 setFeatureEnabledImpl(Features, "lzcnt", true); 2633 setFeatureEnabledImpl(Features, "bmi", true); 2634 setFeatureEnabledImpl(Features, "bmi2", true); 2635 setFeatureEnabledImpl(Features, "rtm", true); 2636 setFeatureEnabledImpl(Features, "fma", true); 2637 // FALLTHROUGH 2638 case CK_IvyBridge: 2639 setFeatureEnabledImpl(Features, "rdrnd", true); 2640 setFeatureEnabledImpl(Features, "f16c", true); 2641 setFeatureEnabledImpl(Features, "fsgsbase", true); 2642 // FALLTHROUGH 2643 case CK_SandyBridge: 2644 setFeatureEnabledImpl(Features, "avx", true); 2645 setFeatureEnabledImpl(Features, "xsave", true); 2646 setFeatureEnabledImpl(Features, "xsaveopt", true); 2647 // FALLTHROUGH 2648 case CK_Westmere: 2649 case CK_Silvermont: 2650 setFeatureEnabledImpl(Features, "aes", true); 2651 setFeatureEnabledImpl(Features, "pclmul", true); 2652 // FALLTHROUGH 2653 case CK_Nehalem: 2654 setFeatureEnabledImpl(Features, "sse4.2", true); 2655 setFeatureEnabledImpl(Features, "fxsr", true); 2656 setFeatureEnabledImpl(Features, "cx16", true); 2657 break; 2658 case CK_KNL: 2659 setFeatureEnabledImpl(Features, "avx512f", true); 2660 setFeatureEnabledImpl(Features, "avx512cd", true); 2661 setFeatureEnabledImpl(Features, "avx512er", true); 2662 setFeatureEnabledImpl(Features, "avx512pf", true); 2663 setFeatureEnabledImpl(Features, "fxsr", true); 2664 setFeatureEnabledImpl(Features, "rdseed", true); 2665 setFeatureEnabledImpl(Features, "adx", true); 2666 setFeatureEnabledImpl(Features, "lzcnt", true); 2667 setFeatureEnabledImpl(Features, "bmi", true); 2668 setFeatureEnabledImpl(Features, "bmi2", true); 2669 setFeatureEnabledImpl(Features, "rtm", true); 2670 setFeatureEnabledImpl(Features, "fma", true); 2671 setFeatureEnabledImpl(Features, "rdrnd", true); 2672 setFeatureEnabledImpl(Features, "f16c", true); 2673 setFeatureEnabledImpl(Features, "fsgsbase", true); 2674 setFeatureEnabledImpl(Features, "aes", true); 2675 setFeatureEnabledImpl(Features, "pclmul", true); 2676 setFeatureEnabledImpl(Features, "cx16", true); 2677 setFeatureEnabledImpl(Features, "xsaveopt", true); 2678 setFeatureEnabledImpl(Features, "xsave", true); 2679 break; 2680 case CK_K6_2: 2681 case CK_K6_3: 2682 case CK_WinChip2: 2683 case CK_C3: 2684 setFeatureEnabledImpl(Features, "3dnow", true); 2685 break; 2686 case CK_Athlon: 2687 case CK_AthlonThunderbird: 2688 case CK_Geode: 2689 setFeatureEnabledImpl(Features, "3dnowa", true); 2690 break; 2691 case CK_Athlon4: 2692 case CK_AthlonXP: 2693 case CK_AthlonMP: 2694 setFeatureEnabledImpl(Features, "sse", true); 2695 setFeatureEnabledImpl(Features, "3dnowa", true); 2696 setFeatureEnabledImpl(Features, "fxsr", true); 2697 break; 2698 case CK_K8: 2699 case CK_Opteron: 2700 case CK_Athlon64: 2701 case CK_AthlonFX: 2702 setFeatureEnabledImpl(Features, "sse2", true); 2703 setFeatureEnabledImpl(Features, "3dnowa", true); 2704 setFeatureEnabledImpl(Features, "fxsr", true); 2705 break; 2706 case CK_AMDFAM10: 2707 setFeatureEnabledImpl(Features, "sse4a", true); 2708 setFeatureEnabledImpl(Features, "lzcnt", true); 2709 setFeatureEnabledImpl(Features, "popcnt", true); 2710 // FALLTHROUGH 2711 case CK_K8SSE3: 2712 case CK_OpteronSSE3: 2713 case CK_Athlon64SSE3: 2714 setFeatureEnabledImpl(Features, "sse3", true); 2715 setFeatureEnabledImpl(Features, "3dnowa", true); 2716 setFeatureEnabledImpl(Features, "fxsr", true); 2717 break; 2718 case CK_BTVER2: 2719 setFeatureEnabledImpl(Features, "avx", true); 2720 setFeatureEnabledImpl(Features, "aes", true); 2721 setFeatureEnabledImpl(Features, "pclmul", true); 2722 setFeatureEnabledImpl(Features, "bmi", true); 2723 setFeatureEnabledImpl(Features, "f16c", true); 2724 setFeatureEnabledImpl(Features, "xsaveopt", true); 2725 // FALLTHROUGH 2726 case CK_BTVER1: 2727 setFeatureEnabledImpl(Features, "ssse3", true); 2728 setFeatureEnabledImpl(Features, "sse4a", true); 2729 setFeatureEnabledImpl(Features, "lzcnt", true); 2730 setFeatureEnabledImpl(Features, "popcnt", true); 2731 setFeatureEnabledImpl(Features, "prfchw", true); 2732 setFeatureEnabledImpl(Features, "cx16", true); 2733 setFeatureEnabledImpl(Features, "fxsr", true); 2734 break; 2735 case CK_BDVER4: 2736 setFeatureEnabledImpl(Features, "avx2", true); 2737 setFeatureEnabledImpl(Features, "bmi2", true); 2738 // FALLTHROUGH 2739 case CK_BDVER3: 2740 setFeatureEnabledImpl(Features, "fsgsbase", true); 2741 setFeatureEnabledImpl(Features, "xsaveopt", true); 2742 // FALLTHROUGH 2743 case CK_BDVER2: 2744 setFeatureEnabledImpl(Features, "bmi", true); 2745 setFeatureEnabledImpl(Features, "fma", true); 2746 setFeatureEnabledImpl(Features, "f16c", true); 2747 setFeatureEnabledImpl(Features, "tbm", true); 2748 // FALLTHROUGH 2749 case CK_BDVER1: 2750 // xop implies avx, sse4a and fma4. 2751 setFeatureEnabledImpl(Features, "xop", true); 2752 setFeatureEnabledImpl(Features, "lzcnt", true); 2753 setFeatureEnabledImpl(Features, "aes", true); 2754 setFeatureEnabledImpl(Features, "pclmul", true); 2755 setFeatureEnabledImpl(Features, "prfchw", true); 2756 setFeatureEnabledImpl(Features, "cx16", true); 2757 setFeatureEnabledImpl(Features, "fxsr", true); 2758 setFeatureEnabledImpl(Features, "xsave", true); 2759 break; 2760 } 2761 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2762 return false; 2763 2764 // Can't do this earlier because we need to be able to explicitly enable 2765 // or disable these features and the things that they depend upon. 2766 2767 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2768 auto I = Features.find("sse4.2"); 2769 if (I != Features.end() && I->getValue() && 2770 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2771 FeaturesVec.end()) 2772 Features["popcnt"] = true; 2773 2774 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2775 I = Features.find("3dnow"); 2776 if (I != Features.end() && I->getValue() && 2777 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2778 FeaturesVec.end()) 2779 Features["prfchw"] = true; 2780 2781 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2782 // then enable MMX. 2783 I = Features.find("sse"); 2784 if (I != Features.end() && I->getValue() && 2785 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2786 FeaturesVec.end()) 2787 Features["mmx"] = true; 2788 2789 return true; 2790 } 2791 2792 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2793 X86SSEEnum Level, bool Enabled) { 2794 if (Enabled) { 2795 switch (Level) { 2796 case AVX512F: 2797 Features["avx512f"] = true; 2798 case AVX2: 2799 Features["avx2"] = true; 2800 case AVX: 2801 Features["avx"] = true; 2802 Features["xsave"] = true; 2803 case SSE42: 2804 Features["sse4.2"] = true; 2805 case SSE41: 2806 Features["sse4.1"] = true; 2807 case SSSE3: 2808 Features["ssse3"] = true; 2809 case SSE3: 2810 Features["sse3"] = true; 2811 case SSE2: 2812 Features["sse2"] = true; 2813 case SSE1: 2814 Features["sse"] = true; 2815 case NoSSE: 2816 break; 2817 } 2818 return; 2819 } 2820 2821 switch (Level) { 2822 case NoSSE: 2823 case SSE1: 2824 Features["sse"] = false; 2825 case SSE2: 2826 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2827 Features["sha"] = false; 2828 case SSE3: 2829 Features["sse3"] = false; 2830 setXOPLevel(Features, NoXOP, false); 2831 case SSSE3: 2832 Features["ssse3"] = false; 2833 case SSE41: 2834 Features["sse4.1"] = false; 2835 case SSE42: 2836 Features["sse4.2"] = false; 2837 case AVX: 2838 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2839 Features["xsaveopt"] = false; 2840 setXOPLevel(Features, FMA4, false); 2841 case AVX2: 2842 Features["avx2"] = false; 2843 case AVX512F: 2844 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2845 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2846 Features["avx512vl"] = false; 2847 } 2848 } 2849 2850 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2851 MMX3DNowEnum Level, bool Enabled) { 2852 if (Enabled) { 2853 switch (Level) { 2854 case AMD3DNowAthlon: 2855 Features["3dnowa"] = true; 2856 case AMD3DNow: 2857 Features["3dnow"] = true; 2858 case MMX: 2859 Features["mmx"] = true; 2860 case NoMMX3DNow: 2861 break; 2862 } 2863 return; 2864 } 2865 2866 switch (Level) { 2867 case NoMMX3DNow: 2868 case MMX: 2869 Features["mmx"] = false; 2870 case AMD3DNow: 2871 Features["3dnow"] = false; 2872 case AMD3DNowAthlon: 2873 Features["3dnowa"] = false; 2874 } 2875 } 2876 2877 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2878 bool Enabled) { 2879 if (Enabled) { 2880 switch (Level) { 2881 case XOP: 2882 Features["xop"] = true; 2883 case FMA4: 2884 Features["fma4"] = true; 2885 setSSELevel(Features, AVX, true); 2886 case SSE4A: 2887 Features["sse4a"] = true; 2888 setSSELevel(Features, SSE3, true); 2889 case NoXOP: 2890 break; 2891 } 2892 return; 2893 } 2894 2895 switch (Level) { 2896 case NoXOP: 2897 case SSE4A: 2898 Features["sse4a"] = false; 2899 case FMA4: 2900 Features["fma4"] = false; 2901 case XOP: 2902 Features["xop"] = false; 2903 } 2904 } 2905 2906 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2907 StringRef Name, bool Enabled) { 2908 // This is a bit of a hack to deal with the sse4 target feature when used 2909 // as part of the target attribute. We handle sse4 correctly everywhere 2910 // else. See below for more information on how we handle the sse4 options. 2911 if (Name != "sse4") 2912 Features[Name] = Enabled; 2913 2914 if (Name == "mmx") { 2915 setMMXLevel(Features, MMX, Enabled); 2916 } else if (Name == "sse") { 2917 setSSELevel(Features, SSE1, Enabled); 2918 } else if (Name == "sse2") { 2919 setSSELevel(Features, SSE2, Enabled); 2920 } else if (Name == "sse3") { 2921 setSSELevel(Features, SSE3, Enabled); 2922 } else if (Name == "ssse3") { 2923 setSSELevel(Features, SSSE3, Enabled); 2924 } else if (Name == "sse4.2") { 2925 setSSELevel(Features, SSE42, Enabled); 2926 } else if (Name == "sse4.1") { 2927 setSSELevel(Features, SSE41, Enabled); 2928 } else if (Name == "3dnow") { 2929 setMMXLevel(Features, AMD3DNow, Enabled); 2930 } else if (Name == "3dnowa") { 2931 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2932 } else if (Name == "aes") { 2933 if (Enabled) 2934 setSSELevel(Features, SSE2, Enabled); 2935 } else if (Name == "pclmul") { 2936 if (Enabled) 2937 setSSELevel(Features, SSE2, Enabled); 2938 } else if (Name == "avx") { 2939 setSSELevel(Features, AVX, Enabled); 2940 } else if (Name == "avx2") { 2941 setSSELevel(Features, AVX2, Enabled); 2942 } else if (Name == "avx512f") { 2943 setSSELevel(Features, AVX512F, Enabled); 2944 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2945 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2946 if (Enabled) 2947 setSSELevel(Features, AVX512F, Enabled); 2948 } else if (Name == "fma") { 2949 if (Enabled) 2950 setSSELevel(Features, AVX, Enabled); 2951 } else if (Name == "fma4") { 2952 setXOPLevel(Features, FMA4, Enabled); 2953 } else if (Name == "xop") { 2954 setXOPLevel(Features, XOP, Enabled); 2955 } else if (Name == "sse4a") { 2956 setXOPLevel(Features, SSE4A, Enabled); 2957 } else if (Name == "f16c") { 2958 if (Enabled) 2959 setSSELevel(Features, AVX, Enabled); 2960 } else if (Name == "sha") { 2961 if (Enabled) 2962 setSSELevel(Features, SSE2, Enabled); 2963 } else if (Name == "sse4") { 2964 // We can get here via the __target__ attribute since that's not controlled 2965 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2966 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2967 // disabled. 2968 if (Enabled) 2969 setSSELevel(Features, SSE42, Enabled); 2970 else 2971 setSSELevel(Features, SSE41, Enabled); 2972 } else if (Name == "xsave") { 2973 if (Enabled) 2974 setSSELevel(Features, AVX, Enabled); 2975 else 2976 Features["xsaveopt"] = false; 2977 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2978 if (Enabled) { 2979 Features["xsave"] = true; 2980 setSSELevel(Features, AVX, Enabled); 2981 } 2982 } 2983 } 2984 2985 /// handleTargetFeatures - Perform initialization based on the user 2986 /// configured set of features. 2987 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2988 DiagnosticsEngine &Diags) { 2989 for (const auto &Feature : Features) { 2990 if (Feature[0] != '+') 2991 continue; 2992 2993 if (Feature == "+aes") { 2994 HasAES = true; 2995 } else if (Feature == "+pclmul") { 2996 HasPCLMUL = true; 2997 } else if (Feature == "+lzcnt") { 2998 HasLZCNT = true; 2999 } else if (Feature == "+rdrnd") { 3000 HasRDRND = true; 3001 } else if (Feature == "+fsgsbase") { 3002 HasFSGSBASE = true; 3003 } else if (Feature == "+bmi") { 3004 HasBMI = true; 3005 } else if (Feature == "+bmi2") { 3006 HasBMI2 = true; 3007 } else if (Feature == "+popcnt") { 3008 HasPOPCNT = true; 3009 } else if (Feature == "+rtm") { 3010 HasRTM = true; 3011 } else if (Feature == "+prfchw") { 3012 HasPRFCHW = true; 3013 } else if (Feature == "+rdseed") { 3014 HasRDSEED = true; 3015 } else if (Feature == "+adx") { 3016 HasADX = true; 3017 } else if (Feature == "+tbm") { 3018 HasTBM = true; 3019 } else if (Feature == "+fma") { 3020 HasFMA = true; 3021 } else if (Feature == "+f16c") { 3022 HasF16C = true; 3023 } else if (Feature == "+avx512cd") { 3024 HasAVX512CD = true; 3025 } else if (Feature == "+avx512er") { 3026 HasAVX512ER = true; 3027 } else if (Feature == "+avx512pf") { 3028 HasAVX512PF = true; 3029 } else if (Feature == "+avx512dq") { 3030 HasAVX512DQ = true; 3031 } else if (Feature == "+avx512bw") { 3032 HasAVX512BW = true; 3033 } else if (Feature == "+avx512vl") { 3034 HasAVX512VL = true; 3035 } else if (Feature == "+sha") { 3036 HasSHA = true; 3037 } else if (Feature == "+cx16") { 3038 HasCX16 = true; 3039 } else if (Feature == "+fxsr") { 3040 HasFXSR = true; 3041 } else if (Feature == "+xsave") { 3042 HasXSAVE = true; 3043 } else if (Feature == "+xsaveopt") { 3044 HasXSAVEOPT = true; 3045 } else if (Feature == "+xsavec") { 3046 HasXSAVEC = true; 3047 } else if (Feature == "+xsaves") { 3048 HasXSAVES = true; 3049 } else if (Feature == "+pku") { 3050 HasPKU = true; 3051 } 3052 3053 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3054 .Case("+avx512f", AVX512F) 3055 .Case("+avx2", AVX2) 3056 .Case("+avx", AVX) 3057 .Case("+sse4.2", SSE42) 3058 .Case("+sse4.1", SSE41) 3059 .Case("+ssse3", SSSE3) 3060 .Case("+sse3", SSE3) 3061 .Case("+sse2", SSE2) 3062 .Case("+sse", SSE1) 3063 .Default(NoSSE); 3064 SSELevel = std::max(SSELevel, Level); 3065 3066 MMX3DNowEnum ThreeDNowLevel = 3067 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3068 .Case("+3dnowa", AMD3DNowAthlon) 3069 .Case("+3dnow", AMD3DNow) 3070 .Case("+mmx", MMX) 3071 .Default(NoMMX3DNow); 3072 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3073 3074 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3075 .Case("+xop", XOP) 3076 .Case("+fma4", FMA4) 3077 .Case("+sse4a", SSE4A) 3078 .Default(NoXOP); 3079 XOPLevel = std::max(XOPLevel, XLevel); 3080 } 3081 3082 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3083 // matches the selected sse level. 3084 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3085 (FPMath == FP_387 && SSELevel >= SSE1)) { 3086 Diags.Report(diag::err_target_unsupported_fpmath) << 3087 (FPMath == FP_SSE ? "sse" : "387"); 3088 return false; 3089 } 3090 3091 SimdDefaultAlign = 3092 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3093 return true; 3094 } 3095 3096 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3097 /// definitions for this particular subtarget. 3098 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3099 MacroBuilder &Builder) const { 3100 // Target identification. 3101 if (getTriple().getArch() == llvm::Triple::x86_64) { 3102 Builder.defineMacro("__amd64__"); 3103 Builder.defineMacro("__amd64"); 3104 Builder.defineMacro("__x86_64"); 3105 Builder.defineMacro("__x86_64__"); 3106 if (getTriple().getArchName() == "x86_64h") { 3107 Builder.defineMacro("__x86_64h"); 3108 Builder.defineMacro("__x86_64h__"); 3109 } 3110 } else { 3111 DefineStd(Builder, "i386", Opts); 3112 } 3113 3114 // Subtarget options. 3115 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3116 // truly should be based on -mtune options. 3117 switch (CPU) { 3118 case CK_Generic: 3119 break; 3120 case CK_i386: 3121 // The rest are coming from the i386 define above. 3122 Builder.defineMacro("__tune_i386__"); 3123 break; 3124 case CK_i486: 3125 case CK_WinChipC6: 3126 case CK_WinChip2: 3127 case CK_C3: 3128 defineCPUMacros(Builder, "i486"); 3129 break; 3130 case CK_PentiumMMX: 3131 Builder.defineMacro("__pentium_mmx__"); 3132 Builder.defineMacro("__tune_pentium_mmx__"); 3133 // Fallthrough 3134 case CK_i586: 3135 case CK_Pentium: 3136 defineCPUMacros(Builder, "i586"); 3137 defineCPUMacros(Builder, "pentium"); 3138 break; 3139 case CK_Pentium3: 3140 case CK_Pentium3M: 3141 case CK_PentiumM: 3142 Builder.defineMacro("__tune_pentium3__"); 3143 // Fallthrough 3144 case CK_Pentium2: 3145 case CK_C3_2: 3146 Builder.defineMacro("__tune_pentium2__"); 3147 // Fallthrough 3148 case CK_PentiumPro: 3149 Builder.defineMacro("__tune_i686__"); 3150 Builder.defineMacro("__tune_pentiumpro__"); 3151 // Fallthrough 3152 case CK_i686: 3153 Builder.defineMacro("__i686"); 3154 Builder.defineMacro("__i686__"); 3155 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3156 Builder.defineMacro("__pentiumpro"); 3157 Builder.defineMacro("__pentiumpro__"); 3158 break; 3159 case CK_Pentium4: 3160 case CK_Pentium4M: 3161 defineCPUMacros(Builder, "pentium4"); 3162 break; 3163 case CK_Yonah: 3164 case CK_Prescott: 3165 case CK_Nocona: 3166 defineCPUMacros(Builder, "nocona"); 3167 break; 3168 case CK_Core2: 3169 case CK_Penryn: 3170 defineCPUMacros(Builder, "core2"); 3171 break; 3172 case CK_Bonnell: 3173 defineCPUMacros(Builder, "atom"); 3174 break; 3175 case CK_Silvermont: 3176 defineCPUMacros(Builder, "slm"); 3177 break; 3178 case CK_Nehalem: 3179 case CK_Westmere: 3180 case CK_SandyBridge: 3181 case CK_IvyBridge: 3182 case CK_Haswell: 3183 case CK_Broadwell: 3184 // FIXME: Historically, we defined this legacy name, it would be nice to 3185 // remove it at some point. We've never exposed fine-grained names for 3186 // recent primary x86 CPUs, and we should keep it that way. 3187 defineCPUMacros(Builder, "corei7"); 3188 break; 3189 case CK_Skylake: 3190 // FIXME: Historically, we defined this legacy name, it would be nice to 3191 // remove it at some point. This is the only fine-grained CPU macro in the 3192 // main intel CPU line, and it would be better to not have these and force 3193 // people to use ISA macros. 3194 defineCPUMacros(Builder, "skx"); 3195 break; 3196 case CK_KNL: 3197 defineCPUMacros(Builder, "knl"); 3198 break; 3199 case CK_K6_2: 3200 Builder.defineMacro("__k6_2__"); 3201 Builder.defineMacro("__tune_k6_2__"); 3202 // Fallthrough 3203 case CK_K6_3: 3204 if (CPU != CK_K6_2) { // In case of fallthrough 3205 // FIXME: GCC may be enabling these in cases where some other k6 3206 // architecture is specified but -m3dnow is explicitly provided. The 3207 // exact semantics need to be determined and emulated here. 3208 Builder.defineMacro("__k6_3__"); 3209 Builder.defineMacro("__tune_k6_3__"); 3210 } 3211 // Fallthrough 3212 case CK_K6: 3213 defineCPUMacros(Builder, "k6"); 3214 break; 3215 case CK_Athlon: 3216 case CK_AthlonThunderbird: 3217 case CK_Athlon4: 3218 case CK_AthlonXP: 3219 case CK_AthlonMP: 3220 defineCPUMacros(Builder, "athlon"); 3221 if (SSELevel != NoSSE) { 3222 Builder.defineMacro("__athlon_sse__"); 3223 Builder.defineMacro("__tune_athlon_sse__"); 3224 } 3225 break; 3226 case CK_K8: 3227 case CK_K8SSE3: 3228 case CK_x86_64: 3229 case CK_Opteron: 3230 case CK_OpteronSSE3: 3231 case CK_Athlon64: 3232 case CK_Athlon64SSE3: 3233 case CK_AthlonFX: 3234 defineCPUMacros(Builder, "k8"); 3235 break; 3236 case CK_AMDFAM10: 3237 defineCPUMacros(Builder, "amdfam10"); 3238 break; 3239 case CK_BTVER1: 3240 defineCPUMacros(Builder, "btver1"); 3241 break; 3242 case CK_BTVER2: 3243 defineCPUMacros(Builder, "btver2"); 3244 break; 3245 case CK_BDVER1: 3246 defineCPUMacros(Builder, "bdver1"); 3247 break; 3248 case CK_BDVER2: 3249 defineCPUMacros(Builder, "bdver2"); 3250 break; 3251 case CK_BDVER3: 3252 defineCPUMacros(Builder, "bdver3"); 3253 break; 3254 case CK_BDVER4: 3255 defineCPUMacros(Builder, "bdver4"); 3256 break; 3257 case CK_Geode: 3258 defineCPUMacros(Builder, "geode"); 3259 break; 3260 } 3261 3262 // Target properties. 3263 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3264 3265 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3266 // functions in glibc header files that use FP Stack inline asm which the 3267 // backend can't deal with (PR879). 3268 Builder.defineMacro("__NO_MATH_INLINES"); 3269 3270 if (HasAES) 3271 Builder.defineMacro("__AES__"); 3272 3273 if (HasPCLMUL) 3274 Builder.defineMacro("__PCLMUL__"); 3275 3276 if (HasLZCNT) 3277 Builder.defineMacro("__LZCNT__"); 3278 3279 if (HasRDRND) 3280 Builder.defineMacro("__RDRND__"); 3281 3282 if (HasFSGSBASE) 3283 Builder.defineMacro("__FSGSBASE__"); 3284 3285 if (HasBMI) 3286 Builder.defineMacro("__BMI__"); 3287 3288 if (HasBMI2) 3289 Builder.defineMacro("__BMI2__"); 3290 3291 if (HasPOPCNT) 3292 Builder.defineMacro("__POPCNT__"); 3293 3294 if (HasRTM) 3295 Builder.defineMacro("__RTM__"); 3296 3297 if (HasPRFCHW) 3298 Builder.defineMacro("__PRFCHW__"); 3299 3300 if (HasRDSEED) 3301 Builder.defineMacro("__RDSEED__"); 3302 3303 if (HasADX) 3304 Builder.defineMacro("__ADX__"); 3305 3306 if (HasTBM) 3307 Builder.defineMacro("__TBM__"); 3308 3309 switch (XOPLevel) { 3310 case XOP: 3311 Builder.defineMacro("__XOP__"); 3312 case FMA4: 3313 Builder.defineMacro("__FMA4__"); 3314 case SSE4A: 3315 Builder.defineMacro("__SSE4A__"); 3316 case NoXOP: 3317 break; 3318 } 3319 3320 if (HasFMA) 3321 Builder.defineMacro("__FMA__"); 3322 3323 if (HasF16C) 3324 Builder.defineMacro("__F16C__"); 3325 3326 if (HasAVX512CD) 3327 Builder.defineMacro("__AVX512CD__"); 3328 if (HasAVX512ER) 3329 Builder.defineMacro("__AVX512ER__"); 3330 if (HasAVX512PF) 3331 Builder.defineMacro("__AVX512PF__"); 3332 if (HasAVX512DQ) 3333 Builder.defineMacro("__AVX512DQ__"); 3334 if (HasAVX512BW) 3335 Builder.defineMacro("__AVX512BW__"); 3336 if (HasAVX512VL) 3337 Builder.defineMacro("__AVX512VL__"); 3338 3339 if (HasSHA) 3340 Builder.defineMacro("__SHA__"); 3341 3342 if (HasFXSR) 3343 Builder.defineMacro("__FXSR__"); 3344 if (HasXSAVE) 3345 Builder.defineMacro("__XSAVE__"); 3346 if (HasXSAVEOPT) 3347 Builder.defineMacro("__XSAVEOPT__"); 3348 if (HasXSAVEC) 3349 Builder.defineMacro("__XSAVEC__"); 3350 if (HasXSAVES) 3351 Builder.defineMacro("__XSAVES__"); 3352 if (HasPKU) 3353 Builder.defineMacro("__PKU__"); 3354 if (HasCX16) 3355 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3356 3357 // Each case falls through to the previous one here. 3358 switch (SSELevel) { 3359 case AVX512F: 3360 Builder.defineMacro("__AVX512F__"); 3361 case AVX2: 3362 Builder.defineMacro("__AVX2__"); 3363 case AVX: 3364 Builder.defineMacro("__AVX__"); 3365 case SSE42: 3366 Builder.defineMacro("__SSE4_2__"); 3367 case SSE41: 3368 Builder.defineMacro("__SSE4_1__"); 3369 case SSSE3: 3370 Builder.defineMacro("__SSSE3__"); 3371 case SSE3: 3372 Builder.defineMacro("__SSE3__"); 3373 case SSE2: 3374 Builder.defineMacro("__SSE2__"); 3375 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3376 case SSE1: 3377 Builder.defineMacro("__SSE__"); 3378 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3379 case NoSSE: 3380 break; 3381 } 3382 3383 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3384 switch (SSELevel) { 3385 case AVX512F: 3386 case AVX2: 3387 case AVX: 3388 case SSE42: 3389 case SSE41: 3390 case SSSE3: 3391 case SSE3: 3392 case SSE2: 3393 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3394 break; 3395 case SSE1: 3396 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3397 break; 3398 default: 3399 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3400 } 3401 } 3402 3403 // Each case falls through to the previous one here. 3404 switch (MMX3DNowLevel) { 3405 case AMD3DNowAthlon: 3406 Builder.defineMacro("__3dNOW_A__"); 3407 case AMD3DNow: 3408 Builder.defineMacro("__3dNOW__"); 3409 case MMX: 3410 Builder.defineMacro("__MMX__"); 3411 case NoMMX3DNow: 3412 break; 3413 } 3414 3415 if (CPU >= CK_i486) { 3416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3417 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3418 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3419 } 3420 if (CPU >= CK_i586) 3421 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3422 } 3423 3424 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3425 return llvm::StringSwitch<bool>(Feature) 3426 .Case("aes", HasAES) 3427 .Case("avx", SSELevel >= AVX) 3428 .Case("avx2", SSELevel >= AVX2) 3429 .Case("avx512f", SSELevel >= AVX512F) 3430 .Case("avx512cd", HasAVX512CD) 3431 .Case("avx512er", HasAVX512ER) 3432 .Case("avx512pf", HasAVX512PF) 3433 .Case("avx512dq", HasAVX512DQ) 3434 .Case("avx512bw", HasAVX512BW) 3435 .Case("avx512vl", HasAVX512VL) 3436 .Case("bmi", HasBMI) 3437 .Case("bmi2", HasBMI2) 3438 .Case("cx16", HasCX16) 3439 .Case("f16c", HasF16C) 3440 .Case("fma", HasFMA) 3441 .Case("fma4", XOPLevel >= FMA4) 3442 .Case("fsgsbase", HasFSGSBASE) 3443 .Case("fxsr", HasFXSR) 3444 .Case("lzcnt", HasLZCNT) 3445 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3446 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3447 .Case("mmx", MMX3DNowLevel >= MMX) 3448 .Case("pclmul", HasPCLMUL) 3449 .Case("popcnt", HasPOPCNT) 3450 .Case("prfchw", HasPRFCHW) 3451 .Case("rdrnd", HasRDRND) 3452 .Case("rdseed", HasRDSEED) 3453 .Case("rtm", HasRTM) 3454 .Case("sha", HasSHA) 3455 .Case("sse", SSELevel >= SSE1) 3456 .Case("sse2", SSELevel >= SSE2) 3457 .Case("sse3", SSELevel >= SSE3) 3458 .Case("ssse3", SSELevel >= SSSE3) 3459 .Case("sse4.1", SSELevel >= SSE41) 3460 .Case("sse4.2", SSELevel >= SSE42) 3461 .Case("sse4a", XOPLevel >= SSE4A) 3462 .Case("tbm", HasTBM) 3463 .Case("x86", true) 3464 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3465 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3466 .Case("xop", XOPLevel >= XOP) 3467 .Case("xsave", HasXSAVE) 3468 .Case("xsavec", HasXSAVEC) 3469 .Case("xsaves", HasXSAVES) 3470 .Case("xsaveopt", HasXSAVEOPT) 3471 .Case("pku", HasPKU) 3472 .Default(false); 3473 } 3474 3475 // We can't use a generic validation scheme for the features accepted here 3476 // versus subtarget features accepted in the target attribute because the 3477 // bitfield structure that's initialized in the runtime only supports the 3478 // below currently rather than the full range of subtarget features. (See 3479 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3480 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3481 return llvm::StringSwitch<bool>(FeatureStr) 3482 .Case("cmov", true) 3483 .Case("mmx", true) 3484 .Case("popcnt", true) 3485 .Case("sse", true) 3486 .Case("sse2", true) 3487 .Case("sse3", true) 3488 .Case("sse4.1", true) 3489 .Case("sse4.2", true) 3490 .Case("avx", true) 3491 .Case("avx2", true) 3492 .Case("sse4a", true) 3493 .Case("fma4", true) 3494 .Case("xop", true) 3495 .Case("fma", true) 3496 .Case("avx512f", true) 3497 .Case("bmi", true) 3498 .Case("bmi2", true) 3499 .Default(false); 3500 } 3501 3502 bool 3503 X86TargetInfo::validateAsmConstraint(const char *&Name, 3504 TargetInfo::ConstraintInfo &Info) const { 3505 switch (*Name) { 3506 default: return false; 3507 // Constant constraints. 3508 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3509 // instructions. 3510 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3511 // x86_64 instructions. 3512 case 's': 3513 Info.setRequiresImmediate(); 3514 return true; 3515 case 'I': 3516 Info.setRequiresImmediate(0, 31); 3517 return true; 3518 case 'J': 3519 Info.setRequiresImmediate(0, 63); 3520 return true; 3521 case 'K': 3522 Info.setRequiresImmediate(-128, 127); 3523 return true; 3524 case 'L': 3525 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3526 return true; 3527 case 'M': 3528 Info.setRequiresImmediate(0, 3); 3529 return true; 3530 case 'N': 3531 Info.setRequiresImmediate(0, 255); 3532 return true; 3533 case 'O': 3534 Info.setRequiresImmediate(0, 127); 3535 return true; 3536 // Register constraints. 3537 case 'Y': // 'Y' is the first character for several 2-character constraints. 3538 // Shift the pointer to the second character of the constraint. 3539 Name++; 3540 switch (*Name) { 3541 default: 3542 return false; 3543 case '0': // First SSE register. 3544 case 't': // Any SSE register, when SSE2 is enabled. 3545 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3546 case 'm': // Any MMX register, when inter-unit moves enabled. 3547 Info.setAllowsRegister(); 3548 return true; 3549 } 3550 case 'f': // Any x87 floating point stack register. 3551 // Constraint 'f' cannot be used for output operands. 3552 if (Info.ConstraintStr[0] == '=') 3553 return false; 3554 Info.setAllowsRegister(); 3555 return true; 3556 case 'a': // eax. 3557 case 'b': // ebx. 3558 case 'c': // ecx. 3559 case 'd': // edx. 3560 case 'S': // esi. 3561 case 'D': // edi. 3562 case 'A': // edx:eax. 3563 case 't': // Top of floating point stack. 3564 case 'u': // Second from top of floating point stack. 3565 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3566 case 'y': // Any MMX register. 3567 case 'x': // Any SSE register. 3568 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3569 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3570 case 'l': // "Index" registers: any general register that can be used as an 3571 // index in a base+index memory access. 3572 Info.setAllowsRegister(); 3573 return true; 3574 // Floating point constant constraints. 3575 case 'C': // SSE floating point constant. 3576 case 'G': // x87 floating point constant. 3577 return true; 3578 } 3579 } 3580 3581 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3582 unsigned Size) const { 3583 // Strip off constraint modifiers. 3584 while (Constraint[0] == '=' || 3585 Constraint[0] == '+' || 3586 Constraint[0] == '&') 3587 Constraint = Constraint.substr(1); 3588 3589 return validateOperandSize(Constraint, Size); 3590 } 3591 3592 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3593 unsigned Size) const { 3594 return validateOperandSize(Constraint, Size); 3595 } 3596 3597 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3598 unsigned Size) const { 3599 switch (Constraint[0]) { 3600 default: break; 3601 case 'y': 3602 return Size <= 64; 3603 case 'f': 3604 case 't': 3605 case 'u': 3606 return Size <= 128; 3607 case 'x': 3608 if (SSELevel >= AVX512F) 3609 // 512-bit zmm registers can be used if target supports AVX512F. 3610 return Size <= 512U; 3611 else if (SSELevel >= AVX) 3612 // 256-bit ymm registers can be used if target supports AVX. 3613 return Size <= 256U; 3614 return Size <= 128U; 3615 case 'Y': 3616 // 'Y' is the first character for several 2-character constraints. 3617 switch (Constraint[1]) { 3618 default: break; 3619 case 'm': 3620 // 'Ym' is synonymous with 'y'. 3621 return Size <= 64; 3622 case 'i': 3623 case 't': 3624 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3625 if (SSELevel >= AVX512F) 3626 return Size <= 512U; 3627 else if (SSELevel >= AVX) 3628 return Size <= 256U; 3629 return SSELevel >= SSE2 && Size <= 128U; 3630 } 3631 3632 } 3633 3634 return true; 3635 } 3636 3637 std::string 3638 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3639 switch (*Constraint) { 3640 case 'a': return std::string("{ax}"); 3641 case 'b': return std::string("{bx}"); 3642 case 'c': return std::string("{cx}"); 3643 case 'd': return std::string("{dx}"); 3644 case 'S': return std::string("{si}"); 3645 case 'D': return std::string("{di}"); 3646 case 'p': // address 3647 return std::string("im"); 3648 case 't': // top of floating point stack. 3649 return std::string("{st}"); 3650 case 'u': // second from top of floating point stack. 3651 return std::string("{st(1)}"); // second from top of floating point stack. 3652 default: 3653 return std::string(1, *Constraint); 3654 } 3655 } 3656 3657 // X86-32 generic target 3658 class X86_32TargetInfo : public X86TargetInfo { 3659 public: 3660 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3661 DoubleAlign = LongLongAlign = 32; 3662 LongDoubleWidth = 96; 3663 LongDoubleAlign = 32; 3664 SuitableAlign = 128; 3665 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3666 SizeType = UnsignedInt; 3667 PtrDiffType = SignedInt; 3668 IntPtrType = SignedInt; 3669 RegParmMax = 3; 3670 3671 // Use fpret for all types. 3672 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3673 (1 << TargetInfo::Double) | 3674 (1 << TargetInfo::LongDouble)); 3675 3676 // x86-32 has atomics up to 8 bytes 3677 // FIXME: Check that we actually have cmpxchg8b before setting 3678 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3679 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3680 } 3681 BuiltinVaListKind getBuiltinVaListKind() const override { 3682 return TargetInfo::CharPtrBuiltinVaList; 3683 } 3684 3685 int getEHDataRegisterNumber(unsigned RegNo) const override { 3686 if (RegNo == 0) return 0; 3687 if (RegNo == 1) return 2; 3688 return -1; 3689 } 3690 bool validateOperandSize(StringRef Constraint, 3691 unsigned Size) const override { 3692 switch (Constraint[0]) { 3693 default: break; 3694 case 'R': 3695 case 'q': 3696 case 'Q': 3697 case 'a': 3698 case 'b': 3699 case 'c': 3700 case 'd': 3701 case 'S': 3702 case 'D': 3703 return Size <= 32; 3704 case 'A': 3705 return Size <= 64; 3706 } 3707 3708 return X86TargetInfo::validateOperandSize(Constraint, Size); 3709 } 3710 }; 3711 3712 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3713 public: 3714 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3715 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3716 3717 unsigned getFloatEvalMethod() const override { 3718 unsigned Major, Minor, Micro; 3719 getTriple().getOSVersion(Major, Minor, Micro); 3720 // New NetBSD uses the default rounding mode. 3721 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3722 return X86_32TargetInfo::getFloatEvalMethod(); 3723 // NetBSD before 6.99.26 defaults to "double" rounding. 3724 return 1; 3725 } 3726 }; 3727 3728 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3729 public: 3730 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3731 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3732 SizeType = UnsignedLong; 3733 IntPtrType = SignedLong; 3734 PtrDiffType = SignedLong; 3735 } 3736 }; 3737 3738 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3739 public: 3740 BitrigI386TargetInfo(const llvm::Triple &Triple) 3741 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3742 SizeType = UnsignedLong; 3743 IntPtrType = SignedLong; 3744 PtrDiffType = SignedLong; 3745 } 3746 }; 3747 3748 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3749 public: 3750 DarwinI386TargetInfo(const llvm::Triple &Triple) 3751 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3752 LongDoubleWidth = 128; 3753 LongDoubleAlign = 128; 3754 SuitableAlign = 128; 3755 MaxVectorAlign = 256; 3756 // The watchOS simulator uses the builtin bool type for Objective-C. 3757 llvm::Triple T = llvm::Triple(Triple); 3758 if (T.isWatchOS()) 3759 UseSignedCharForObjCBool = false; 3760 SizeType = UnsignedLong; 3761 IntPtrType = SignedLong; 3762 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3763 HasAlignMac68kSupport = true; 3764 } 3765 3766 bool handleTargetFeatures(std::vector<std::string> &Features, 3767 DiagnosticsEngine &Diags) override { 3768 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3769 Diags)) 3770 return false; 3771 // We now know the features we have: we can decide how to align vectors. 3772 MaxVectorAlign = 3773 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3774 return true; 3775 } 3776 }; 3777 3778 // x86-32 Windows target 3779 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3780 public: 3781 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3782 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3783 WCharType = UnsignedShort; 3784 DoubleAlign = LongLongAlign = 64; 3785 bool IsWinCOFF = 3786 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3787 DataLayoutString = IsWinCOFF 3788 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3789 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3790 } 3791 void getTargetDefines(const LangOptions &Opts, 3792 MacroBuilder &Builder) const override { 3793 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3794 } 3795 }; 3796 3797 // x86-32 Windows Visual Studio target 3798 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3799 public: 3800 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3801 : WindowsX86_32TargetInfo(Triple) { 3802 LongDoubleWidth = LongDoubleAlign = 64; 3803 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3804 } 3805 void getTargetDefines(const LangOptions &Opts, 3806 MacroBuilder &Builder) const override { 3807 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3808 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3809 // The value of the following reflects processor type. 3810 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3811 // We lost the original triple, so we use the default. 3812 Builder.defineMacro("_M_IX86", "600"); 3813 } 3814 }; 3815 3816 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3817 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3818 // supports __declspec natively under -fms-extensions, but we define a no-op 3819 // __declspec macro anyway for pre-processor compatibility. 3820 if (Opts.MicrosoftExt) 3821 Builder.defineMacro("__declspec", "__declspec"); 3822 else 3823 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3824 3825 if (!Opts.MicrosoftExt) { 3826 // Provide macros for all the calling convention keywords. Provide both 3827 // single and double underscore prefixed variants. These are available on 3828 // x64 as well as x86, even though they have no effect. 3829 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3830 for (const char *CC : CCs) { 3831 std::string GCCSpelling = "__attribute__((__"; 3832 GCCSpelling += CC; 3833 GCCSpelling += "__))"; 3834 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3835 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3836 } 3837 } 3838 } 3839 3840 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3841 Builder.defineMacro("__MSVCRT__"); 3842 Builder.defineMacro("__MINGW32__"); 3843 addCygMingDefines(Opts, Builder); 3844 } 3845 3846 // x86-32 MinGW target 3847 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3848 public: 3849 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3850 : WindowsX86_32TargetInfo(Triple) {} 3851 void getTargetDefines(const LangOptions &Opts, 3852 MacroBuilder &Builder) const override { 3853 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3854 DefineStd(Builder, "WIN32", Opts); 3855 DefineStd(Builder, "WINNT", Opts); 3856 Builder.defineMacro("_X86_"); 3857 addMinGWDefines(Opts, Builder); 3858 } 3859 }; 3860 3861 // x86-32 Cygwin target 3862 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3863 public: 3864 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3865 : X86_32TargetInfo(Triple) { 3866 WCharType = UnsignedShort; 3867 DoubleAlign = LongLongAlign = 64; 3868 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3869 } 3870 void getTargetDefines(const LangOptions &Opts, 3871 MacroBuilder &Builder) const override { 3872 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3873 Builder.defineMacro("_X86_"); 3874 Builder.defineMacro("__CYGWIN__"); 3875 Builder.defineMacro("__CYGWIN32__"); 3876 addCygMingDefines(Opts, Builder); 3877 DefineStd(Builder, "unix", Opts); 3878 if (Opts.CPlusPlus) 3879 Builder.defineMacro("_GNU_SOURCE"); 3880 } 3881 }; 3882 3883 // x86-32 Haiku target 3884 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3885 public: 3886 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3887 SizeType = UnsignedLong; 3888 IntPtrType = SignedLong; 3889 PtrDiffType = SignedLong; 3890 ProcessIDType = SignedLong; 3891 this->UserLabelPrefix = ""; 3892 this->TLSSupported = false; 3893 } 3894 void getTargetDefines(const LangOptions &Opts, 3895 MacroBuilder &Builder) const override { 3896 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3897 Builder.defineMacro("__INTEL__"); 3898 Builder.defineMacro("__HAIKU__"); 3899 } 3900 }; 3901 3902 // X86-32 MCU target 3903 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3904 public: 3905 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3906 LongDoubleWidth = 64; 3907 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3908 } 3909 3910 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3911 // On MCU we support only C calling convention. 3912 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3913 } 3914 3915 void getTargetDefines(const LangOptions &Opts, 3916 MacroBuilder &Builder) const override { 3917 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3918 Builder.defineMacro("__iamcu"); 3919 Builder.defineMacro("__iamcu__"); 3920 } 3921 }; 3922 3923 // RTEMS Target 3924 template<typename Target> 3925 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3926 protected: 3927 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3928 MacroBuilder &Builder) const override { 3929 // RTEMS defines; list based off of gcc output 3930 3931 Builder.defineMacro("__rtems__"); 3932 Builder.defineMacro("__ELF__"); 3933 } 3934 3935 public: 3936 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3937 this->UserLabelPrefix = ""; 3938 3939 switch (Triple.getArch()) { 3940 default: 3941 case llvm::Triple::x86: 3942 // this->MCountName = ".mcount"; 3943 break; 3944 case llvm::Triple::mips: 3945 case llvm::Triple::mipsel: 3946 case llvm::Triple::ppc: 3947 case llvm::Triple::ppc64: 3948 case llvm::Triple::ppc64le: 3949 // this->MCountName = "_mcount"; 3950 break; 3951 case llvm::Triple::arm: 3952 // this->MCountName = "__mcount"; 3953 break; 3954 } 3955 } 3956 }; 3957 3958 // x86-32 RTEMS target 3959 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3960 public: 3961 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3962 SizeType = UnsignedLong; 3963 IntPtrType = SignedLong; 3964 PtrDiffType = SignedLong; 3965 this->UserLabelPrefix = ""; 3966 } 3967 void getTargetDefines(const LangOptions &Opts, 3968 MacroBuilder &Builder) const override { 3969 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3970 Builder.defineMacro("__INTEL__"); 3971 Builder.defineMacro("__rtems__"); 3972 } 3973 }; 3974 3975 // x86-64 generic target 3976 class X86_64TargetInfo : public X86TargetInfo { 3977 public: 3978 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3979 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3980 bool IsWinCOFF = 3981 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3982 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3983 LongDoubleWidth = 128; 3984 LongDoubleAlign = 128; 3985 LargeArrayMinWidth = 128; 3986 LargeArrayAlign = 128; 3987 SuitableAlign = 128; 3988 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3989 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3990 IntPtrType = IsX32 ? SignedInt : SignedLong; 3991 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3992 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3993 RegParmMax = 6; 3994 3995 // Pointers are 32-bit in x32. 3996 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3997 : IsWinCOFF 3998 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3999 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 4000 4001 // Use fpret only for long double. 4002 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4003 4004 // Use fp2ret for _Complex long double. 4005 ComplexLongDoubleUsesFP2Ret = true; 4006 4007 // Make __builtin_ms_va_list available. 4008 HasBuiltinMSVaList = true; 4009 4010 // x86-64 has atomics up to 16 bytes. 4011 MaxAtomicPromoteWidth = 128; 4012 MaxAtomicInlineWidth = 128; 4013 } 4014 BuiltinVaListKind getBuiltinVaListKind() const override { 4015 return TargetInfo::X86_64ABIBuiltinVaList; 4016 } 4017 4018 int getEHDataRegisterNumber(unsigned RegNo) const override { 4019 if (RegNo == 0) return 0; 4020 if (RegNo == 1) return 1; 4021 return -1; 4022 } 4023 4024 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4025 return (CC == CC_C || 4026 CC == CC_X86VectorCall || 4027 CC == CC_IntelOclBicc || 4028 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 4029 } 4030 4031 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4032 return CC_C; 4033 } 4034 4035 // for x32 we need it here explicitly 4036 bool hasInt128Type() const override { return true; } 4037 4038 bool validateGlobalRegisterVariable(StringRef RegName, 4039 unsigned RegSize, 4040 bool &HasSizeMismatch) const override { 4041 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4042 // handle. 4043 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4044 // Check that the register size is 64-bit. 4045 HasSizeMismatch = RegSize != 64; 4046 return true; 4047 } 4048 4049 // Check if the register is a 32-bit register the backend can handle. 4050 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4051 HasSizeMismatch); 4052 } 4053 }; 4054 4055 // x86-64 Windows target 4056 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4057 public: 4058 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4059 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4060 WCharType = UnsignedShort; 4061 LongWidth = LongAlign = 32; 4062 DoubleAlign = LongLongAlign = 64; 4063 IntMaxType = SignedLongLong; 4064 Int64Type = SignedLongLong; 4065 SizeType = UnsignedLongLong; 4066 PtrDiffType = SignedLongLong; 4067 IntPtrType = SignedLongLong; 4068 this->UserLabelPrefix = ""; 4069 } 4070 4071 void getTargetDefines(const LangOptions &Opts, 4072 MacroBuilder &Builder) const override { 4073 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4074 Builder.defineMacro("_WIN64"); 4075 } 4076 4077 BuiltinVaListKind getBuiltinVaListKind() const override { 4078 return TargetInfo::CharPtrBuiltinVaList; 4079 } 4080 4081 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4082 switch (CC) { 4083 case CC_X86StdCall: 4084 case CC_X86ThisCall: 4085 case CC_X86FastCall: 4086 return CCCR_Ignore; 4087 case CC_C: 4088 case CC_X86VectorCall: 4089 case CC_IntelOclBicc: 4090 case CC_X86_64SysV: 4091 return CCCR_OK; 4092 default: 4093 return CCCR_Warning; 4094 } 4095 } 4096 }; 4097 4098 // x86-64 Windows Visual Studio target 4099 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4100 public: 4101 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4102 : WindowsX86_64TargetInfo(Triple) { 4103 LongDoubleWidth = LongDoubleAlign = 64; 4104 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4105 } 4106 void getTargetDefines(const LangOptions &Opts, 4107 MacroBuilder &Builder) const override { 4108 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4109 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4110 Builder.defineMacro("_M_X64", "100"); 4111 Builder.defineMacro("_M_AMD64", "100"); 4112 } 4113 }; 4114 4115 // x86-64 MinGW target 4116 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4117 public: 4118 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4119 : WindowsX86_64TargetInfo(Triple) { 4120 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4121 // with x86 FP ops. Weird. 4122 LongDoubleWidth = LongDoubleAlign = 128; 4123 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4124 } 4125 4126 void getTargetDefines(const LangOptions &Opts, 4127 MacroBuilder &Builder) const override { 4128 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4129 DefineStd(Builder, "WIN64", Opts); 4130 Builder.defineMacro("__MINGW64__"); 4131 addMinGWDefines(Opts, Builder); 4132 4133 // GCC defines this macro when it is using __gxx_personality_seh0. 4134 if (!Opts.SjLjExceptions) 4135 Builder.defineMacro("__SEH__"); 4136 } 4137 }; 4138 4139 // x86-64 Cygwin target 4140 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4141 public: 4142 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4143 : X86_64TargetInfo(Triple) { 4144 TLSSupported = false; 4145 WCharType = UnsignedShort; 4146 } 4147 void getTargetDefines(const LangOptions &Opts, 4148 MacroBuilder &Builder) const override { 4149 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4150 Builder.defineMacro("__x86_64__"); 4151 Builder.defineMacro("__CYGWIN__"); 4152 Builder.defineMacro("__CYGWIN64__"); 4153 addCygMingDefines(Opts, Builder); 4154 DefineStd(Builder, "unix", Opts); 4155 if (Opts.CPlusPlus) 4156 Builder.defineMacro("_GNU_SOURCE"); 4157 4158 // GCC defines this macro when it is using __gxx_personality_seh0. 4159 if (!Opts.SjLjExceptions) 4160 Builder.defineMacro("__SEH__"); 4161 } 4162 }; 4163 4164 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4165 public: 4166 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4167 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4168 Int64Type = SignedLongLong; 4169 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4170 llvm::Triple T = llvm::Triple(Triple); 4171 if (T.isiOS()) 4172 UseSignedCharForObjCBool = false; 4173 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4174 } 4175 4176 bool handleTargetFeatures(std::vector<std::string> &Features, 4177 DiagnosticsEngine &Diags) override { 4178 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4179 Diags)) 4180 return false; 4181 // We now know the features we have: we can decide how to align vectors. 4182 MaxVectorAlign = 4183 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4184 return true; 4185 } 4186 }; 4187 4188 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4189 public: 4190 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4191 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4192 IntMaxType = SignedLongLong; 4193 Int64Type = SignedLongLong; 4194 } 4195 }; 4196 4197 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4198 public: 4199 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4200 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4201 IntMaxType = SignedLongLong; 4202 Int64Type = SignedLongLong; 4203 } 4204 }; 4205 4206 class ARMTargetInfo : public TargetInfo { 4207 // Possible FPU choices. 4208 enum FPUMode { 4209 VFP2FPU = (1 << 0), 4210 VFP3FPU = (1 << 1), 4211 VFP4FPU = (1 << 2), 4212 NeonFPU = (1 << 3), 4213 FPARMV8 = (1 << 4) 4214 }; 4215 4216 // Possible HWDiv features. 4217 enum HWDivMode { 4218 HWDivThumb = (1 << 0), 4219 HWDivARM = (1 << 1) 4220 }; 4221 4222 static bool FPUModeIsVFP(FPUMode Mode) { 4223 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4224 } 4225 4226 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4227 static const char * const GCCRegNames[]; 4228 4229 std::string ABI, CPU; 4230 4231 StringRef CPUProfile; 4232 StringRef CPUAttr; 4233 4234 enum { 4235 FP_Default, 4236 FP_VFP, 4237 FP_Neon 4238 } FPMath; 4239 4240 unsigned ArchISA; 4241 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4242 unsigned ArchProfile; 4243 unsigned ArchVersion; 4244 4245 unsigned FPU : 5; 4246 4247 unsigned IsAAPCS : 1; 4248 unsigned HWDiv : 2; 4249 4250 // Initialized via features. 4251 unsigned SoftFloat : 1; 4252 unsigned SoftFloatABI : 1; 4253 4254 unsigned CRC : 1; 4255 unsigned Crypto : 1; 4256 unsigned DSP : 1; 4257 unsigned Unaligned : 1; 4258 4259 enum { 4260 LDREX_B = (1 << 0), /// byte (8-bit) 4261 LDREX_H = (1 << 1), /// half (16-bit) 4262 LDREX_W = (1 << 2), /// word (32-bit) 4263 LDREX_D = (1 << 3), /// double (64-bit) 4264 }; 4265 4266 uint32_t LDREX; 4267 4268 // ACLE 6.5.1 Hardware floating point 4269 enum { 4270 HW_FP_HP = (1 << 1), /// half (16-bit) 4271 HW_FP_SP = (1 << 2), /// single (32-bit) 4272 HW_FP_DP = (1 << 3), /// double (64-bit) 4273 }; 4274 uint32_t HW_FP; 4275 4276 static const Builtin::Info BuiltinInfo[]; 4277 4278 void setABIAAPCS() { 4279 IsAAPCS = true; 4280 4281 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4282 const llvm::Triple &T = getTriple(); 4283 4284 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4285 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4286 T.getOS() == llvm::Triple::Bitrig) 4287 SizeType = UnsignedLong; 4288 else 4289 SizeType = UnsignedInt; 4290 4291 switch (T.getOS()) { 4292 case llvm::Triple::NetBSD: 4293 WCharType = SignedInt; 4294 break; 4295 case llvm::Triple::Win32: 4296 WCharType = UnsignedShort; 4297 break; 4298 case llvm::Triple::Linux: 4299 default: 4300 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4301 WCharType = UnsignedInt; 4302 break; 4303 } 4304 4305 UseBitFieldTypeAlignment = true; 4306 4307 ZeroLengthBitfieldBoundary = 0; 4308 4309 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4310 // so set preferred for small types to 32. 4311 if (T.isOSBinFormatMachO()) { 4312 DataLayoutString = 4313 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4314 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4315 } else if (T.isOSWindows()) { 4316 assert(!BigEndian && "Windows on ARM does not support big endian"); 4317 DataLayoutString = "e" 4318 "-m:w" 4319 "-p:32:32" 4320 "-i64:64" 4321 "-v128:64:128" 4322 "-a:0:32" 4323 "-n32" 4324 "-S64"; 4325 } else if (T.isOSNaCl()) { 4326 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4327 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4328 } else { 4329 DataLayoutString = 4330 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4331 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4332 } 4333 4334 // FIXME: Enumerated types are variable width in straight AAPCS. 4335 } 4336 4337 void setABIAPCS(bool IsAAPCS16) { 4338 const llvm::Triple &T = getTriple(); 4339 4340 IsAAPCS = false; 4341 4342 if (IsAAPCS16) 4343 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4344 else 4345 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4346 4347 // size_t is unsigned int on FreeBSD. 4348 if (T.getOS() == llvm::Triple::FreeBSD) 4349 SizeType = UnsignedInt; 4350 else 4351 SizeType = UnsignedLong; 4352 4353 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4354 WCharType = SignedInt; 4355 4356 // Do not respect the alignment of bit-field types when laying out 4357 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4358 UseBitFieldTypeAlignment = false; 4359 4360 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4361 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4362 /// gcc. 4363 ZeroLengthBitfieldBoundary = 32; 4364 4365 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4366 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4367 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4368 } else if (T.isOSBinFormatMachO()) 4369 DataLayoutString = 4370 BigEndian 4371 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4372 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4373 else 4374 DataLayoutString = 4375 BigEndian 4376 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4377 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4378 4379 // FIXME: Override "preferred align" for double and long long. 4380 } 4381 4382 void setArchInfo() { 4383 StringRef ArchName = getTriple().getArchName(); 4384 4385 ArchISA = llvm::ARM::parseArchISA(ArchName); 4386 CPU = llvm::ARM::getDefaultCPU(ArchName); 4387 unsigned AK = llvm::ARM::parseArch(ArchName); 4388 if (AK != llvm::ARM::AK_INVALID) 4389 ArchKind = AK; 4390 setArchInfo(ArchKind); 4391 } 4392 4393 void setArchInfo(unsigned Kind) { 4394 StringRef SubArch; 4395 4396 // cache TargetParser info 4397 ArchKind = Kind; 4398 SubArch = llvm::ARM::getSubArch(ArchKind); 4399 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4400 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4401 4402 // cache CPU related strings 4403 CPUAttr = getCPUAttr(); 4404 CPUProfile = getCPUProfile(); 4405 } 4406 4407 void setAtomic() { 4408 // when triple does not specify a sub arch, 4409 // then we are not using inline atomics 4410 bool ShouldUseInlineAtomic = 4411 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4412 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4413 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4414 if (ArchProfile == llvm::ARM::PK_M) { 4415 MaxAtomicPromoteWidth = 32; 4416 if (ShouldUseInlineAtomic) 4417 MaxAtomicInlineWidth = 32; 4418 } 4419 else { 4420 MaxAtomicPromoteWidth = 64; 4421 if (ShouldUseInlineAtomic) 4422 MaxAtomicInlineWidth = 64; 4423 } 4424 } 4425 4426 bool isThumb() const { 4427 return (ArchISA == llvm::ARM::IK_THUMB); 4428 } 4429 4430 bool supportsThumb() const { 4431 return CPUAttr.count('T') || ArchVersion >= 6; 4432 } 4433 4434 bool supportsThumb2() const { 4435 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4436 } 4437 4438 StringRef getCPUAttr() const { 4439 // For most sub-arches, the build attribute CPU name is enough. 4440 // For Cortex variants, it's slightly different. 4441 switch(ArchKind) { 4442 default: 4443 return llvm::ARM::getCPUAttr(ArchKind); 4444 case llvm::ARM::AK_ARMV6M: 4445 return "6M"; 4446 case llvm::ARM::AK_ARMV7S: 4447 return "7S"; 4448 case llvm::ARM::AK_ARMV7A: 4449 return "7A"; 4450 case llvm::ARM::AK_ARMV7R: 4451 return "7R"; 4452 case llvm::ARM::AK_ARMV7M: 4453 return "7M"; 4454 case llvm::ARM::AK_ARMV7EM: 4455 return "7EM"; 4456 case llvm::ARM::AK_ARMV8A: 4457 return "8A"; 4458 case llvm::ARM::AK_ARMV8_1A: 4459 return "8_1A"; 4460 } 4461 } 4462 4463 StringRef getCPUProfile() const { 4464 switch(ArchProfile) { 4465 case llvm::ARM::PK_A: 4466 return "A"; 4467 case llvm::ARM::PK_R: 4468 return "R"; 4469 case llvm::ARM::PK_M: 4470 return "M"; 4471 default: 4472 return ""; 4473 } 4474 } 4475 4476 public: 4477 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4478 : TargetInfo(Triple), FPMath(FP_Default), 4479 IsAAPCS(true), LDREX(0), HW_FP(0) { 4480 BigEndian = IsBigEndian; 4481 4482 switch (getTriple().getOS()) { 4483 case llvm::Triple::NetBSD: 4484 PtrDiffType = SignedLong; 4485 break; 4486 default: 4487 PtrDiffType = SignedInt; 4488 break; 4489 } 4490 4491 // Cache arch related info. 4492 setArchInfo(); 4493 4494 // {} in inline assembly are neon specifiers, not assembly variant 4495 // specifiers. 4496 NoAsmVariants = true; 4497 4498 // FIXME: This duplicates code from the driver that sets the -target-abi 4499 // option - this code is used if -target-abi isn't passed and should 4500 // be unified in some way. 4501 if (Triple.isOSBinFormatMachO()) { 4502 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4503 // the frontend matches that. 4504 if (Triple.getEnvironment() == llvm::Triple::EABI || 4505 Triple.getOS() == llvm::Triple::UnknownOS || 4506 StringRef(CPU).startswith("cortex-m")) { 4507 setABI("aapcs"); 4508 } else if (Triple.isWatchOS()) { 4509 setABI("aapcs16"); 4510 } else { 4511 setABI("apcs-gnu"); 4512 } 4513 } else if (Triple.isOSWindows()) { 4514 // FIXME: this is invalid for WindowsCE 4515 setABI("aapcs"); 4516 } else { 4517 // Select the default based on the platform. 4518 switch (Triple.getEnvironment()) { 4519 case llvm::Triple::Android: 4520 case llvm::Triple::GNUEABI: 4521 case llvm::Triple::GNUEABIHF: 4522 setABI("aapcs-linux"); 4523 break; 4524 case llvm::Triple::EABIHF: 4525 case llvm::Triple::EABI: 4526 setABI("aapcs"); 4527 break; 4528 case llvm::Triple::GNU: 4529 setABI("apcs-gnu"); 4530 break; 4531 default: 4532 if (Triple.getOS() == llvm::Triple::NetBSD) 4533 setABI("apcs-gnu"); 4534 else 4535 setABI("aapcs"); 4536 break; 4537 } 4538 } 4539 4540 // ARM targets default to using the ARM C++ ABI. 4541 TheCXXABI.set(TargetCXXABI::GenericARM); 4542 4543 // ARM has atomics up to 8 bytes 4544 setAtomic(); 4545 4546 // Do force alignment of members that follow zero length bitfields. If 4547 // the alignment of the zero-length bitfield is greater than the member 4548 // that follows it, `bar', `bar' will be aligned as the type of the 4549 // zero length bitfield. 4550 UseZeroLengthBitfieldAlignment = true; 4551 } 4552 4553 StringRef getABI() const override { return ABI; } 4554 4555 bool setABI(const std::string &Name) override { 4556 ABI = Name; 4557 4558 // The defaults (above) are for AAPCS, check if we need to change them. 4559 // 4560 // FIXME: We need support for -meabi... we could just mangle it into the 4561 // name. 4562 if (Name == "apcs-gnu" || Name == "aapcs16") { 4563 setABIAPCS(Name == "aapcs16"); 4564 return true; 4565 } 4566 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4567 setABIAAPCS(); 4568 return true; 4569 } 4570 return false; 4571 } 4572 4573 // FIXME: This should be based on Arch attributes, not CPU names. 4574 bool 4575 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4576 StringRef CPU, 4577 const std::vector<std::string> &FeaturesVec) const override { 4578 4579 std::vector<const char*> TargetFeatures; 4580 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4581 4582 // get default FPU features 4583 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4584 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4585 4586 // get default Extension features 4587 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4588 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4589 4590 for (const char *Feature : TargetFeatures) 4591 if (Feature[0] == '+') 4592 Features[Feature+1] = true; 4593 4594 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4595 } 4596 4597 bool handleTargetFeatures(std::vector<std::string> &Features, 4598 DiagnosticsEngine &Diags) override { 4599 FPU = 0; 4600 CRC = 0; 4601 Crypto = 0; 4602 DSP = 0; 4603 Unaligned = 1; 4604 SoftFloat = SoftFloatABI = false; 4605 HWDiv = 0; 4606 4607 // This does not diagnose illegal cases like having both 4608 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4609 uint32_t HW_FP_remove = 0; 4610 for (const auto &Feature : Features) { 4611 if (Feature == "+soft-float") { 4612 SoftFloat = true; 4613 } else if (Feature == "+soft-float-abi") { 4614 SoftFloatABI = true; 4615 } else if (Feature == "+vfp2") { 4616 FPU |= VFP2FPU; 4617 HW_FP |= HW_FP_SP | HW_FP_DP; 4618 } else if (Feature == "+vfp3") { 4619 FPU |= VFP3FPU; 4620 HW_FP |= HW_FP_SP | HW_FP_DP; 4621 } else if (Feature == "+vfp4") { 4622 FPU |= VFP4FPU; 4623 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4624 } else if (Feature == "+fp-armv8") { 4625 FPU |= FPARMV8; 4626 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4627 } else if (Feature == "+neon") { 4628 FPU |= NeonFPU; 4629 HW_FP |= HW_FP_SP | HW_FP_DP; 4630 } else if (Feature == "+hwdiv") { 4631 HWDiv |= HWDivThumb; 4632 } else if (Feature == "+hwdiv-arm") { 4633 HWDiv |= HWDivARM; 4634 } else if (Feature == "+crc") { 4635 CRC = 1; 4636 } else if (Feature == "+crypto") { 4637 Crypto = 1; 4638 } else if (Feature == "+dsp") { 4639 DSP = 1; 4640 } else if (Feature == "+fp-only-sp") { 4641 HW_FP_remove |= HW_FP_DP; 4642 } else if (Feature == "+strict-align") { 4643 Unaligned = 0; 4644 } else if (Feature == "+fp16") { 4645 HW_FP |= HW_FP_HP; 4646 } 4647 } 4648 HW_FP &= ~HW_FP_remove; 4649 4650 switch (ArchVersion) { 4651 case 6: 4652 if (ArchProfile == llvm::ARM::PK_M) 4653 LDREX = 0; 4654 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4655 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4656 else 4657 LDREX = LDREX_W; 4658 break; 4659 case 7: 4660 if (ArchProfile == llvm::ARM::PK_M) 4661 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4662 else 4663 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4664 break; 4665 case 8: 4666 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4667 } 4668 4669 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4670 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4671 return false; 4672 } 4673 4674 if (FPMath == FP_Neon) 4675 Features.push_back("+neonfp"); 4676 else if (FPMath == FP_VFP) 4677 Features.push_back("-neonfp"); 4678 4679 // Remove front-end specific options which the backend handles differently. 4680 auto Feature = 4681 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4682 if (Feature != Features.end()) 4683 Features.erase(Feature); 4684 4685 return true; 4686 } 4687 4688 bool hasFeature(StringRef Feature) const override { 4689 return llvm::StringSwitch<bool>(Feature) 4690 .Case("arm", true) 4691 .Case("aarch32", true) 4692 .Case("softfloat", SoftFloat) 4693 .Case("thumb", isThumb()) 4694 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4695 .Case("hwdiv", HWDiv & HWDivThumb) 4696 .Case("hwdiv-arm", HWDiv & HWDivARM) 4697 .Default(false); 4698 } 4699 4700 bool setCPU(const std::string &Name) override { 4701 if (Name != "generic") 4702 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4703 4704 if (ArchKind == llvm::ARM::AK_INVALID) 4705 return false; 4706 setAtomic(); 4707 CPU = Name; 4708 return true; 4709 } 4710 4711 bool setFPMath(StringRef Name) override; 4712 4713 void getTargetDefines(const LangOptions &Opts, 4714 MacroBuilder &Builder) const override { 4715 // Target identification. 4716 Builder.defineMacro("__arm"); 4717 Builder.defineMacro("__arm__"); 4718 4719 // Target properties. 4720 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4721 4722 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4723 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4724 if (getTriple().isWatchOS()) 4725 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4726 4727 if (!CPUAttr.empty()) 4728 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4729 4730 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4731 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4732 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4733 4734 if (ArchVersion >= 8) { 4735 // ACLE 6.5.7 Crypto Extension 4736 if (Crypto) 4737 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4738 // ACLE 6.5.8 CRC32 Extension 4739 if (CRC) 4740 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4741 // ACLE 6.5.10 Numeric Maximum and Minimum 4742 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4743 // ACLE 6.5.9 Directed Rounding 4744 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4745 } 4746 4747 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4748 // is not defined for the M-profile. 4749 // NOTE that the deffault profile is assumed to be 'A' 4750 if (CPUProfile.empty() || CPUProfile != "M") 4751 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4752 4753 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4754 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4755 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4756 if (supportsThumb2()) 4757 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4758 else if (supportsThumb()) 4759 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4760 4761 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4762 // instruction set such as ARM or Thumb. 4763 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4764 4765 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4766 4767 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4768 if (!CPUProfile.empty()) 4769 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4770 4771 // ACLE 6.4.3 Unaligned access supported in hardware 4772 if (Unaligned) 4773 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4774 4775 // ACLE 6.4.4 LDREX/STREX 4776 if (LDREX) 4777 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4778 4779 // ACLE 6.4.5 CLZ 4780 if (ArchVersion == 5 || 4781 (ArchVersion == 6 && CPUProfile != "M") || 4782 ArchVersion > 6) 4783 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4784 4785 // ACLE 6.5.1 Hardware Floating Point 4786 if (HW_FP) 4787 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4788 4789 // ACLE predefines. 4790 Builder.defineMacro("__ARM_ACLE", "200"); 4791 4792 // FP16 support (we currently only support IEEE format). 4793 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4794 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4795 4796 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4797 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4798 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4799 4800 // Subtarget options. 4801 4802 // FIXME: It's more complicated than this and we don't really support 4803 // interworking. 4804 // Windows on ARM does not "support" interworking 4805 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4806 Builder.defineMacro("__THUMB_INTERWORK__"); 4807 4808 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4809 // Embedded targets on Darwin follow AAPCS, but not EABI. 4810 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4811 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4812 Builder.defineMacro("__ARM_EABI__"); 4813 Builder.defineMacro("__ARM_PCS", "1"); 4814 4815 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4816 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4817 } 4818 4819 if (SoftFloat) 4820 Builder.defineMacro("__SOFTFP__"); 4821 4822 if (CPU == "xscale") 4823 Builder.defineMacro("__XSCALE__"); 4824 4825 if (isThumb()) { 4826 Builder.defineMacro("__THUMBEL__"); 4827 Builder.defineMacro("__thumb__"); 4828 if (supportsThumb2()) 4829 Builder.defineMacro("__thumb2__"); 4830 } 4831 4832 // ACLE 6.4.9 32-bit SIMD instructions 4833 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4834 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4835 4836 // ACLE 6.4.10 Hardware Integer Divide 4837 if (((HWDiv & HWDivThumb) && isThumb()) || 4838 ((HWDiv & HWDivARM) && !isThumb())) { 4839 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4840 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4841 } 4842 4843 // Note, this is always on in gcc, even though it doesn't make sense. 4844 Builder.defineMacro("__APCS_32__"); 4845 4846 if (FPUModeIsVFP((FPUMode) FPU)) { 4847 Builder.defineMacro("__VFP_FP__"); 4848 if (FPU & VFP2FPU) 4849 Builder.defineMacro("__ARM_VFPV2__"); 4850 if (FPU & VFP3FPU) 4851 Builder.defineMacro("__ARM_VFPV3__"); 4852 if (FPU & VFP4FPU) 4853 Builder.defineMacro("__ARM_VFPV4__"); 4854 } 4855 4856 // This only gets set when Neon instructions are actually available, unlike 4857 // the VFP define, hence the soft float and arch check. This is subtly 4858 // different from gcc, we follow the intent which was that it should be set 4859 // when Neon instructions are actually available. 4860 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4861 Builder.defineMacro("__ARM_NEON", "1"); 4862 Builder.defineMacro("__ARM_NEON__"); 4863 // current AArch32 NEON implementations do not support double-precision 4864 // floating-point even when it is present in VFP. 4865 Builder.defineMacro("__ARM_NEON_FP", 4866 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4867 } 4868 4869 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4870 Opts.ShortWChar ? "2" : "4"); 4871 4872 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4873 Opts.ShortEnums ? "1" : "4"); 4874 4875 if (ArchVersion >= 6 && CPUAttr != "6M") { 4876 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4877 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4878 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4879 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4880 } 4881 4882 // ACLE 6.4.7 DSP instructions 4883 if (DSP) { 4884 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4885 } 4886 4887 // ACLE 6.4.8 Saturation instructions 4888 bool SAT = false; 4889 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4890 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4891 SAT = true; 4892 } 4893 4894 // ACLE 6.4.6 Q (saturation) flag 4895 if (DSP || SAT) 4896 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4897 4898 if (Opts.UnsafeFPMath) 4899 Builder.defineMacro("__ARM_FP_FAST", "1"); 4900 4901 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4902 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4903 } 4904 4905 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4906 return llvm::makeArrayRef(BuiltinInfo, 4907 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4908 } 4909 bool isCLZForZeroUndef() const override { return false; } 4910 BuiltinVaListKind getBuiltinVaListKind() const override { 4911 return IsAAPCS 4912 ? AAPCSABIBuiltinVaList 4913 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList 4914 : TargetInfo::VoidPtrBuiltinVaList); 4915 } 4916 ArrayRef<const char *> getGCCRegNames() const override; 4917 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4918 bool validateAsmConstraint(const char *&Name, 4919 TargetInfo::ConstraintInfo &Info) const override { 4920 switch (*Name) { 4921 default: break; 4922 case 'l': // r0-r7 4923 case 'h': // r8-r15 4924 case 't': // VFP Floating point register single precision 4925 case 'w': // VFP Floating point register double precision 4926 Info.setAllowsRegister(); 4927 return true; 4928 case 'I': 4929 case 'J': 4930 case 'K': 4931 case 'L': 4932 case 'M': 4933 // FIXME 4934 return true; 4935 case 'Q': // A memory address that is a single base register. 4936 Info.setAllowsMemory(); 4937 return true; 4938 case 'U': // a memory reference... 4939 switch (Name[1]) { 4940 case 'q': // ...ARMV4 ldrsb 4941 case 'v': // ...VFP load/store (reg+constant offset) 4942 case 'y': // ...iWMMXt load/store 4943 case 't': // address valid for load/store opaque types wider 4944 // than 128-bits 4945 case 'n': // valid address for Neon doubleword vector load/store 4946 case 'm': // valid address for Neon element and structure load/store 4947 case 's': // valid address for non-offset loads/stores of quad-word 4948 // values in four ARM registers 4949 Info.setAllowsMemory(); 4950 Name++; 4951 return true; 4952 } 4953 } 4954 return false; 4955 } 4956 std::string convertConstraint(const char *&Constraint) const override { 4957 std::string R; 4958 switch (*Constraint) { 4959 case 'U': // Two-character constraint; add "^" hint for later parsing. 4960 R = std::string("^") + std::string(Constraint, 2); 4961 Constraint++; 4962 break; 4963 case 'p': // 'p' should be translated to 'r' by default. 4964 R = std::string("r"); 4965 break; 4966 default: 4967 return std::string(1, *Constraint); 4968 } 4969 return R; 4970 } 4971 bool 4972 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4973 std::string &SuggestedModifier) const override { 4974 bool isOutput = (Constraint[0] == '='); 4975 bool isInOut = (Constraint[0] == '+'); 4976 4977 // Strip off constraint modifiers. 4978 while (Constraint[0] == '=' || 4979 Constraint[0] == '+' || 4980 Constraint[0] == '&') 4981 Constraint = Constraint.substr(1); 4982 4983 switch (Constraint[0]) { 4984 default: break; 4985 case 'r': { 4986 switch (Modifier) { 4987 default: 4988 return (isInOut || isOutput || Size <= 64); 4989 case 'q': 4990 // A register of size 32 cannot fit a vector type. 4991 return false; 4992 } 4993 } 4994 } 4995 4996 return true; 4997 } 4998 const char *getClobbers() const override { 4999 // FIXME: Is this really right? 5000 return ""; 5001 } 5002 5003 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5004 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 5005 } 5006 5007 int getEHDataRegisterNumber(unsigned RegNo) const override { 5008 if (RegNo == 0) return 0; 5009 if (RegNo == 1) return 1; 5010 return -1; 5011 } 5012 5013 bool hasSjLjLowering() const override { 5014 return true; 5015 } 5016 }; 5017 5018 bool ARMTargetInfo::setFPMath(StringRef Name) { 5019 if (Name == "neon") { 5020 FPMath = FP_Neon; 5021 return true; 5022 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5023 Name == "vfp4") { 5024 FPMath = FP_VFP; 5025 return true; 5026 } 5027 return false; 5028 } 5029 5030 const char * const ARMTargetInfo::GCCRegNames[] = { 5031 // Integer registers 5032 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5033 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5034 5035 // Float registers 5036 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5037 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5038 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5039 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5040 5041 // Double registers 5042 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5043 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5044 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5045 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5046 5047 // Quad registers 5048 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5049 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5050 }; 5051 5052 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5053 return llvm::makeArrayRef(GCCRegNames); 5054 } 5055 5056 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5057 { { "a1" }, "r0" }, 5058 { { "a2" }, "r1" }, 5059 { { "a3" }, "r2" }, 5060 { { "a4" }, "r3" }, 5061 { { "v1" }, "r4" }, 5062 { { "v2" }, "r5" }, 5063 { { "v3" }, "r6" }, 5064 { { "v4" }, "r7" }, 5065 { { "v5" }, "r8" }, 5066 { { "v6", "rfp" }, "r9" }, 5067 { { "sl" }, "r10" }, 5068 { { "fp" }, "r11" }, 5069 { { "ip" }, "r12" }, 5070 { { "r13" }, "sp" }, 5071 { { "r14" }, "lr" }, 5072 { { "r15" }, "pc" }, 5073 // The S, D and Q registers overlap, but aren't really aliases; we 5074 // don't want to substitute one of these for a different-sized one. 5075 }; 5076 5077 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5078 return llvm::makeArrayRef(GCCRegAliases); 5079 } 5080 5081 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5082 #define BUILTIN(ID, TYPE, ATTRS) \ 5083 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5084 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5085 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5086 #include "clang/Basic/BuiltinsNEON.def" 5087 5088 #define BUILTIN(ID, TYPE, ATTRS) \ 5089 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5090 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5091 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5092 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5093 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5094 #include "clang/Basic/BuiltinsARM.def" 5095 }; 5096 5097 class ARMleTargetInfo : public ARMTargetInfo { 5098 public: 5099 ARMleTargetInfo(const llvm::Triple &Triple) 5100 : ARMTargetInfo(Triple, false) { } 5101 void getTargetDefines(const LangOptions &Opts, 5102 MacroBuilder &Builder) const override { 5103 Builder.defineMacro("__ARMEL__"); 5104 ARMTargetInfo::getTargetDefines(Opts, Builder); 5105 } 5106 }; 5107 5108 class ARMbeTargetInfo : public ARMTargetInfo { 5109 public: 5110 ARMbeTargetInfo(const llvm::Triple &Triple) 5111 : ARMTargetInfo(Triple, true) { } 5112 void getTargetDefines(const LangOptions &Opts, 5113 MacroBuilder &Builder) const override { 5114 Builder.defineMacro("__ARMEB__"); 5115 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5116 ARMTargetInfo::getTargetDefines(Opts, Builder); 5117 } 5118 }; 5119 5120 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5121 const llvm::Triple Triple; 5122 public: 5123 WindowsARMTargetInfo(const llvm::Triple &Triple) 5124 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5125 TLSSupported = false; 5126 WCharType = UnsignedShort; 5127 SizeType = UnsignedInt; 5128 UserLabelPrefix = ""; 5129 } 5130 void getVisualStudioDefines(const LangOptions &Opts, 5131 MacroBuilder &Builder) const { 5132 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5133 5134 // FIXME: this is invalid for WindowsCE 5135 Builder.defineMacro("_M_ARM_NT", "1"); 5136 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5137 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5138 5139 assert((Triple.getArch() == llvm::Triple::arm || 5140 Triple.getArch() == llvm::Triple::thumb) && 5141 "invalid architecture for Windows ARM target info"); 5142 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5143 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5144 5145 // TODO map the complete set of values 5146 // 31: VFPv3 40: VFPv4 5147 Builder.defineMacro("_M_ARM_FP", "31"); 5148 } 5149 BuiltinVaListKind getBuiltinVaListKind() const override { 5150 return TargetInfo::CharPtrBuiltinVaList; 5151 } 5152 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5153 switch (CC) { 5154 case CC_X86StdCall: 5155 case CC_X86ThisCall: 5156 case CC_X86FastCall: 5157 case CC_X86VectorCall: 5158 return CCCR_Ignore; 5159 case CC_C: 5160 return CCCR_OK; 5161 default: 5162 return CCCR_Warning; 5163 } 5164 } 5165 }; 5166 5167 // Windows ARM + Itanium C++ ABI Target 5168 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5169 public: 5170 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5171 : WindowsARMTargetInfo(Triple) { 5172 TheCXXABI.set(TargetCXXABI::GenericARM); 5173 } 5174 5175 void getTargetDefines(const LangOptions &Opts, 5176 MacroBuilder &Builder) const override { 5177 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5178 5179 if (Opts.MSVCCompat) 5180 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5181 } 5182 }; 5183 5184 // Windows ARM, MS (C++) ABI 5185 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5186 public: 5187 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5188 : WindowsARMTargetInfo(Triple) { 5189 TheCXXABI.set(TargetCXXABI::Microsoft); 5190 } 5191 5192 void getTargetDefines(const LangOptions &Opts, 5193 MacroBuilder &Builder) const override { 5194 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5195 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5196 } 5197 }; 5198 5199 // ARM MinGW target 5200 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5201 public: 5202 MinGWARMTargetInfo(const llvm::Triple &Triple) 5203 : WindowsARMTargetInfo(Triple) { 5204 TheCXXABI.set(TargetCXXABI::GenericARM); 5205 } 5206 5207 void getTargetDefines(const LangOptions &Opts, 5208 MacroBuilder &Builder) const override { 5209 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5210 DefineStd(Builder, "WIN32", Opts); 5211 DefineStd(Builder, "WINNT", Opts); 5212 Builder.defineMacro("_ARM_"); 5213 addMinGWDefines(Opts, Builder); 5214 } 5215 }; 5216 5217 // ARM Cygwin target 5218 class CygwinARMTargetInfo : public ARMleTargetInfo { 5219 public: 5220 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5221 TLSSupported = false; 5222 WCharType = UnsignedShort; 5223 DoubleAlign = LongLongAlign = 64; 5224 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5225 } 5226 void getTargetDefines(const LangOptions &Opts, 5227 MacroBuilder &Builder) const override { 5228 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5229 Builder.defineMacro("_ARM_"); 5230 Builder.defineMacro("__CYGWIN__"); 5231 Builder.defineMacro("__CYGWIN32__"); 5232 DefineStd(Builder, "unix", Opts); 5233 if (Opts.CPlusPlus) 5234 Builder.defineMacro("_GNU_SOURCE"); 5235 } 5236 }; 5237 5238 class DarwinARMTargetInfo : 5239 public DarwinTargetInfo<ARMleTargetInfo> { 5240 protected: 5241 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5242 MacroBuilder &Builder) const override { 5243 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5244 } 5245 5246 public: 5247 DarwinARMTargetInfo(const llvm::Triple &Triple) 5248 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5249 HasAlignMac68kSupport = true; 5250 // iOS always has 64-bit atomic instructions. 5251 // FIXME: This should be based off of the target features in 5252 // ARMleTargetInfo. 5253 MaxAtomicInlineWidth = 64; 5254 5255 if (Triple.isWatchOS()) { 5256 // Darwin on iOS uses a variant of the ARM C++ ABI. 5257 TheCXXABI.set(TargetCXXABI::WatchOS); 5258 5259 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5260 // size_t is long, it's a bit weird for it to be int. 5261 PtrDiffType = SignedLong; 5262 5263 // BOOL should be a real boolean on the new ABI 5264 UseSignedCharForObjCBool = false; 5265 } else 5266 TheCXXABI.set(TargetCXXABI::iOS); 5267 } 5268 }; 5269 5270 class AArch64TargetInfo : public TargetInfo { 5271 virtual void setDataLayoutString() = 0; 5272 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5273 static const char *const GCCRegNames[]; 5274 5275 enum FPUModeEnum { 5276 FPUMode, 5277 NeonMode 5278 }; 5279 5280 unsigned FPU; 5281 unsigned CRC; 5282 unsigned Crypto; 5283 unsigned Unaligned; 5284 unsigned V8_1A; 5285 5286 static const Builtin::Info BuiltinInfo[]; 5287 5288 std::string ABI; 5289 5290 public: 5291 AArch64TargetInfo(const llvm::Triple &Triple) 5292 : TargetInfo(Triple), ABI("aapcs") { 5293 5294 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5295 WCharType = SignedInt; 5296 5297 // NetBSD apparently prefers consistency across ARM targets to consistency 5298 // across 64-bit targets. 5299 Int64Type = SignedLongLong; 5300 IntMaxType = SignedLongLong; 5301 } else { 5302 WCharType = UnsignedInt; 5303 Int64Type = SignedLong; 5304 IntMaxType = SignedLong; 5305 } 5306 5307 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5308 MaxVectorAlign = 128; 5309 MaxAtomicInlineWidth = 128; 5310 MaxAtomicPromoteWidth = 128; 5311 5312 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5313 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5314 5315 // {} in inline assembly are neon specifiers, not assembly variant 5316 // specifiers. 5317 NoAsmVariants = true; 5318 5319 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5320 // contributes to the alignment of the containing aggregate in the same way 5321 // a plain (non bit-field) member of that type would, without exception for 5322 // zero-sized or anonymous bit-fields." 5323 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5324 UseZeroLengthBitfieldAlignment = true; 5325 5326 // AArch64 targets default to using the ARM C++ ABI. 5327 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5328 } 5329 5330 StringRef getABI() const override { return ABI; } 5331 bool setABI(const std::string &Name) override { 5332 if (Name != "aapcs" && Name != "darwinpcs") 5333 return false; 5334 5335 ABI = Name; 5336 return true; 5337 } 5338 5339 bool setCPU(const std::string &Name) override { 5340 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5341 .Case("generic", true) 5342 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5343 "cortex-a35", "exynos-m1", true) 5344 .Case("cyclone", true) 5345 .Default(false); 5346 return CPUKnown; 5347 } 5348 5349 void getTargetDefines(const LangOptions &Opts, 5350 MacroBuilder &Builder) const override { 5351 // Target identification. 5352 Builder.defineMacro("__aarch64__"); 5353 5354 // Target properties. 5355 Builder.defineMacro("_LP64"); 5356 Builder.defineMacro("__LP64__"); 5357 5358 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5359 Builder.defineMacro("__ARM_ACLE", "200"); 5360 Builder.defineMacro("__ARM_ARCH", "8"); 5361 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5362 5363 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5364 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5365 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5366 5367 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5368 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5369 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5370 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5371 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5372 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5373 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5374 5375 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5376 5377 // 0xe implies support for half, single and double precision operations. 5378 Builder.defineMacro("__ARM_FP", "0xE"); 5379 5380 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5381 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5382 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5383 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5384 5385 if (Opts.UnsafeFPMath) 5386 Builder.defineMacro("__ARM_FP_FAST", "1"); 5387 5388 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5389 5390 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5391 Opts.ShortEnums ? "1" : "4"); 5392 5393 if (FPU == NeonMode) { 5394 Builder.defineMacro("__ARM_NEON", "1"); 5395 // 64-bit NEON supports half, single and double precision operations. 5396 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5397 } 5398 5399 if (CRC) 5400 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5401 5402 if (Crypto) 5403 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5404 5405 if (Unaligned) 5406 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5407 5408 if (V8_1A) 5409 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5410 5411 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5413 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5415 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5416 } 5417 5418 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5419 return llvm::makeArrayRef(BuiltinInfo, 5420 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5421 } 5422 5423 bool hasFeature(StringRef Feature) const override { 5424 return Feature == "aarch64" || 5425 Feature == "arm64" || 5426 Feature == "arm" || 5427 (Feature == "neon" && FPU == NeonMode); 5428 } 5429 5430 bool handleTargetFeatures(std::vector<std::string> &Features, 5431 DiagnosticsEngine &Diags) override { 5432 FPU = FPUMode; 5433 CRC = 0; 5434 Crypto = 0; 5435 Unaligned = 1; 5436 V8_1A = 0; 5437 5438 for (const auto &Feature : Features) { 5439 if (Feature == "+neon") 5440 FPU = NeonMode; 5441 if (Feature == "+crc") 5442 CRC = 1; 5443 if (Feature == "+crypto") 5444 Crypto = 1; 5445 if (Feature == "+strict-align") 5446 Unaligned = 0; 5447 if (Feature == "+v8.1a") 5448 V8_1A = 1; 5449 } 5450 5451 setDataLayoutString(); 5452 5453 return true; 5454 } 5455 5456 bool isCLZForZeroUndef() const override { return false; } 5457 5458 BuiltinVaListKind getBuiltinVaListKind() const override { 5459 return TargetInfo::AArch64ABIBuiltinVaList; 5460 } 5461 5462 ArrayRef<const char *> getGCCRegNames() const override; 5463 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5464 5465 bool validateAsmConstraint(const char *&Name, 5466 TargetInfo::ConstraintInfo &Info) const override { 5467 switch (*Name) { 5468 default: 5469 return false; 5470 case 'w': // Floating point and SIMD registers (V0-V31) 5471 Info.setAllowsRegister(); 5472 return true; 5473 case 'I': // Constant that can be used with an ADD instruction 5474 case 'J': // Constant that can be used with a SUB instruction 5475 case 'K': // Constant that can be used with a 32-bit logical instruction 5476 case 'L': // Constant that can be used with a 64-bit logical instruction 5477 case 'M': // Constant that can be used as a 32-bit MOV immediate 5478 case 'N': // Constant that can be used as a 64-bit MOV immediate 5479 case 'Y': // Floating point constant zero 5480 case 'Z': // Integer constant zero 5481 return true; 5482 case 'Q': // A memory reference with base register and no offset 5483 Info.setAllowsMemory(); 5484 return true; 5485 case 'S': // A symbolic address 5486 Info.setAllowsRegister(); 5487 return true; 5488 case 'U': 5489 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5490 // Utf: A memory address suitable for ldp/stp in TF mode. 5491 // Usa: An absolute symbolic address. 5492 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5493 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5494 case 'z': // Zero register, wzr or xzr 5495 Info.setAllowsRegister(); 5496 return true; 5497 case 'x': // Floating point and SIMD registers (V0-V15) 5498 Info.setAllowsRegister(); 5499 return true; 5500 } 5501 return false; 5502 } 5503 5504 bool 5505 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5506 std::string &SuggestedModifier) const override { 5507 // Strip off constraint modifiers. 5508 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5509 Constraint = Constraint.substr(1); 5510 5511 switch (Constraint[0]) { 5512 default: 5513 return true; 5514 case 'z': 5515 case 'r': { 5516 switch (Modifier) { 5517 case 'x': 5518 case 'w': 5519 // For now assume that the person knows what they're 5520 // doing with the modifier. 5521 return true; 5522 default: 5523 // By default an 'r' constraint will be in the 'x' 5524 // registers. 5525 if (Size == 64) 5526 return true; 5527 5528 SuggestedModifier = "w"; 5529 return false; 5530 } 5531 } 5532 } 5533 } 5534 5535 const char *getClobbers() const override { return ""; } 5536 5537 int getEHDataRegisterNumber(unsigned RegNo) const override { 5538 if (RegNo == 0) 5539 return 0; 5540 if (RegNo == 1) 5541 return 1; 5542 return -1; 5543 } 5544 }; 5545 5546 const char *const AArch64TargetInfo::GCCRegNames[] = { 5547 // 32-bit Integer registers 5548 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5549 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5550 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5551 5552 // 64-bit Integer registers 5553 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5554 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5555 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5556 5557 // 32-bit floating point regsisters 5558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5559 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5560 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5561 5562 // 64-bit floating point regsisters 5563 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5564 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5565 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5566 5567 // Vector registers 5568 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5569 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5570 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5571 }; 5572 5573 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5574 return llvm::makeArrayRef(GCCRegNames); 5575 } 5576 5577 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5578 { { "w31" }, "wsp" }, 5579 { { "x29" }, "fp" }, 5580 { { "x30" }, "lr" }, 5581 { { "x31" }, "sp" }, 5582 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5583 // don't want to substitute one of these for a different-sized one. 5584 }; 5585 5586 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5587 return llvm::makeArrayRef(GCCRegAliases); 5588 } 5589 5590 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5591 #define BUILTIN(ID, TYPE, ATTRS) \ 5592 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5593 #include "clang/Basic/BuiltinsNEON.def" 5594 5595 #define BUILTIN(ID, TYPE, ATTRS) \ 5596 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5597 #include "clang/Basic/BuiltinsAArch64.def" 5598 }; 5599 5600 class AArch64leTargetInfo : public AArch64TargetInfo { 5601 void setDataLayoutString() override { 5602 if (getTriple().isOSBinFormatMachO()) 5603 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5604 else 5605 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5606 } 5607 5608 public: 5609 AArch64leTargetInfo(const llvm::Triple &Triple) 5610 : AArch64TargetInfo(Triple) { 5611 BigEndian = false; 5612 } 5613 void getTargetDefines(const LangOptions &Opts, 5614 MacroBuilder &Builder) const override { 5615 Builder.defineMacro("__AARCH64EL__"); 5616 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5617 } 5618 }; 5619 5620 class AArch64beTargetInfo : public AArch64TargetInfo { 5621 void setDataLayoutString() override { 5622 assert(!getTriple().isOSBinFormatMachO()); 5623 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5624 } 5625 5626 public: 5627 AArch64beTargetInfo(const llvm::Triple &Triple) 5628 : AArch64TargetInfo(Triple) { } 5629 void getTargetDefines(const LangOptions &Opts, 5630 MacroBuilder &Builder) const override { 5631 Builder.defineMacro("__AARCH64EB__"); 5632 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5633 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5634 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5635 } 5636 }; 5637 5638 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5639 protected: 5640 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5641 MacroBuilder &Builder) const override { 5642 Builder.defineMacro("__AARCH64_SIMD__"); 5643 Builder.defineMacro("__ARM64_ARCH_8__"); 5644 Builder.defineMacro("__ARM_NEON__"); 5645 Builder.defineMacro("__LITTLE_ENDIAN__"); 5646 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5647 Builder.defineMacro("__arm64", "1"); 5648 Builder.defineMacro("__arm64__", "1"); 5649 5650 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5651 } 5652 5653 public: 5654 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5655 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5656 Int64Type = SignedLongLong; 5657 WCharType = SignedInt; 5658 UseSignedCharForObjCBool = false; 5659 5660 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5661 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5662 5663 TheCXXABI.set(TargetCXXABI::iOS64); 5664 } 5665 5666 BuiltinVaListKind getBuiltinVaListKind() const override { 5667 return TargetInfo::CharPtrBuiltinVaList; 5668 } 5669 }; 5670 5671 // Hexagon abstract base class 5672 class HexagonTargetInfo : public TargetInfo { 5673 static const Builtin::Info BuiltinInfo[]; 5674 static const char * const GCCRegNames[]; 5675 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5676 std::string CPU; 5677 bool HasHVX, HasHVXDouble; 5678 5679 public: 5680 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5681 BigEndian = false; 5682 DataLayoutString = "e-m:e-p:32:32:32-" 5683 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-" 5684 "f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"; 5685 SizeType = UnsignedInt; 5686 PtrDiffType = SignedInt; 5687 IntPtrType = SignedInt; 5688 5689 // {} in inline assembly are packet specifiers, not assembly variant 5690 // specifiers. 5691 NoAsmVariants = true; 5692 5693 LargeArrayMinWidth = 64; 5694 LargeArrayAlign = 64; 5695 UseBitFieldTypeAlignment = true; 5696 ZeroLengthBitfieldBoundary = 32; 5697 HasHVX = HasHVXDouble = false; 5698 } 5699 5700 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5701 return llvm::makeArrayRef(BuiltinInfo, 5702 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5703 } 5704 5705 bool validateAsmConstraint(const char *&Name, 5706 TargetInfo::ConstraintInfo &Info) const override { 5707 return true; 5708 } 5709 5710 void getTargetDefines(const LangOptions &Opts, 5711 MacroBuilder &Builder) const override; 5712 5713 bool isCLZForZeroUndef() const override { return false; } 5714 5715 bool hasFeature(StringRef Feature) const override { 5716 return llvm::StringSwitch<bool>(Feature) 5717 .Case("hexagon", true) 5718 .Case("hvx", HasHVX) 5719 .Case("hvx-double", HasHVXDouble) 5720 .Default(false); 5721 } 5722 5723 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5724 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5725 const override; 5726 5727 bool handleTargetFeatures(std::vector<std::string> &Features, 5728 DiagnosticsEngine &Diags) override; 5729 5730 BuiltinVaListKind getBuiltinVaListKind() const override { 5731 return TargetInfo::CharPtrBuiltinVaList; 5732 } 5733 ArrayRef<const char *> getGCCRegNames() const override; 5734 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5735 const char *getClobbers() const override { 5736 return ""; 5737 } 5738 5739 static const char *getHexagonCPUSuffix(StringRef Name) { 5740 return llvm::StringSwitch<const char*>(Name) 5741 .Case("hexagonv4", "4") 5742 .Case("hexagonv5", "5") 5743 .Case("hexagonv55", "55") 5744 .Case("hexagonv60", "60") 5745 .Default(nullptr); 5746 } 5747 5748 bool setCPU(const std::string &Name) override { 5749 if (!getHexagonCPUSuffix(Name)) 5750 return false; 5751 CPU = Name; 5752 return true; 5753 } 5754 5755 int getEHDataRegisterNumber(unsigned RegNo) const override { 5756 return RegNo < 2 ? RegNo : -1; 5757 } 5758 }; 5759 5760 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5761 MacroBuilder &Builder) const { 5762 Builder.defineMacro("__qdsp6__", "1"); 5763 Builder.defineMacro("__hexagon__", "1"); 5764 5765 if (CPU == "hexagonv4") { 5766 Builder.defineMacro("__HEXAGON_V4__"); 5767 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5768 if (Opts.HexagonQdsp6Compat) { 5769 Builder.defineMacro("__QDSP6_V4__"); 5770 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5771 } 5772 } else if (CPU == "hexagonv5") { 5773 Builder.defineMacro("__HEXAGON_V5__"); 5774 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5775 if(Opts.HexagonQdsp6Compat) { 5776 Builder.defineMacro("__QDSP6_V5__"); 5777 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5778 } 5779 } else if (CPU == "hexagonv60") { 5780 Builder.defineMacro("__HEXAGON_V60__"); 5781 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5782 Builder.defineMacro("__QDSP6_V60__"); 5783 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5784 } 5785 } 5786 5787 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5788 DiagnosticsEngine &Diags) { 5789 for (auto &F : Features) { 5790 if (F == "+hvx") 5791 HasHVX = true; 5792 else if (F == "-hvx") 5793 HasHVX = HasHVXDouble = false; 5794 else if (F == "+hvx-double") 5795 HasHVX = HasHVXDouble = true; 5796 else if (F == "-hvx-double") 5797 HasHVXDouble = false; 5798 } 5799 return true; 5800 } 5801 5802 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5803 DiagnosticsEngine &Diags, StringRef CPU, 5804 const std::vector<std::string> &FeaturesVec) const { 5805 // Default for v60: -hvx, -hvx-double. 5806 Features["hvx"] = false; 5807 Features["hvx-double"] = false; 5808 5809 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5810 } 5811 5812 5813 const char *const HexagonTargetInfo::GCCRegNames[] = { 5814 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5815 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5816 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5817 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5818 "p0", "p1", "p2", "p3", 5819 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5820 }; 5821 5822 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5823 return llvm::makeArrayRef(GCCRegNames); 5824 } 5825 5826 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5827 { { "sp" }, "r29" }, 5828 { { "fp" }, "r30" }, 5829 { { "lr" }, "r31" }, 5830 }; 5831 5832 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5833 return llvm::makeArrayRef(GCCRegAliases); 5834 } 5835 5836 5837 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5838 #define BUILTIN(ID, TYPE, ATTRS) \ 5839 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5840 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5841 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5842 #include "clang/Basic/BuiltinsHexagon.def" 5843 }; 5844 5845 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5846 class SparcTargetInfo : public TargetInfo { 5847 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5848 static const char * const GCCRegNames[]; 5849 bool SoftFloat; 5850 public: 5851 SparcTargetInfo(const llvm::Triple &Triple) 5852 : TargetInfo(Triple), SoftFloat(false) {} 5853 5854 bool handleTargetFeatures(std::vector<std::string> &Features, 5855 DiagnosticsEngine &Diags) override { 5856 // The backend doesn't actually handle soft float yet, but in case someone 5857 // is using the support for the front end continue to support it. 5858 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5859 if (Feature != Features.end()) { 5860 SoftFloat = true; 5861 Features.erase(Feature); 5862 } 5863 return true; 5864 } 5865 void getTargetDefines(const LangOptions &Opts, 5866 MacroBuilder &Builder) const override { 5867 DefineStd(Builder, "sparc", Opts); 5868 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5869 5870 if (SoftFloat) 5871 Builder.defineMacro("SOFT_FLOAT", "1"); 5872 } 5873 5874 bool hasFeature(StringRef Feature) const override { 5875 return llvm::StringSwitch<bool>(Feature) 5876 .Case("softfloat", SoftFloat) 5877 .Case("sparc", true) 5878 .Default(false); 5879 } 5880 5881 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5882 // FIXME: Implement! 5883 return None; 5884 } 5885 BuiltinVaListKind getBuiltinVaListKind() const override { 5886 return TargetInfo::VoidPtrBuiltinVaList; 5887 } 5888 ArrayRef<const char *> getGCCRegNames() const override; 5889 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5890 bool validateAsmConstraint(const char *&Name, 5891 TargetInfo::ConstraintInfo &info) const override { 5892 // FIXME: Implement! 5893 switch (*Name) { 5894 case 'I': // Signed 13-bit constant 5895 case 'J': // Zero 5896 case 'K': // 32-bit constant with the low 12 bits clear 5897 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5898 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5899 case 'N': // Same as 'K' but zext (required for SIMode) 5900 case 'O': // The constant 4096 5901 return true; 5902 } 5903 return false; 5904 } 5905 const char *getClobbers() const override { 5906 // FIXME: Implement! 5907 return ""; 5908 } 5909 5910 // No Sparc V7 for now, the backend doesn't support it anyway. 5911 enum CPUKind { 5912 CK_GENERIC, 5913 CK_V8, 5914 CK_SUPERSPARC, 5915 CK_SPARCLITE, 5916 CK_F934, 5917 CK_HYPERSPARC, 5918 CK_SPARCLITE86X, 5919 CK_SPARCLET, 5920 CK_TSC701, 5921 CK_V9, 5922 CK_ULTRASPARC, 5923 CK_ULTRASPARC3, 5924 CK_NIAGARA, 5925 CK_NIAGARA2, 5926 CK_NIAGARA3, 5927 CK_NIAGARA4 5928 } CPU = CK_GENERIC; 5929 5930 enum CPUGeneration { 5931 CG_V8, 5932 CG_V9, 5933 }; 5934 5935 CPUGeneration getCPUGeneration(CPUKind Kind) const { 5936 switch (Kind) { 5937 case CK_GENERIC: 5938 case CK_V8: 5939 case CK_SUPERSPARC: 5940 case CK_SPARCLITE: 5941 case CK_F934: 5942 case CK_HYPERSPARC: 5943 case CK_SPARCLITE86X: 5944 case CK_SPARCLET: 5945 case CK_TSC701: 5946 return CG_V8; 5947 case CK_V9: 5948 case CK_ULTRASPARC: 5949 case CK_ULTRASPARC3: 5950 case CK_NIAGARA: 5951 case CK_NIAGARA2: 5952 case CK_NIAGARA3: 5953 case CK_NIAGARA4: 5954 return CG_V9; 5955 } 5956 llvm_unreachable("Unexpected CPU kind"); 5957 } 5958 5959 CPUKind getCPUKind(StringRef Name) const { 5960 return llvm::StringSwitch<CPUKind>(Name) 5961 .Case("v8", CK_V8) 5962 .Case("supersparc", CK_SUPERSPARC) 5963 .Case("sparclite", CK_SPARCLITE) 5964 .Case("f934", CK_F934) 5965 .Case("hypersparc", CK_HYPERSPARC) 5966 .Case("sparclite86x", CK_SPARCLITE86X) 5967 .Case("sparclet", CK_SPARCLET) 5968 .Case("tsc701", CK_TSC701) 5969 .Case("v9", CK_V9) 5970 .Case("ultrasparc", CK_ULTRASPARC) 5971 .Case("ultrasparc3", CK_ULTRASPARC3) 5972 .Case("niagara", CK_NIAGARA) 5973 .Case("niagara2", CK_NIAGARA2) 5974 .Case("niagara3", CK_NIAGARA3) 5975 .Case("niagara4", CK_NIAGARA4) 5976 .Default(CK_GENERIC); 5977 } 5978 5979 bool setCPU(const std::string &Name) override { 5980 CPU = getCPUKind(Name); 5981 return CPU != CK_GENERIC; 5982 } 5983 }; 5984 5985 const char * const SparcTargetInfo::GCCRegNames[] = { 5986 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5987 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5988 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5989 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5990 }; 5991 5992 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5993 return llvm::makeArrayRef(GCCRegNames); 5994 } 5995 5996 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5997 { { "g0" }, "r0" }, 5998 { { "g1" }, "r1" }, 5999 { { "g2" }, "r2" }, 6000 { { "g3" }, "r3" }, 6001 { { "g4" }, "r4" }, 6002 { { "g5" }, "r5" }, 6003 { { "g6" }, "r6" }, 6004 { { "g7" }, "r7" }, 6005 { { "o0" }, "r8" }, 6006 { { "o1" }, "r9" }, 6007 { { "o2" }, "r10" }, 6008 { { "o3" }, "r11" }, 6009 { { "o4" }, "r12" }, 6010 { { "o5" }, "r13" }, 6011 { { "o6", "sp" }, "r14" }, 6012 { { "o7" }, "r15" }, 6013 { { "l0" }, "r16" }, 6014 { { "l1" }, "r17" }, 6015 { { "l2" }, "r18" }, 6016 { { "l3" }, "r19" }, 6017 { { "l4" }, "r20" }, 6018 { { "l5" }, "r21" }, 6019 { { "l6" }, "r22" }, 6020 { { "l7" }, "r23" }, 6021 { { "i0" }, "r24" }, 6022 { { "i1" }, "r25" }, 6023 { { "i2" }, "r26" }, 6024 { { "i3" }, "r27" }, 6025 { { "i4" }, "r28" }, 6026 { { "i5" }, "r29" }, 6027 { { "i6", "fp" }, "r30" }, 6028 { { "i7" }, "r31" }, 6029 }; 6030 6031 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6032 return llvm::makeArrayRef(GCCRegAliases); 6033 } 6034 6035 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6036 class SparcV8TargetInfo : public SparcTargetInfo { 6037 public: 6038 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6039 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6040 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6041 switch (getTriple().getOS()) { 6042 default: 6043 SizeType = UnsignedInt; 6044 IntPtrType = SignedInt; 6045 PtrDiffType = SignedInt; 6046 break; 6047 case llvm::Triple::NetBSD: 6048 case llvm::Triple::OpenBSD: 6049 SizeType = UnsignedLong; 6050 IntPtrType = SignedLong; 6051 PtrDiffType = SignedLong; 6052 break; 6053 } 6054 } 6055 6056 void getTargetDefines(const LangOptions &Opts, 6057 MacroBuilder &Builder) const override { 6058 SparcTargetInfo::getTargetDefines(Opts, Builder); 6059 switch (getCPUGeneration(CPU)) { 6060 case CG_V8: 6061 Builder.defineMacro("__sparcv8"); 6062 if (getTriple().getOS() != llvm::Triple::Solaris) 6063 Builder.defineMacro("__sparcv8__"); 6064 break; 6065 case CG_V9: 6066 Builder.defineMacro("__sparcv9"); 6067 if (getTriple().getOS() != llvm::Triple::Solaris) { 6068 Builder.defineMacro("__sparcv9__"); 6069 Builder.defineMacro("__sparc_v9__"); 6070 } 6071 break; 6072 } 6073 } 6074 }; 6075 6076 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6077 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6078 public: 6079 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6080 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6081 BigEndian = false; 6082 } 6083 }; 6084 6085 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6086 class SparcV9TargetInfo : public SparcTargetInfo { 6087 public: 6088 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6089 // FIXME: Support Sparc quad-precision long double? 6090 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6091 // This is an LP64 platform. 6092 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6093 6094 // OpenBSD uses long long for int64_t and intmax_t. 6095 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6096 IntMaxType = SignedLongLong; 6097 else 6098 IntMaxType = SignedLong; 6099 Int64Type = IntMaxType; 6100 6101 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6102 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6103 LongDoubleWidth = 128; 6104 LongDoubleAlign = 128; 6105 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6106 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6107 } 6108 6109 void getTargetDefines(const LangOptions &Opts, 6110 MacroBuilder &Builder) const override { 6111 SparcTargetInfo::getTargetDefines(Opts, Builder); 6112 Builder.defineMacro("__sparcv9"); 6113 Builder.defineMacro("__arch64__"); 6114 // Solaris doesn't need these variants, but the BSDs do. 6115 if (getTriple().getOS() != llvm::Triple::Solaris) { 6116 Builder.defineMacro("__sparc64__"); 6117 Builder.defineMacro("__sparc_v9__"); 6118 Builder.defineMacro("__sparcv9__"); 6119 } 6120 } 6121 6122 bool setCPU(const std::string &Name) override { 6123 if (!SparcTargetInfo::setCPU(Name)) 6124 return false; 6125 return getCPUGeneration(CPU) == CG_V9; 6126 } 6127 }; 6128 6129 class SystemZTargetInfo : public TargetInfo { 6130 static const Builtin::Info BuiltinInfo[]; 6131 static const char *const GCCRegNames[]; 6132 std::string CPU; 6133 bool HasTransactionalExecution; 6134 bool HasVector; 6135 6136 public: 6137 SystemZTargetInfo(const llvm::Triple &Triple) 6138 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6139 HasVector(false) { 6140 IntMaxType = SignedLong; 6141 Int64Type = SignedLong; 6142 TLSSupported = true; 6143 IntWidth = IntAlign = 32; 6144 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6145 PointerWidth = PointerAlign = 64; 6146 LongDoubleWidth = 128; 6147 LongDoubleAlign = 64; 6148 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6149 DefaultAlignForAttributeAligned = 64; 6150 MinGlobalAlign = 16; 6151 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6152 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6153 } 6154 void getTargetDefines(const LangOptions &Opts, 6155 MacroBuilder &Builder) const override { 6156 Builder.defineMacro("__s390__"); 6157 Builder.defineMacro("__s390x__"); 6158 Builder.defineMacro("__zarch__"); 6159 Builder.defineMacro("__LONG_DOUBLE_128__"); 6160 6161 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6162 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6163 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6164 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6165 6166 if (HasTransactionalExecution) 6167 Builder.defineMacro("__HTM__"); 6168 if (Opts.ZVector) 6169 Builder.defineMacro("__VEC__", "10301"); 6170 } 6171 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6172 return llvm::makeArrayRef(BuiltinInfo, 6173 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6174 } 6175 6176 ArrayRef<const char *> getGCCRegNames() const override; 6177 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6178 // No aliases. 6179 return None; 6180 } 6181 bool validateAsmConstraint(const char *&Name, 6182 TargetInfo::ConstraintInfo &info) const override; 6183 const char *getClobbers() const override { 6184 // FIXME: Is this really right? 6185 return ""; 6186 } 6187 BuiltinVaListKind getBuiltinVaListKind() const override { 6188 return TargetInfo::SystemZBuiltinVaList; 6189 } 6190 bool setCPU(const std::string &Name) override { 6191 CPU = Name; 6192 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6193 .Case("z10", true) 6194 .Case("z196", true) 6195 .Case("zEC12", true) 6196 .Case("z13", true) 6197 .Default(false); 6198 6199 return CPUKnown; 6200 } 6201 bool 6202 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6203 StringRef CPU, 6204 const std::vector<std::string> &FeaturesVec) const override { 6205 if (CPU == "zEC12") 6206 Features["transactional-execution"] = true; 6207 if (CPU == "z13") { 6208 Features["transactional-execution"] = true; 6209 Features["vector"] = true; 6210 } 6211 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6212 } 6213 6214 bool handleTargetFeatures(std::vector<std::string> &Features, 6215 DiagnosticsEngine &Diags) override { 6216 HasTransactionalExecution = false; 6217 for (const auto &Feature : Features) { 6218 if (Feature == "+transactional-execution") 6219 HasTransactionalExecution = true; 6220 else if (Feature == "+vector") 6221 HasVector = true; 6222 } 6223 // If we use the vector ABI, vector types are 64-bit aligned. 6224 if (HasVector) { 6225 MaxVectorAlign = 64; 6226 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6227 "-v128:64-a:8:16-n32:64"; 6228 } 6229 return true; 6230 } 6231 6232 bool hasFeature(StringRef Feature) const override { 6233 return llvm::StringSwitch<bool>(Feature) 6234 .Case("systemz", true) 6235 .Case("htm", HasTransactionalExecution) 6236 .Case("vx", HasVector) 6237 .Default(false); 6238 } 6239 6240 StringRef getABI() const override { 6241 if (HasVector) 6242 return "vector"; 6243 return ""; 6244 } 6245 6246 bool useFloat128ManglingForLongDouble() const override { 6247 return true; 6248 } 6249 }; 6250 6251 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6252 #define BUILTIN(ID, TYPE, ATTRS) \ 6253 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6254 #include "clang/Basic/BuiltinsSystemZ.def" 6255 }; 6256 6257 const char *const SystemZTargetInfo::GCCRegNames[] = { 6258 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6259 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6260 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6261 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6262 }; 6263 6264 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6265 return llvm::makeArrayRef(GCCRegNames); 6266 } 6267 6268 bool SystemZTargetInfo:: 6269 validateAsmConstraint(const char *&Name, 6270 TargetInfo::ConstraintInfo &Info) const { 6271 switch (*Name) { 6272 default: 6273 return false; 6274 6275 case 'a': // Address register 6276 case 'd': // Data register (equivalent to 'r') 6277 case 'f': // Floating-point register 6278 Info.setAllowsRegister(); 6279 return true; 6280 6281 case 'I': // Unsigned 8-bit constant 6282 case 'J': // Unsigned 12-bit constant 6283 case 'K': // Signed 16-bit constant 6284 case 'L': // Signed 20-bit displacement (on all targets we support) 6285 case 'M': // 0x7fffffff 6286 return true; 6287 6288 case 'Q': // Memory with base and unsigned 12-bit displacement 6289 case 'R': // Likewise, plus an index 6290 case 'S': // Memory with base and signed 20-bit displacement 6291 case 'T': // Likewise, plus an index 6292 Info.setAllowsMemory(); 6293 return true; 6294 } 6295 } 6296 6297 class MSP430TargetInfo : public TargetInfo { 6298 static const char *const GCCRegNames[]; 6299 6300 public: 6301 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6302 BigEndian = false; 6303 TLSSupported = false; 6304 IntWidth = 16; 6305 IntAlign = 16; 6306 LongWidth = 32; 6307 LongLongWidth = 64; 6308 LongAlign = LongLongAlign = 16; 6309 PointerWidth = 16; 6310 PointerAlign = 16; 6311 SuitableAlign = 16; 6312 SizeType = UnsignedInt; 6313 IntMaxType = SignedLongLong; 6314 IntPtrType = SignedInt; 6315 PtrDiffType = SignedInt; 6316 SigAtomicType = SignedLong; 6317 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6318 } 6319 void getTargetDefines(const LangOptions &Opts, 6320 MacroBuilder &Builder) const override { 6321 Builder.defineMacro("MSP430"); 6322 Builder.defineMacro("__MSP430__"); 6323 // FIXME: defines for different 'flavours' of MCU 6324 } 6325 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6326 // FIXME: Implement. 6327 return None; 6328 } 6329 bool hasFeature(StringRef Feature) const override { 6330 return Feature == "msp430"; 6331 } 6332 ArrayRef<const char *> getGCCRegNames() const override; 6333 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6334 // No aliases. 6335 return None; 6336 } 6337 bool validateAsmConstraint(const char *&Name, 6338 TargetInfo::ConstraintInfo &info) const override { 6339 // FIXME: implement 6340 switch (*Name) { 6341 case 'K': // the constant 1 6342 case 'L': // constant -1^20 .. 1^19 6343 case 'M': // constant 1-4: 6344 return true; 6345 } 6346 // No target constraints for now. 6347 return false; 6348 } 6349 const char *getClobbers() const override { 6350 // FIXME: Is this really right? 6351 return ""; 6352 } 6353 BuiltinVaListKind getBuiltinVaListKind() const override { 6354 // FIXME: implement 6355 return TargetInfo::CharPtrBuiltinVaList; 6356 } 6357 }; 6358 6359 const char *const MSP430TargetInfo::GCCRegNames[] = { 6360 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6361 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6362 6363 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6364 return llvm::makeArrayRef(GCCRegNames); 6365 } 6366 6367 // LLVM and Clang cannot be used directly to output native binaries for 6368 // target, but is used to compile C code to llvm bitcode with correct 6369 // type and alignment information. 6370 // 6371 // TCE uses the llvm bitcode as input and uses it for generating customized 6372 // target processor and program binary. TCE co-design environment is 6373 // publicly available in http://tce.cs.tut.fi 6374 6375 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6376 3, // opencl_global 6377 4, // opencl_local 6378 5, // opencl_constant 6379 // FIXME: generic has to be added to the target 6380 0, // opencl_generic 6381 0, // cuda_device 6382 0, // cuda_constant 6383 0 // cuda_shared 6384 }; 6385 6386 class TCETargetInfo : public TargetInfo { 6387 public: 6388 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6389 TLSSupported = false; 6390 IntWidth = 32; 6391 LongWidth = LongLongWidth = 32; 6392 PointerWidth = 32; 6393 IntAlign = 32; 6394 LongAlign = LongLongAlign = 32; 6395 PointerAlign = 32; 6396 SuitableAlign = 32; 6397 SizeType = UnsignedInt; 6398 IntMaxType = SignedLong; 6399 IntPtrType = SignedInt; 6400 PtrDiffType = SignedInt; 6401 FloatWidth = 32; 6402 FloatAlign = 32; 6403 DoubleWidth = 32; 6404 DoubleAlign = 32; 6405 LongDoubleWidth = 32; 6406 LongDoubleAlign = 32; 6407 FloatFormat = &llvm::APFloat::IEEEsingle; 6408 DoubleFormat = &llvm::APFloat::IEEEsingle; 6409 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6410 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6411 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6412 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6413 UseAddrSpaceMapMangling = true; 6414 } 6415 6416 void getTargetDefines(const LangOptions &Opts, 6417 MacroBuilder &Builder) const override { 6418 DefineStd(Builder, "tce", Opts); 6419 Builder.defineMacro("__TCE__"); 6420 Builder.defineMacro("__TCE_V1__"); 6421 } 6422 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6423 6424 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6425 const char *getClobbers() const override { return ""; } 6426 BuiltinVaListKind getBuiltinVaListKind() const override { 6427 return TargetInfo::VoidPtrBuiltinVaList; 6428 } 6429 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6430 bool validateAsmConstraint(const char *&Name, 6431 TargetInfo::ConstraintInfo &info) const override { 6432 return true; 6433 } 6434 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6435 return None; 6436 } 6437 }; 6438 6439 class BPFTargetInfo : public TargetInfo { 6440 public: 6441 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6442 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6443 SizeType = UnsignedLong; 6444 PtrDiffType = SignedLong; 6445 IntPtrType = SignedLong; 6446 IntMaxType = SignedLong; 6447 Int64Type = SignedLong; 6448 RegParmMax = 5; 6449 if (Triple.getArch() == llvm::Triple::bpfeb) { 6450 BigEndian = true; 6451 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6452 } else { 6453 BigEndian = false; 6454 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6455 } 6456 MaxAtomicPromoteWidth = 64; 6457 MaxAtomicInlineWidth = 64; 6458 TLSSupported = false; 6459 } 6460 void getTargetDefines(const LangOptions &Opts, 6461 MacroBuilder &Builder) const override { 6462 DefineStd(Builder, "bpf", Opts); 6463 Builder.defineMacro("__BPF__"); 6464 } 6465 bool hasFeature(StringRef Feature) const override { 6466 return Feature == "bpf"; 6467 } 6468 6469 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6470 const char *getClobbers() const override { 6471 return ""; 6472 } 6473 BuiltinVaListKind getBuiltinVaListKind() const override { 6474 return TargetInfo::VoidPtrBuiltinVaList; 6475 } 6476 ArrayRef<const char *> getGCCRegNames() const override { 6477 return None; 6478 } 6479 bool validateAsmConstraint(const char *&Name, 6480 TargetInfo::ConstraintInfo &info) const override { 6481 return true; 6482 } 6483 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6484 return None; 6485 } 6486 }; 6487 6488 class MipsTargetInfoBase : public TargetInfo { 6489 virtual void setDataLayoutString() = 0; 6490 6491 static const Builtin::Info BuiltinInfo[]; 6492 std::string CPU; 6493 bool IsMips16; 6494 bool IsMicromips; 6495 bool IsNan2008; 6496 bool IsSingleFloat; 6497 enum MipsFloatABI { 6498 HardFloat, SoftFloat 6499 } FloatABI; 6500 enum DspRevEnum { 6501 NoDSP, DSP1, DSP2 6502 } DspRev; 6503 bool HasMSA; 6504 6505 protected: 6506 bool HasFP64; 6507 std::string ABI; 6508 6509 public: 6510 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6511 const std::string &CPUStr) 6512 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6513 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6514 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6515 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6516 } 6517 6518 bool isNaN2008Default() const { 6519 return CPU == "mips32r6" || CPU == "mips64r6"; 6520 } 6521 6522 bool isFP64Default() const { 6523 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6524 } 6525 6526 bool isNan2008() const override { 6527 return IsNan2008; 6528 } 6529 6530 StringRef getABI() const override { return ABI; } 6531 bool setCPU(const std::string &Name) override { 6532 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6533 getTriple().getArch() == llvm::Triple::mipsel; 6534 CPU = Name; 6535 return llvm::StringSwitch<bool>(Name) 6536 .Case("mips1", IsMips32) 6537 .Case("mips2", IsMips32) 6538 .Case("mips3", true) 6539 .Case("mips4", true) 6540 .Case("mips5", true) 6541 .Case("mips32", IsMips32) 6542 .Case("mips32r2", IsMips32) 6543 .Case("mips32r3", IsMips32) 6544 .Case("mips32r5", IsMips32) 6545 .Case("mips32r6", IsMips32) 6546 .Case("mips64", true) 6547 .Case("mips64r2", true) 6548 .Case("mips64r3", true) 6549 .Case("mips64r5", true) 6550 .Case("mips64r6", true) 6551 .Case("octeon", true) 6552 .Case("p5600", true) 6553 .Default(false); 6554 } 6555 const std::string& getCPU() const { return CPU; } 6556 bool 6557 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6558 StringRef CPU, 6559 const std::vector<std::string> &FeaturesVec) const override { 6560 if (CPU == "octeon") 6561 Features["mips64r2"] = Features["cnmips"] = true; 6562 else 6563 Features[CPU] = true; 6564 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6565 } 6566 6567 void getTargetDefines(const LangOptions &Opts, 6568 MacroBuilder &Builder) const override { 6569 Builder.defineMacro("__mips__"); 6570 Builder.defineMacro("_mips"); 6571 if (Opts.GNUMode) 6572 Builder.defineMacro("mips"); 6573 6574 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6575 6576 switch (FloatABI) { 6577 case HardFloat: 6578 Builder.defineMacro("__mips_hard_float", Twine(1)); 6579 break; 6580 case SoftFloat: 6581 Builder.defineMacro("__mips_soft_float", Twine(1)); 6582 break; 6583 } 6584 6585 if (IsSingleFloat) 6586 Builder.defineMacro("__mips_single_float", Twine(1)); 6587 6588 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6589 Builder.defineMacro("_MIPS_FPSET", 6590 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6591 6592 if (IsMips16) 6593 Builder.defineMacro("__mips16", Twine(1)); 6594 6595 if (IsMicromips) 6596 Builder.defineMacro("__mips_micromips", Twine(1)); 6597 6598 if (IsNan2008) 6599 Builder.defineMacro("__mips_nan2008", Twine(1)); 6600 6601 switch (DspRev) { 6602 default: 6603 break; 6604 case DSP1: 6605 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6606 Builder.defineMacro("__mips_dsp", Twine(1)); 6607 break; 6608 case DSP2: 6609 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6610 Builder.defineMacro("__mips_dspr2", Twine(1)); 6611 Builder.defineMacro("__mips_dsp", Twine(1)); 6612 break; 6613 } 6614 6615 if (HasMSA) 6616 Builder.defineMacro("__mips_msa", Twine(1)); 6617 6618 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6619 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6620 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6621 6622 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6623 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6624 6625 // These shouldn't be defined for MIPS-I but there's no need to check 6626 // for that since MIPS-I isn't supported. 6627 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6628 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6629 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6630 } 6631 6632 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6633 return llvm::makeArrayRef(BuiltinInfo, 6634 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6635 } 6636 bool hasFeature(StringRef Feature) const override { 6637 return llvm::StringSwitch<bool>(Feature) 6638 .Case("mips", true) 6639 .Case("fp64", HasFP64) 6640 .Default(false); 6641 } 6642 BuiltinVaListKind getBuiltinVaListKind() const override { 6643 return TargetInfo::VoidPtrBuiltinVaList; 6644 } 6645 ArrayRef<const char *> getGCCRegNames() const override { 6646 static const char *const GCCRegNames[] = { 6647 // CPU register names 6648 // Must match second column of GCCRegAliases 6649 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6650 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6651 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6652 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6653 // Floating point register names 6654 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6655 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6656 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6657 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6658 // Hi/lo and condition register names 6659 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6660 "$fcc5","$fcc6","$fcc7", 6661 // MSA register names 6662 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6663 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6664 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6665 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6666 // MSA control register names 6667 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6668 "$msarequest", "$msamap", "$msaunmap" 6669 }; 6670 return llvm::makeArrayRef(GCCRegNames); 6671 } 6672 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6673 bool validateAsmConstraint(const char *&Name, 6674 TargetInfo::ConstraintInfo &Info) const override { 6675 switch (*Name) { 6676 default: 6677 return false; 6678 case 'r': // CPU registers. 6679 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6680 case 'y': // Equivalent to "r", backward compatibility only. 6681 case 'f': // floating-point registers. 6682 case 'c': // $25 for indirect jumps 6683 case 'l': // lo register 6684 case 'x': // hilo register pair 6685 Info.setAllowsRegister(); 6686 return true; 6687 case 'I': // Signed 16-bit constant 6688 case 'J': // Integer 0 6689 case 'K': // Unsigned 16-bit constant 6690 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6691 case 'M': // Constants not loadable via lui, addiu, or ori 6692 case 'N': // Constant -1 to -65535 6693 case 'O': // A signed 15-bit constant 6694 case 'P': // A constant between 1 go 65535 6695 return true; 6696 case 'R': // An address that can be used in a non-macro load or store 6697 Info.setAllowsMemory(); 6698 return true; 6699 case 'Z': 6700 if (Name[1] == 'C') { // An address usable by ll, and sc. 6701 Info.setAllowsMemory(); 6702 Name++; // Skip over 'Z'. 6703 return true; 6704 } 6705 return false; 6706 } 6707 } 6708 6709 std::string convertConstraint(const char *&Constraint) const override { 6710 std::string R; 6711 switch (*Constraint) { 6712 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6713 if (Constraint[1] == 'C') { 6714 R = std::string("^") + std::string(Constraint, 2); 6715 Constraint++; 6716 return R; 6717 } 6718 break; 6719 } 6720 return TargetInfo::convertConstraint(Constraint); 6721 } 6722 6723 const char *getClobbers() const override { 6724 // In GCC, $1 is not widely used in generated code (it's used only in a few 6725 // specific situations), so there is no real need for users to add it to 6726 // the clobbers list if they want to use it in their inline assembly code. 6727 // 6728 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6729 // code generation, so using it in inline assembly without adding it to the 6730 // clobbers list can cause conflicts between the inline assembly code and 6731 // the surrounding generated code. 6732 // 6733 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6734 // operands, which will conflict with the ".set at" assembler option (which 6735 // we use only for inline assembly, in order to maintain compatibility with 6736 // GCC) and will also conflict with the user's usage of $1. 6737 // 6738 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6739 // register for generated code is to automatically clobber $1 for all inline 6740 // assembly code. 6741 // 6742 // FIXME: We should automatically clobber $1 only for inline assembly code 6743 // which actually uses it. This would allow LLVM to use $1 for inline 6744 // assembly operands if the user's assembly code doesn't use it. 6745 return "~{$1}"; 6746 } 6747 6748 bool handleTargetFeatures(std::vector<std::string> &Features, 6749 DiagnosticsEngine &Diags) override { 6750 IsMips16 = false; 6751 IsMicromips = false; 6752 IsNan2008 = isNaN2008Default(); 6753 IsSingleFloat = false; 6754 FloatABI = HardFloat; 6755 DspRev = NoDSP; 6756 HasFP64 = isFP64Default(); 6757 6758 for (const auto &Feature : Features) { 6759 if (Feature == "+single-float") 6760 IsSingleFloat = true; 6761 else if (Feature == "+soft-float") 6762 FloatABI = SoftFloat; 6763 else if (Feature == "+mips16") 6764 IsMips16 = true; 6765 else if (Feature == "+micromips") 6766 IsMicromips = true; 6767 else if (Feature == "+dsp") 6768 DspRev = std::max(DspRev, DSP1); 6769 else if (Feature == "+dspr2") 6770 DspRev = std::max(DspRev, DSP2); 6771 else if (Feature == "+msa") 6772 HasMSA = true; 6773 else if (Feature == "+fp64") 6774 HasFP64 = true; 6775 else if (Feature == "-fp64") 6776 HasFP64 = false; 6777 else if (Feature == "+nan2008") 6778 IsNan2008 = true; 6779 else if (Feature == "-nan2008") 6780 IsNan2008 = false; 6781 } 6782 6783 setDataLayoutString(); 6784 6785 return true; 6786 } 6787 6788 int getEHDataRegisterNumber(unsigned RegNo) const override { 6789 if (RegNo == 0) return 4; 6790 if (RegNo == 1) return 5; 6791 return -1; 6792 } 6793 6794 bool isCLZForZeroUndef() const override { return false; } 6795 }; 6796 6797 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6798 #define BUILTIN(ID, TYPE, ATTRS) \ 6799 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6800 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6801 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6802 #include "clang/Basic/BuiltinsMips.def" 6803 }; 6804 6805 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6806 public: 6807 Mips32TargetInfoBase(const llvm::Triple &Triple) 6808 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6809 SizeType = UnsignedInt; 6810 PtrDiffType = SignedInt; 6811 Int64Type = SignedLongLong; 6812 IntMaxType = Int64Type; 6813 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6814 } 6815 bool setABI(const std::string &Name) override { 6816 if (Name == "o32" || Name == "eabi") { 6817 ABI = Name; 6818 return true; 6819 } 6820 return false; 6821 } 6822 void getTargetDefines(const LangOptions &Opts, 6823 MacroBuilder &Builder) const override { 6824 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6825 6826 Builder.defineMacro("__mips", "32"); 6827 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6828 6829 const std::string& CPUStr = getCPU(); 6830 if (CPUStr == "mips32") 6831 Builder.defineMacro("__mips_isa_rev", "1"); 6832 else if (CPUStr == "mips32r2") 6833 Builder.defineMacro("__mips_isa_rev", "2"); 6834 else if (CPUStr == "mips32r3") 6835 Builder.defineMacro("__mips_isa_rev", "3"); 6836 else if (CPUStr == "mips32r5") 6837 Builder.defineMacro("__mips_isa_rev", "5"); 6838 else if (CPUStr == "mips32r6") 6839 Builder.defineMacro("__mips_isa_rev", "6"); 6840 6841 if (ABI == "o32") { 6842 Builder.defineMacro("__mips_o32"); 6843 Builder.defineMacro("_ABIO32", "1"); 6844 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6845 } 6846 else if (ABI == "eabi") 6847 Builder.defineMacro("__mips_eabi"); 6848 else 6849 llvm_unreachable("Invalid ABI for Mips32."); 6850 } 6851 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6852 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6853 { { "at" }, "$1" }, 6854 { { "v0" }, "$2" }, 6855 { { "v1" }, "$3" }, 6856 { { "a0" }, "$4" }, 6857 { { "a1" }, "$5" }, 6858 { { "a2" }, "$6" }, 6859 { { "a3" }, "$7" }, 6860 { { "t0" }, "$8" }, 6861 { { "t1" }, "$9" }, 6862 { { "t2" }, "$10" }, 6863 { { "t3" }, "$11" }, 6864 { { "t4" }, "$12" }, 6865 { { "t5" }, "$13" }, 6866 { { "t6" }, "$14" }, 6867 { { "t7" }, "$15" }, 6868 { { "s0" }, "$16" }, 6869 { { "s1" }, "$17" }, 6870 { { "s2" }, "$18" }, 6871 { { "s3" }, "$19" }, 6872 { { "s4" }, "$20" }, 6873 { { "s5" }, "$21" }, 6874 { { "s6" }, "$22" }, 6875 { { "s7" }, "$23" }, 6876 { { "t8" }, "$24" }, 6877 { { "t9" }, "$25" }, 6878 { { "k0" }, "$26" }, 6879 { { "k1" }, "$27" }, 6880 { { "gp" }, "$28" }, 6881 { { "sp","$sp" }, "$29" }, 6882 { { "fp","$fp" }, "$30" }, 6883 { { "ra" }, "$31" } 6884 }; 6885 return llvm::makeArrayRef(GCCRegAliases); 6886 } 6887 }; 6888 6889 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6890 void setDataLayoutString() override { 6891 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6892 } 6893 6894 public: 6895 Mips32EBTargetInfo(const llvm::Triple &Triple) 6896 : Mips32TargetInfoBase(Triple) { 6897 } 6898 void getTargetDefines(const LangOptions &Opts, 6899 MacroBuilder &Builder) const override { 6900 DefineStd(Builder, "MIPSEB", Opts); 6901 Builder.defineMacro("_MIPSEB"); 6902 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6903 } 6904 }; 6905 6906 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6907 void setDataLayoutString() override { 6908 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6909 } 6910 6911 public: 6912 Mips32ELTargetInfo(const llvm::Triple &Triple) 6913 : Mips32TargetInfoBase(Triple) { 6914 BigEndian = false; 6915 } 6916 void getTargetDefines(const LangOptions &Opts, 6917 MacroBuilder &Builder) const override { 6918 DefineStd(Builder, "MIPSEL", Opts); 6919 Builder.defineMacro("_MIPSEL"); 6920 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6921 } 6922 }; 6923 6924 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6925 public: 6926 Mips64TargetInfoBase(const llvm::Triple &Triple) 6927 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6928 LongDoubleWidth = LongDoubleAlign = 128; 6929 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6930 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6931 LongDoubleWidth = LongDoubleAlign = 64; 6932 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6933 } 6934 setN64ABITypes(); 6935 SuitableAlign = 128; 6936 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6937 } 6938 6939 void setN64ABITypes() { 6940 LongWidth = LongAlign = 64; 6941 PointerWidth = PointerAlign = 64; 6942 SizeType = UnsignedLong; 6943 PtrDiffType = SignedLong; 6944 Int64Type = SignedLong; 6945 IntMaxType = Int64Type; 6946 } 6947 6948 void setN32ABITypes() { 6949 LongWidth = LongAlign = 32; 6950 PointerWidth = PointerAlign = 32; 6951 SizeType = UnsignedInt; 6952 PtrDiffType = SignedInt; 6953 Int64Type = SignedLongLong; 6954 IntMaxType = Int64Type; 6955 } 6956 6957 bool setABI(const std::string &Name) override { 6958 if (Name == "n32") { 6959 setN32ABITypes(); 6960 ABI = Name; 6961 return true; 6962 } 6963 if (Name == "n64") { 6964 setN64ABITypes(); 6965 ABI = Name; 6966 return true; 6967 } 6968 return false; 6969 } 6970 6971 void getTargetDefines(const LangOptions &Opts, 6972 MacroBuilder &Builder) const override { 6973 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6974 6975 Builder.defineMacro("__mips", "64"); 6976 Builder.defineMacro("__mips64"); 6977 Builder.defineMacro("__mips64__"); 6978 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6979 6980 const std::string& CPUStr = getCPU(); 6981 if (CPUStr == "mips64") 6982 Builder.defineMacro("__mips_isa_rev", "1"); 6983 else if (CPUStr == "mips64r2") 6984 Builder.defineMacro("__mips_isa_rev", "2"); 6985 else if (CPUStr == "mips64r3") 6986 Builder.defineMacro("__mips_isa_rev", "3"); 6987 else if (CPUStr == "mips64r5") 6988 Builder.defineMacro("__mips_isa_rev", "5"); 6989 else if (CPUStr == "mips64r6") 6990 Builder.defineMacro("__mips_isa_rev", "6"); 6991 6992 if (ABI == "n32") { 6993 Builder.defineMacro("__mips_n32"); 6994 Builder.defineMacro("_ABIN32", "2"); 6995 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6996 } 6997 else if (ABI == "n64") { 6998 Builder.defineMacro("__mips_n64"); 6999 Builder.defineMacro("_ABI64", "3"); 7000 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7001 } 7002 else 7003 llvm_unreachable("Invalid ABI for Mips64."); 7004 7005 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7006 } 7007 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7008 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7009 { { "at" }, "$1" }, 7010 { { "v0" }, "$2" }, 7011 { { "v1" }, "$3" }, 7012 { { "a0" }, "$4" }, 7013 { { "a1" }, "$5" }, 7014 { { "a2" }, "$6" }, 7015 { { "a3" }, "$7" }, 7016 { { "a4" }, "$8" }, 7017 { { "a5" }, "$9" }, 7018 { { "a6" }, "$10" }, 7019 { { "a7" }, "$11" }, 7020 { { "t0" }, "$12" }, 7021 { { "t1" }, "$13" }, 7022 { { "t2" }, "$14" }, 7023 { { "t3" }, "$15" }, 7024 { { "s0" }, "$16" }, 7025 { { "s1" }, "$17" }, 7026 { { "s2" }, "$18" }, 7027 { { "s3" }, "$19" }, 7028 { { "s4" }, "$20" }, 7029 { { "s5" }, "$21" }, 7030 { { "s6" }, "$22" }, 7031 { { "s7" }, "$23" }, 7032 { { "t8" }, "$24" }, 7033 { { "t9" }, "$25" }, 7034 { { "k0" }, "$26" }, 7035 { { "k1" }, "$27" }, 7036 { { "gp" }, "$28" }, 7037 { { "sp","$sp" }, "$29" }, 7038 { { "fp","$fp" }, "$30" }, 7039 { { "ra" }, "$31" } 7040 }; 7041 return llvm::makeArrayRef(GCCRegAliases); 7042 } 7043 7044 bool hasInt128Type() const override { return true; } 7045 }; 7046 7047 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7048 void setDataLayoutString() override { 7049 if (ABI == "n32") 7050 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7051 else 7052 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7053 7054 } 7055 7056 public: 7057 Mips64EBTargetInfo(const llvm::Triple &Triple) 7058 : Mips64TargetInfoBase(Triple) {} 7059 void getTargetDefines(const LangOptions &Opts, 7060 MacroBuilder &Builder) const override { 7061 DefineStd(Builder, "MIPSEB", Opts); 7062 Builder.defineMacro("_MIPSEB"); 7063 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7064 } 7065 }; 7066 7067 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7068 void setDataLayoutString() override { 7069 if (ABI == "n32") 7070 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7071 else 7072 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7073 } 7074 public: 7075 Mips64ELTargetInfo(const llvm::Triple &Triple) 7076 : Mips64TargetInfoBase(Triple) { 7077 // Default ABI is n64. 7078 BigEndian = false; 7079 } 7080 void getTargetDefines(const LangOptions &Opts, 7081 MacroBuilder &Builder) const override { 7082 DefineStd(Builder, "MIPSEL", Opts); 7083 Builder.defineMacro("_MIPSEL"); 7084 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7085 } 7086 }; 7087 7088 class PNaClTargetInfo : public TargetInfo { 7089 public: 7090 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7091 BigEndian = false; 7092 this->UserLabelPrefix = ""; 7093 this->LongAlign = 32; 7094 this->LongWidth = 32; 7095 this->PointerAlign = 32; 7096 this->PointerWidth = 32; 7097 this->IntMaxType = TargetInfo::SignedLongLong; 7098 this->Int64Type = TargetInfo::SignedLongLong; 7099 this->DoubleAlign = 64; 7100 this->LongDoubleWidth = 64; 7101 this->LongDoubleAlign = 64; 7102 this->SizeType = TargetInfo::UnsignedInt; 7103 this->PtrDiffType = TargetInfo::SignedInt; 7104 this->IntPtrType = TargetInfo::SignedInt; 7105 this->RegParmMax = 0; // Disallow regparm 7106 } 7107 7108 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7109 Builder.defineMacro("__le32__"); 7110 Builder.defineMacro("__pnacl__"); 7111 } 7112 void getTargetDefines(const LangOptions &Opts, 7113 MacroBuilder &Builder) const override { 7114 getArchDefines(Opts, Builder); 7115 } 7116 bool hasFeature(StringRef Feature) const override { 7117 return Feature == "pnacl"; 7118 } 7119 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7120 BuiltinVaListKind getBuiltinVaListKind() const override { 7121 return TargetInfo::PNaClABIBuiltinVaList; 7122 } 7123 ArrayRef<const char *> getGCCRegNames() const override; 7124 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7125 bool validateAsmConstraint(const char *&Name, 7126 TargetInfo::ConstraintInfo &Info) const override { 7127 return false; 7128 } 7129 7130 const char *getClobbers() const override { 7131 return ""; 7132 } 7133 }; 7134 7135 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7136 return None; 7137 } 7138 7139 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7140 return None; 7141 } 7142 7143 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7144 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7145 public: 7146 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7147 Mips32ELTargetInfo(Triple) { 7148 } 7149 7150 BuiltinVaListKind getBuiltinVaListKind() const override { 7151 return TargetInfo::PNaClABIBuiltinVaList; 7152 } 7153 }; 7154 7155 class Le64TargetInfo : public TargetInfo { 7156 static const Builtin::Info BuiltinInfo[]; 7157 7158 public: 7159 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7160 BigEndian = false; 7161 NoAsmVariants = true; 7162 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7163 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7164 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7165 } 7166 7167 void getTargetDefines(const LangOptions &Opts, 7168 MacroBuilder &Builder) const override { 7169 DefineStd(Builder, "unix", Opts); 7170 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7171 Builder.defineMacro("__ELF__"); 7172 } 7173 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7174 return llvm::makeArrayRef(BuiltinInfo, 7175 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7176 } 7177 BuiltinVaListKind getBuiltinVaListKind() const override { 7178 return TargetInfo::PNaClABIBuiltinVaList; 7179 } 7180 const char *getClobbers() const override { return ""; } 7181 ArrayRef<const char *> getGCCRegNames() const override { 7182 return None; 7183 } 7184 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7185 return None; 7186 } 7187 bool validateAsmConstraint(const char *&Name, 7188 TargetInfo::ConstraintInfo &Info) const override { 7189 return false; 7190 } 7191 7192 bool hasProtectedVisibility() const override { return false; } 7193 }; 7194 7195 class WebAssemblyTargetInfo : public TargetInfo { 7196 static const Builtin::Info BuiltinInfo[]; 7197 7198 enum SIMDEnum { 7199 NoSIMD, 7200 SIMD128, 7201 } SIMDLevel; 7202 7203 public: 7204 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7205 : TargetInfo(T), SIMDLevel(NoSIMD) { 7206 BigEndian = false; 7207 NoAsmVariants = true; 7208 SuitableAlign = 128; 7209 LargeArrayMinWidth = 128; 7210 LargeArrayAlign = 128; 7211 SimdDefaultAlign = 128; 7212 SigAtomicType = SignedLong; 7213 LongDoubleWidth = LongDoubleAlign = 128; 7214 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7215 } 7216 7217 protected: 7218 void getTargetDefines(const LangOptions &Opts, 7219 MacroBuilder &Builder) const override { 7220 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7221 if (SIMDLevel >= SIMD128) 7222 Builder.defineMacro("__wasm_simd128__"); 7223 } 7224 7225 private: 7226 bool 7227 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7228 StringRef CPU, 7229 const std::vector<std::string> &FeaturesVec) const override { 7230 if (CPU == "bleeding-edge") 7231 Features["simd128"] = true; 7232 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7233 } 7234 bool hasFeature(StringRef Feature) const final { 7235 return llvm::StringSwitch<bool>(Feature) 7236 .Case("simd128", SIMDLevel >= SIMD128) 7237 .Default(false); 7238 } 7239 bool handleTargetFeatures(std::vector<std::string> &Features, 7240 DiagnosticsEngine &Diags) final { 7241 for (const auto &Feature : Features) { 7242 if (Feature == "+simd128") { 7243 SIMDLevel = std::max(SIMDLevel, SIMD128); 7244 continue; 7245 } 7246 if (Feature == "-simd128") { 7247 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7248 continue; 7249 } 7250 7251 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7252 << "-target-feature"; 7253 return false; 7254 } 7255 return true; 7256 } 7257 bool setCPU(const std::string &Name) final { 7258 return llvm::StringSwitch<bool>(Name) 7259 .Case("mvp", true) 7260 .Case("bleeding-edge", true) 7261 .Case("generic", true) 7262 .Default(false); 7263 } 7264 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7265 return llvm::makeArrayRef(BuiltinInfo, 7266 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7267 } 7268 BuiltinVaListKind getBuiltinVaListKind() const final { 7269 return VoidPtrBuiltinVaList; 7270 } 7271 ArrayRef<const char *> getGCCRegNames() const final { 7272 return None; 7273 } 7274 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7275 return None; 7276 } 7277 bool 7278 validateAsmConstraint(const char *&Name, 7279 TargetInfo::ConstraintInfo &Info) const final { 7280 return false; 7281 } 7282 const char *getClobbers() const final { return ""; } 7283 bool isCLZForZeroUndef() const final { return false; } 7284 bool hasInt128Type() const final { return true; } 7285 IntType getIntTypeByWidth(unsigned BitWidth, 7286 bool IsSigned) const final { 7287 // WebAssembly prefers long long for explicitly 64-bit integers. 7288 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7289 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7290 } 7291 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7292 bool IsSigned) const final { 7293 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7294 return BitWidth == 64 7295 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7296 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7297 } 7298 }; 7299 7300 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7301 #define BUILTIN(ID, TYPE, ATTRS) \ 7302 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7303 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7304 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7305 #include "clang/Basic/BuiltinsWebAssembly.def" 7306 }; 7307 7308 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7309 public: 7310 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7311 : WebAssemblyTargetInfo(T) { 7312 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7313 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128"; 7314 } 7315 7316 protected: 7317 void getTargetDefines(const LangOptions &Opts, 7318 MacroBuilder &Builder) const override { 7319 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7320 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7321 } 7322 }; 7323 7324 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7325 public: 7326 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7327 : WebAssemblyTargetInfo(T) { 7328 LongAlign = LongWidth = 64; 7329 PointerAlign = PointerWidth = 64; 7330 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7331 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 7332 } 7333 7334 protected: 7335 void getTargetDefines(const LangOptions &Opts, 7336 MacroBuilder &Builder) const override { 7337 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7338 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7339 } 7340 }; 7341 7342 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7343 #define BUILTIN(ID, TYPE, ATTRS) \ 7344 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7345 #include "clang/Basic/BuiltinsLe64.def" 7346 }; 7347 7348 static const unsigned SPIRAddrSpaceMap[] = { 7349 1, // opencl_global 7350 3, // opencl_local 7351 2, // opencl_constant 7352 4, // opencl_generic 7353 0, // cuda_device 7354 0, // cuda_constant 7355 0 // cuda_shared 7356 }; 7357 class SPIRTargetInfo : public TargetInfo { 7358 public: 7359 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7360 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7361 "SPIR target must use unknown OS"); 7362 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7363 "SPIR target must use unknown environment type"); 7364 BigEndian = false; 7365 TLSSupported = false; 7366 LongWidth = LongAlign = 64; 7367 AddrSpaceMap = &SPIRAddrSpaceMap; 7368 UseAddrSpaceMapMangling = true; 7369 // Define available target features 7370 // These must be defined in sorted order! 7371 NoAsmVariants = true; 7372 } 7373 void getTargetDefines(const LangOptions &Opts, 7374 MacroBuilder &Builder) const override { 7375 DefineStd(Builder, "SPIR", Opts); 7376 } 7377 bool hasFeature(StringRef Feature) const override { 7378 return Feature == "spir"; 7379 } 7380 7381 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7382 const char *getClobbers() const override { return ""; } 7383 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7384 bool validateAsmConstraint(const char *&Name, 7385 TargetInfo::ConstraintInfo &info) const override { 7386 return true; 7387 } 7388 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7389 return None; 7390 } 7391 BuiltinVaListKind getBuiltinVaListKind() const override { 7392 return TargetInfo::VoidPtrBuiltinVaList; 7393 } 7394 7395 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7396 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7397 : CCCR_Warning; 7398 } 7399 7400 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7401 return CC_SpirFunction; 7402 } 7403 }; 7404 7405 class SPIR32TargetInfo : public SPIRTargetInfo { 7406 public: 7407 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7408 PointerWidth = PointerAlign = 32; 7409 SizeType = TargetInfo::UnsignedInt; 7410 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7411 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7412 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7413 } 7414 void getTargetDefines(const LangOptions &Opts, 7415 MacroBuilder &Builder) const override { 7416 DefineStd(Builder, "SPIR32", Opts); 7417 } 7418 }; 7419 7420 class SPIR64TargetInfo : public SPIRTargetInfo { 7421 public: 7422 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7423 PointerWidth = PointerAlign = 64; 7424 SizeType = TargetInfo::UnsignedLong; 7425 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7426 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7427 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7428 } 7429 void getTargetDefines(const LangOptions &Opts, 7430 MacroBuilder &Builder) const override { 7431 DefineStd(Builder, "SPIR64", Opts); 7432 } 7433 }; 7434 7435 class XCoreTargetInfo : public TargetInfo { 7436 static const Builtin::Info BuiltinInfo[]; 7437 public: 7438 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7439 BigEndian = false; 7440 NoAsmVariants = true; 7441 LongLongAlign = 32; 7442 SuitableAlign = 32; 7443 DoubleAlign = LongDoubleAlign = 32; 7444 SizeType = UnsignedInt; 7445 PtrDiffType = SignedInt; 7446 IntPtrType = SignedInt; 7447 WCharType = UnsignedChar; 7448 WIntType = UnsignedInt; 7449 UseZeroLengthBitfieldAlignment = true; 7450 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7451 "-f64:32-a:0:32-n32"; 7452 } 7453 void getTargetDefines(const LangOptions &Opts, 7454 MacroBuilder &Builder) const override { 7455 Builder.defineMacro("__XS1B__"); 7456 } 7457 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7458 return llvm::makeArrayRef(BuiltinInfo, 7459 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7460 } 7461 BuiltinVaListKind getBuiltinVaListKind() const override { 7462 return TargetInfo::VoidPtrBuiltinVaList; 7463 } 7464 const char *getClobbers() const override { 7465 return ""; 7466 } 7467 ArrayRef<const char *> getGCCRegNames() const override { 7468 static const char * const GCCRegNames[] = { 7469 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7470 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7471 }; 7472 return llvm::makeArrayRef(GCCRegNames); 7473 } 7474 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7475 return None; 7476 } 7477 bool validateAsmConstraint(const char *&Name, 7478 TargetInfo::ConstraintInfo &Info) const override { 7479 return false; 7480 } 7481 int getEHDataRegisterNumber(unsigned RegNo) const override { 7482 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7483 return (RegNo < 2)? RegNo : -1; 7484 } 7485 }; 7486 7487 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7488 #define BUILTIN(ID, TYPE, ATTRS) \ 7489 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7490 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7491 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7492 #include "clang/Basic/BuiltinsXCore.def" 7493 }; 7494 7495 // x86_32 Android target 7496 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7497 public: 7498 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7499 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7500 SuitableAlign = 32; 7501 LongDoubleWidth = 64; 7502 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7503 } 7504 }; 7505 7506 // x86_64 Android target 7507 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7508 public: 7509 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7510 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7511 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7512 } 7513 7514 bool useFloat128ManglingForLongDouble() const override { 7515 return true; 7516 } 7517 }; 7518 } // end anonymous namespace 7519 7520 //===----------------------------------------------------------------------===// 7521 // Driver code 7522 //===----------------------------------------------------------------------===// 7523 7524 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7525 llvm::Triple::OSType os = Triple.getOS(); 7526 7527 switch (Triple.getArch()) { 7528 default: 7529 return nullptr; 7530 7531 case llvm::Triple::xcore: 7532 return new XCoreTargetInfo(Triple); 7533 7534 case llvm::Triple::hexagon: 7535 return new HexagonTargetInfo(Triple); 7536 7537 case llvm::Triple::aarch64: 7538 if (Triple.isOSDarwin()) 7539 return new DarwinAArch64TargetInfo(Triple); 7540 7541 switch (os) { 7542 case llvm::Triple::CloudABI: 7543 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7544 case llvm::Triple::FreeBSD: 7545 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7546 case llvm::Triple::Linux: 7547 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7548 case llvm::Triple::NetBSD: 7549 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7550 default: 7551 return new AArch64leTargetInfo(Triple); 7552 } 7553 7554 case llvm::Triple::aarch64_be: 7555 switch (os) { 7556 case llvm::Triple::FreeBSD: 7557 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7558 case llvm::Triple::Linux: 7559 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7560 case llvm::Triple::NetBSD: 7561 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7562 default: 7563 return new AArch64beTargetInfo(Triple); 7564 } 7565 7566 case llvm::Triple::arm: 7567 case llvm::Triple::thumb: 7568 if (Triple.isOSBinFormatMachO()) 7569 return new DarwinARMTargetInfo(Triple); 7570 7571 switch (os) { 7572 case llvm::Triple::Linux: 7573 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7574 case llvm::Triple::FreeBSD: 7575 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7576 case llvm::Triple::NetBSD: 7577 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7578 case llvm::Triple::OpenBSD: 7579 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7580 case llvm::Triple::Bitrig: 7581 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7582 case llvm::Triple::RTEMS: 7583 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7584 case llvm::Triple::NaCl: 7585 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7586 case llvm::Triple::Win32: 7587 switch (Triple.getEnvironment()) { 7588 case llvm::Triple::Cygnus: 7589 return new CygwinARMTargetInfo(Triple); 7590 case llvm::Triple::GNU: 7591 return new MinGWARMTargetInfo(Triple); 7592 case llvm::Triple::Itanium: 7593 return new ItaniumWindowsARMleTargetInfo(Triple); 7594 case llvm::Triple::MSVC: 7595 default: // Assume MSVC for unknown environments 7596 return new MicrosoftARMleTargetInfo(Triple); 7597 } 7598 default: 7599 return new ARMleTargetInfo(Triple); 7600 } 7601 7602 case llvm::Triple::armeb: 7603 case llvm::Triple::thumbeb: 7604 if (Triple.isOSDarwin()) 7605 return new DarwinARMTargetInfo(Triple); 7606 7607 switch (os) { 7608 case llvm::Triple::Linux: 7609 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7610 case llvm::Triple::FreeBSD: 7611 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7612 case llvm::Triple::NetBSD: 7613 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7614 case llvm::Triple::OpenBSD: 7615 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7616 case llvm::Triple::Bitrig: 7617 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7618 case llvm::Triple::RTEMS: 7619 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7620 case llvm::Triple::NaCl: 7621 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7622 default: 7623 return new ARMbeTargetInfo(Triple); 7624 } 7625 7626 case llvm::Triple::bpfeb: 7627 case llvm::Triple::bpfel: 7628 return new BPFTargetInfo(Triple); 7629 7630 case llvm::Triple::msp430: 7631 return new MSP430TargetInfo(Triple); 7632 7633 case llvm::Triple::mips: 7634 switch (os) { 7635 case llvm::Triple::Linux: 7636 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7637 case llvm::Triple::RTEMS: 7638 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7639 case llvm::Triple::FreeBSD: 7640 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7641 case llvm::Triple::NetBSD: 7642 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7643 default: 7644 return new Mips32EBTargetInfo(Triple); 7645 } 7646 7647 case llvm::Triple::mipsel: 7648 switch (os) { 7649 case llvm::Triple::Linux: 7650 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7651 case llvm::Triple::RTEMS: 7652 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7653 case llvm::Triple::FreeBSD: 7654 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7655 case llvm::Triple::NetBSD: 7656 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7657 case llvm::Triple::NaCl: 7658 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7659 default: 7660 return new Mips32ELTargetInfo(Triple); 7661 } 7662 7663 case llvm::Triple::mips64: 7664 switch (os) { 7665 case llvm::Triple::Linux: 7666 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7667 case llvm::Triple::RTEMS: 7668 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7669 case llvm::Triple::FreeBSD: 7670 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7671 case llvm::Triple::NetBSD: 7672 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7673 case llvm::Triple::OpenBSD: 7674 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7675 default: 7676 return new Mips64EBTargetInfo(Triple); 7677 } 7678 7679 case llvm::Triple::mips64el: 7680 switch (os) { 7681 case llvm::Triple::Linux: 7682 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7683 case llvm::Triple::RTEMS: 7684 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7685 case llvm::Triple::FreeBSD: 7686 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7687 case llvm::Triple::NetBSD: 7688 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7689 case llvm::Triple::OpenBSD: 7690 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7691 default: 7692 return new Mips64ELTargetInfo(Triple); 7693 } 7694 7695 case llvm::Triple::le32: 7696 switch (os) { 7697 case llvm::Triple::NaCl: 7698 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7699 default: 7700 return nullptr; 7701 } 7702 7703 case llvm::Triple::le64: 7704 return new Le64TargetInfo(Triple); 7705 7706 case llvm::Triple::ppc: 7707 if (Triple.isOSDarwin()) 7708 return new DarwinPPC32TargetInfo(Triple); 7709 switch (os) { 7710 case llvm::Triple::Linux: 7711 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7712 case llvm::Triple::FreeBSD: 7713 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7714 case llvm::Triple::NetBSD: 7715 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7716 case llvm::Triple::OpenBSD: 7717 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7718 case llvm::Triple::RTEMS: 7719 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7720 default: 7721 return new PPC32TargetInfo(Triple); 7722 } 7723 7724 case llvm::Triple::ppc64: 7725 if (Triple.isOSDarwin()) 7726 return new DarwinPPC64TargetInfo(Triple); 7727 switch (os) { 7728 case llvm::Triple::Linux: 7729 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7730 case llvm::Triple::Lv2: 7731 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7732 case llvm::Triple::FreeBSD: 7733 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7734 case llvm::Triple::NetBSD: 7735 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7736 default: 7737 return new PPC64TargetInfo(Triple); 7738 } 7739 7740 case llvm::Triple::ppc64le: 7741 switch (os) { 7742 case llvm::Triple::Linux: 7743 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7744 case llvm::Triple::NetBSD: 7745 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7746 default: 7747 return new PPC64TargetInfo(Triple); 7748 } 7749 7750 case llvm::Triple::nvptx: 7751 return new NVPTX32TargetInfo(Triple); 7752 case llvm::Triple::nvptx64: 7753 return new NVPTX64TargetInfo(Triple); 7754 7755 case llvm::Triple::amdgcn: 7756 case llvm::Triple::r600: 7757 return new AMDGPUTargetInfo(Triple); 7758 7759 case llvm::Triple::sparc: 7760 switch (os) { 7761 case llvm::Triple::Linux: 7762 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7763 case llvm::Triple::Solaris: 7764 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7765 case llvm::Triple::NetBSD: 7766 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7767 case llvm::Triple::OpenBSD: 7768 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7769 case llvm::Triple::RTEMS: 7770 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7771 default: 7772 return new SparcV8TargetInfo(Triple); 7773 } 7774 7775 // The 'sparcel' architecture copies all the above cases except for Solaris. 7776 case llvm::Triple::sparcel: 7777 switch (os) { 7778 case llvm::Triple::Linux: 7779 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7780 case llvm::Triple::NetBSD: 7781 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7782 case llvm::Triple::OpenBSD: 7783 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7784 case llvm::Triple::RTEMS: 7785 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7786 default: 7787 return new SparcV8elTargetInfo(Triple); 7788 } 7789 7790 case llvm::Triple::sparcv9: 7791 switch (os) { 7792 case llvm::Triple::Linux: 7793 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7794 case llvm::Triple::Solaris: 7795 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7796 case llvm::Triple::NetBSD: 7797 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7798 case llvm::Triple::OpenBSD: 7799 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7800 case llvm::Triple::FreeBSD: 7801 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7802 default: 7803 return new SparcV9TargetInfo(Triple); 7804 } 7805 7806 case llvm::Triple::systemz: 7807 switch (os) { 7808 case llvm::Triple::Linux: 7809 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7810 default: 7811 return new SystemZTargetInfo(Triple); 7812 } 7813 7814 case llvm::Triple::tce: 7815 return new TCETargetInfo(Triple); 7816 7817 case llvm::Triple::x86: 7818 if (Triple.isOSDarwin()) 7819 return new DarwinI386TargetInfo(Triple); 7820 7821 switch (os) { 7822 case llvm::Triple::CloudABI: 7823 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7824 case llvm::Triple::Linux: { 7825 switch (Triple.getEnvironment()) { 7826 default: 7827 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7828 case llvm::Triple::Android: 7829 return new AndroidX86_32TargetInfo(Triple); 7830 } 7831 } 7832 case llvm::Triple::DragonFly: 7833 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7834 case llvm::Triple::NetBSD: 7835 return new NetBSDI386TargetInfo(Triple); 7836 case llvm::Triple::OpenBSD: 7837 return new OpenBSDI386TargetInfo(Triple); 7838 case llvm::Triple::Bitrig: 7839 return new BitrigI386TargetInfo(Triple); 7840 case llvm::Triple::FreeBSD: 7841 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7842 case llvm::Triple::KFreeBSD: 7843 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7844 case llvm::Triple::Minix: 7845 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7846 case llvm::Triple::Solaris: 7847 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7848 case llvm::Triple::Win32: { 7849 switch (Triple.getEnvironment()) { 7850 case llvm::Triple::Cygnus: 7851 return new CygwinX86_32TargetInfo(Triple); 7852 case llvm::Triple::GNU: 7853 return new MinGWX86_32TargetInfo(Triple); 7854 case llvm::Triple::Itanium: 7855 case llvm::Triple::MSVC: 7856 default: // Assume MSVC for unknown environments 7857 return new MicrosoftX86_32TargetInfo(Triple); 7858 } 7859 } 7860 case llvm::Triple::Haiku: 7861 return new HaikuX86_32TargetInfo(Triple); 7862 case llvm::Triple::RTEMS: 7863 return new RTEMSX86_32TargetInfo(Triple); 7864 case llvm::Triple::NaCl: 7865 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7866 case llvm::Triple::ELFIAMCU: 7867 return new MCUX86_32TargetInfo(Triple); 7868 default: 7869 return new X86_32TargetInfo(Triple); 7870 } 7871 7872 case llvm::Triple::x86_64: 7873 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7874 return new DarwinX86_64TargetInfo(Triple); 7875 7876 switch (os) { 7877 case llvm::Triple::CloudABI: 7878 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7879 case llvm::Triple::Linux: { 7880 switch (Triple.getEnvironment()) { 7881 default: 7882 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7883 case llvm::Triple::Android: 7884 return new AndroidX86_64TargetInfo(Triple); 7885 } 7886 } 7887 case llvm::Triple::DragonFly: 7888 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7889 case llvm::Triple::NetBSD: 7890 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7891 case llvm::Triple::OpenBSD: 7892 return new OpenBSDX86_64TargetInfo(Triple); 7893 case llvm::Triple::Bitrig: 7894 return new BitrigX86_64TargetInfo(Triple); 7895 case llvm::Triple::FreeBSD: 7896 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7897 case llvm::Triple::KFreeBSD: 7898 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7899 case llvm::Triple::Solaris: 7900 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7901 case llvm::Triple::Win32: { 7902 switch (Triple.getEnvironment()) { 7903 case llvm::Triple::Cygnus: 7904 return new CygwinX86_64TargetInfo(Triple); 7905 case llvm::Triple::GNU: 7906 return new MinGWX86_64TargetInfo(Triple); 7907 case llvm::Triple::MSVC: 7908 default: // Assume MSVC for unknown environments 7909 return new MicrosoftX86_64TargetInfo(Triple); 7910 } 7911 } 7912 case llvm::Triple::NaCl: 7913 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7914 case llvm::Triple::PS4: 7915 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7916 default: 7917 return new X86_64TargetInfo(Triple); 7918 } 7919 7920 case llvm::Triple::spir: { 7921 if (Triple.getOS() != llvm::Triple::UnknownOS || 7922 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7923 return nullptr; 7924 return new SPIR32TargetInfo(Triple); 7925 } 7926 case llvm::Triple::spir64: { 7927 if (Triple.getOS() != llvm::Triple::UnknownOS || 7928 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7929 return nullptr; 7930 return new SPIR64TargetInfo(Triple); 7931 } 7932 case llvm::Triple::wasm32: 7933 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7934 return nullptr; 7935 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7936 case llvm::Triple::wasm64: 7937 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7938 return nullptr; 7939 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7940 } 7941 } 7942 7943 /// CreateTargetInfo - Return the target info object for the specified target 7944 /// options. 7945 TargetInfo * 7946 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7947 const std::shared_ptr<TargetOptions> &Opts) { 7948 llvm::Triple Triple(Opts->Triple); 7949 7950 // Construct the target 7951 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7952 if (!Target) { 7953 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7954 return nullptr; 7955 } 7956 Target->TargetOpts = Opts; 7957 7958 // Set the target CPU if specified. 7959 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7960 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7961 return nullptr; 7962 } 7963 7964 // Set the target ABI if specified. 7965 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7966 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7967 return nullptr; 7968 } 7969 7970 // Set the fp math unit. 7971 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7972 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7973 return nullptr; 7974 } 7975 7976 // Compute the default target features, we need the target to handle this 7977 // because features may have dependencies on one another. 7978 llvm::StringMap<bool> Features; 7979 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7980 Opts->FeaturesAsWritten)) 7981 return nullptr; 7982 7983 // Add the features to the compile options. 7984 Opts->Features.clear(); 7985 for (const auto &F : Features) 7986 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7987 7988 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7989 return nullptr; 7990 7991 return Target.release(); 7992 } 7993