1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 // By default, no TLS, and we whitelist permitted architecture/OS 227 // combinations. 228 this->TLSSupported = false; 229 230 if (Triple.isMacOSX()) 231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 232 else if (Triple.isiOS()) { 233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 234 if (Triple.getArch() == llvm::Triple::x86_64 || 235 Triple.getArch() == llvm::Triple::aarch64) 236 this->TLSSupported = !Triple.isOSVersionLT(8); 237 else if (Triple.getArch() == llvm::Triple::x86 || 238 Triple.getArch() == llvm::Triple::arm || 239 Triple.getArch() == llvm::Triple::thumb) 240 this->TLSSupported = !Triple.isOSVersionLT(9); 241 } else if (Triple.isWatchOS()) 242 this->TLSSupported = !Triple.isOSVersionLT(2); 243 244 this->MCountName = "\01mcount"; 245 } 246 247 std::string isValidSectionSpecifier(StringRef SR) const override { 248 // Let MCSectionMachO validate this. 249 StringRef Segment, Section; 250 unsigned TAA, StubSize; 251 bool HasTAA; 252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 253 TAA, HasTAA, StubSize); 254 } 255 256 const char *getStaticInitSectionSpecifier() const override { 257 // FIXME: We should return 0 when building kexts. 258 return "__TEXT,__StaticInit,regular,pure_instructions"; 259 } 260 261 /// Darwin does not support protected visibility. Darwin's "default" 262 /// is very similar to ELF's "protected"; Darwin requires a "weak" 263 /// attribute on declarations that can be dynamically replaced. 264 bool hasProtectedVisibility() const override { 265 return false; 266 } 267 }; 268 269 270 // DragonFlyBSD Target 271 template<typename Target> 272 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 273 protected: 274 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 275 MacroBuilder &Builder) const override { 276 // DragonFly defines; list based off of gcc output 277 Builder.defineMacro("__DragonFly__"); 278 Builder.defineMacro("__DragonFly_cc_version", "100001"); 279 Builder.defineMacro("__ELF__"); 280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 281 Builder.defineMacro("__tune_i386__"); 282 DefineStd(Builder, "unix", Opts); 283 } 284 public: 285 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 286 : OSTargetInfo<Target>(Triple) { 287 this->UserLabelPrefix = ""; 288 289 switch (Triple.getArch()) { 290 default: 291 case llvm::Triple::x86: 292 case llvm::Triple::x86_64: 293 this->MCountName = ".mcount"; 294 break; 295 } 296 } 297 }; 298 299 #ifndef FREEBSD_CC_VERSION 300 #define FREEBSD_CC_VERSION 0U 301 #endif 302 303 // FreeBSD Target 304 template<typename Target> 305 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 306 protected: 307 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 308 MacroBuilder &Builder) const override { 309 // FreeBSD defines; list based off of gcc output 310 311 unsigned Release = Triple.getOSMajorVersion(); 312 if (Release == 0U) 313 Release = 8U; 314 unsigned CCVersion = FREEBSD_CC_VERSION; 315 if (CCVersion == 0U) 316 CCVersion = Release * 100000U + 1U; 317 318 Builder.defineMacro("__FreeBSD__", Twine(Release)); 319 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 320 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 321 DefineStd(Builder, "unix", Opts); 322 Builder.defineMacro("__ELF__"); 323 324 // On FreeBSD, wchar_t contains the number of the code point as 325 // used by the character set of the locale. These character sets are 326 // not necessarily a superset of ASCII. 327 // 328 // FIXME: This is wrong; the macro refers to the numerical values 329 // of wchar_t *literals*, which are not locale-dependent. However, 330 // FreeBSD systems apparently depend on us getting this wrong, and 331 // setting this to 1 is conforming even if all the basic source 332 // character literals have the same encoding as char and wchar_t. 333 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 334 } 335 public: 336 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 337 this->UserLabelPrefix = ""; 338 339 switch (Triple.getArch()) { 340 default: 341 case llvm::Triple::x86: 342 case llvm::Triple::x86_64: 343 this->MCountName = ".mcount"; 344 break; 345 case llvm::Triple::mips: 346 case llvm::Triple::mipsel: 347 case llvm::Triple::ppc: 348 case llvm::Triple::ppc64: 349 case llvm::Triple::ppc64le: 350 this->MCountName = "_mcount"; 351 break; 352 case llvm::Triple::arm: 353 this->MCountName = "__mcount"; 354 break; 355 } 356 } 357 }; 358 359 // GNU/kFreeBSD Target 360 template<typename Target> 361 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 362 protected: 363 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 364 MacroBuilder &Builder) const override { 365 // GNU/kFreeBSD defines; list based off of gcc output 366 367 DefineStd(Builder, "unix", Opts); 368 Builder.defineMacro("__FreeBSD_kernel__"); 369 Builder.defineMacro("__GLIBC__"); 370 Builder.defineMacro("__ELF__"); 371 if (Opts.POSIXThreads) 372 Builder.defineMacro("_REENTRANT"); 373 if (Opts.CPlusPlus) 374 Builder.defineMacro("_GNU_SOURCE"); 375 } 376 public: 377 KFreeBSDTargetInfo(const llvm::Triple &Triple) 378 : OSTargetInfo<Target>(Triple) { 379 this->UserLabelPrefix = ""; 380 } 381 }; 382 383 // Minix Target 384 template<typename Target> 385 class MinixTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // Minix defines 390 391 Builder.defineMacro("__minix", "3"); 392 Builder.defineMacro("_EM_WSIZE", "4"); 393 Builder.defineMacro("_EM_PSIZE", "4"); 394 Builder.defineMacro("_EM_SSIZE", "2"); 395 Builder.defineMacro("_EM_LSIZE", "4"); 396 Builder.defineMacro("_EM_FSIZE", "4"); 397 Builder.defineMacro("_EM_DSIZE", "8"); 398 Builder.defineMacro("__ELF__"); 399 DefineStd(Builder, "unix", Opts); 400 } 401 public: 402 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 } 405 }; 406 407 // Linux target 408 template<typename Target> 409 class LinuxTargetInfo : public OSTargetInfo<Target> { 410 protected: 411 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 412 MacroBuilder &Builder) const override { 413 // Linux defines; list based off of gcc output 414 DefineStd(Builder, "unix", Opts); 415 DefineStd(Builder, "linux", Opts); 416 Builder.defineMacro("__gnu_linux__"); 417 Builder.defineMacro("__ELF__"); 418 if (Triple.isAndroid()) { 419 Builder.defineMacro("__ANDROID__", "1"); 420 unsigned Maj, Min, Rev; 421 Triple.getEnvironmentVersion(Maj, Min, Rev); 422 this->PlatformName = "android"; 423 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 424 } 425 if (Opts.POSIXThreads) 426 Builder.defineMacro("_REENTRANT"); 427 if (Opts.CPlusPlus) 428 Builder.defineMacro("_GNU_SOURCE"); 429 } 430 public: 431 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 432 this->UserLabelPrefix = ""; 433 this->WIntType = TargetInfo::UnsignedInt; 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::ppc: 439 case llvm::Triple::ppc64: 440 case llvm::Triple::ppc64le: 441 this->MCountName = "_mcount"; 442 break; 443 } 444 } 445 446 const char *getStaticInitSectionSpecifier() const override { 447 return ".text.startup"; 448 } 449 }; 450 451 // NetBSD Target 452 template<typename Target> 453 class NetBSDTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // NetBSD defines; list based off of gcc output 458 Builder.defineMacro("__NetBSD__"); 459 Builder.defineMacro("__unix__"); 460 Builder.defineMacro("__ELF__"); 461 if (Opts.POSIXThreads) 462 Builder.defineMacro("_POSIX_THREADS"); 463 464 switch (Triple.getArch()) { 465 default: 466 break; 467 case llvm::Triple::arm: 468 case llvm::Triple::armeb: 469 case llvm::Triple::thumb: 470 case llvm::Triple::thumbeb: 471 Builder.defineMacro("__ARM_DWARF_EH__"); 472 break; 473 } 474 } 475 public: 476 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 477 this->UserLabelPrefix = ""; 478 this->MCountName = "_mcount"; 479 } 480 }; 481 482 // OpenBSD Target 483 template<typename Target> 484 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 485 protected: 486 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 487 MacroBuilder &Builder) const override { 488 // OpenBSD defines; list based off of gcc output 489 490 Builder.defineMacro("__OpenBSD__"); 491 DefineStd(Builder, "unix", Opts); 492 Builder.defineMacro("__ELF__"); 493 if (Opts.POSIXThreads) 494 Builder.defineMacro("_REENTRANT"); 495 } 496 public: 497 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 498 this->UserLabelPrefix = ""; 499 this->TLSSupported = false; 500 501 switch (Triple.getArch()) { 502 default: 503 case llvm::Triple::x86: 504 case llvm::Triple::x86_64: 505 case llvm::Triple::arm: 506 case llvm::Triple::sparc: 507 this->MCountName = "__mcount"; 508 break; 509 case llvm::Triple::mips64: 510 case llvm::Triple::mips64el: 511 case llvm::Triple::ppc: 512 case llvm::Triple::sparcv9: 513 this->MCountName = "_mcount"; 514 break; 515 } 516 } 517 }; 518 519 // Bitrig Target 520 template<typename Target> 521 class BitrigTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const override { 525 // Bitrig defines; list based off of gcc output 526 527 Builder.defineMacro("__Bitrig__"); 528 DefineStd(Builder, "unix", Opts); 529 Builder.defineMacro("__ELF__"); 530 if (Opts.POSIXThreads) 531 Builder.defineMacro("_REENTRANT"); 532 533 switch (Triple.getArch()) { 534 default: 535 break; 536 case llvm::Triple::arm: 537 case llvm::Triple::armeb: 538 case llvm::Triple::thumb: 539 case llvm::Triple::thumbeb: 540 Builder.defineMacro("__ARM_DWARF_EH__"); 541 break; 542 } 543 } 544 public: 545 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 546 this->UserLabelPrefix = ""; 547 this->MCountName = "__mcount"; 548 } 549 }; 550 551 // PSP Target 552 template<typename Target> 553 class PSPTargetInfo : public OSTargetInfo<Target> { 554 protected: 555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 556 MacroBuilder &Builder) const override { 557 // PSP defines; list based on the output of the pspdev gcc toolchain. 558 Builder.defineMacro("PSP"); 559 Builder.defineMacro("_PSP"); 560 Builder.defineMacro("__psp__"); 561 Builder.defineMacro("__ELF__"); 562 } 563 public: 564 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 565 this->UserLabelPrefix = ""; 566 } 567 }; 568 569 // PS3 PPU Target 570 template<typename Target> 571 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 572 protected: 573 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 574 MacroBuilder &Builder) const override { 575 // PS3 PPU defines. 576 Builder.defineMacro("__PPC__"); 577 Builder.defineMacro("__PPU__"); 578 Builder.defineMacro("__CELLOS_LV2__"); 579 Builder.defineMacro("__ELF__"); 580 Builder.defineMacro("__LP32__"); 581 Builder.defineMacro("_ARCH_PPC64"); 582 Builder.defineMacro("__powerpc64__"); 583 } 584 public: 585 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 586 this->UserLabelPrefix = ""; 587 this->LongWidth = this->LongAlign = 32; 588 this->PointerWidth = this->PointerAlign = 32; 589 this->IntMaxType = TargetInfo::SignedLongLong; 590 this->Int64Type = TargetInfo::SignedLongLong; 591 this->SizeType = TargetInfo::UnsignedInt; 592 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 593 } 594 }; 595 596 template <typename Target> 597 class PS4OSTargetInfo : public OSTargetInfo<Target> { 598 protected: 599 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 600 MacroBuilder &Builder) const override { 601 Builder.defineMacro("__FreeBSD__", "9"); 602 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 603 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 604 DefineStd(Builder, "unix", Opts); 605 Builder.defineMacro("__ELF__"); 606 Builder.defineMacro("__PS4__"); 607 } 608 public: 609 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 610 this->WCharType = this->UnsignedShort; 611 612 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 613 this->MaxTLSAlign = 256; 614 this->UserLabelPrefix = ""; 615 616 switch (Triple.getArch()) { 617 default: 618 case llvm::Triple::x86_64: 619 this->MCountName = ".mcount"; 620 break; 621 } 622 } 623 }; 624 625 // Solaris target 626 template<typename Target> 627 class SolarisTargetInfo : public OSTargetInfo<Target> { 628 protected: 629 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 630 MacroBuilder &Builder) const override { 631 DefineStd(Builder, "sun", Opts); 632 DefineStd(Builder, "unix", Opts); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__svr4__"); 635 Builder.defineMacro("__SVR4"); 636 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 637 // newer, but to 500 for everything else. feature_test.h has a check to 638 // ensure that you are not using C99 with an old version of X/Open or C89 639 // with a new version. 640 if (Opts.C99) 641 Builder.defineMacro("_XOPEN_SOURCE", "600"); 642 else 643 Builder.defineMacro("_XOPEN_SOURCE", "500"); 644 if (Opts.CPlusPlus) 645 Builder.defineMacro("__C99FEATURES__"); 646 Builder.defineMacro("_LARGEFILE_SOURCE"); 647 Builder.defineMacro("_LARGEFILE64_SOURCE"); 648 Builder.defineMacro("__EXTENSIONS__"); 649 Builder.defineMacro("_REENTRANT"); 650 } 651 public: 652 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 653 this->UserLabelPrefix = ""; 654 this->WCharType = this->SignedInt; 655 // FIXME: WIntType should be SignedLong 656 } 657 }; 658 659 // Windows target 660 template<typename Target> 661 class WindowsTargetInfo : public OSTargetInfo<Target> { 662 protected: 663 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 664 MacroBuilder &Builder) const override { 665 Builder.defineMacro("_WIN32"); 666 } 667 void getVisualStudioDefines(const LangOptions &Opts, 668 MacroBuilder &Builder) const { 669 if (Opts.CPlusPlus) { 670 if (Opts.RTTIData) 671 Builder.defineMacro("_CPPRTTI"); 672 673 if (Opts.CXXExceptions) 674 Builder.defineMacro("_CPPUNWIND"); 675 } 676 677 if (Opts.Bool) 678 Builder.defineMacro("__BOOL_DEFINED"); 679 680 if (!Opts.CharIsSigned) 681 Builder.defineMacro("_CHAR_UNSIGNED"); 682 683 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 684 // but it works for now. 685 if (Opts.POSIXThreads) 686 Builder.defineMacro("_MT"); 687 688 if (Opts.MSCompatibilityVersion) { 689 Builder.defineMacro("_MSC_VER", 690 Twine(Opts.MSCompatibilityVersion / 100000)); 691 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 692 // FIXME We cannot encode the revision information into 32-bits 693 Builder.defineMacro("_MSC_BUILD", Twine(1)); 694 695 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 696 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 697 } 698 699 if (Opts.MicrosoftExt) { 700 Builder.defineMacro("_MSC_EXTENSIONS"); 701 702 if (Opts.CPlusPlus11) { 703 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 704 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 705 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 706 } 707 } 708 709 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 710 } 711 712 public: 713 WindowsTargetInfo(const llvm::Triple &Triple) 714 : OSTargetInfo<Target>(Triple) {} 715 }; 716 717 template <typename Target> 718 class NaClTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 if (Opts.POSIXThreads) 723 Builder.defineMacro("_REENTRANT"); 724 if (Opts.CPlusPlus) 725 Builder.defineMacro("_GNU_SOURCE"); 726 727 DefineStd(Builder, "unix", Opts); 728 Builder.defineMacro("__ELF__"); 729 Builder.defineMacro("__native_client__"); 730 } 731 732 public: 733 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 734 this->UserLabelPrefix = ""; 735 this->LongAlign = 32; 736 this->LongWidth = 32; 737 this->PointerAlign = 32; 738 this->PointerWidth = 32; 739 this->IntMaxType = TargetInfo::SignedLongLong; 740 this->Int64Type = TargetInfo::SignedLongLong; 741 this->DoubleAlign = 64; 742 this->LongDoubleWidth = 64; 743 this->LongDoubleAlign = 64; 744 this->LongLongWidth = 64; 745 this->LongLongAlign = 64; 746 this->SizeType = TargetInfo::UnsignedInt; 747 this->PtrDiffType = TargetInfo::SignedInt; 748 this->IntPtrType = TargetInfo::SignedInt; 749 // RegParmMax is inherited from the underlying architecture 750 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 751 if (Triple.getArch() == llvm::Triple::arm) { 752 // Handled in ARM's setABI(). 753 } else if (Triple.getArch() == llvm::Triple::x86) { 754 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 755 } else if (Triple.getArch() == llvm::Triple::x86_64) { 756 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 757 } else if (Triple.getArch() == llvm::Triple::mipsel) { 758 // Handled on mips' setDataLayoutString. 759 } else { 760 assert(Triple.getArch() == llvm::Triple::le32); 761 this->DataLayoutString = "e-p:32:32-i64:64"; 762 } 763 } 764 }; 765 766 // WebAssembly target 767 template <typename Target> 768 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 769 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 770 MacroBuilder &Builder) const final { 771 // A common platform macro. 772 if (Opts.POSIXThreads) 773 Builder.defineMacro("_REENTRANT"); 774 // Follow g++ convention and predefine _GNU_SOURCE for C++. 775 if (Opts.CPlusPlus) 776 Builder.defineMacro("_GNU_SOURCE"); 777 } 778 779 // As an optimization, group static init code together in a section. 780 const char *getStaticInitSectionSpecifier() const final { 781 return ".text.__startup"; 782 } 783 784 public: 785 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 786 : OSTargetInfo<Target>(Triple) { 787 this->MCountName = "__mcount"; 788 this->UserLabelPrefix = ""; 789 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 790 } 791 }; 792 793 //===----------------------------------------------------------------------===// 794 // Specific target implementations. 795 //===----------------------------------------------------------------------===// 796 797 // PPC abstract base class 798 class PPCTargetInfo : public TargetInfo { 799 static const Builtin::Info BuiltinInfo[]; 800 static const char * const GCCRegNames[]; 801 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 802 std::string CPU; 803 804 // Target cpu features. 805 bool HasVSX; 806 bool HasP8Vector; 807 bool HasP8Crypto; 808 bool HasDirectMove; 809 bool HasQPX; 810 bool HasHTM; 811 bool HasBPERMD; 812 bool HasExtDiv; 813 814 protected: 815 std::string ABI; 816 817 public: 818 PPCTargetInfo(const llvm::Triple &Triple) 819 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 820 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 821 HasBPERMD(false), HasExtDiv(false) { 822 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 823 SimdDefaultAlign = 128; 824 LongDoubleWidth = LongDoubleAlign = 128; 825 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 826 } 827 828 /// \brief Flags for architecture specific defines. 829 typedef enum { 830 ArchDefineNone = 0, 831 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 832 ArchDefinePpcgr = 1 << 1, 833 ArchDefinePpcsq = 1 << 2, 834 ArchDefine440 = 1 << 3, 835 ArchDefine603 = 1 << 4, 836 ArchDefine604 = 1 << 5, 837 ArchDefinePwr4 = 1 << 6, 838 ArchDefinePwr5 = 1 << 7, 839 ArchDefinePwr5x = 1 << 8, 840 ArchDefinePwr6 = 1 << 9, 841 ArchDefinePwr6x = 1 << 10, 842 ArchDefinePwr7 = 1 << 11, 843 ArchDefinePwr8 = 1 << 12, 844 ArchDefineA2 = 1 << 13, 845 ArchDefineA2q = 1 << 14 846 } ArchDefineTypes; 847 848 // Note: GCC recognizes the following additional cpus: 849 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 850 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 851 // titan, rs64. 852 bool setCPU(const std::string &Name) override { 853 bool CPUKnown = llvm::StringSwitch<bool>(Name) 854 .Case("generic", true) 855 .Case("440", true) 856 .Case("450", true) 857 .Case("601", true) 858 .Case("602", true) 859 .Case("603", true) 860 .Case("603e", true) 861 .Case("603ev", true) 862 .Case("604", true) 863 .Case("604e", true) 864 .Case("620", true) 865 .Case("630", true) 866 .Case("g3", true) 867 .Case("7400", true) 868 .Case("g4", true) 869 .Case("7450", true) 870 .Case("g4+", true) 871 .Case("750", true) 872 .Case("970", true) 873 .Case("g5", true) 874 .Case("a2", true) 875 .Case("a2q", true) 876 .Case("e500mc", true) 877 .Case("e5500", true) 878 .Case("power3", true) 879 .Case("pwr3", true) 880 .Case("power4", true) 881 .Case("pwr4", true) 882 .Case("power5", true) 883 .Case("pwr5", true) 884 .Case("power5x", true) 885 .Case("pwr5x", true) 886 .Case("power6", true) 887 .Case("pwr6", true) 888 .Case("power6x", true) 889 .Case("pwr6x", true) 890 .Case("power7", true) 891 .Case("pwr7", true) 892 .Case("power8", true) 893 .Case("pwr8", true) 894 .Case("powerpc", true) 895 .Case("ppc", true) 896 .Case("powerpc64", true) 897 .Case("ppc64", true) 898 .Case("powerpc64le", true) 899 .Case("ppc64le", true) 900 .Default(false); 901 902 if (CPUKnown) 903 CPU = Name; 904 905 return CPUKnown; 906 } 907 908 909 StringRef getABI() const override { return ABI; } 910 911 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 912 return llvm::makeArrayRef(BuiltinInfo, 913 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 914 } 915 916 bool isCLZForZeroUndef() const override { return false; } 917 918 void getTargetDefines(const LangOptions &Opts, 919 MacroBuilder &Builder) const override; 920 921 bool 922 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 923 StringRef CPU, 924 const std::vector<std::string> &FeaturesVec) const override; 925 926 bool handleTargetFeatures(std::vector<std::string> &Features, 927 DiagnosticsEngine &Diags) override; 928 bool hasFeature(StringRef Feature) const override; 929 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 930 bool Enabled) const override; 931 932 ArrayRef<const char *> getGCCRegNames() const override; 933 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 934 bool validateAsmConstraint(const char *&Name, 935 TargetInfo::ConstraintInfo &Info) const override { 936 switch (*Name) { 937 default: return false; 938 case 'O': // Zero 939 break; 940 case 'b': // Base register 941 case 'f': // Floating point register 942 Info.setAllowsRegister(); 943 break; 944 // FIXME: The following are added to allow parsing. 945 // I just took a guess at what the actions should be. 946 // Also, is more specific checking needed? I.e. specific registers? 947 case 'd': // Floating point register (containing 64-bit value) 948 case 'v': // Altivec vector register 949 Info.setAllowsRegister(); 950 break; 951 case 'w': 952 switch (Name[1]) { 953 case 'd':// VSX vector register to hold vector double data 954 case 'f':// VSX vector register to hold vector float data 955 case 's':// VSX vector register to hold scalar float data 956 case 'a':// Any VSX register 957 case 'c':// An individual CR bit 958 break; 959 default: 960 return false; 961 } 962 Info.setAllowsRegister(); 963 Name++; // Skip over 'w'. 964 break; 965 case 'h': // `MQ', `CTR', or `LINK' register 966 case 'q': // `MQ' register 967 case 'c': // `CTR' register 968 case 'l': // `LINK' register 969 case 'x': // `CR' register (condition register) number 0 970 case 'y': // `CR' register (condition register) 971 case 'z': // `XER[CA]' carry bit (part of the XER register) 972 Info.setAllowsRegister(); 973 break; 974 case 'I': // Signed 16-bit constant 975 case 'J': // Unsigned 16-bit constant shifted left 16 bits 976 // (use `L' instead for SImode constants) 977 case 'K': // Unsigned 16-bit constant 978 case 'L': // Signed 16-bit constant shifted left 16 bits 979 case 'M': // Constant larger than 31 980 case 'N': // Exact power of 2 981 case 'P': // Constant whose negation is a signed 16-bit constant 982 case 'G': // Floating point constant that can be loaded into a 983 // register with one instruction per word 984 case 'H': // Integer/Floating point constant that can be loaded 985 // into a register using three instructions 986 break; 987 case 'm': // Memory operand. Note that on PowerPC targets, m can 988 // include addresses that update the base register. It 989 // is therefore only safe to use `m' in an asm statement 990 // if that asm statement accesses the operand exactly once. 991 // The asm statement must also use `%U<opno>' as a 992 // placeholder for the "update" flag in the corresponding 993 // load or store instruction. For example: 994 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 995 // is correct but: 996 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 997 // is not. Use es rather than m if you don't want the base 998 // register to be updated. 999 case 'e': 1000 if (Name[1] != 's') 1001 return false; 1002 // es: A "stable" memory operand; that is, one which does not 1003 // include any automodification of the base register. Unlike 1004 // `m', this constraint can be used in asm statements that 1005 // might access the operand several times, or that might not 1006 // access it at all. 1007 Info.setAllowsMemory(); 1008 Name++; // Skip over 'e'. 1009 break; 1010 case 'Q': // Memory operand that is an offset from a register (it is 1011 // usually better to use `m' or `es' in asm statements) 1012 case 'Z': // Memory operand that is an indexed or indirect from a 1013 // register (it is usually better to use `m' or `es' in 1014 // asm statements) 1015 Info.setAllowsMemory(); 1016 Info.setAllowsRegister(); 1017 break; 1018 case 'R': // AIX TOC entry 1019 case 'a': // Address operand that is an indexed or indirect from a 1020 // register (`p' is preferable for asm statements) 1021 case 'S': // Constant suitable as a 64-bit mask operand 1022 case 'T': // Constant suitable as a 32-bit mask operand 1023 case 'U': // System V Release 4 small data area reference 1024 case 't': // AND masks that can be performed by two rldic{l, r} 1025 // instructions 1026 case 'W': // Vector constant that does not require memory 1027 case 'j': // Vector constant that is all zeros. 1028 break; 1029 // End FIXME. 1030 } 1031 return true; 1032 } 1033 std::string convertConstraint(const char *&Constraint) const override { 1034 std::string R; 1035 switch (*Constraint) { 1036 case 'e': 1037 case 'w': 1038 // Two-character constraint; add "^" hint for later parsing. 1039 R = std::string("^") + std::string(Constraint, 2); 1040 Constraint++; 1041 break; 1042 default: 1043 return TargetInfo::convertConstraint(Constraint); 1044 } 1045 return R; 1046 } 1047 const char *getClobbers() const override { 1048 return ""; 1049 } 1050 int getEHDataRegisterNumber(unsigned RegNo) const override { 1051 if (RegNo == 0) return 3; 1052 if (RegNo == 1) return 4; 1053 return -1; 1054 } 1055 1056 bool hasSjLjLowering() const override { 1057 return true; 1058 } 1059 1060 bool useFloat128ManglingForLongDouble() const override { 1061 return LongDoubleWidth == 128 && 1062 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1063 getTriple().isOSBinFormatELF(); 1064 } 1065 }; 1066 1067 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1068 #define BUILTIN(ID, TYPE, ATTRS) \ 1069 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1070 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1071 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1072 #include "clang/Basic/BuiltinsPPC.def" 1073 }; 1074 1075 /// handleTargetFeatures - Perform initialization based on the user 1076 /// configured set of features. 1077 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1078 DiagnosticsEngine &Diags) { 1079 for (const auto &Feature : Features) { 1080 if (Feature == "+vsx") { 1081 HasVSX = true; 1082 } else if (Feature == "+bpermd") { 1083 HasBPERMD = true; 1084 } else if (Feature == "+extdiv") { 1085 HasExtDiv = true; 1086 } else if (Feature == "+power8-vector") { 1087 HasP8Vector = true; 1088 } else if (Feature == "+crypto") { 1089 HasP8Crypto = true; 1090 } else if (Feature == "+direct-move") { 1091 HasDirectMove = true; 1092 } else if (Feature == "+qpx") { 1093 HasQPX = true; 1094 } else if (Feature == "+htm") { 1095 HasHTM = true; 1096 } 1097 // TODO: Finish this list and add an assert that we've handled them 1098 // all. 1099 } 1100 1101 return true; 1102 } 1103 1104 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1105 /// #defines that are not tied to a specific subtarget. 1106 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1107 MacroBuilder &Builder) const { 1108 // Target identification. 1109 Builder.defineMacro("__ppc__"); 1110 Builder.defineMacro("__PPC__"); 1111 Builder.defineMacro("_ARCH_PPC"); 1112 Builder.defineMacro("__powerpc__"); 1113 Builder.defineMacro("__POWERPC__"); 1114 if (PointerWidth == 64) { 1115 Builder.defineMacro("_ARCH_PPC64"); 1116 Builder.defineMacro("__powerpc64__"); 1117 Builder.defineMacro("__ppc64__"); 1118 Builder.defineMacro("__PPC64__"); 1119 } 1120 1121 // Target properties. 1122 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1123 Builder.defineMacro("_LITTLE_ENDIAN"); 1124 } else { 1125 if (getTriple().getOS() != llvm::Triple::NetBSD && 1126 getTriple().getOS() != llvm::Triple::OpenBSD) 1127 Builder.defineMacro("_BIG_ENDIAN"); 1128 } 1129 1130 // ABI options. 1131 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1132 Builder.defineMacro("_CALL_ELF", "1"); 1133 if (ABI == "elfv2") 1134 Builder.defineMacro("_CALL_ELF", "2"); 1135 1136 // Subtarget options. 1137 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1138 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1139 1140 // FIXME: Should be controlled by command line option. 1141 if (LongDoubleWidth == 128) 1142 Builder.defineMacro("__LONG_DOUBLE_128__"); 1143 1144 if (Opts.AltiVec) { 1145 Builder.defineMacro("__VEC__", "10206"); 1146 Builder.defineMacro("__ALTIVEC__"); 1147 } 1148 1149 // CPU identification. 1150 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1151 .Case("440", ArchDefineName) 1152 .Case("450", ArchDefineName | ArchDefine440) 1153 .Case("601", ArchDefineName) 1154 .Case("602", ArchDefineName | ArchDefinePpcgr) 1155 .Case("603", ArchDefineName | ArchDefinePpcgr) 1156 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1157 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1158 .Case("604", ArchDefineName | ArchDefinePpcgr) 1159 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1160 .Case("620", ArchDefineName | ArchDefinePpcgr) 1161 .Case("630", ArchDefineName | ArchDefinePpcgr) 1162 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1163 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1164 .Case("750", ArchDefineName | ArchDefinePpcgr) 1165 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1166 | ArchDefinePpcsq) 1167 .Case("a2", ArchDefineA2) 1168 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1169 .Case("pwr3", ArchDefinePpcgr) 1170 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1171 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1174 | ArchDefinePpcgr | ArchDefinePpcsq) 1175 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1176 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1177 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1178 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1179 | ArchDefinePpcsq) 1180 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1181 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1182 | ArchDefinePpcgr | ArchDefinePpcsq) 1183 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1184 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1185 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1186 .Case("power3", ArchDefinePpcgr) 1187 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1188 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1189 | ArchDefinePpcsq) 1190 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1191 | ArchDefinePpcgr | ArchDefinePpcsq) 1192 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1193 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1194 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1195 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1196 | ArchDefinePpcsq) 1197 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1198 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1199 | ArchDefinePpcgr | ArchDefinePpcsq) 1200 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1201 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1202 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1203 .Default(ArchDefineNone); 1204 1205 if (defs & ArchDefineName) 1206 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1207 if (defs & ArchDefinePpcgr) 1208 Builder.defineMacro("_ARCH_PPCGR"); 1209 if (defs & ArchDefinePpcsq) 1210 Builder.defineMacro("_ARCH_PPCSQ"); 1211 if (defs & ArchDefine440) 1212 Builder.defineMacro("_ARCH_440"); 1213 if (defs & ArchDefine603) 1214 Builder.defineMacro("_ARCH_603"); 1215 if (defs & ArchDefine604) 1216 Builder.defineMacro("_ARCH_604"); 1217 if (defs & ArchDefinePwr4) 1218 Builder.defineMacro("_ARCH_PWR4"); 1219 if (defs & ArchDefinePwr5) 1220 Builder.defineMacro("_ARCH_PWR5"); 1221 if (defs & ArchDefinePwr5x) 1222 Builder.defineMacro("_ARCH_PWR5X"); 1223 if (defs & ArchDefinePwr6) 1224 Builder.defineMacro("_ARCH_PWR6"); 1225 if (defs & ArchDefinePwr6x) 1226 Builder.defineMacro("_ARCH_PWR6X"); 1227 if (defs & ArchDefinePwr7) 1228 Builder.defineMacro("_ARCH_PWR7"); 1229 if (defs & ArchDefinePwr8) 1230 Builder.defineMacro("_ARCH_PWR8"); 1231 if (defs & ArchDefineA2) 1232 Builder.defineMacro("_ARCH_A2"); 1233 if (defs & ArchDefineA2q) { 1234 Builder.defineMacro("_ARCH_A2Q"); 1235 Builder.defineMacro("_ARCH_QP"); 1236 } 1237 1238 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1239 Builder.defineMacro("__bg__"); 1240 Builder.defineMacro("__THW_BLUEGENE__"); 1241 Builder.defineMacro("__bgq__"); 1242 Builder.defineMacro("__TOS_BGQ__"); 1243 } 1244 1245 if (HasVSX) 1246 Builder.defineMacro("__VSX__"); 1247 if (HasP8Vector) 1248 Builder.defineMacro("__POWER8_VECTOR__"); 1249 if (HasP8Crypto) 1250 Builder.defineMacro("__CRYPTO__"); 1251 if (HasHTM) 1252 Builder.defineMacro("__HTM__"); 1253 1254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1257 if (PointerWidth == 64) 1258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1259 1260 // FIXME: The following are not yet generated here by Clang, but are 1261 // generated by GCC: 1262 // 1263 // _SOFT_FLOAT_ 1264 // __RECIP_PRECISION__ 1265 // __APPLE_ALTIVEC__ 1266 // __RECIP__ 1267 // __RECIPF__ 1268 // __RSQRTE__ 1269 // __RSQRTEF__ 1270 // _SOFT_DOUBLE_ 1271 // __NO_LWSYNC__ 1272 // __HAVE_BSWAP__ 1273 // __LONGDOUBLE128 1274 // __CMODEL_MEDIUM__ 1275 // __CMODEL_LARGE__ 1276 // _CALL_SYSV 1277 // _CALL_DARWIN 1278 // __NO_FPRS__ 1279 } 1280 1281 // Handle explicit options being passed to the compiler here: if we've 1282 // explicitly turned off vsx and turned on power8-vector or direct-move then 1283 // go ahead and error since the customer has expressed a somewhat incompatible 1284 // set of options. 1285 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1286 const std::vector<std::string> &FeaturesVec) { 1287 1288 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1289 FeaturesVec.end()) { 1290 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1291 FeaturesVec.end()) { 1292 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1293 << "-mno-vsx"; 1294 return false; 1295 } 1296 1297 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1298 FeaturesVec.end()) { 1299 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1300 << "-mno-vsx"; 1301 return false; 1302 } 1303 } 1304 1305 return true; 1306 } 1307 1308 bool PPCTargetInfo::initFeatureMap( 1309 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1310 const std::vector<std::string> &FeaturesVec) const { 1311 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1312 .Case("7400", true) 1313 .Case("g4", true) 1314 .Case("7450", true) 1315 .Case("g4+", true) 1316 .Case("970", true) 1317 .Case("g5", true) 1318 .Case("pwr6", true) 1319 .Case("pwr7", true) 1320 .Case("pwr8", true) 1321 .Case("ppc64", true) 1322 .Case("ppc64le", true) 1323 .Default(false); 1324 1325 Features["qpx"] = (CPU == "a2q"); 1326 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1327 .Case("ppc64le", true) 1328 .Case("pwr8", true) 1329 .Default(false); 1330 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1331 .Case("ppc64le", true) 1332 .Case("pwr8", true) 1333 .Default(false); 1334 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1335 .Case("ppc64le", true) 1336 .Case("pwr8", true) 1337 .Case("pwr7", true) 1338 .Default(false); 1339 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1340 .Case("ppc64le", true) 1341 .Case("pwr8", true) 1342 .Case("pwr7", true) 1343 .Default(false); 1344 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1345 .Case("ppc64le", true) 1346 .Case("pwr8", true) 1347 .Default(false); 1348 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1349 .Case("ppc64le", true) 1350 .Case("pwr8", true) 1351 .Case("pwr7", true) 1352 .Default(false); 1353 1354 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1355 return false; 1356 1357 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1358 } 1359 1360 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1361 return llvm::StringSwitch<bool>(Feature) 1362 .Case("powerpc", true) 1363 .Case("vsx", HasVSX) 1364 .Case("power8-vector", HasP8Vector) 1365 .Case("crypto", HasP8Crypto) 1366 .Case("direct-move", HasDirectMove) 1367 .Case("qpx", HasQPX) 1368 .Case("htm", HasHTM) 1369 .Case("bpermd", HasBPERMD) 1370 .Case("extdiv", HasExtDiv) 1371 .Default(false); 1372 } 1373 1374 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1375 StringRef Name, bool Enabled) const { 1376 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1377 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1378 // incompatible options. 1379 if (Enabled) { 1380 if (Name == "vsx") { 1381 Features[Name] = true; 1382 } else if (Name == "direct-move") { 1383 Features[Name] = Features["vsx"] = true; 1384 } else if (Name == "power8-vector") { 1385 Features[Name] = Features["vsx"] = true; 1386 } else { 1387 Features[Name] = true; 1388 } 1389 } else { 1390 if (Name == "vsx") { 1391 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1392 false; 1393 } else { 1394 Features[Name] = false; 1395 } 1396 } 1397 } 1398 1399 const char * const PPCTargetInfo::GCCRegNames[] = { 1400 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1401 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1402 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1403 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1408 "mq", "lr", "ctr", "ap", 1409 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1410 "xer", 1411 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1412 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1413 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1414 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1415 "vrsave", "vscr", 1416 "spe_acc", "spefscr", 1417 "sfp" 1418 }; 1419 1420 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1421 return llvm::makeArrayRef(GCCRegNames); 1422 } 1423 1424 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1425 // While some of these aliases do map to different registers 1426 // they still share the same register name. 1427 { { "0" }, "r0" }, 1428 { { "1"}, "r1" }, 1429 { { "2" }, "r2" }, 1430 { { "3" }, "r3" }, 1431 { { "4" }, "r4" }, 1432 { { "5" }, "r5" }, 1433 { { "6" }, "r6" }, 1434 { { "7" }, "r7" }, 1435 { { "8" }, "r8" }, 1436 { { "9" }, "r9" }, 1437 { { "10" }, "r10" }, 1438 { { "11" }, "r11" }, 1439 { { "12" }, "r12" }, 1440 { { "13" }, "r13" }, 1441 { { "14" }, "r14" }, 1442 { { "15" }, "r15" }, 1443 { { "16" }, "r16" }, 1444 { { "17" }, "r17" }, 1445 { { "18" }, "r18" }, 1446 { { "19" }, "r19" }, 1447 { { "20" }, "r20" }, 1448 { { "21" }, "r21" }, 1449 { { "22" }, "r22" }, 1450 { { "23" }, "r23" }, 1451 { { "24" }, "r24" }, 1452 { { "25" }, "r25" }, 1453 { { "26" }, "r26" }, 1454 { { "27" }, "r27" }, 1455 { { "28" }, "r28" }, 1456 { { "29" }, "r29" }, 1457 { { "30" }, "r30" }, 1458 { { "31" }, "r31" }, 1459 { { "fr0" }, "f0" }, 1460 { { "fr1" }, "f1" }, 1461 { { "fr2" }, "f2" }, 1462 { { "fr3" }, "f3" }, 1463 { { "fr4" }, "f4" }, 1464 { { "fr5" }, "f5" }, 1465 { { "fr6" }, "f6" }, 1466 { { "fr7" }, "f7" }, 1467 { { "fr8" }, "f8" }, 1468 { { "fr9" }, "f9" }, 1469 { { "fr10" }, "f10" }, 1470 { { "fr11" }, "f11" }, 1471 { { "fr12" }, "f12" }, 1472 { { "fr13" }, "f13" }, 1473 { { "fr14" }, "f14" }, 1474 { { "fr15" }, "f15" }, 1475 { { "fr16" }, "f16" }, 1476 { { "fr17" }, "f17" }, 1477 { { "fr18" }, "f18" }, 1478 { { "fr19" }, "f19" }, 1479 { { "fr20" }, "f20" }, 1480 { { "fr21" }, "f21" }, 1481 { { "fr22" }, "f22" }, 1482 { { "fr23" }, "f23" }, 1483 { { "fr24" }, "f24" }, 1484 { { "fr25" }, "f25" }, 1485 { { "fr26" }, "f26" }, 1486 { { "fr27" }, "f27" }, 1487 { { "fr28" }, "f28" }, 1488 { { "fr29" }, "f29" }, 1489 { { "fr30" }, "f30" }, 1490 { { "fr31" }, "f31" }, 1491 { { "cc" }, "cr0" }, 1492 }; 1493 1494 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1495 return llvm::makeArrayRef(GCCRegAliases); 1496 } 1497 1498 class PPC32TargetInfo : public PPCTargetInfo { 1499 public: 1500 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1501 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1502 1503 switch (getTriple().getOS()) { 1504 case llvm::Triple::Linux: 1505 case llvm::Triple::FreeBSD: 1506 case llvm::Triple::NetBSD: 1507 SizeType = UnsignedInt; 1508 PtrDiffType = SignedInt; 1509 IntPtrType = SignedInt; 1510 break; 1511 default: 1512 break; 1513 } 1514 1515 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1516 LongDoubleWidth = LongDoubleAlign = 64; 1517 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1518 } 1519 1520 // PPC32 supports atomics up to 4 bytes. 1521 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1522 } 1523 1524 BuiltinVaListKind getBuiltinVaListKind() const override { 1525 // This is the ELF definition, and is overridden by the Darwin sub-target 1526 return TargetInfo::PowerABIBuiltinVaList; 1527 } 1528 }; 1529 1530 // Note: ABI differences may eventually require us to have a separate 1531 // TargetInfo for little endian. 1532 class PPC64TargetInfo : public PPCTargetInfo { 1533 public: 1534 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1535 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1536 IntMaxType = SignedLong; 1537 Int64Type = SignedLong; 1538 1539 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1540 DataLayoutString = "e-m:e-i64:64-n32:64"; 1541 ABI = "elfv2"; 1542 } else { 1543 DataLayoutString = "E-m:e-i64:64-n32:64"; 1544 ABI = "elfv1"; 1545 } 1546 1547 switch (getTriple().getOS()) { 1548 case llvm::Triple::FreeBSD: 1549 LongDoubleWidth = LongDoubleAlign = 64; 1550 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1551 break; 1552 case llvm::Triple::NetBSD: 1553 IntMaxType = SignedLongLong; 1554 Int64Type = SignedLongLong; 1555 break; 1556 default: 1557 break; 1558 } 1559 1560 // PPC64 supports atomics up to 8 bytes. 1561 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1562 } 1563 BuiltinVaListKind getBuiltinVaListKind() const override { 1564 return TargetInfo::CharPtrBuiltinVaList; 1565 } 1566 // PPC64 Linux-specific ABI options. 1567 bool setABI(const std::string &Name) override { 1568 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1569 ABI = Name; 1570 return true; 1571 } 1572 return false; 1573 } 1574 }; 1575 1576 class DarwinPPC32TargetInfo : 1577 public DarwinTargetInfo<PPC32TargetInfo> { 1578 public: 1579 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1580 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1581 HasAlignMac68kSupport = true; 1582 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1583 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1584 LongLongAlign = 32; 1585 SuitableAlign = 128; 1586 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1587 } 1588 BuiltinVaListKind getBuiltinVaListKind() const override { 1589 return TargetInfo::CharPtrBuiltinVaList; 1590 } 1591 }; 1592 1593 class DarwinPPC64TargetInfo : 1594 public DarwinTargetInfo<PPC64TargetInfo> { 1595 public: 1596 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1597 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1598 HasAlignMac68kSupport = true; 1599 SuitableAlign = 128; 1600 DataLayoutString = "E-m:o-i64:64-n32:64"; 1601 } 1602 }; 1603 1604 static const unsigned NVPTXAddrSpaceMap[] = { 1605 1, // opencl_global 1606 3, // opencl_local 1607 4, // opencl_constant 1608 // FIXME: generic has to be added to the target 1609 0, // opencl_generic 1610 1, // cuda_device 1611 4, // cuda_constant 1612 3, // cuda_shared 1613 }; 1614 1615 class NVPTXTargetInfo : public TargetInfo { 1616 static const char *const GCCRegNames[]; 1617 static const Builtin::Info BuiltinInfo[]; 1618 1619 // The GPU profiles supported by the NVPTX backend 1620 enum GPUKind { 1621 GK_NONE, 1622 GK_SM20, 1623 GK_SM21, 1624 GK_SM30, 1625 GK_SM35, 1626 GK_SM37, 1627 } GPU; 1628 1629 public: 1630 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1631 BigEndian = false; 1632 TLSSupported = false; 1633 LongWidth = LongAlign = 64; 1634 AddrSpaceMap = &NVPTXAddrSpaceMap; 1635 UseAddrSpaceMapMangling = true; 1636 // Define available target features 1637 // These must be defined in sorted order! 1638 NoAsmVariants = true; 1639 // Set the default GPU to sm20 1640 GPU = GK_SM20; 1641 } 1642 void getTargetDefines(const LangOptions &Opts, 1643 MacroBuilder &Builder) const override { 1644 Builder.defineMacro("__PTX__"); 1645 Builder.defineMacro("__NVPTX__"); 1646 if (Opts.CUDAIsDevice) { 1647 // Set __CUDA_ARCH__ for the GPU specified. 1648 std::string CUDAArchCode; 1649 switch (GPU) { 1650 case GK_SM20: 1651 CUDAArchCode = "200"; 1652 break; 1653 case GK_SM21: 1654 CUDAArchCode = "210"; 1655 break; 1656 case GK_SM30: 1657 CUDAArchCode = "300"; 1658 break; 1659 case GK_SM35: 1660 CUDAArchCode = "350"; 1661 break; 1662 case GK_SM37: 1663 CUDAArchCode = "370"; 1664 break; 1665 default: 1666 llvm_unreachable("Unhandled target CPU"); 1667 } 1668 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1669 } 1670 } 1671 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1672 return llvm::makeArrayRef(BuiltinInfo, 1673 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1674 } 1675 bool hasFeature(StringRef Feature) const override { 1676 return Feature == "ptx" || Feature == "nvptx"; 1677 } 1678 1679 ArrayRef<const char *> getGCCRegNames() const override; 1680 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1681 // No aliases. 1682 return None; 1683 } 1684 bool validateAsmConstraint(const char *&Name, 1685 TargetInfo::ConstraintInfo &Info) const override { 1686 switch (*Name) { 1687 default: 1688 return false; 1689 case 'c': 1690 case 'h': 1691 case 'r': 1692 case 'l': 1693 case 'f': 1694 case 'd': 1695 Info.setAllowsRegister(); 1696 return true; 1697 } 1698 } 1699 const char *getClobbers() const override { 1700 // FIXME: Is this really right? 1701 return ""; 1702 } 1703 BuiltinVaListKind getBuiltinVaListKind() const override { 1704 // FIXME: implement 1705 return TargetInfo::CharPtrBuiltinVaList; 1706 } 1707 bool setCPU(const std::string &Name) override { 1708 GPU = llvm::StringSwitch<GPUKind>(Name) 1709 .Case("sm_20", GK_SM20) 1710 .Case("sm_21", GK_SM21) 1711 .Case("sm_30", GK_SM30) 1712 .Case("sm_35", GK_SM35) 1713 .Case("sm_37", GK_SM37) 1714 .Default(GK_NONE); 1715 1716 return GPU != GK_NONE; 1717 } 1718 }; 1719 1720 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1721 #define BUILTIN(ID, TYPE, ATTRS) \ 1722 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1723 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1724 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1725 #include "clang/Basic/BuiltinsNVPTX.def" 1726 }; 1727 1728 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1729 1730 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1731 return llvm::makeArrayRef(GCCRegNames); 1732 } 1733 1734 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1735 public: 1736 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1737 LongWidth = LongAlign = 32; 1738 PointerWidth = PointerAlign = 32; 1739 SizeType = TargetInfo::UnsignedInt; 1740 PtrDiffType = TargetInfo::SignedInt; 1741 IntPtrType = TargetInfo::SignedInt; 1742 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1743 } 1744 }; 1745 1746 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1747 public: 1748 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1749 PointerWidth = PointerAlign = 64; 1750 SizeType = TargetInfo::UnsignedLong; 1751 PtrDiffType = TargetInfo::SignedLong; 1752 IntPtrType = TargetInfo::SignedLong; 1753 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1754 } 1755 }; 1756 1757 static const unsigned AMDGPUAddrSpaceMap[] = { 1758 1, // opencl_global 1759 3, // opencl_local 1760 2, // opencl_constant 1761 4, // opencl_generic 1762 1, // cuda_device 1763 2, // cuda_constant 1764 3 // cuda_shared 1765 }; 1766 1767 // If you edit the description strings, make sure you update 1768 // getPointerWidthV(). 1769 1770 static const char *const DataLayoutStringR600 = 1771 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1772 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1773 1774 static const char *const DataLayoutStringR600DoubleOps = 1775 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1776 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1777 1778 static const char *const DataLayoutStringSI = 1779 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1780 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1781 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1782 1783 class AMDGPUTargetInfo : public TargetInfo { 1784 static const Builtin::Info BuiltinInfo[]; 1785 static const char * const GCCRegNames[]; 1786 1787 /// \brief The GPU profiles supported by the AMDGPU target. 1788 enum GPUKind { 1789 GK_NONE, 1790 GK_R600, 1791 GK_R600_DOUBLE_OPS, 1792 GK_R700, 1793 GK_R700_DOUBLE_OPS, 1794 GK_EVERGREEN, 1795 GK_EVERGREEN_DOUBLE_OPS, 1796 GK_NORTHERN_ISLANDS, 1797 GK_CAYMAN, 1798 GK_SOUTHERN_ISLANDS, 1799 GK_SEA_ISLANDS, 1800 GK_VOLCANIC_ISLANDS 1801 } GPU; 1802 1803 bool hasFP64:1; 1804 bool hasFMAF:1; 1805 bool hasLDEXPF:1; 1806 1807 public: 1808 AMDGPUTargetInfo(const llvm::Triple &Triple) 1809 : TargetInfo(Triple) { 1810 1811 if (Triple.getArch() == llvm::Triple::amdgcn) { 1812 DataLayoutString = DataLayoutStringSI; 1813 GPU = GK_SOUTHERN_ISLANDS; 1814 hasFP64 = true; 1815 hasFMAF = true; 1816 hasLDEXPF = true; 1817 } else { 1818 DataLayoutString = DataLayoutStringR600; 1819 GPU = GK_R600; 1820 hasFP64 = false; 1821 hasFMAF = false; 1822 hasLDEXPF = false; 1823 } 1824 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1825 UseAddrSpaceMapMangling = true; 1826 } 1827 1828 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1829 if (GPU <= GK_CAYMAN) 1830 return 32; 1831 1832 switch(AddrSpace) { 1833 default: 1834 return 64; 1835 case 0: 1836 case 3: 1837 case 5: 1838 return 32; 1839 } 1840 } 1841 1842 const char * getClobbers() const override { 1843 return ""; 1844 } 1845 1846 ArrayRef<const char *> getGCCRegNames() const override; 1847 1848 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1849 return None; 1850 } 1851 1852 bool validateAsmConstraint(const char *&Name, 1853 TargetInfo::ConstraintInfo &Info) const override { 1854 switch (*Name) { 1855 default: break; 1856 case 'v': // vgpr 1857 case 's': // sgpr 1858 Info.setAllowsRegister(); 1859 return true; 1860 } 1861 return false; 1862 } 1863 1864 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1865 return llvm::makeArrayRef(BuiltinInfo, 1866 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1867 } 1868 1869 void getTargetDefines(const LangOptions &Opts, 1870 MacroBuilder &Builder) const override { 1871 Builder.defineMacro("__R600__"); 1872 if (hasFMAF) 1873 Builder.defineMacro("__HAS_FMAF__"); 1874 if (hasLDEXPF) 1875 Builder.defineMacro("__HAS_LDEXPF__"); 1876 if (hasFP64 && Opts.OpenCL) 1877 Builder.defineMacro("cl_khr_fp64"); 1878 if (Opts.OpenCL) { 1879 if (GPU >= GK_NORTHERN_ISLANDS) { 1880 Builder.defineMacro("cl_khr_byte_addressable_store"); 1881 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1882 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1883 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1884 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1885 } 1886 } 1887 } 1888 1889 BuiltinVaListKind getBuiltinVaListKind() const override { 1890 return TargetInfo::CharPtrBuiltinVaList; 1891 } 1892 1893 bool setCPU(const std::string &Name) override { 1894 GPU = llvm::StringSwitch<GPUKind>(Name) 1895 .Case("r600" , GK_R600) 1896 .Case("rv610", GK_R600) 1897 .Case("rv620", GK_R600) 1898 .Case("rv630", GK_R600) 1899 .Case("rv635", GK_R600) 1900 .Case("rs780", GK_R600) 1901 .Case("rs880", GK_R600) 1902 .Case("rv670", GK_R600_DOUBLE_OPS) 1903 .Case("rv710", GK_R700) 1904 .Case("rv730", GK_R700) 1905 .Case("rv740", GK_R700_DOUBLE_OPS) 1906 .Case("rv770", GK_R700_DOUBLE_OPS) 1907 .Case("palm", GK_EVERGREEN) 1908 .Case("cedar", GK_EVERGREEN) 1909 .Case("sumo", GK_EVERGREEN) 1910 .Case("sumo2", GK_EVERGREEN) 1911 .Case("redwood", GK_EVERGREEN) 1912 .Case("juniper", GK_EVERGREEN) 1913 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1914 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1915 .Case("barts", GK_NORTHERN_ISLANDS) 1916 .Case("turks", GK_NORTHERN_ISLANDS) 1917 .Case("caicos", GK_NORTHERN_ISLANDS) 1918 .Case("cayman", GK_CAYMAN) 1919 .Case("aruba", GK_CAYMAN) 1920 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1921 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1922 .Case("verde", GK_SOUTHERN_ISLANDS) 1923 .Case("oland", GK_SOUTHERN_ISLANDS) 1924 .Case("hainan", GK_SOUTHERN_ISLANDS) 1925 .Case("bonaire", GK_SEA_ISLANDS) 1926 .Case("kabini", GK_SEA_ISLANDS) 1927 .Case("kaveri", GK_SEA_ISLANDS) 1928 .Case("hawaii", GK_SEA_ISLANDS) 1929 .Case("mullins", GK_SEA_ISLANDS) 1930 .Case("tonga", GK_VOLCANIC_ISLANDS) 1931 .Case("iceland", GK_VOLCANIC_ISLANDS) 1932 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1933 .Default(GK_NONE); 1934 1935 if (GPU == GK_NONE) { 1936 return false; 1937 } 1938 1939 // Set the correct data layout 1940 switch (GPU) { 1941 case GK_NONE: 1942 case GK_R600: 1943 case GK_R700: 1944 case GK_EVERGREEN: 1945 case GK_NORTHERN_ISLANDS: 1946 DataLayoutString = DataLayoutStringR600; 1947 hasFP64 = false; 1948 hasFMAF = false; 1949 hasLDEXPF = false; 1950 break; 1951 case GK_R600_DOUBLE_OPS: 1952 case GK_R700_DOUBLE_OPS: 1953 case GK_EVERGREEN_DOUBLE_OPS: 1954 case GK_CAYMAN: 1955 DataLayoutString = DataLayoutStringR600DoubleOps; 1956 hasFP64 = true; 1957 hasFMAF = true; 1958 hasLDEXPF = false; 1959 break; 1960 case GK_SOUTHERN_ISLANDS: 1961 case GK_SEA_ISLANDS: 1962 case GK_VOLCANIC_ISLANDS: 1963 DataLayoutString = DataLayoutStringSI; 1964 hasFP64 = true; 1965 hasFMAF = true; 1966 hasLDEXPF = true; 1967 break; 1968 } 1969 1970 return true; 1971 } 1972 }; 1973 1974 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1975 #define BUILTIN(ID, TYPE, ATTRS) \ 1976 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1977 #include "clang/Basic/BuiltinsAMDGPU.def" 1978 }; 1979 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1980 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1981 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1982 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1983 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1984 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1985 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1986 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1987 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1988 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1989 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1990 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1991 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1992 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1993 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1994 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1995 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1996 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1997 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1998 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1999 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2000 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2001 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2002 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2003 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2004 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2005 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2006 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2007 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2008 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2009 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2010 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2011 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2012 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2013 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2014 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2015 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2016 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2017 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2018 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2019 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2020 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2021 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2022 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2023 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2024 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2025 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2026 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2027 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2028 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2029 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2030 }; 2031 2032 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2033 return llvm::makeArrayRef(GCCRegNames); 2034 } 2035 2036 // Namespace for x86 abstract base class 2037 const Builtin::Info BuiltinInfo[] = { 2038 #define BUILTIN(ID, TYPE, ATTRS) \ 2039 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2040 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2041 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2042 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2043 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2044 #include "clang/Basic/BuiltinsX86.def" 2045 }; 2046 2047 static const char* const GCCRegNames[] = { 2048 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2049 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2050 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2051 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2052 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2053 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2054 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2055 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2056 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2057 }; 2058 2059 const TargetInfo::AddlRegName AddlRegNames[] = { 2060 { { "al", "ah", "eax", "rax" }, 0 }, 2061 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2062 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2063 { { "dl", "dh", "edx", "rdx" }, 1 }, 2064 { { "esi", "rsi" }, 4 }, 2065 { { "edi", "rdi" }, 5 }, 2066 { { "esp", "rsp" }, 7 }, 2067 { { "ebp", "rbp" }, 6 }, 2068 { { "r8d", "r8w", "r8b" }, 38 }, 2069 { { "r9d", "r9w", "r9b" }, 39 }, 2070 { { "r10d", "r10w", "r10b" }, 40 }, 2071 { { "r11d", "r11w", "r11b" }, 41 }, 2072 { { "r12d", "r12w", "r12b" }, 42 }, 2073 { { "r13d", "r13w", "r13b" }, 43 }, 2074 { { "r14d", "r14w", "r14b" }, 44 }, 2075 { { "r15d", "r15w", "r15b" }, 45 }, 2076 }; 2077 2078 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2079 // most of the implementation can be shared. 2080 class X86TargetInfo : public TargetInfo { 2081 enum X86SSEEnum { 2082 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2083 } SSELevel = NoSSE; 2084 enum MMX3DNowEnum { 2085 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2086 } MMX3DNowLevel = NoMMX3DNow; 2087 enum XOPEnum { 2088 NoXOP, 2089 SSE4A, 2090 FMA4, 2091 XOP 2092 } XOPLevel = NoXOP; 2093 2094 bool HasAES = false; 2095 bool HasPCLMUL = false; 2096 bool HasLZCNT = false; 2097 bool HasRDRND = false; 2098 bool HasFSGSBASE = false; 2099 bool HasBMI = false; 2100 bool HasBMI2 = false; 2101 bool HasPOPCNT = false; 2102 bool HasRTM = false; 2103 bool HasPRFCHW = false; 2104 bool HasRDSEED = false; 2105 bool HasADX = false; 2106 bool HasTBM = false; 2107 bool HasFMA = false; 2108 bool HasF16C = false; 2109 bool HasAVX512CD = false; 2110 bool HasAVX512ER = false; 2111 bool HasAVX512PF = false; 2112 bool HasAVX512DQ = false; 2113 bool HasAVX512BW = false; 2114 bool HasAVX512VL = false; 2115 bool HasSHA = false; 2116 bool HasCX16 = false; 2117 bool HasFXSR = false; 2118 bool HasXSAVE = false; 2119 bool HasXSAVEOPT = false; 2120 bool HasXSAVEC = false; 2121 bool HasXSAVES = false; 2122 bool HasPKU = false; 2123 2124 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2125 /// 2126 /// Each enumeration represents a particular CPU supported by Clang. These 2127 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2128 enum CPUKind { 2129 CK_Generic, 2130 2131 /// \name i386 2132 /// i386-generation processors. 2133 //@{ 2134 CK_i386, 2135 //@} 2136 2137 /// \name i486 2138 /// i486-generation processors. 2139 //@{ 2140 CK_i486, 2141 CK_WinChipC6, 2142 CK_WinChip2, 2143 CK_C3, 2144 //@} 2145 2146 /// \name i586 2147 /// i586-generation processors, P5 microarchitecture based. 2148 //@{ 2149 CK_i586, 2150 CK_Pentium, 2151 CK_PentiumMMX, 2152 //@} 2153 2154 /// \name i686 2155 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2156 //@{ 2157 CK_i686, 2158 CK_PentiumPro, 2159 CK_Pentium2, 2160 CK_Pentium3, 2161 CK_Pentium3M, 2162 CK_PentiumM, 2163 CK_C3_2, 2164 2165 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2166 /// Clang however has some logic to suport this. 2167 // FIXME: Warn, deprecate, and potentially remove this. 2168 CK_Yonah, 2169 //@} 2170 2171 /// \name Netburst 2172 /// Netburst microarchitecture based processors. 2173 //@{ 2174 CK_Pentium4, 2175 CK_Pentium4M, 2176 CK_Prescott, 2177 CK_Nocona, 2178 //@} 2179 2180 /// \name Core 2181 /// Core microarchitecture based processors. 2182 //@{ 2183 CK_Core2, 2184 2185 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2186 /// codename which GCC no longer accepts as an option to -march, but Clang 2187 /// has some logic for recognizing it. 2188 // FIXME: Warn, deprecate, and potentially remove this. 2189 CK_Penryn, 2190 //@} 2191 2192 /// \name Atom 2193 /// Atom processors 2194 //@{ 2195 CK_Bonnell, 2196 CK_Silvermont, 2197 //@} 2198 2199 /// \name Nehalem 2200 /// Nehalem microarchitecture based processors. 2201 CK_Nehalem, 2202 2203 /// \name Westmere 2204 /// Westmere microarchitecture based processors. 2205 CK_Westmere, 2206 2207 /// \name Sandy Bridge 2208 /// Sandy Bridge microarchitecture based processors. 2209 CK_SandyBridge, 2210 2211 /// \name Ivy Bridge 2212 /// Ivy Bridge microarchitecture based processors. 2213 CK_IvyBridge, 2214 2215 /// \name Haswell 2216 /// Haswell microarchitecture based processors. 2217 CK_Haswell, 2218 2219 /// \name Broadwell 2220 /// Broadwell microarchitecture based processors. 2221 CK_Broadwell, 2222 2223 /// \name Skylake 2224 /// Skylake microarchitecture based processors. 2225 CK_Skylake, 2226 2227 /// \name Knights Landing 2228 /// Knights Landing processor. 2229 CK_KNL, 2230 2231 /// \name K6 2232 /// K6 architecture processors. 2233 //@{ 2234 CK_K6, 2235 CK_K6_2, 2236 CK_K6_3, 2237 //@} 2238 2239 /// \name K7 2240 /// K7 architecture processors. 2241 //@{ 2242 CK_Athlon, 2243 CK_AthlonThunderbird, 2244 CK_Athlon4, 2245 CK_AthlonXP, 2246 CK_AthlonMP, 2247 //@} 2248 2249 /// \name K8 2250 /// K8 architecture processors. 2251 //@{ 2252 CK_Athlon64, 2253 CK_Athlon64SSE3, 2254 CK_AthlonFX, 2255 CK_K8, 2256 CK_K8SSE3, 2257 CK_Opteron, 2258 CK_OpteronSSE3, 2259 CK_AMDFAM10, 2260 //@} 2261 2262 /// \name Bobcat 2263 /// Bobcat architecture processors. 2264 //@{ 2265 CK_BTVER1, 2266 CK_BTVER2, 2267 //@} 2268 2269 /// \name Bulldozer 2270 /// Bulldozer architecture processors. 2271 //@{ 2272 CK_BDVER1, 2273 CK_BDVER2, 2274 CK_BDVER3, 2275 CK_BDVER4, 2276 //@} 2277 2278 /// This specification is deprecated and will be removed in the future. 2279 /// Users should prefer \see CK_K8. 2280 // FIXME: Warn on this when the CPU is set to it. 2281 //@{ 2282 CK_x86_64, 2283 //@} 2284 2285 /// \name Geode 2286 /// Geode processors. 2287 //@{ 2288 CK_Geode 2289 //@} 2290 } CPU = CK_Generic; 2291 2292 CPUKind getCPUKind(StringRef CPU) const { 2293 return llvm::StringSwitch<CPUKind>(CPU) 2294 .Case("i386", CK_i386) 2295 .Case("i486", CK_i486) 2296 .Case("winchip-c6", CK_WinChipC6) 2297 .Case("winchip2", CK_WinChip2) 2298 .Case("c3", CK_C3) 2299 .Case("i586", CK_i586) 2300 .Case("pentium", CK_Pentium) 2301 .Case("pentium-mmx", CK_PentiumMMX) 2302 .Case("i686", CK_i686) 2303 .Case("pentiumpro", CK_PentiumPro) 2304 .Case("pentium2", CK_Pentium2) 2305 .Case("pentium3", CK_Pentium3) 2306 .Case("pentium3m", CK_Pentium3M) 2307 .Case("pentium-m", CK_PentiumM) 2308 .Case("c3-2", CK_C3_2) 2309 .Case("yonah", CK_Yonah) 2310 .Case("pentium4", CK_Pentium4) 2311 .Case("pentium4m", CK_Pentium4M) 2312 .Case("prescott", CK_Prescott) 2313 .Case("nocona", CK_Nocona) 2314 .Case("core2", CK_Core2) 2315 .Case("penryn", CK_Penryn) 2316 .Case("bonnell", CK_Bonnell) 2317 .Case("atom", CK_Bonnell) // Legacy name. 2318 .Case("silvermont", CK_Silvermont) 2319 .Case("slm", CK_Silvermont) // Legacy name. 2320 .Case("nehalem", CK_Nehalem) 2321 .Case("corei7", CK_Nehalem) // Legacy name. 2322 .Case("westmere", CK_Westmere) 2323 .Case("sandybridge", CK_SandyBridge) 2324 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2325 .Case("ivybridge", CK_IvyBridge) 2326 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2327 .Case("haswell", CK_Haswell) 2328 .Case("core-avx2", CK_Haswell) // Legacy name. 2329 .Case("broadwell", CK_Broadwell) 2330 .Case("skylake", CK_Skylake) 2331 .Case("skx", CK_Skylake) // Legacy name. 2332 .Case("knl", CK_KNL) 2333 .Case("k6", CK_K6) 2334 .Case("k6-2", CK_K6_2) 2335 .Case("k6-3", CK_K6_3) 2336 .Case("athlon", CK_Athlon) 2337 .Case("athlon-tbird", CK_AthlonThunderbird) 2338 .Case("athlon-4", CK_Athlon4) 2339 .Case("athlon-xp", CK_AthlonXP) 2340 .Case("athlon-mp", CK_AthlonMP) 2341 .Case("athlon64", CK_Athlon64) 2342 .Case("athlon64-sse3", CK_Athlon64SSE3) 2343 .Case("athlon-fx", CK_AthlonFX) 2344 .Case("k8", CK_K8) 2345 .Case("k8-sse3", CK_K8SSE3) 2346 .Case("opteron", CK_Opteron) 2347 .Case("opteron-sse3", CK_OpteronSSE3) 2348 .Case("barcelona", CK_AMDFAM10) 2349 .Case("amdfam10", CK_AMDFAM10) 2350 .Case("btver1", CK_BTVER1) 2351 .Case("btver2", CK_BTVER2) 2352 .Case("bdver1", CK_BDVER1) 2353 .Case("bdver2", CK_BDVER2) 2354 .Case("bdver3", CK_BDVER3) 2355 .Case("bdver4", CK_BDVER4) 2356 .Case("x86-64", CK_x86_64) 2357 .Case("geode", CK_Geode) 2358 .Default(CK_Generic); 2359 } 2360 2361 enum FPMathKind { 2362 FP_Default, 2363 FP_SSE, 2364 FP_387 2365 } FPMath = FP_Default; 2366 2367 public: 2368 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2369 BigEndian = false; 2370 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2371 } 2372 unsigned getFloatEvalMethod() const override { 2373 // X87 evaluates with 80 bits "long double" precision. 2374 return SSELevel == NoSSE ? 2 : 0; 2375 } 2376 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2377 return llvm::makeArrayRef(BuiltinInfo, 2378 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2379 } 2380 ArrayRef<const char *> getGCCRegNames() const override { 2381 return llvm::makeArrayRef(GCCRegNames); 2382 } 2383 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2384 return None; 2385 } 2386 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2387 return llvm::makeArrayRef(AddlRegNames); 2388 } 2389 bool validateCpuSupports(StringRef Name) const override; 2390 bool validateAsmConstraint(const char *&Name, 2391 TargetInfo::ConstraintInfo &info) const override; 2392 2393 bool validateGlobalRegisterVariable(StringRef RegName, 2394 unsigned RegSize, 2395 bool &HasSizeMismatch) const override { 2396 // esp and ebp are the only 32-bit registers the x86 backend can currently 2397 // handle. 2398 if (RegName.equals("esp") || RegName.equals("ebp")) { 2399 // Check that the register size is 32-bit. 2400 HasSizeMismatch = RegSize != 32; 2401 return true; 2402 } 2403 2404 return false; 2405 } 2406 2407 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2408 2409 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2410 2411 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2412 2413 std::string convertConstraint(const char *&Constraint) const override; 2414 const char *getClobbers() const override { 2415 return "~{dirflag},~{fpsr},~{flags}"; 2416 } 2417 void getTargetDefines(const LangOptions &Opts, 2418 MacroBuilder &Builder) const override; 2419 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2420 bool Enabled); 2421 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2422 bool Enabled); 2423 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2424 bool Enabled); 2425 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2426 StringRef Name, bool Enabled) const override { 2427 setFeatureEnabledImpl(Features, Name, Enabled); 2428 } 2429 // This exists purely to cut down on the number of virtual calls in 2430 // initFeatureMap which calls this repeatedly. 2431 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2432 StringRef Name, bool Enabled); 2433 bool 2434 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2435 StringRef CPU, 2436 const std::vector<std::string> &FeaturesVec) const override; 2437 bool hasFeature(StringRef Feature) const override; 2438 bool handleTargetFeatures(std::vector<std::string> &Features, 2439 DiagnosticsEngine &Diags) override; 2440 StringRef getABI() const override { 2441 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2442 return "avx512"; 2443 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2444 return "avx"; 2445 if (getTriple().getArch() == llvm::Triple::x86 && 2446 MMX3DNowLevel == NoMMX3DNow) 2447 return "no-mmx"; 2448 return ""; 2449 } 2450 bool setCPU(const std::string &Name) override { 2451 CPU = getCPUKind(Name); 2452 2453 // Perform any per-CPU checks necessary to determine if this CPU is 2454 // acceptable. 2455 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2456 // invalid without explaining *why*. 2457 switch (CPU) { 2458 case CK_Generic: 2459 // No processor selected! 2460 return false; 2461 2462 case CK_i386: 2463 case CK_i486: 2464 case CK_WinChipC6: 2465 case CK_WinChip2: 2466 case CK_C3: 2467 case CK_i586: 2468 case CK_Pentium: 2469 case CK_PentiumMMX: 2470 case CK_i686: 2471 case CK_PentiumPro: 2472 case CK_Pentium2: 2473 case CK_Pentium3: 2474 case CK_Pentium3M: 2475 case CK_PentiumM: 2476 case CK_Yonah: 2477 case CK_C3_2: 2478 case CK_Pentium4: 2479 case CK_Pentium4M: 2480 case CK_Prescott: 2481 case CK_K6: 2482 case CK_K6_2: 2483 case CK_K6_3: 2484 case CK_Athlon: 2485 case CK_AthlonThunderbird: 2486 case CK_Athlon4: 2487 case CK_AthlonXP: 2488 case CK_AthlonMP: 2489 case CK_Geode: 2490 // Only accept certain architectures when compiling in 32-bit mode. 2491 if (getTriple().getArch() != llvm::Triple::x86) 2492 return false; 2493 2494 // Fallthrough 2495 case CK_Nocona: 2496 case CK_Core2: 2497 case CK_Penryn: 2498 case CK_Bonnell: 2499 case CK_Silvermont: 2500 case CK_Nehalem: 2501 case CK_Westmere: 2502 case CK_SandyBridge: 2503 case CK_IvyBridge: 2504 case CK_Haswell: 2505 case CK_Broadwell: 2506 case CK_Skylake: 2507 case CK_KNL: 2508 case CK_Athlon64: 2509 case CK_Athlon64SSE3: 2510 case CK_AthlonFX: 2511 case CK_K8: 2512 case CK_K8SSE3: 2513 case CK_Opteron: 2514 case CK_OpteronSSE3: 2515 case CK_AMDFAM10: 2516 case CK_BTVER1: 2517 case CK_BTVER2: 2518 case CK_BDVER1: 2519 case CK_BDVER2: 2520 case CK_BDVER3: 2521 case CK_BDVER4: 2522 case CK_x86_64: 2523 return true; 2524 } 2525 llvm_unreachable("Unhandled CPU kind"); 2526 } 2527 2528 bool setFPMath(StringRef Name) override; 2529 2530 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2531 // We accept all non-ARM calling conventions 2532 return (CC == CC_X86ThisCall || 2533 CC == CC_X86FastCall || 2534 CC == CC_X86StdCall || 2535 CC == CC_X86VectorCall || 2536 CC == CC_C || 2537 CC == CC_X86Pascal || 2538 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2539 } 2540 2541 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2542 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2543 } 2544 2545 bool hasSjLjLowering() const override { 2546 return true; 2547 } 2548 }; 2549 2550 bool X86TargetInfo::setFPMath(StringRef Name) { 2551 if (Name == "387") { 2552 FPMath = FP_387; 2553 return true; 2554 } 2555 if (Name == "sse") { 2556 FPMath = FP_SSE; 2557 return true; 2558 } 2559 return false; 2560 } 2561 2562 bool X86TargetInfo::initFeatureMap( 2563 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2564 const std::vector<std::string> &FeaturesVec) const { 2565 // FIXME: This *really* should not be here. 2566 // X86_64 always has SSE2. 2567 if (getTriple().getArch() == llvm::Triple::x86_64) 2568 setFeatureEnabledImpl(Features, "sse2", true); 2569 2570 switch (getCPUKind(CPU)) { 2571 case CK_Generic: 2572 case CK_i386: 2573 case CK_i486: 2574 case CK_i586: 2575 case CK_Pentium: 2576 case CK_i686: 2577 case CK_PentiumPro: 2578 break; 2579 case CK_PentiumMMX: 2580 case CK_Pentium2: 2581 case CK_K6: 2582 case CK_WinChipC6: 2583 setFeatureEnabledImpl(Features, "mmx", true); 2584 break; 2585 case CK_Pentium3: 2586 case CK_Pentium3M: 2587 case CK_C3_2: 2588 setFeatureEnabledImpl(Features, "sse", true); 2589 setFeatureEnabledImpl(Features, "fxsr", true); 2590 break; 2591 case CK_PentiumM: 2592 case CK_Pentium4: 2593 case CK_Pentium4M: 2594 case CK_x86_64: 2595 setFeatureEnabledImpl(Features, "sse2", true); 2596 setFeatureEnabledImpl(Features, "fxsr", true); 2597 break; 2598 case CK_Yonah: 2599 case CK_Prescott: 2600 case CK_Nocona: 2601 setFeatureEnabledImpl(Features, "sse3", true); 2602 setFeatureEnabledImpl(Features, "fxsr", true); 2603 setFeatureEnabledImpl(Features, "cx16", true); 2604 break; 2605 case CK_Core2: 2606 case CK_Bonnell: 2607 setFeatureEnabledImpl(Features, "ssse3", true); 2608 setFeatureEnabledImpl(Features, "fxsr", true); 2609 setFeatureEnabledImpl(Features, "cx16", true); 2610 break; 2611 case CK_Penryn: 2612 setFeatureEnabledImpl(Features, "sse4.1", true); 2613 setFeatureEnabledImpl(Features, "fxsr", true); 2614 setFeatureEnabledImpl(Features, "cx16", true); 2615 break; 2616 case CK_Skylake: 2617 setFeatureEnabledImpl(Features, "avx512f", true); 2618 setFeatureEnabledImpl(Features, "avx512cd", true); 2619 setFeatureEnabledImpl(Features, "avx512dq", true); 2620 setFeatureEnabledImpl(Features, "avx512bw", true); 2621 setFeatureEnabledImpl(Features, "avx512vl", true); 2622 setFeatureEnabledImpl(Features, "xsavec", true); 2623 setFeatureEnabledImpl(Features, "xsaves", true); 2624 setFeatureEnabledImpl(Features, "pku", true); 2625 // FALLTHROUGH 2626 case CK_Broadwell: 2627 setFeatureEnabledImpl(Features, "rdseed", true); 2628 setFeatureEnabledImpl(Features, "adx", true); 2629 // FALLTHROUGH 2630 case CK_Haswell: 2631 setFeatureEnabledImpl(Features, "avx2", true); 2632 setFeatureEnabledImpl(Features, "lzcnt", true); 2633 setFeatureEnabledImpl(Features, "bmi", true); 2634 setFeatureEnabledImpl(Features, "bmi2", true); 2635 setFeatureEnabledImpl(Features, "rtm", true); 2636 setFeatureEnabledImpl(Features, "fma", true); 2637 // FALLTHROUGH 2638 case CK_IvyBridge: 2639 setFeatureEnabledImpl(Features, "rdrnd", true); 2640 setFeatureEnabledImpl(Features, "f16c", true); 2641 setFeatureEnabledImpl(Features, "fsgsbase", true); 2642 // FALLTHROUGH 2643 case CK_SandyBridge: 2644 setFeatureEnabledImpl(Features, "avx", true); 2645 setFeatureEnabledImpl(Features, "xsave", true); 2646 setFeatureEnabledImpl(Features, "xsaveopt", true); 2647 // FALLTHROUGH 2648 case CK_Westmere: 2649 case CK_Silvermont: 2650 setFeatureEnabledImpl(Features, "aes", true); 2651 setFeatureEnabledImpl(Features, "pclmul", true); 2652 // FALLTHROUGH 2653 case CK_Nehalem: 2654 setFeatureEnabledImpl(Features, "sse4.2", true); 2655 setFeatureEnabledImpl(Features, "fxsr", true); 2656 setFeatureEnabledImpl(Features, "cx16", true); 2657 break; 2658 case CK_KNL: 2659 setFeatureEnabledImpl(Features, "avx512f", true); 2660 setFeatureEnabledImpl(Features, "avx512cd", true); 2661 setFeatureEnabledImpl(Features, "avx512er", true); 2662 setFeatureEnabledImpl(Features, "avx512pf", true); 2663 setFeatureEnabledImpl(Features, "fxsr", true); 2664 setFeatureEnabledImpl(Features, "rdseed", true); 2665 setFeatureEnabledImpl(Features, "adx", true); 2666 setFeatureEnabledImpl(Features, "lzcnt", true); 2667 setFeatureEnabledImpl(Features, "bmi", true); 2668 setFeatureEnabledImpl(Features, "bmi2", true); 2669 setFeatureEnabledImpl(Features, "rtm", true); 2670 setFeatureEnabledImpl(Features, "fma", true); 2671 setFeatureEnabledImpl(Features, "rdrnd", true); 2672 setFeatureEnabledImpl(Features, "f16c", true); 2673 setFeatureEnabledImpl(Features, "fsgsbase", true); 2674 setFeatureEnabledImpl(Features, "aes", true); 2675 setFeatureEnabledImpl(Features, "pclmul", true); 2676 setFeatureEnabledImpl(Features, "cx16", true); 2677 setFeatureEnabledImpl(Features, "xsaveopt", true); 2678 setFeatureEnabledImpl(Features, "xsave", true); 2679 break; 2680 case CK_K6_2: 2681 case CK_K6_3: 2682 case CK_WinChip2: 2683 case CK_C3: 2684 setFeatureEnabledImpl(Features, "3dnow", true); 2685 break; 2686 case CK_Athlon: 2687 case CK_AthlonThunderbird: 2688 case CK_Geode: 2689 setFeatureEnabledImpl(Features, "3dnowa", true); 2690 break; 2691 case CK_Athlon4: 2692 case CK_AthlonXP: 2693 case CK_AthlonMP: 2694 setFeatureEnabledImpl(Features, "sse", true); 2695 setFeatureEnabledImpl(Features, "3dnowa", true); 2696 setFeatureEnabledImpl(Features, "fxsr", true); 2697 break; 2698 case CK_K8: 2699 case CK_Opteron: 2700 case CK_Athlon64: 2701 case CK_AthlonFX: 2702 setFeatureEnabledImpl(Features, "sse2", true); 2703 setFeatureEnabledImpl(Features, "3dnowa", true); 2704 setFeatureEnabledImpl(Features, "fxsr", true); 2705 break; 2706 case CK_AMDFAM10: 2707 setFeatureEnabledImpl(Features, "sse4a", true); 2708 setFeatureEnabledImpl(Features, "lzcnt", true); 2709 setFeatureEnabledImpl(Features, "popcnt", true); 2710 // FALLTHROUGH 2711 case CK_K8SSE3: 2712 case CK_OpteronSSE3: 2713 case CK_Athlon64SSE3: 2714 setFeatureEnabledImpl(Features, "sse3", true); 2715 setFeatureEnabledImpl(Features, "3dnowa", true); 2716 setFeatureEnabledImpl(Features, "fxsr", true); 2717 break; 2718 case CK_BTVER2: 2719 setFeatureEnabledImpl(Features, "avx", true); 2720 setFeatureEnabledImpl(Features, "aes", true); 2721 setFeatureEnabledImpl(Features, "pclmul", true); 2722 setFeatureEnabledImpl(Features, "bmi", true); 2723 setFeatureEnabledImpl(Features, "f16c", true); 2724 setFeatureEnabledImpl(Features, "xsaveopt", true); 2725 // FALLTHROUGH 2726 case CK_BTVER1: 2727 setFeatureEnabledImpl(Features, "ssse3", true); 2728 setFeatureEnabledImpl(Features, "sse4a", true); 2729 setFeatureEnabledImpl(Features, "lzcnt", true); 2730 setFeatureEnabledImpl(Features, "popcnt", true); 2731 setFeatureEnabledImpl(Features, "prfchw", true); 2732 setFeatureEnabledImpl(Features, "cx16", true); 2733 setFeatureEnabledImpl(Features, "fxsr", true); 2734 setFeatureEnabledImpl(Features, "xsave", true); 2735 break; 2736 case CK_BDVER4: 2737 setFeatureEnabledImpl(Features, "avx2", true); 2738 setFeatureEnabledImpl(Features, "bmi2", true); 2739 // FALLTHROUGH 2740 case CK_BDVER3: 2741 setFeatureEnabledImpl(Features, "fsgsbase", true); 2742 setFeatureEnabledImpl(Features, "xsaveopt", true); 2743 // FALLTHROUGH 2744 case CK_BDVER2: 2745 setFeatureEnabledImpl(Features, "bmi", true); 2746 setFeatureEnabledImpl(Features, "fma", true); 2747 setFeatureEnabledImpl(Features, "f16c", true); 2748 setFeatureEnabledImpl(Features, "tbm", true); 2749 // FALLTHROUGH 2750 case CK_BDVER1: 2751 // xop implies avx, sse4a and fma4. 2752 setFeatureEnabledImpl(Features, "xop", true); 2753 setFeatureEnabledImpl(Features, "lzcnt", true); 2754 setFeatureEnabledImpl(Features, "aes", true); 2755 setFeatureEnabledImpl(Features, "pclmul", true); 2756 setFeatureEnabledImpl(Features, "prfchw", true); 2757 setFeatureEnabledImpl(Features, "cx16", true); 2758 setFeatureEnabledImpl(Features, "fxsr", true); 2759 setFeatureEnabledImpl(Features, "xsave", true); 2760 break; 2761 } 2762 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2763 return false; 2764 2765 // Can't do this earlier because we need to be able to explicitly enable 2766 // or disable these features and the things that they depend upon. 2767 2768 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2769 auto I = Features.find("sse4.2"); 2770 if (I != Features.end() && I->getValue() && 2771 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2772 FeaturesVec.end()) 2773 Features["popcnt"] = true; 2774 2775 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2776 I = Features.find("3dnow"); 2777 if (I != Features.end() && I->getValue() && 2778 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2779 FeaturesVec.end()) 2780 Features["prfchw"] = true; 2781 2782 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2783 // then enable MMX. 2784 I = Features.find("sse"); 2785 if (I != Features.end() && I->getValue() && 2786 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2787 FeaturesVec.end()) 2788 Features["mmx"] = true; 2789 2790 return true; 2791 } 2792 2793 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2794 X86SSEEnum Level, bool Enabled) { 2795 if (Enabled) { 2796 switch (Level) { 2797 case AVX512F: 2798 Features["avx512f"] = true; 2799 case AVX2: 2800 Features["avx2"] = true; 2801 case AVX: 2802 Features["avx"] = true; 2803 Features["xsave"] = true; 2804 case SSE42: 2805 Features["sse4.2"] = true; 2806 case SSE41: 2807 Features["sse4.1"] = true; 2808 case SSSE3: 2809 Features["ssse3"] = true; 2810 case SSE3: 2811 Features["sse3"] = true; 2812 case SSE2: 2813 Features["sse2"] = true; 2814 case SSE1: 2815 Features["sse"] = true; 2816 case NoSSE: 2817 break; 2818 } 2819 return; 2820 } 2821 2822 switch (Level) { 2823 case NoSSE: 2824 case SSE1: 2825 Features["sse"] = false; 2826 case SSE2: 2827 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2828 Features["sha"] = false; 2829 case SSE3: 2830 Features["sse3"] = false; 2831 setXOPLevel(Features, NoXOP, false); 2832 case SSSE3: 2833 Features["ssse3"] = false; 2834 case SSE41: 2835 Features["sse4.1"] = false; 2836 case SSE42: 2837 Features["sse4.2"] = false; 2838 case AVX: 2839 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2840 Features["xsaveopt"] = false; 2841 setXOPLevel(Features, FMA4, false); 2842 case AVX2: 2843 Features["avx2"] = false; 2844 case AVX512F: 2845 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2846 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2847 Features["avx512vl"] = false; 2848 } 2849 } 2850 2851 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2852 MMX3DNowEnum Level, bool Enabled) { 2853 if (Enabled) { 2854 switch (Level) { 2855 case AMD3DNowAthlon: 2856 Features["3dnowa"] = true; 2857 case AMD3DNow: 2858 Features["3dnow"] = true; 2859 case MMX: 2860 Features["mmx"] = true; 2861 case NoMMX3DNow: 2862 break; 2863 } 2864 return; 2865 } 2866 2867 switch (Level) { 2868 case NoMMX3DNow: 2869 case MMX: 2870 Features["mmx"] = false; 2871 case AMD3DNow: 2872 Features["3dnow"] = false; 2873 case AMD3DNowAthlon: 2874 Features["3dnowa"] = false; 2875 } 2876 } 2877 2878 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2879 bool Enabled) { 2880 if (Enabled) { 2881 switch (Level) { 2882 case XOP: 2883 Features["xop"] = true; 2884 case FMA4: 2885 Features["fma4"] = true; 2886 setSSELevel(Features, AVX, true); 2887 case SSE4A: 2888 Features["sse4a"] = true; 2889 setSSELevel(Features, SSE3, true); 2890 case NoXOP: 2891 break; 2892 } 2893 return; 2894 } 2895 2896 switch (Level) { 2897 case NoXOP: 2898 case SSE4A: 2899 Features["sse4a"] = false; 2900 case FMA4: 2901 Features["fma4"] = false; 2902 case XOP: 2903 Features["xop"] = false; 2904 } 2905 } 2906 2907 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2908 StringRef Name, bool Enabled) { 2909 // This is a bit of a hack to deal with the sse4 target feature when used 2910 // as part of the target attribute. We handle sse4 correctly everywhere 2911 // else. See below for more information on how we handle the sse4 options. 2912 if (Name != "sse4") 2913 Features[Name] = Enabled; 2914 2915 if (Name == "mmx") { 2916 setMMXLevel(Features, MMX, Enabled); 2917 } else if (Name == "sse") { 2918 setSSELevel(Features, SSE1, Enabled); 2919 } else if (Name == "sse2") { 2920 setSSELevel(Features, SSE2, Enabled); 2921 } else if (Name == "sse3") { 2922 setSSELevel(Features, SSE3, Enabled); 2923 } else if (Name == "ssse3") { 2924 setSSELevel(Features, SSSE3, Enabled); 2925 } else if (Name == "sse4.2") { 2926 setSSELevel(Features, SSE42, Enabled); 2927 } else if (Name == "sse4.1") { 2928 setSSELevel(Features, SSE41, Enabled); 2929 } else if (Name == "3dnow") { 2930 setMMXLevel(Features, AMD3DNow, Enabled); 2931 } else if (Name == "3dnowa") { 2932 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2933 } else if (Name == "aes") { 2934 if (Enabled) 2935 setSSELevel(Features, SSE2, Enabled); 2936 } else if (Name == "pclmul") { 2937 if (Enabled) 2938 setSSELevel(Features, SSE2, Enabled); 2939 } else if (Name == "avx") { 2940 setSSELevel(Features, AVX, Enabled); 2941 } else if (Name == "avx2") { 2942 setSSELevel(Features, AVX2, Enabled); 2943 } else if (Name == "avx512f") { 2944 setSSELevel(Features, AVX512F, Enabled); 2945 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2946 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2947 if (Enabled) 2948 setSSELevel(Features, AVX512F, Enabled); 2949 } else if (Name == "fma") { 2950 if (Enabled) 2951 setSSELevel(Features, AVX, Enabled); 2952 } else if (Name == "fma4") { 2953 setXOPLevel(Features, FMA4, Enabled); 2954 } else if (Name == "xop") { 2955 setXOPLevel(Features, XOP, Enabled); 2956 } else if (Name == "sse4a") { 2957 setXOPLevel(Features, SSE4A, Enabled); 2958 } else if (Name == "f16c") { 2959 if (Enabled) 2960 setSSELevel(Features, AVX, Enabled); 2961 } else if (Name == "sha") { 2962 if (Enabled) 2963 setSSELevel(Features, SSE2, Enabled); 2964 } else if (Name == "sse4") { 2965 // We can get here via the __target__ attribute since that's not controlled 2966 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2967 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2968 // disabled. 2969 if (Enabled) 2970 setSSELevel(Features, SSE42, Enabled); 2971 else 2972 setSSELevel(Features, SSE41, Enabled); 2973 } else if (Name == "xsave") { 2974 if (Enabled) 2975 setSSELevel(Features, AVX, Enabled); 2976 else 2977 Features["xsaveopt"] = false; 2978 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2979 if (Enabled) { 2980 Features["xsave"] = true; 2981 setSSELevel(Features, AVX, Enabled); 2982 } 2983 } 2984 } 2985 2986 /// handleTargetFeatures - Perform initialization based on the user 2987 /// configured set of features. 2988 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2989 DiagnosticsEngine &Diags) { 2990 for (const auto &Feature : Features) { 2991 if (Feature[0] != '+') 2992 continue; 2993 2994 if (Feature == "+aes") { 2995 HasAES = true; 2996 } else if (Feature == "+pclmul") { 2997 HasPCLMUL = true; 2998 } else if (Feature == "+lzcnt") { 2999 HasLZCNT = true; 3000 } else if (Feature == "+rdrnd") { 3001 HasRDRND = true; 3002 } else if (Feature == "+fsgsbase") { 3003 HasFSGSBASE = true; 3004 } else if (Feature == "+bmi") { 3005 HasBMI = true; 3006 } else if (Feature == "+bmi2") { 3007 HasBMI2 = true; 3008 } else if (Feature == "+popcnt") { 3009 HasPOPCNT = true; 3010 } else if (Feature == "+rtm") { 3011 HasRTM = true; 3012 } else if (Feature == "+prfchw") { 3013 HasPRFCHW = true; 3014 } else if (Feature == "+rdseed") { 3015 HasRDSEED = true; 3016 } else if (Feature == "+adx") { 3017 HasADX = true; 3018 } else if (Feature == "+tbm") { 3019 HasTBM = true; 3020 } else if (Feature == "+fma") { 3021 HasFMA = true; 3022 } else if (Feature == "+f16c") { 3023 HasF16C = true; 3024 } else if (Feature == "+avx512cd") { 3025 HasAVX512CD = true; 3026 } else if (Feature == "+avx512er") { 3027 HasAVX512ER = true; 3028 } else if (Feature == "+avx512pf") { 3029 HasAVX512PF = true; 3030 } else if (Feature == "+avx512dq") { 3031 HasAVX512DQ = true; 3032 } else if (Feature == "+avx512bw") { 3033 HasAVX512BW = true; 3034 } else if (Feature == "+avx512vl") { 3035 HasAVX512VL = true; 3036 } else if (Feature == "+sha") { 3037 HasSHA = true; 3038 } else if (Feature == "+cx16") { 3039 HasCX16 = true; 3040 } else if (Feature == "+fxsr") { 3041 HasFXSR = true; 3042 } else if (Feature == "+xsave") { 3043 HasXSAVE = true; 3044 } else if (Feature == "+xsaveopt") { 3045 HasXSAVEOPT = true; 3046 } else if (Feature == "+xsavec") { 3047 HasXSAVEC = true; 3048 } else if (Feature == "+xsaves") { 3049 HasXSAVES = true; 3050 } else if (Feature == "+pku") { 3051 HasPKU = true; 3052 } 3053 3054 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3055 .Case("+avx512f", AVX512F) 3056 .Case("+avx2", AVX2) 3057 .Case("+avx", AVX) 3058 .Case("+sse4.2", SSE42) 3059 .Case("+sse4.1", SSE41) 3060 .Case("+ssse3", SSSE3) 3061 .Case("+sse3", SSE3) 3062 .Case("+sse2", SSE2) 3063 .Case("+sse", SSE1) 3064 .Default(NoSSE); 3065 SSELevel = std::max(SSELevel, Level); 3066 3067 MMX3DNowEnum ThreeDNowLevel = 3068 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3069 .Case("+3dnowa", AMD3DNowAthlon) 3070 .Case("+3dnow", AMD3DNow) 3071 .Case("+mmx", MMX) 3072 .Default(NoMMX3DNow); 3073 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3074 3075 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3076 .Case("+xop", XOP) 3077 .Case("+fma4", FMA4) 3078 .Case("+sse4a", SSE4A) 3079 .Default(NoXOP); 3080 XOPLevel = std::max(XOPLevel, XLevel); 3081 } 3082 3083 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3084 // matches the selected sse level. 3085 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3086 (FPMath == FP_387 && SSELevel >= SSE1)) { 3087 Diags.Report(diag::err_target_unsupported_fpmath) << 3088 (FPMath == FP_SSE ? "sse" : "387"); 3089 return false; 3090 } 3091 3092 SimdDefaultAlign = 3093 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3094 return true; 3095 } 3096 3097 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3098 /// definitions for this particular subtarget. 3099 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3100 MacroBuilder &Builder) const { 3101 // Target identification. 3102 if (getTriple().getArch() == llvm::Triple::x86_64) { 3103 Builder.defineMacro("__amd64__"); 3104 Builder.defineMacro("__amd64"); 3105 Builder.defineMacro("__x86_64"); 3106 Builder.defineMacro("__x86_64__"); 3107 if (getTriple().getArchName() == "x86_64h") { 3108 Builder.defineMacro("__x86_64h"); 3109 Builder.defineMacro("__x86_64h__"); 3110 } 3111 } else { 3112 DefineStd(Builder, "i386", Opts); 3113 } 3114 3115 // Subtarget options. 3116 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3117 // truly should be based on -mtune options. 3118 switch (CPU) { 3119 case CK_Generic: 3120 break; 3121 case CK_i386: 3122 // The rest are coming from the i386 define above. 3123 Builder.defineMacro("__tune_i386__"); 3124 break; 3125 case CK_i486: 3126 case CK_WinChipC6: 3127 case CK_WinChip2: 3128 case CK_C3: 3129 defineCPUMacros(Builder, "i486"); 3130 break; 3131 case CK_PentiumMMX: 3132 Builder.defineMacro("__pentium_mmx__"); 3133 Builder.defineMacro("__tune_pentium_mmx__"); 3134 // Fallthrough 3135 case CK_i586: 3136 case CK_Pentium: 3137 defineCPUMacros(Builder, "i586"); 3138 defineCPUMacros(Builder, "pentium"); 3139 break; 3140 case CK_Pentium3: 3141 case CK_Pentium3M: 3142 case CK_PentiumM: 3143 Builder.defineMacro("__tune_pentium3__"); 3144 // Fallthrough 3145 case CK_Pentium2: 3146 case CK_C3_2: 3147 Builder.defineMacro("__tune_pentium2__"); 3148 // Fallthrough 3149 case CK_PentiumPro: 3150 Builder.defineMacro("__tune_i686__"); 3151 Builder.defineMacro("__tune_pentiumpro__"); 3152 // Fallthrough 3153 case CK_i686: 3154 Builder.defineMacro("__i686"); 3155 Builder.defineMacro("__i686__"); 3156 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3157 Builder.defineMacro("__pentiumpro"); 3158 Builder.defineMacro("__pentiumpro__"); 3159 break; 3160 case CK_Pentium4: 3161 case CK_Pentium4M: 3162 defineCPUMacros(Builder, "pentium4"); 3163 break; 3164 case CK_Yonah: 3165 case CK_Prescott: 3166 case CK_Nocona: 3167 defineCPUMacros(Builder, "nocona"); 3168 break; 3169 case CK_Core2: 3170 case CK_Penryn: 3171 defineCPUMacros(Builder, "core2"); 3172 break; 3173 case CK_Bonnell: 3174 defineCPUMacros(Builder, "atom"); 3175 break; 3176 case CK_Silvermont: 3177 defineCPUMacros(Builder, "slm"); 3178 break; 3179 case CK_Nehalem: 3180 case CK_Westmere: 3181 case CK_SandyBridge: 3182 case CK_IvyBridge: 3183 case CK_Haswell: 3184 case CK_Broadwell: 3185 // FIXME: Historically, we defined this legacy name, it would be nice to 3186 // remove it at some point. We've never exposed fine-grained names for 3187 // recent primary x86 CPUs, and we should keep it that way. 3188 defineCPUMacros(Builder, "corei7"); 3189 break; 3190 case CK_Skylake: 3191 // FIXME: Historically, we defined this legacy name, it would be nice to 3192 // remove it at some point. This is the only fine-grained CPU macro in the 3193 // main intel CPU line, and it would be better to not have these and force 3194 // people to use ISA macros. 3195 defineCPUMacros(Builder, "skx"); 3196 break; 3197 case CK_KNL: 3198 defineCPUMacros(Builder, "knl"); 3199 break; 3200 case CK_K6_2: 3201 Builder.defineMacro("__k6_2__"); 3202 Builder.defineMacro("__tune_k6_2__"); 3203 // Fallthrough 3204 case CK_K6_3: 3205 if (CPU != CK_K6_2) { // In case of fallthrough 3206 // FIXME: GCC may be enabling these in cases where some other k6 3207 // architecture is specified but -m3dnow is explicitly provided. The 3208 // exact semantics need to be determined and emulated here. 3209 Builder.defineMacro("__k6_3__"); 3210 Builder.defineMacro("__tune_k6_3__"); 3211 } 3212 // Fallthrough 3213 case CK_K6: 3214 defineCPUMacros(Builder, "k6"); 3215 break; 3216 case CK_Athlon: 3217 case CK_AthlonThunderbird: 3218 case CK_Athlon4: 3219 case CK_AthlonXP: 3220 case CK_AthlonMP: 3221 defineCPUMacros(Builder, "athlon"); 3222 if (SSELevel != NoSSE) { 3223 Builder.defineMacro("__athlon_sse__"); 3224 Builder.defineMacro("__tune_athlon_sse__"); 3225 } 3226 break; 3227 case CK_K8: 3228 case CK_K8SSE3: 3229 case CK_x86_64: 3230 case CK_Opteron: 3231 case CK_OpteronSSE3: 3232 case CK_Athlon64: 3233 case CK_Athlon64SSE3: 3234 case CK_AthlonFX: 3235 defineCPUMacros(Builder, "k8"); 3236 break; 3237 case CK_AMDFAM10: 3238 defineCPUMacros(Builder, "amdfam10"); 3239 break; 3240 case CK_BTVER1: 3241 defineCPUMacros(Builder, "btver1"); 3242 break; 3243 case CK_BTVER2: 3244 defineCPUMacros(Builder, "btver2"); 3245 break; 3246 case CK_BDVER1: 3247 defineCPUMacros(Builder, "bdver1"); 3248 break; 3249 case CK_BDVER2: 3250 defineCPUMacros(Builder, "bdver2"); 3251 break; 3252 case CK_BDVER3: 3253 defineCPUMacros(Builder, "bdver3"); 3254 break; 3255 case CK_BDVER4: 3256 defineCPUMacros(Builder, "bdver4"); 3257 break; 3258 case CK_Geode: 3259 defineCPUMacros(Builder, "geode"); 3260 break; 3261 } 3262 3263 // Target properties. 3264 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3265 3266 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3267 // functions in glibc header files that use FP Stack inline asm which the 3268 // backend can't deal with (PR879). 3269 Builder.defineMacro("__NO_MATH_INLINES"); 3270 3271 if (HasAES) 3272 Builder.defineMacro("__AES__"); 3273 3274 if (HasPCLMUL) 3275 Builder.defineMacro("__PCLMUL__"); 3276 3277 if (HasLZCNT) 3278 Builder.defineMacro("__LZCNT__"); 3279 3280 if (HasRDRND) 3281 Builder.defineMacro("__RDRND__"); 3282 3283 if (HasFSGSBASE) 3284 Builder.defineMacro("__FSGSBASE__"); 3285 3286 if (HasBMI) 3287 Builder.defineMacro("__BMI__"); 3288 3289 if (HasBMI2) 3290 Builder.defineMacro("__BMI2__"); 3291 3292 if (HasPOPCNT) 3293 Builder.defineMacro("__POPCNT__"); 3294 3295 if (HasRTM) 3296 Builder.defineMacro("__RTM__"); 3297 3298 if (HasPRFCHW) 3299 Builder.defineMacro("__PRFCHW__"); 3300 3301 if (HasRDSEED) 3302 Builder.defineMacro("__RDSEED__"); 3303 3304 if (HasADX) 3305 Builder.defineMacro("__ADX__"); 3306 3307 if (HasTBM) 3308 Builder.defineMacro("__TBM__"); 3309 3310 switch (XOPLevel) { 3311 case XOP: 3312 Builder.defineMacro("__XOP__"); 3313 case FMA4: 3314 Builder.defineMacro("__FMA4__"); 3315 case SSE4A: 3316 Builder.defineMacro("__SSE4A__"); 3317 case NoXOP: 3318 break; 3319 } 3320 3321 if (HasFMA) 3322 Builder.defineMacro("__FMA__"); 3323 3324 if (HasF16C) 3325 Builder.defineMacro("__F16C__"); 3326 3327 if (HasAVX512CD) 3328 Builder.defineMacro("__AVX512CD__"); 3329 if (HasAVX512ER) 3330 Builder.defineMacro("__AVX512ER__"); 3331 if (HasAVX512PF) 3332 Builder.defineMacro("__AVX512PF__"); 3333 if (HasAVX512DQ) 3334 Builder.defineMacro("__AVX512DQ__"); 3335 if (HasAVX512BW) 3336 Builder.defineMacro("__AVX512BW__"); 3337 if (HasAVX512VL) 3338 Builder.defineMacro("__AVX512VL__"); 3339 3340 if (HasSHA) 3341 Builder.defineMacro("__SHA__"); 3342 3343 if (HasFXSR) 3344 Builder.defineMacro("__FXSR__"); 3345 if (HasXSAVE) 3346 Builder.defineMacro("__XSAVE__"); 3347 if (HasXSAVEOPT) 3348 Builder.defineMacro("__XSAVEOPT__"); 3349 if (HasXSAVEC) 3350 Builder.defineMacro("__XSAVEC__"); 3351 if (HasXSAVES) 3352 Builder.defineMacro("__XSAVES__"); 3353 if (HasPKU) 3354 Builder.defineMacro("__PKU__"); 3355 if (HasCX16) 3356 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3357 3358 // Each case falls through to the previous one here. 3359 switch (SSELevel) { 3360 case AVX512F: 3361 Builder.defineMacro("__AVX512F__"); 3362 case AVX2: 3363 Builder.defineMacro("__AVX2__"); 3364 case AVX: 3365 Builder.defineMacro("__AVX__"); 3366 case SSE42: 3367 Builder.defineMacro("__SSE4_2__"); 3368 case SSE41: 3369 Builder.defineMacro("__SSE4_1__"); 3370 case SSSE3: 3371 Builder.defineMacro("__SSSE3__"); 3372 case SSE3: 3373 Builder.defineMacro("__SSE3__"); 3374 case SSE2: 3375 Builder.defineMacro("__SSE2__"); 3376 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3377 case SSE1: 3378 Builder.defineMacro("__SSE__"); 3379 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3380 case NoSSE: 3381 break; 3382 } 3383 3384 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3385 switch (SSELevel) { 3386 case AVX512F: 3387 case AVX2: 3388 case AVX: 3389 case SSE42: 3390 case SSE41: 3391 case SSSE3: 3392 case SSE3: 3393 case SSE2: 3394 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3395 break; 3396 case SSE1: 3397 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3398 break; 3399 default: 3400 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3401 } 3402 } 3403 3404 // Each case falls through to the previous one here. 3405 switch (MMX3DNowLevel) { 3406 case AMD3DNowAthlon: 3407 Builder.defineMacro("__3dNOW_A__"); 3408 case AMD3DNow: 3409 Builder.defineMacro("__3dNOW__"); 3410 case MMX: 3411 Builder.defineMacro("__MMX__"); 3412 case NoMMX3DNow: 3413 break; 3414 } 3415 3416 if (CPU >= CK_i486) { 3417 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3418 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3419 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3420 } 3421 if (CPU >= CK_i586) 3422 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3423 } 3424 3425 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3426 return llvm::StringSwitch<bool>(Feature) 3427 .Case("aes", HasAES) 3428 .Case("avx", SSELevel >= AVX) 3429 .Case("avx2", SSELevel >= AVX2) 3430 .Case("avx512f", SSELevel >= AVX512F) 3431 .Case("avx512cd", HasAVX512CD) 3432 .Case("avx512er", HasAVX512ER) 3433 .Case("avx512pf", HasAVX512PF) 3434 .Case("avx512dq", HasAVX512DQ) 3435 .Case("avx512bw", HasAVX512BW) 3436 .Case("avx512vl", HasAVX512VL) 3437 .Case("bmi", HasBMI) 3438 .Case("bmi2", HasBMI2) 3439 .Case("cx16", HasCX16) 3440 .Case("f16c", HasF16C) 3441 .Case("fma", HasFMA) 3442 .Case("fma4", XOPLevel >= FMA4) 3443 .Case("fsgsbase", HasFSGSBASE) 3444 .Case("fxsr", HasFXSR) 3445 .Case("lzcnt", HasLZCNT) 3446 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3447 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3448 .Case("mmx", MMX3DNowLevel >= MMX) 3449 .Case("pclmul", HasPCLMUL) 3450 .Case("popcnt", HasPOPCNT) 3451 .Case("prfchw", HasPRFCHW) 3452 .Case("rdrnd", HasRDRND) 3453 .Case("rdseed", HasRDSEED) 3454 .Case("rtm", HasRTM) 3455 .Case("sha", HasSHA) 3456 .Case("sse", SSELevel >= SSE1) 3457 .Case("sse2", SSELevel >= SSE2) 3458 .Case("sse3", SSELevel >= SSE3) 3459 .Case("ssse3", SSELevel >= SSSE3) 3460 .Case("sse4.1", SSELevel >= SSE41) 3461 .Case("sse4.2", SSELevel >= SSE42) 3462 .Case("sse4a", XOPLevel >= SSE4A) 3463 .Case("tbm", HasTBM) 3464 .Case("x86", true) 3465 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3466 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3467 .Case("xop", XOPLevel >= XOP) 3468 .Case("xsave", HasXSAVE) 3469 .Case("xsavec", HasXSAVEC) 3470 .Case("xsaves", HasXSAVES) 3471 .Case("xsaveopt", HasXSAVEOPT) 3472 .Case("pku", HasPKU) 3473 .Default(false); 3474 } 3475 3476 // We can't use a generic validation scheme for the features accepted here 3477 // versus subtarget features accepted in the target attribute because the 3478 // bitfield structure that's initialized in the runtime only supports the 3479 // below currently rather than the full range of subtarget features. (See 3480 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3481 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3482 return llvm::StringSwitch<bool>(FeatureStr) 3483 .Case("cmov", true) 3484 .Case("mmx", true) 3485 .Case("popcnt", true) 3486 .Case("sse", true) 3487 .Case("sse2", true) 3488 .Case("sse3", true) 3489 .Case("sse4.1", true) 3490 .Case("sse4.2", true) 3491 .Case("avx", true) 3492 .Case("avx2", true) 3493 .Case("sse4a", true) 3494 .Case("fma4", true) 3495 .Case("xop", true) 3496 .Case("fma", true) 3497 .Case("avx512f", true) 3498 .Case("bmi", true) 3499 .Case("bmi2", true) 3500 .Default(false); 3501 } 3502 3503 bool 3504 X86TargetInfo::validateAsmConstraint(const char *&Name, 3505 TargetInfo::ConstraintInfo &Info) const { 3506 switch (*Name) { 3507 default: return false; 3508 // Constant constraints. 3509 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3510 // instructions. 3511 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3512 // x86_64 instructions. 3513 case 's': 3514 Info.setRequiresImmediate(); 3515 return true; 3516 case 'I': 3517 Info.setRequiresImmediate(0, 31); 3518 return true; 3519 case 'J': 3520 Info.setRequiresImmediate(0, 63); 3521 return true; 3522 case 'K': 3523 Info.setRequiresImmediate(-128, 127); 3524 return true; 3525 case 'L': 3526 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3527 return true; 3528 case 'M': 3529 Info.setRequiresImmediate(0, 3); 3530 return true; 3531 case 'N': 3532 Info.setRequiresImmediate(0, 255); 3533 return true; 3534 case 'O': 3535 Info.setRequiresImmediate(0, 127); 3536 return true; 3537 // Register constraints. 3538 case 'Y': // 'Y' is the first character for several 2-character constraints. 3539 // Shift the pointer to the second character of the constraint. 3540 Name++; 3541 switch (*Name) { 3542 default: 3543 return false; 3544 case '0': // First SSE register. 3545 case 't': // Any SSE register, when SSE2 is enabled. 3546 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3547 case 'm': // Any MMX register, when inter-unit moves enabled. 3548 Info.setAllowsRegister(); 3549 return true; 3550 } 3551 case 'f': // Any x87 floating point stack register. 3552 // Constraint 'f' cannot be used for output operands. 3553 if (Info.ConstraintStr[0] == '=') 3554 return false; 3555 Info.setAllowsRegister(); 3556 return true; 3557 case 'a': // eax. 3558 case 'b': // ebx. 3559 case 'c': // ecx. 3560 case 'd': // edx. 3561 case 'S': // esi. 3562 case 'D': // edi. 3563 case 'A': // edx:eax. 3564 case 't': // Top of floating point stack. 3565 case 'u': // Second from top of floating point stack. 3566 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3567 case 'y': // Any MMX register. 3568 case 'x': // Any SSE register. 3569 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3570 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3571 case 'l': // "Index" registers: any general register that can be used as an 3572 // index in a base+index memory access. 3573 Info.setAllowsRegister(); 3574 return true; 3575 // Floating point constant constraints. 3576 case 'C': // SSE floating point constant. 3577 case 'G': // x87 floating point constant. 3578 return true; 3579 } 3580 } 3581 3582 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3583 unsigned Size) const { 3584 // Strip off constraint modifiers. 3585 while (Constraint[0] == '=' || 3586 Constraint[0] == '+' || 3587 Constraint[0] == '&') 3588 Constraint = Constraint.substr(1); 3589 3590 return validateOperandSize(Constraint, Size); 3591 } 3592 3593 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3594 unsigned Size) const { 3595 return validateOperandSize(Constraint, Size); 3596 } 3597 3598 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3599 unsigned Size) const { 3600 switch (Constraint[0]) { 3601 default: break; 3602 case 'y': 3603 return Size <= 64; 3604 case 'f': 3605 case 't': 3606 case 'u': 3607 return Size <= 128; 3608 case 'x': 3609 if (SSELevel >= AVX512F) 3610 // 512-bit zmm registers can be used if target supports AVX512F. 3611 return Size <= 512U; 3612 else if (SSELevel >= AVX) 3613 // 256-bit ymm registers can be used if target supports AVX. 3614 return Size <= 256U; 3615 return Size <= 128U; 3616 case 'Y': 3617 // 'Y' is the first character for several 2-character constraints. 3618 switch (Constraint[1]) { 3619 default: break; 3620 case 'm': 3621 // 'Ym' is synonymous with 'y'. 3622 return Size <= 64; 3623 case 'i': 3624 case 't': 3625 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3626 if (SSELevel >= AVX512F) 3627 return Size <= 512U; 3628 else if (SSELevel >= AVX) 3629 return Size <= 256U; 3630 return SSELevel >= SSE2 && Size <= 128U; 3631 } 3632 3633 } 3634 3635 return true; 3636 } 3637 3638 std::string 3639 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3640 switch (*Constraint) { 3641 case 'a': return std::string("{ax}"); 3642 case 'b': return std::string("{bx}"); 3643 case 'c': return std::string("{cx}"); 3644 case 'd': return std::string("{dx}"); 3645 case 'S': return std::string("{si}"); 3646 case 'D': return std::string("{di}"); 3647 case 'p': // address 3648 return std::string("im"); 3649 case 't': // top of floating point stack. 3650 return std::string("{st}"); 3651 case 'u': // second from top of floating point stack. 3652 return std::string("{st(1)}"); // second from top of floating point stack. 3653 default: 3654 return std::string(1, *Constraint); 3655 } 3656 } 3657 3658 // X86-32 generic target 3659 class X86_32TargetInfo : public X86TargetInfo { 3660 public: 3661 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3662 DoubleAlign = LongLongAlign = 32; 3663 LongDoubleWidth = 96; 3664 LongDoubleAlign = 32; 3665 SuitableAlign = 128; 3666 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3667 SizeType = UnsignedInt; 3668 PtrDiffType = SignedInt; 3669 IntPtrType = SignedInt; 3670 RegParmMax = 3; 3671 3672 // Use fpret for all types. 3673 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3674 (1 << TargetInfo::Double) | 3675 (1 << TargetInfo::LongDouble)); 3676 3677 // x86-32 has atomics up to 8 bytes 3678 // FIXME: Check that we actually have cmpxchg8b before setting 3679 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3680 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3681 } 3682 BuiltinVaListKind getBuiltinVaListKind() const override { 3683 return TargetInfo::CharPtrBuiltinVaList; 3684 } 3685 3686 int getEHDataRegisterNumber(unsigned RegNo) const override { 3687 if (RegNo == 0) return 0; 3688 if (RegNo == 1) return 2; 3689 return -1; 3690 } 3691 bool validateOperandSize(StringRef Constraint, 3692 unsigned Size) const override { 3693 switch (Constraint[0]) { 3694 default: break; 3695 case 'R': 3696 case 'q': 3697 case 'Q': 3698 case 'a': 3699 case 'b': 3700 case 'c': 3701 case 'd': 3702 case 'S': 3703 case 'D': 3704 return Size <= 32; 3705 case 'A': 3706 return Size <= 64; 3707 } 3708 3709 return X86TargetInfo::validateOperandSize(Constraint, Size); 3710 } 3711 }; 3712 3713 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3714 public: 3715 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3716 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3717 3718 unsigned getFloatEvalMethod() const override { 3719 unsigned Major, Minor, Micro; 3720 getTriple().getOSVersion(Major, Minor, Micro); 3721 // New NetBSD uses the default rounding mode. 3722 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3723 return X86_32TargetInfo::getFloatEvalMethod(); 3724 // NetBSD before 6.99.26 defaults to "double" rounding. 3725 return 1; 3726 } 3727 }; 3728 3729 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3730 public: 3731 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3732 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3733 SizeType = UnsignedLong; 3734 IntPtrType = SignedLong; 3735 PtrDiffType = SignedLong; 3736 } 3737 }; 3738 3739 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3740 public: 3741 BitrigI386TargetInfo(const llvm::Triple &Triple) 3742 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3743 SizeType = UnsignedLong; 3744 IntPtrType = SignedLong; 3745 PtrDiffType = SignedLong; 3746 } 3747 }; 3748 3749 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3750 public: 3751 DarwinI386TargetInfo(const llvm::Triple &Triple) 3752 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3753 LongDoubleWidth = 128; 3754 LongDoubleAlign = 128; 3755 SuitableAlign = 128; 3756 MaxVectorAlign = 256; 3757 // The watchOS simulator uses the builtin bool type for Objective-C. 3758 llvm::Triple T = llvm::Triple(Triple); 3759 if (T.isWatchOS()) 3760 UseSignedCharForObjCBool = false; 3761 SizeType = UnsignedLong; 3762 IntPtrType = SignedLong; 3763 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3764 HasAlignMac68kSupport = true; 3765 } 3766 3767 bool handleTargetFeatures(std::vector<std::string> &Features, 3768 DiagnosticsEngine &Diags) override { 3769 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3770 Diags)) 3771 return false; 3772 // We now know the features we have: we can decide how to align vectors. 3773 MaxVectorAlign = 3774 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3775 return true; 3776 } 3777 }; 3778 3779 // x86-32 Windows target 3780 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3781 public: 3782 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3783 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3784 WCharType = UnsignedShort; 3785 DoubleAlign = LongLongAlign = 64; 3786 bool IsWinCOFF = 3787 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3788 DataLayoutString = IsWinCOFF 3789 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3790 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3791 } 3792 void getTargetDefines(const LangOptions &Opts, 3793 MacroBuilder &Builder) const override { 3794 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3795 } 3796 }; 3797 3798 // x86-32 Windows Visual Studio target 3799 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3800 public: 3801 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3802 : WindowsX86_32TargetInfo(Triple) { 3803 LongDoubleWidth = LongDoubleAlign = 64; 3804 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3805 } 3806 void getTargetDefines(const LangOptions &Opts, 3807 MacroBuilder &Builder) const override { 3808 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3809 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3810 // The value of the following reflects processor type. 3811 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3812 // We lost the original triple, so we use the default. 3813 Builder.defineMacro("_M_IX86", "600"); 3814 } 3815 }; 3816 3817 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3818 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3819 // supports __declspec natively under -fms-extensions, but we define a no-op 3820 // __declspec macro anyway for pre-processor compatibility. 3821 if (Opts.MicrosoftExt) 3822 Builder.defineMacro("__declspec", "__declspec"); 3823 else 3824 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3825 3826 if (!Opts.MicrosoftExt) { 3827 // Provide macros for all the calling convention keywords. Provide both 3828 // single and double underscore prefixed variants. These are available on 3829 // x64 as well as x86, even though they have no effect. 3830 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3831 for (const char *CC : CCs) { 3832 std::string GCCSpelling = "__attribute__((__"; 3833 GCCSpelling += CC; 3834 GCCSpelling += "__))"; 3835 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3836 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3837 } 3838 } 3839 } 3840 3841 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3842 Builder.defineMacro("__MSVCRT__"); 3843 Builder.defineMacro("__MINGW32__"); 3844 addCygMingDefines(Opts, Builder); 3845 } 3846 3847 // x86-32 MinGW target 3848 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3849 public: 3850 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3851 : WindowsX86_32TargetInfo(Triple) {} 3852 void getTargetDefines(const LangOptions &Opts, 3853 MacroBuilder &Builder) const override { 3854 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3855 DefineStd(Builder, "WIN32", Opts); 3856 DefineStd(Builder, "WINNT", Opts); 3857 Builder.defineMacro("_X86_"); 3858 addMinGWDefines(Opts, Builder); 3859 } 3860 }; 3861 3862 // x86-32 Cygwin target 3863 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3864 public: 3865 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3866 : X86_32TargetInfo(Triple) { 3867 WCharType = UnsignedShort; 3868 DoubleAlign = LongLongAlign = 64; 3869 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3870 } 3871 void getTargetDefines(const LangOptions &Opts, 3872 MacroBuilder &Builder) const override { 3873 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3874 Builder.defineMacro("_X86_"); 3875 Builder.defineMacro("__CYGWIN__"); 3876 Builder.defineMacro("__CYGWIN32__"); 3877 addCygMingDefines(Opts, Builder); 3878 DefineStd(Builder, "unix", Opts); 3879 if (Opts.CPlusPlus) 3880 Builder.defineMacro("_GNU_SOURCE"); 3881 } 3882 }; 3883 3884 // x86-32 Haiku target 3885 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3886 public: 3887 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3888 SizeType = UnsignedLong; 3889 IntPtrType = SignedLong; 3890 PtrDiffType = SignedLong; 3891 ProcessIDType = SignedLong; 3892 this->UserLabelPrefix = ""; 3893 this->TLSSupported = false; 3894 } 3895 void getTargetDefines(const LangOptions &Opts, 3896 MacroBuilder &Builder) const override { 3897 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3898 Builder.defineMacro("__INTEL__"); 3899 Builder.defineMacro("__HAIKU__"); 3900 } 3901 }; 3902 3903 // X86-32 MCU target 3904 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3905 public: 3906 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3907 LongDoubleWidth = 64; 3908 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3909 } 3910 3911 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3912 // On MCU we support only C calling convention. 3913 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3914 } 3915 3916 void getTargetDefines(const LangOptions &Opts, 3917 MacroBuilder &Builder) const override { 3918 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3919 Builder.defineMacro("__iamcu"); 3920 Builder.defineMacro("__iamcu__"); 3921 } 3922 }; 3923 3924 // RTEMS Target 3925 template<typename Target> 3926 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3927 protected: 3928 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3929 MacroBuilder &Builder) const override { 3930 // RTEMS defines; list based off of gcc output 3931 3932 Builder.defineMacro("__rtems__"); 3933 Builder.defineMacro("__ELF__"); 3934 } 3935 3936 public: 3937 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3938 this->UserLabelPrefix = ""; 3939 3940 switch (Triple.getArch()) { 3941 default: 3942 case llvm::Triple::x86: 3943 // this->MCountName = ".mcount"; 3944 break; 3945 case llvm::Triple::mips: 3946 case llvm::Triple::mipsel: 3947 case llvm::Triple::ppc: 3948 case llvm::Triple::ppc64: 3949 case llvm::Triple::ppc64le: 3950 // this->MCountName = "_mcount"; 3951 break; 3952 case llvm::Triple::arm: 3953 // this->MCountName = "__mcount"; 3954 break; 3955 } 3956 } 3957 }; 3958 3959 // x86-32 RTEMS target 3960 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3961 public: 3962 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3963 SizeType = UnsignedLong; 3964 IntPtrType = SignedLong; 3965 PtrDiffType = SignedLong; 3966 this->UserLabelPrefix = ""; 3967 } 3968 void getTargetDefines(const LangOptions &Opts, 3969 MacroBuilder &Builder) const override { 3970 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3971 Builder.defineMacro("__INTEL__"); 3972 Builder.defineMacro("__rtems__"); 3973 } 3974 }; 3975 3976 // x86-64 generic target 3977 class X86_64TargetInfo : public X86TargetInfo { 3978 public: 3979 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3980 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3981 bool IsWinCOFF = 3982 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3983 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3984 LongDoubleWidth = 128; 3985 LongDoubleAlign = 128; 3986 LargeArrayMinWidth = 128; 3987 LargeArrayAlign = 128; 3988 SuitableAlign = 128; 3989 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3990 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3991 IntPtrType = IsX32 ? SignedInt : SignedLong; 3992 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3993 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3994 RegParmMax = 6; 3995 3996 // Pointers are 32-bit in x32. 3997 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3998 : IsWinCOFF 3999 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4000 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 4001 4002 // Use fpret only for long double. 4003 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4004 4005 // Use fp2ret for _Complex long double. 4006 ComplexLongDoubleUsesFP2Ret = true; 4007 4008 // Make __builtin_ms_va_list available. 4009 HasBuiltinMSVaList = true; 4010 4011 // x86-64 has atomics up to 16 bytes. 4012 MaxAtomicPromoteWidth = 128; 4013 MaxAtomicInlineWidth = 128; 4014 } 4015 BuiltinVaListKind getBuiltinVaListKind() const override { 4016 return TargetInfo::X86_64ABIBuiltinVaList; 4017 } 4018 4019 int getEHDataRegisterNumber(unsigned RegNo) const override { 4020 if (RegNo == 0) return 0; 4021 if (RegNo == 1) return 1; 4022 return -1; 4023 } 4024 4025 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4026 return (CC == CC_C || 4027 CC == CC_X86VectorCall || 4028 CC == CC_IntelOclBicc || 4029 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 4030 } 4031 4032 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4033 return CC_C; 4034 } 4035 4036 // for x32 we need it here explicitly 4037 bool hasInt128Type() const override { return true; } 4038 4039 bool validateGlobalRegisterVariable(StringRef RegName, 4040 unsigned RegSize, 4041 bool &HasSizeMismatch) const override { 4042 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4043 // handle. 4044 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4045 // Check that the register size is 64-bit. 4046 HasSizeMismatch = RegSize != 64; 4047 return true; 4048 } 4049 4050 // Check if the register is a 32-bit register the backend can handle. 4051 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4052 HasSizeMismatch); 4053 } 4054 }; 4055 4056 // x86-64 Windows target 4057 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4058 public: 4059 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4060 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4061 WCharType = UnsignedShort; 4062 LongWidth = LongAlign = 32; 4063 DoubleAlign = LongLongAlign = 64; 4064 IntMaxType = SignedLongLong; 4065 Int64Type = SignedLongLong; 4066 SizeType = UnsignedLongLong; 4067 PtrDiffType = SignedLongLong; 4068 IntPtrType = SignedLongLong; 4069 this->UserLabelPrefix = ""; 4070 } 4071 4072 void getTargetDefines(const LangOptions &Opts, 4073 MacroBuilder &Builder) const override { 4074 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4075 Builder.defineMacro("_WIN64"); 4076 } 4077 4078 BuiltinVaListKind getBuiltinVaListKind() const override { 4079 return TargetInfo::CharPtrBuiltinVaList; 4080 } 4081 4082 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4083 switch (CC) { 4084 case CC_X86StdCall: 4085 case CC_X86ThisCall: 4086 case CC_X86FastCall: 4087 return CCCR_Ignore; 4088 case CC_C: 4089 case CC_X86VectorCall: 4090 case CC_IntelOclBicc: 4091 case CC_X86_64SysV: 4092 return CCCR_OK; 4093 default: 4094 return CCCR_Warning; 4095 } 4096 } 4097 }; 4098 4099 // x86-64 Windows Visual Studio target 4100 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4101 public: 4102 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4103 : WindowsX86_64TargetInfo(Triple) { 4104 LongDoubleWidth = LongDoubleAlign = 64; 4105 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4106 } 4107 void getTargetDefines(const LangOptions &Opts, 4108 MacroBuilder &Builder) const override { 4109 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4110 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4111 Builder.defineMacro("_M_X64", "100"); 4112 Builder.defineMacro("_M_AMD64", "100"); 4113 } 4114 }; 4115 4116 // x86-64 MinGW target 4117 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4118 public: 4119 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4120 : WindowsX86_64TargetInfo(Triple) { 4121 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4122 // with x86 FP ops. Weird. 4123 LongDoubleWidth = LongDoubleAlign = 128; 4124 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4125 } 4126 4127 void getTargetDefines(const LangOptions &Opts, 4128 MacroBuilder &Builder) const override { 4129 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4130 DefineStd(Builder, "WIN64", Opts); 4131 Builder.defineMacro("__MINGW64__"); 4132 addMinGWDefines(Opts, Builder); 4133 4134 // GCC defines this macro when it is using __gxx_personality_seh0. 4135 if (!Opts.SjLjExceptions) 4136 Builder.defineMacro("__SEH__"); 4137 } 4138 }; 4139 4140 // x86-64 Cygwin target 4141 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4142 public: 4143 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4144 : X86_64TargetInfo(Triple) { 4145 TLSSupported = false; 4146 WCharType = UnsignedShort; 4147 } 4148 void getTargetDefines(const LangOptions &Opts, 4149 MacroBuilder &Builder) const override { 4150 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4151 Builder.defineMacro("__x86_64__"); 4152 Builder.defineMacro("__CYGWIN__"); 4153 Builder.defineMacro("__CYGWIN64__"); 4154 addCygMingDefines(Opts, Builder); 4155 DefineStd(Builder, "unix", Opts); 4156 if (Opts.CPlusPlus) 4157 Builder.defineMacro("_GNU_SOURCE"); 4158 4159 // GCC defines this macro when it is using __gxx_personality_seh0. 4160 if (!Opts.SjLjExceptions) 4161 Builder.defineMacro("__SEH__"); 4162 } 4163 }; 4164 4165 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4166 public: 4167 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4168 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4169 Int64Type = SignedLongLong; 4170 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4171 llvm::Triple T = llvm::Triple(Triple); 4172 if (T.isiOS()) 4173 UseSignedCharForObjCBool = false; 4174 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4175 } 4176 4177 bool handleTargetFeatures(std::vector<std::string> &Features, 4178 DiagnosticsEngine &Diags) override { 4179 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4180 Diags)) 4181 return false; 4182 // We now know the features we have: we can decide how to align vectors. 4183 MaxVectorAlign = 4184 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4185 return true; 4186 } 4187 }; 4188 4189 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4190 public: 4191 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4192 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4193 IntMaxType = SignedLongLong; 4194 Int64Type = SignedLongLong; 4195 } 4196 }; 4197 4198 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4199 public: 4200 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4201 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4202 IntMaxType = SignedLongLong; 4203 Int64Type = SignedLongLong; 4204 } 4205 }; 4206 4207 class ARMTargetInfo : public TargetInfo { 4208 // Possible FPU choices. 4209 enum FPUMode { 4210 VFP2FPU = (1 << 0), 4211 VFP3FPU = (1 << 1), 4212 VFP4FPU = (1 << 2), 4213 NeonFPU = (1 << 3), 4214 FPARMV8 = (1 << 4) 4215 }; 4216 4217 // Possible HWDiv features. 4218 enum HWDivMode { 4219 HWDivThumb = (1 << 0), 4220 HWDivARM = (1 << 1) 4221 }; 4222 4223 static bool FPUModeIsVFP(FPUMode Mode) { 4224 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4225 } 4226 4227 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4228 static const char * const GCCRegNames[]; 4229 4230 std::string ABI, CPU; 4231 4232 StringRef CPUProfile; 4233 StringRef CPUAttr; 4234 4235 enum { 4236 FP_Default, 4237 FP_VFP, 4238 FP_Neon 4239 } FPMath; 4240 4241 unsigned ArchISA; 4242 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4243 unsigned ArchProfile; 4244 unsigned ArchVersion; 4245 4246 unsigned FPU : 5; 4247 4248 unsigned IsAAPCS : 1; 4249 unsigned HWDiv : 2; 4250 4251 // Initialized via features. 4252 unsigned SoftFloat : 1; 4253 unsigned SoftFloatABI : 1; 4254 4255 unsigned CRC : 1; 4256 unsigned Crypto : 1; 4257 unsigned DSP : 1; 4258 unsigned Unaligned : 1; 4259 4260 enum { 4261 LDREX_B = (1 << 0), /// byte (8-bit) 4262 LDREX_H = (1 << 1), /// half (16-bit) 4263 LDREX_W = (1 << 2), /// word (32-bit) 4264 LDREX_D = (1 << 3), /// double (64-bit) 4265 }; 4266 4267 uint32_t LDREX; 4268 4269 // ACLE 6.5.1 Hardware floating point 4270 enum { 4271 HW_FP_HP = (1 << 1), /// half (16-bit) 4272 HW_FP_SP = (1 << 2), /// single (32-bit) 4273 HW_FP_DP = (1 << 3), /// double (64-bit) 4274 }; 4275 uint32_t HW_FP; 4276 4277 static const Builtin::Info BuiltinInfo[]; 4278 4279 void setABIAAPCS() { 4280 IsAAPCS = true; 4281 4282 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4283 const llvm::Triple &T = getTriple(); 4284 4285 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4286 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4287 T.getOS() == llvm::Triple::Bitrig) 4288 SizeType = UnsignedLong; 4289 else 4290 SizeType = UnsignedInt; 4291 4292 switch (T.getOS()) { 4293 case llvm::Triple::NetBSD: 4294 WCharType = SignedInt; 4295 break; 4296 case llvm::Triple::Win32: 4297 WCharType = UnsignedShort; 4298 break; 4299 case llvm::Triple::Linux: 4300 default: 4301 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4302 WCharType = UnsignedInt; 4303 break; 4304 } 4305 4306 UseBitFieldTypeAlignment = true; 4307 4308 ZeroLengthBitfieldBoundary = 0; 4309 4310 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4311 // so set preferred for small types to 32. 4312 if (T.isOSBinFormatMachO()) { 4313 DataLayoutString = 4314 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4315 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4316 } else if (T.isOSWindows()) { 4317 assert(!BigEndian && "Windows on ARM does not support big endian"); 4318 DataLayoutString = "e" 4319 "-m:w" 4320 "-p:32:32" 4321 "-i64:64" 4322 "-v128:64:128" 4323 "-a:0:32" 4324 "-n32" 4325 "-S64"; 4326 } else if (T.isOSNaCl()) { 4327 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4328 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4329 } else { 4330 DataLayoutString = 4331 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4332 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4333 } 4334 4335 // FIXME: Enumerated types are variable width in straight AAPCS. 4336 } 4337 4338 void setABIAPCS(bool IsAAPCS16) { 4339 const llvm::Triple &T = getTriple(); 4340 4341 IsAAPCS = false; 4342 4343 if (IsAAPCS16) 4344 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4345 else 4346 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4347 4348 // size_t is unsigned int on FreeBSD. 4349 if (T.getOS() == llvm::Triple::FreeBSD) 4350 SizeType = UnsignedInt; 4351 else 4352 SizeType = UnsignedLong; 4353 4354 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4355 WCharType = SignedInt; 4356 4357 // Do not respect the alignment of bit-field types when laying out 4358 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4359 UseBitFieldTypeAlignment = false; 4360 4361 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4362 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4363 /// gcc. 4364 ZeroLengthBitfieldBoundary = 32; 4365 4366 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4367 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4368 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4369 } else if (T.isOSBinFormatMachO()) 4370 DataLayoutString = 4371 BigEndian 4372 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4373 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4374 else 4375 DataLayoutString = 4376 BigEndian 4377 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4378 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4379 4380 // FIXME: Override "preferred align" for double and long long. 4381 } 4382 4383 void setArchInfo() { 4384 StringRef ArchName = getTriple().getArchName(); 4385 4386 ArchISA = llvm::ARM::parseArchISA(ArchName); 4387 CPU = llvm::ARM::getDefaultCPU(ArchName); 4388 unsigned AK = llvm::ARM::parseArch(ArchName); 4389 if (AK != llvm::ARM::AK_INVALID) 4390 ArchKind = AK; 4391 setArchInfo(ArchKind); 4392 } 4393 4394 void setArchInfo(unsigned Kind) { 4395 StringRef SubArch; 4396 4397 // cache TargetParser info 4398 ArchKind = Kind; 4399 SubArch = llvm::ARM::getSubArch(ArchKind); 4400 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4401 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4402 4403 // cache CPU related strings 4404 CPUAttr = getCPUAttr(); 4405 CPUProfile = getCPUProfile(); 4406 } 4407 4408 void setAtomic() { 4409 // when triple does not specify a sub arch, 4410 // then we are not using inline atomics 4411 bool ShouldUseInlineAtomic = 4412 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4413 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4414 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4415 if (ArchProfile == llvm::ARM::PK_M) { 4416 MaxAtomicPromoteWidth = 32; 4417 if (ShouldUseInlineAtomic) 4418 MaxAtomicInlineWidth = 32; 4419 } 4420 else { 4421 MaxAtomicPromoteWidth = 64; 4422 if (ShouldUseInlineAtomic) 4423 MaxAtomicInlineWidth = 64; 4424 } 4425 } 4426 4427 bool isThumb() const { 4428 return (ArchISA == llvm::ARM::IK_THUMB); 4429 } 4430 4431 bool supportsThumb() const { 4432 return CPUAttr.count('T') || ArchVersion >= 6; 4433 } 4434 4435 bool supportsThumb2() const { 4436 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4437 } 4438 4439 StringRef getCPUAttr() const { 4440 // For most sub-arches, the build attribute CPU name is enough. 4441 // For Cortex variants, it's slightly different. 4442 switch(ArchKind) { 4443 default: 4444 return llvm::ARM::getCPUAttr(ArchKind); 4445 case llvm::ARM::AK_ARMV6M: 4446 return "6M"; 4447 case llvm::ARM::AK_ARMV7S: 4448 return "7S"; 4449 case llvm::ARM::AK_ARMV7A: 4450 return "7A"; 4451 case llvm::ARM::AK_ARMV7R: 4452 return "7R"; 4453 case llvm::ARM::AK_ARMV7M: 4454 return "7M"; 4455 case llvm::ARM::AK_ARMV7EM: 4456 return "7EM"; 4457 case llvm::ARM::AK_ARMV8A: 4458 return "8A"; 4459 case llvm::ARM::AK_ARMV8_1A: 4460 return "8_1A"; 4461 } 4462 } 4463 4464 StringRef getCPUProfile() const { 4465 switch(ArchProfile) { 4466 case llvm::ARM::PK_A: 4467 return "A"; 4468 case llvm::ARM::PK_R: 4469 return "R"; 4470 case llvm::ARM::PK_M: 4471 return "M"; 4472 default: 4473 return ""; 4474 } 4475 } 4476 4477 public: 4478 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4479 : TargetInfo(Triple), FPMath(FP_Default), 4480 IsAAPCS(true), LDREX(0), HW_FP(0) { 4481 BigEndian = IsBigEndian; 4482 4483 switch (getTriple().getOS()) { 4484 case llvm::Triple::NetBSD: 4485 PtrDiffType = SignedLong; 4486 break; 4487 default: 4488 PtrDiffType = SignedInt; 4489 break; 4490 } 4491 4492 // Cache arch related info. 4493 setArchInfo(); 4494 4495 // {} in inline assembly are neon specifiers, not assembly variant 4496 // specifiers. 4497 NoAsmVariants = true; 4498 4499 // FIXME: This duplicates code from the driver that sets the -target-abi 4500 // option - this code is used if -target-abi isn't passed and should 4501 // be unified in some way. 4502 if (Triple.isOSBinFormatMachO()) { 4503 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4504 // the frontend matches that. 4505 if (Triple.getEnvironment() == llvm::Triple::EABI || 4506 Triple.getOS() == llvm::Triple::UnknownOS || 4507 StringRef(CPU).startswith("cortex-m")) { 4508 setABI("aapcs"); 4509 } else if (Triple.isWatchOS()) { 4510 setABI("aapcs16"); 4511 } else { 4512 setABI("apcs-gnu"); 4513 } 4514 } else if (Triple.isOSWindows()) { 4515 // FIXME: this is invalid for WindowsCE 4516 setABI("aapcs"); 4517 } else { 4518 // Select the default based on the platform. 4519 switch (Triple.getEnvironment()) { 4520 case llvm::Triple::Android: 4521 case llvm::Triple::GNUEABI: 4522 case llvm::Triple::GNUEABIHF: 4523 setABI("aapcs-linux"); 4524 break; 4525 case llvm::Triple::EABIHF: 4526 case llvm::Triple::EABI: 4527 setABI("aapcs"); 4528 break; 4529 case llvm::Triple::GNU: 4530 setABI("apcs-gnu"); 4531 break; 4532 default: 4533 if (Triple.getOS() == llvm::Triple::NetBSD) 4534 setABI("apcs-gnu"); 4535 else 4536 setABI("aapcs"); 4537 break; 4538 } 4539 } 4540 4541 // ARM targets default to using the ARM C++ ABI. 4542 TheCXXABI.set(TargetCXXABI::GenericARM); 4543 4544 // ARM has atomics up to 8 bytes 4545 setAtomic(); 4546 4547 // Do force alignment of members that follow zero length bitfields. If 4548 // the alignment of the zero-length bitfield is greater than the member 4549 // that follows it, `bar', `bar' will be aligned as the type of the 4550 // zero length bitfield. 4551 UseZeroLengthBitfieldAlignment = true; 4552 } 4553 4554 StringRef getABI() const override { return ABI; } 4555 4556 bool setABI(const std::string &Name) override { 4557 ABI = Name; 4558 4559 // The defaults (above) are for AAPCS, check if we need to change them. 4560 // 4561 // FIXME: We need support for -meabi... we could just mangle it into the 4562 // name. 4563 if (Name == "apcs-gnu" || Name == "aapcs16") { 4564 setABIAPCS(Name == "aapcs16"); 4565 return true; 4566 } 4567 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4568 setABIAAPCS(); 4569 return true; 4570 } 4571 return false; 4572 } 4573 4574 // FIXME: This should be based on Arch attributes, not CPU names. 4575 bool 4576 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4577 StringRef CPU, 4578 const std::vector<std::string> &FeaturesVec) const override { 4579 4580 std::vector<const char*> TargetFeatures; 4581 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4582 4583 // get default FPU features 4584 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4585 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4586 4587 // get default Extension features 4588 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4589 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4590 4591 for (const char *Feature : TargetFeatures) 4592 if (Feature[0] == '+') 4593 Features[Feature+1] = true; 4594 4595 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4596 } 4597 4598 bool handleTargetFeatures(std::vector<std::string> &Features, 4599 DiagnosticsEngine &Diags) override { 4600 FPU = 0; 4601 CRC = 0; 4602 Crypto = 0; 4603 DSP = 0; 4604 Unaligned = 1; 4605 SoftFloat = SoftFloatABI = false; 4606 HWDiv = 0; 4607 4608 // This does not diagnose illegal cases like having both 4609 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4610 uint32_t HW_FP_remove = 0; 4611 for (const auto &Feature : Features) { 4612 if (Feature == "+soft-float") { 4613 SoftFloat = true; 4614 } else if (Feature == "+soft-float-abi") { 4615 SoftFloatABI = true; 4616 } else if (Feature == "+vfp2") { 4617 FPU |= VFP2FPU; 4618 HW_FP |= HW_FP_SP | HW_FP_DP; 4619 } else if (Feature == "+vfp3") { 4620 FPU |= VFP3FPU; 4621 HW_FP |= HW_FP_SP | HW_FP_DP; 4622 } else if (Feature == "+vfp4") { 4623 FPU |= VFP4FPU; 4624 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4625 } else if (Feature == "+fp-armv8") { 4626 FPU |= FPARMV8; 4627 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4628 } else if (Feature == "+neon") { 4629 FPU |= NeonFPU; 4630 HW_FP |= HW_FP_SP | HW_FP_DP; 4631 } else if (Feature == "+hwdiv") { 4632 HWDiv |= HWDivThumb; 4633 } else if (Feature == "+hwdiv-arm") { 4634 HWDiv |= HWDivARM; 4635 } else if (Feature == "+crc") { 4636 CRC = 1; 4637 } else if (Feature == "+crypto") { 4638 Crypto = 1; 4639 } else if (Feature == "+dsp") { 4640 DSP = 1; 4641 } else if (Feature == "+fp-only-sp") { 4642 HW_FP_remove |= HW_FP_DP; 4643 } else if (Feature == "+strict-align") { 4644 Unaligned = 0; 4645 } else if (Feature == "+fp16") { 4646 HW_FP |= HW_FP_HP; 4647 } 4648 } 4649 HW_FP &= ~HW_FP_remove; 4650 4651 switch (ArchVersion) { 4652 case 6: 4653 if (ArchProfile == llvm::ARM::PK_M) 4654 LDREX = 0; 4655 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4656 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4657 else 4658 LDREX = LDREX_W; 4659 break; 4660 case 7: 4661 if (ArchProfile == llvm::ARM::PK_M) 4662 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4663 else 4664 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4665 break; 4666 case 8: 4667 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4668 } 4669 4670 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4671 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4672 return false; 4673 } 4674 4675 if (FPMath == FP_Neon) 4676 Features.push_back("+neonfp"); 4677 else if (FPMath == FP_VFP) 4678 Features.push_back("-neonfp"); 4679 4680 // Remove front-end specific options which the backend handles differently. 4681 auto Feature = 4682 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4683 if (Feature != Features.end()) 4684 Features.erase(Feature); 4685 4686 return true; 4687 } 4688 4689 bool hasFeature(StringRef Feature) const override { 4690 return llvm::StringSwitch<bool>(Feature) 4691 .Case("arm", true) 4692 .Case("aarch32", true) 4693 .Case("softfloat", SoftFloat) 4694 .Case("thumb", isThumb()) 4695 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4696 .Case("hwdiv", HWDiv & HWDivThumb) 4697 .Case("hwdiv-arm", HWDiv & HWDivARM) 4698 .Default(false); 4699 } 4700 4701 bool setCPU(const std::string &Name) override { 4702 if (Name != "generic") 4703 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4704 4705 if (ArchKind == llvm::ARM::AK_INVALID) 4706 return false; 4707 setAtomic(); 4708 CPU = Name; 4709 return true; 4710 } 4711 4712 bool setFPMath(StringRef Name) override; 4713 4714 void getTargetDefines(const LangOptions &Opts, 4715 MacroBuilder &Builder) const override { 4716 // Target identification. 4717 Builder.defineMacro("__arm"); 4718 Builder.defineMacro("__arm__"); 4719 4720 // Target properties. 4721 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4722 4723 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4724 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4725 if (getTriple().isWatchOS()) 4726 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4727 4728 if (!CPUAttr.empty()) 4729 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4730 4731 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4732 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4733 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4734 4735 if (ArchVersion >= 8) { 4736 // ACLE 6.5.7 Crypto Extension 4737 if (Crypto) 4738 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4739 // ACLE 6.5.8 CRC32 Extension 4740 if (CRC) 4741 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4742 // ACLE 6.5.10 Numeric Maximum and Minimum 4743 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4744 // ACLE 6.5.9 Directed Rounding 4745 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4746 } 4747 4748 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4749 // is not defined for the M-profile. 4750 // NOTE that the deffault profile is assumed to be 'A' 4751 if (CPUProfile.empty() || CPUProfile != "M") 4752 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4753 4754 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4755 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4756 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4757 if (supportsThumb2()) 4758 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4759 else if (supportsThumb()) 4760 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4761 4762 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4763 // instruction set such as ARM or Thumb. 4764 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4765 4766 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4767 4768 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4769 if (!CPUProfile.empty()) 4770 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4771 4772 // ACLE 6.4.3 Unaligned access supported in hardware 4773 if (Unaligned) 4774 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4775 4776 // ACLE 6.4.4 LDREX/STREX 4777 if (LDREX) 4778 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4779 4780 // ACLE 6.4.5 CLZ 4781 if (ArchVersion == 5 || 4782 (ArchVersion == 6 && CPUProfile != "M") || 4783 ArchVersion > 6) 4784 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4785 4786 // ACLE 6.5.1 Hardware Floating Point 4787 if (HW_FP) 4788 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4789 4790 // ACLE predefines. 4791 Builder.defineMacro("__ARM_ACLE", "200"); 4792 4793 // FP16 support (we currently only support IEEE format). 4794 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4795 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4796 4797 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4798 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4799 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4800 4801 // Subtarget options. 4802 4803 // FIXME: It's more complicated than this and we don't really support 4804 // interworking. 4805 // Windows on ARM does not "support" interworking 4806 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4807 Builder.defineMacro("__THUMB_INTERWORK__"); 4808 4809 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4810 // Embedded targets on Darwin follow AAPCS, but not EABI. 4811 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4812 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4813 Builder.defineMacro("__ARM_EABI__"); 4814 Builder.defineMacro("__ARM_PCS", "1"); 4815 4816 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4817 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4818 } 4819 4820 if (SoftFloat) 4821 Builder.defineMacro("__SOFTFP__"); 4822 4823 if (CPU == "xscale") 4824 Builder.defineMacro("__XSCALE__"); 4825 4826 if (isThumb()) { 4827 Builder.defineMacro("__THUMBEL__"); 4828 Builder.defineMacro("__thumb__"); 4829 if (supportsThumb2()) 4830 Builder.defineMacro("__thumb2__"); 4831 } 4832 4833 // ACLE 6.4.9 32-bit SIMD instructions 4834 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4835 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4836 4837 // ACLE 6.4.10 Hardware Integer Divide 4838 if (((HWDiv & HWDivThumb) && isThumb()) || 4839 ((HWDiv & HWDivARM) && !isThumb())) { 4840 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4841 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4842 } 4843 4844 // Note, this is always on in gcc, even though it doesn't make sense. 4845 Builder.defineMacro("__APCS_32__"); 4846 4847 if (FPUModeIsVFP((FPUMode) FPU)) { 4848 Builder.defineMacro("__VFP_FP__"); 4849 if (FPU & VFP2FPU) 4850 Builder.defineMacro("__ARM_VFPV2__"); 4851 if (FPU & VFP3FPU) 4852 Builder.defineMacro("__ARM_VFPV3__"); 4853 if (FPU & VFP4FPU) 4854 Builder.defineMacro("__ARM_VFPV4__"); 4855 } 4856 4857 // This only gets set when Neon instructions are actually available, unlike 4858 // the VFP define, hence the soft float and arch check. This is subtly 4859 // different from gcc, we follow the intent which was that it should be set 4860 // when Neon instructions are actually available. 4861 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4862 Builder.defineMacro("__ARM_NEON", "1"); 4863 Builder.defineMacro("__ARM_NEON__"); 4864 // current AArch32 NEON implementations do not support double-precision 4865 // floating-point even when it is present in VFP. 4866 Builder.defineMacro("__ARM_NEON_FP", 4867 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4868 } 4869 4870 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4871 Opts.ShortWChar ? "2" : "4"); 4872 4873 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4874 Opts.ShortEnums ? "1" : "4"); 4875 4876 if (ArchVersion >= 6 && CPUAttr != "6M") { 4877 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4878 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4879 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4880 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4881 } 4882 4883 // ACLE 6.4.7 DSP instructions 4884 if (DSP) { 4885 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4886 } 4887 4888 // ACLE 6.4.8 Saturation instructions 4889 bool SAT = false; 4890 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4891 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4892 SAT = true; 4893 } 4894 4895 // ACLE 6.4.6 Q (saturation) flag 4896 if (DSP || SAT) 4897 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4898 4899 if (Opts.UnsafeFPMath) 4900 Builder.defineMacro("__ARM_FP_FAST", "1"); 4901 4902 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4903 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4904 } 4905 4906 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4907 return llvm::makeArrayRef(BuiltinInfo, 4908 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4909 } 4910 bool isCLZForZeroUndef() const override { return false; } 4911 BuiltinVaListKind getBuiltinVaListKind() const override { 4912 return IsAAPCS 4913 ? AAPCSABIBuiltinVaList 4914 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList 4915 : TargetInfo::VoidPtrBuiltinVaList); 4916 } 4917 ArrayRef<const char *> getGCCRegNames() const override; 4918 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4919 bool validateAsmConstraint(const char *&Name, 4920 TargetInfo::ConstraintInfo &Info) const override { 4921 switch (*Name) { 4922 default: break; 4923 case 'l': // r0-r7 4924 case 'h': // r8-r15 4925 case 't': // VFP Floating point register single precision 4926 case 'w': // VFP Floating point register double precision 4927 Info.setAllowsRegister(); 4928 return true; 4929 case 'I': 4930 case 'J': 4931 case 'K': 4932 case 'L': 4933 case 'M': 4934 // FIXME 4935 return true; 4936 case 'Q': // A memory address that is a single base register. 4937 Info.setAllowsMemory(); 4938 return true; 4939 case 'U': // a memory reference... 4940 switch (Name[1]) { 4941 case 'q': // ...ARMV4 ldrsb 4942 case 'v': // ...VFP load/store (reg+constant offset) 4943 case 'y': // ...iWMMXt load/store 4944 case 't': // address valid for load/store opaque types wider 4945 // than 128-bits 4946 case 'n': // valid address for Neon doubleword vector load/store 4947 case 'm': // valid address for Neon element and structure load/store 4948 case 's': // valid address for non-offset loads/stores of quad-word 4949 // values in four ARM registers 4950 Info.setAllowsMemory(); 4951 Name++; 4952 return true; 4953 } 4954 } 4955 return false; 4956 } 4957 std::string convertConstraint(const char *&Constraint) const override { 4958 std::string R; 4959 switch (*Constraint) { 4960 case 'U': // Two-character constraint; add "^" hint for later parsing. 4961 R = std::string("^") + std::string(Constraint, 2); 4962 Constraint++; 4963 break; 4964 case 'p': // 'p' should be translated to 'r' by default. 4965 R = std::string("r"); 4966 break; 4967 default: 4968 return std::string(1, *Constraint); 4969 } 4970 return R; 4971 } 4972 bool 4973 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4974 std::string &SuggestedModifier) const override { 4975 bool isOutput = (Constraint[0] == '='); 4976 bool isInOut = (Constraint[0] == '+'); 4977 4978 // Strip off constraint modifiers. 4979 while (Constraint[0] == '=' || 4980 Constraint[0] == '+' || 4981 Constraint[0] == '&') 4982 Constraint = Constraint.substr(1); 4983 4984 switch (Constraint[0]) { 4985 default: break; 4986 case 'r': { 4987 switch (Modifier) { 4988 default: 4989 return (isInOut || isOutput || Size <= 64); 4990 case 'q': 4991 // A register of size 32 cannot fit a vector type. 4992 return false; 4993 } 4994 } 4995 } 4996 4997 return true; 4998 } 4999 const char *getClobbers() const override { 5000 // FIXME: Is this really right? 5001 return ""; 5002 } 5003 5004 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5005 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 5006 } 5007 5008 int getEHDataRegisterNumber(unsigned RegNo) const override { 5009 if (RegNo == 0) return 0; 5010 if (RegNo == 1) return 1; 5011 return -1; 5012 } 5013 5014 bool hasSjLjLowering() const override { 5015 return true; 5016 } 5017 }; 5018 5019 bool ARMTargetInfo::setFPMath(StringRef Name) { 5020 if (Name == "neon") { 5021 FPMath = FP_Neon; 5022 return true; 5023 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5024 Name == "vfp4") { 5025 FPMath = FP_VFP; 5026 return true; 5027 } 5028 return false; 5029 } 5030 5031 const char * const ARMTargetInfo::GCCRegNames[] = { 5032 // Integer registers 5033 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5034 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5035 5036 // Float registers 5037 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5038 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5039 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5040 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5041 5042 // Double registers 5043 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5044 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5045 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5046 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5047 5048 // Quad registers 5049 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5050 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5051 }; 5052 5053 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5054 return llvm::makeArrayRef(GCCRegNames); 5055 } 5056 5057 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5058 { { "a1" }, "r0" }, 5059 { { "a2" }, "r1" }, 5060 { { "a3" }, "r2" }, 5061 { { "a4" }, "r3" }, 5062 { { "v1" }, "r4" }, 5063 { { "v2" }, "r5" }, 5064 { { "v3" }, "r6" }, 5065 { { "v4" }, "r7" }, 5066 { { "v5" }, "r8" }, 5067 { { "v6", "rfp" }, "r9" }, 5068 { { "sl" }, "r10" }, 5069 { { "fp" }, "r11" }, 5070 { { "ip" }, "r12" }, 5071 { { "r13" }, "sp" }, 5072 { { "r14" }, "lr" }, 5073 { { "r15" }, "pc" }, 5074 // The S, D and Q registers overlap, but aren't really aliases; we 5075 // don't want to substitute one of these for a different-sized one. 5076 }; 5077 5078 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5079 return llvm::makeArrayRef(GCCRegAliases); 5080 } 5081 5082 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5083 #define BUILTIN(ID, TYPE, ATTRS) \ 5084 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5085 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5086 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5087 #include "clang/Basic/BuiltinsNEON.def" 5088 5089 #define BUILTIN(ID, TYPE, ATTRS) \ 5090 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5091 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5092 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5093 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5094 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5095 #include "clang/Basic/BuiltinsARM.def" 5096 }; 5097 5098 class ARMleTargetInfo : public ARMTargetInfo { 5099 public: 5100 ARMleTargetInfo(const llvm::Triple &Triple) 5101 : ARMTargetInfo(Triple, false) { } 5102 void getTargetDefines(const LangOptions &Opts, 5103 MacroBuilder &Builder) const override { 5104 Builder.defineMacro("__ARMEL__"); 5105 ARMTargetInfo::getTargetDefines(Opts, Builder); 5106 } 5107 }; 5108 5109 class ARMbeTargetInfo : public ARMTargetInfo { 5110 public: 5111 ARMbeTargetInfo(const llvm::Triple &Triple) 5112 : ARMTargetInfo(Triple, true) { } 5113 void getTargetDefines(const LangOptions &Opts, 5114 MacroBuilder &Builder) const override { 5115 Builder.defineMacro("__ARMEB__"); 5116 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5117 ARMTargetInfo::getTargetDefines(Opts, Builder); 5118 } 5119 }; 5120 5121 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5122 const llvm::Triple Triple; 5123 public: 5124 WindowsARMTargetInfo(const llvm::Triple &Triple) 5125 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5126 TLSSupported = false; 5127 WCharType = UnsignedShort; 5128 SizeType = UnsignedInt; 5129 UserLabelPrefix = ""; 5130 } 5131 void getVisualStudioDefines(const LangOptions &Opts, 5132 MacroBuilder &Builder) const { 5133 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5134 5135 // FIXME: this is invalid for WindowsCE 5136 Builder.defineMacro("_M_ARM_NT", "1"); 5137 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5138 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5139 5140 assert((Triple.getArch() == llvm::Triple::arm || 5141 Triple.getArch() == llvm::Triple::thumb) && 5142 "invalid architecture for Windows ARM target info"); 5143 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5144 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5145 5146 // TODO map the complete set of values 5147 // 31: VFPv3 40: VFPv4 5148 Builder.defineMacro("_M_ARM_FP", "31"); 5149 } 5150 BuiltinVaListKind getBuiltinVaListKind() const override { 5151 return TargetInfo::CharPtrBuiltinVaList; 5152 } 5153 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5154 switch (CC) { 5155 case CC_X86StdCall: 5156 case CC_X86ThisCall: 5157 case CC_X86FastCall: 5158 case CC_X86VectorCall: 5159 return CCCR_Ignore; 5160 case CC_C: 5161 return CCCR_OK; 5162 default: 5163 return CCCR_Warning; 5164 } 5165 } 5166 }; 5167 5168 // Windows ARM + Itanium C++ ABI Target 5169 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5170 public: 5171 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5172 : WindowsARMTargetInfo(Triple) { 5173 TheCXXABI.set(TargetCXXABI::GenericARM); 5174 } 5175 5176 void getTargetDefines(const LangOptions &Opts, 5177 MacroBuilder &Builder) const override { 5178 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5179 5180 if (Opts.MSVCCompat) 5181 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5182 } 5183 }; 5184 5185 // Windows ARM, MS (C++) ABI 5186 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5187 public: 5188 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5189 : WindowsARMTargetInfo(Triple) { 5190 TheCXXABI.set(TargetCXXABI::Microsoft); 5191 } 5192 5193 void getTargetDefines(const LangOptions &Opts, 5194 MacroBuilder &Builder) const override { 5195 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5196 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5197 } 5198 }; 5199 5200 // ARM MinGW target 5201 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5202 public: 5203 MinGWARMTargetInfo(const llvm::Triple &Triple) 5204 : WindowsARMTargetInfo(Triple) { 5205 TheCXXABI.set(TargetCXXABI::GenericARM); 5206 } 5207 5208 void getTargetDefines(const LangOptions &Opts, 5209 MacroBuilder &Builder) const override { 5210 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5211 DefineStd(Builder, "WIN32", Opts); 5212 DefineStd(Builder, "WINNT", Opts); 5213 Builder.defineMacro("_ARM_"); 5214 addMinGWDefines(Opts, Builder); 5215 } 5216 }; 5217 5218 // ARM Cygwin target 5219 class CygwinARMTargetInfo : public ARMleTargetInfo { 5220 public: 5221 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5222 TLSSupported = false; 5223 WCharType = UnsignedShort; 5224 DoubleAlign = LongLongAlign = 64; 5225 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5226 } 5227 void getTargetDefines(const LangOptions &Opts, 5228 MacroBuilder &Builder) const override { 5229 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5230 Builder.defineMacro("_ARM_"); 5231 Builder.defineMacro("__CYGWIN__"); 5232 Builder.defineMacro("__CYGWIN32__"); 5233 DefineStd(Builder, "unix", Opts); 5234 if (Opts.CPlusPlus) 5235 Builder.defineMacro("_GNU_SOURCE"); 5236 } 5237 }; 5238 5239 class DarwinARMTargetInfo : 5240 public DarwinTargetInfo<ARMleTargetInfo> { 5241 protected: 5242 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5243 MacroBuilder &Builder) const override { 5244 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5245 } 5246 5247 public: 5248 DarwinARMTargetInfo(const llvm::Triple &Triple) 5249 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5250 HasAlignMac68kSupport = true; 5251 // iOS always has 64-bit atomic instructions. 5252 // FIXME: This should be based off of the target features in 5253 // ARMleTargetInfo. 5254 MaxAtomicInlineWidth = 64; 5255 5256 if (Triple.isWatchOS()) { 5257 // Darwin on iOS uses a variant of the ARM C++ ABI. 5258 TheCXXABI.set(TargetCXXABI::WatchOS); 5259 5260 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5261 // size_t is long, it's a bit weird for it to be int. 5262 PtrDiffType = SignedLong; 5263 5264 // BOOL should be a real boolean on the new ABI 5265 UseSignedCharForObjCBool = false; 5266 } else 5267 TheCXXABI.set(TargetCXXABI::iOS); 5268 } 5269 }; 5270 5271 class AArch64TargetInfo : public TargetInfo { 5272 virtual void setDataLayoutString() = 0; 5273 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5274 static const char *const GCCRegNames[]; 5275 5276 enum FPUModeEnum { 5277 FPUMode, 5278 NeonMode 5279 }; 5280 5281 unsigned FPU; 5282 unsigned CRC; 5283 unsigned Crypto; 5284 unsigned Unaligned; 5285 unsigned V8_1A; 5286 5287 static const Builtin::Info BuiltinInfo[]; 5288 5289 std::string ABI; 5290 5291 public: 5292 AArch64TargetInfo(const llvm::Triple &Triple) 5293 : TargetInfo(Triple), ABI("aapcs") { 5294 5295 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5296 WCharType = SignedInt; 5297 5298 // NetBSD apparently prefers consistency across ARM targets to consistency 5299 // across 64-bit targets. 5300 Int64Type = SignedLongLong; 5301 IntMaxType = SignedLongLong; 5302 } else { 5303 WCharType = UnsignedInt; 5304 Int64Type = SignedLong; 5305 IntMaxType = SignedLong; 5306 } 5307 5308 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5309 MaxVectorAlign = 128; 5310 MaxAtomicInlineWidth = 128; 5311 MaxAtomicPromoteWidth = 128; 5312 5313 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5314 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5315 5316 // {} in inline assembly are neon specifiers, not assembly variant 5317 // specifiers. 5318 NoAsmVariants = true; 5319 5320 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5321 // contributes to the alignment of the containing aggregate in the same way 5322 // a plain (non bit-field) member of that type would, without exception for 5323 // zero-sized or anonymous bit-fields." 5324 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5325 UseZeroLengthBitfieldAlignment = true; 5326 5327 // AArch64 targets default to using the ARM C++ ABI. 5328 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5329 } 5330 5331 StringRef getABI() const override { return ABI; } 5332 bool setABI(const std::string &Name) override { 5333 if (Name != "aapcs" && Name != "darwinpcs") 5334 return false; 5335 5336 ABI = Name; 5337 return true; 5338 } 5339 5340 bool setCPU(const std::string &Name) override { 5341 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5342 .Case("generic", true) 5343 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5344 "cortex-a35", "exynos-m1", true) 5345 .Case("cyclone", true) 5346 .Default(false); 5347 return CPUKnown; 5348 } 5349 5350 void getTargetDefines(const LangOptions &Opts, 5351 MacroBuilder &Builder) const override { 5352 // Target identification. 5353 Builder.defineMacro("__aarch64__"); 5354 5355 // Target properties. 5356 Builder.defineMacro("_LP64"); 5357 Builder.defineMacro("__LP64__"); 5358 5359 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5360 Builder.defineMacro("__ARM_ACLE", "200"); 5361 Builder.defineMacro("__ARM_ARCH", "8"); 5362 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5363 5364 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5365 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5366 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5367 5368 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5369 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5370 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5371 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5372 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5373 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5374 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5375 5376 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5377 5378 // 0xe implies support for half, single and double precision operations. 5379 Builder.defineMacro("__ARM_FP", "0xE"); 5380 5381 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5382 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5383 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5384 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5385 5386 if (Opts.UnsafeFPMath) 5387 Builder.defineMacro("__ARM_FP_FAST", "1"); 5388 5389 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5390 5391 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5392 Opts.ShortEnums ? "1" : "4"); 5393 5394 if (FPU == NeonMode) { 5395 Builder.defineMacro("__ARM_NEON", "1"); 5396 // 64-bit NEON supports half, single and double precision operations. 5397 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5398 } 5399 5400 if (CRC) 5401 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5402 5403 if (Crypto) 5404 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5405 5406 if (Unaligned) 5407 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5408 5409 if (V8_1A) 5410 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5411 5412 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5413 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5415 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5417 } 5418 5419 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5420 return llvm::makeArrayRef(BuiltinInfo, 5421 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5422 } 5423 5424 bool hasFeature(StringRef Feature) const override { 5425 return Feature == "aarch64" || 5426 Feature == "arm64" || 5427 Feature == "arm" || 5428 (Feature == "neon" && FPU == NeonMode); 5429 } 5430 5431 bool handleTargetFeatures(std::vector<std::string> &Features, 5432 DiagnosticsEngine &Diags) override { 5433 FPU = FPUMode; 5434 CRC = 0; 5435 Crypto = 0; 5436 Unaligned = 1; 5437 V8_1A = 0; 5438 5439 for (const auto &Feature : Features) { 5440 if (Feature == "+neon") 5441 FPU = NeonMode; 5442 if (Feature == "+crc") 5443 CRC = 1; 5444 if (Feature == "+crypto") 5445 Crypto = 1; 5446 if (Feature == "+strict-align") 5447 Unaligned = 0; 5448 if (Feature == "+v8.1a") 5449 V8_1A = 1; 5450 } 5451 5452 setDataLayoutString(); 5453 5454 return true; 5455 } 5456 5457 bool isCLZForZeroUndef() const override { return false; } 5458 5459 BuiltinVaListKind getBuiltinVaListKind() const override { 5460 return TargetInfo::AArch64ABIBuiltinVaList; 5461 } 5462 5463 ArrayRef<const char *> getGCCRegNames() const override; 5464 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5465 5466 bool validateAsmConstraint(const char *&Name, 5467 TargetInfo::ConstraintInfo &Info) const override { 5468 switch (*Name) { 5469 default: 5470 return false; 5471 case 'w': // Floating point and SIMD registers (V0-V31) 5472 Info.setAllowsRegister(); 5473 return true; 5474 case 'I': // Constant that can be used with an ADD instruction 5475 case 'J': // Constant that can be used with a SUB instruction 5476 case 'K': // Constant that can be used with a 32-bit logical instruction 5477 case 'L': // Constant that can be used with a 64-bit logical instruction 5478 case 'M': // Constant that can be used as a 32-bit MOV immediate 5479 case 'N': // Constant that can be used as a 64-bit MOV immediate 5480 case 'Y': // Floating point constant zero 5481 case 'Z': // Integer constant zero 5482 return true; 5483 case 'Q': // A memory reference with base register and no offset 5484 Info.setAllowsMemory(); 5485 return true; 5486 case 'S': // A symbolic address 5487 Info.setAllowsRegister(); 5488 return true; 5489 case 'U': 5490 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5491 // Utf: A memory address suitable for ldp/stp in TF mode. 5492 // Usa: An absolute symbolic address. 5493 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5494 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5495 case 'z': // Zero register, wzr or xzr 5496 Info.setAllowsRegister(); 5497 return true; 5498 case 'x': // Floating point and SIMD registers (V0-V15) 5499 Info.setAllowsRegister(); 5500 return true; 5501 } 5502 return false; 5503 } 5504 5505 bool 5506 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5507 std::string &SuggestedModifier) const override { 5508 // Strip off constraint modifiers. 5509 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5510 Constraint = Constraint.substr(1); 5511 5512 switch (Constraint[0]) { 5513 default: 5514 return true; 5515 case 'z': 5516 case 'r': { 5517 switch (Modifier) { 5518 case 'x': 5519 case 'w': 5520 // For now assume that the person knows what they're 5521 // doing with the modifier. 5522 return true; 5523 default: 5524 // By default an 'r' constraint will be in the 'x' 5525 // registers. 5526 if (Size == 64) 5527 return true; 5528 5529 SuggestedModifier = "w"; 5530 return false; 5531 } 5532 } 5533 } 5534 } 5535 5536 const char *getClobbers() const override { return ""; } 5537 5538 int getEHDataRegisterNumber(unsigned RegNo) const override { 5539 if (RegNo == 0) 5540 return 0; 5541 if (RegNo == 1) 5542 return 1; 5543 return -1; 5544 } 5545 }; 5546 5547 const char *const AArch64TargetInfo::GCCRegNames[] = { 5548 // 32-bit Integer registers 5549 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5550 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5551 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5552 5553 // 64-bit Integer registers 5554 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5555 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5556 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5557 5558 // 32-bit floating point regsisters 5559 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5560 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5561 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5562 5563 // 64-bit floating point regsisters 5564 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5565 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5566 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5567 5568 // Vector registers 5569 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5570 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5571 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5572 }; 5573 5574 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5575 return llvm::makeArrayRef(GCCRegNames); 5576 } 5577 5578 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5579 { { "w31" }, "wsp" }, 5580 { { "x29" }, "fp" }, 5581 { { "x30" }, "lr" }, 5582 { { "x31" }, "sp" }, 5583 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5584 // don't want to substitute one of these for a different-sized one. 5585 }; 5586 5587 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5588 return llvm::makeArrayRef(GCCRegAliases); 5589 } 5590 5591 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5592 #define BUILTIN(ID, TYPE, ATTRS) \ 5593 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5594 #include "clang/Basic/BuiltinsNEON.def" 5595 5596 #define BUILTIN(ID, TYPE, ATTRS) \ 5597 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5598 #include "clang/Basic/BuiltinsAArch64.def" 5599 }; 5600 5601 class AArch64leTargetInfo : public AArch64TargetInfo { 5602 void setDataLayoutString() override { 5603 if (getTriple().isOSBinFormatMachO()) 5604 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5605 else 5606 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5607 } 5608 5609 public: 5610 AArch64leTargetInfo(const llvm::Triple &Triple) 5611 : AArch64TargetInfo(Triple) { 5612 BigEndian = false; 5613 } 5614 void getTargetDefines(const LangOptions &Opts, 5615 MacroBuilder &Builder) const override { 5616 Builder.defineMacro("__AARCH64EL__"); 5617 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5618 } 5619 }; 5620 5621 class AArch64beTargetInfo : public AArch64TargetInfo { 5622 void setDataLayoutString() override { 5623 assert(!getTriple().isOSBinFormatMachO()); 5624 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5625 } 5626 5627 public: 5628 AArch64beTargetInfo(const llvm::Triple &Triple) 5629 : AArch64TargetInfo(Triple) { } 5630 void getTargetDefines(const LangOptions &Opts, 5631 MacroBuilder &Builder) const override { 5632 Builder.defineMacro("__AARCH64EB__"); 5633 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5634 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5635 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5636 } 5637 }; 5638 5639 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5640 protected: 5641 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5642 MacroBuilder &Builder) const override { 5643 Builder.defineMacro("__AARCH64_SIMD__"); 5644 Builder.defineMacro("__ARM64_ARCH_8__"); 5645 Builder.defineMacro("__ARM_NEON__"); 5646 Builder.defineMacro("__LITTLE_ENDIAN__"); 5647 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5648 Builder.defineMacro("__arm64", "1"); 5649 Builder.defineMacro("__arm64__", "1"); 5650 5651 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5652 } 5653 5654 public: 5655 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5656 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5657 Int64Type = SignedLongLong; 5658 WCharType = SignedInt; 5659 UseSignedCharForObjCBool = false; 5660 5661 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5662 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5663 5664 TheCXXABI.set(TargetCXXABI::iOS64); 5665 } 5666 5667 BuiltinVaListKind getBuiltinVaListKind() const override { 5668 return TargetInfo::CharPtrBuiltinVaList; 5669 } 5670 }; 5671 5672 // Hexagon abstract base class 5673 class HexagonTargetInfo : public TargetInfo { 5674 static const Builtin::Info BuiltinInfo[]; 5675 static const char * const GCCRegNames[]; 5676 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5677 std::string CPU; 5678 bool HasHVX, HasHVXDouble; 5679 5680 public: 5681 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5682 BigEndian = false; 5683 DataLayoutString = "e-m:e-p:32:32:32-" 5684 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-" 5685 "f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"; 5686 SizeType = UnsignedInt; 5687 PtrDiffType = SignedInt; 5688 IntPtrType = SignedInt; 5689 5690 // {} in inline assembly are packet specifiers, not assembly variant 5691 // specifiers. 5692 NoAsmVariants = true; 5693 5694 LargeArrayMinWidth = 64; 5695 LargeArrayAlign = 64; 5696 UseBitFieldTypeAlignment = true; 5697 ZeroLengthBitfieldBoundary = 32; 5698 HasHVX = HasHVXDouble = false; 5699 } 5700 5701 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5702 return llvm::makeArrayRef(BuiltinInfo, 5703 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5704 } 5705 5706 bool validateAsmConstraint(const char *&Name, 5707 TargetInfo::ConstraintInfo &Info) const override { 5708 return true; 5709 } 5710 5711 void getTargetDefines(const LangOptions &Opts, 5712 MacroBuilder &Builder) const override; 5713 5714 bool isCLZForZeroUndef() const override { return false; } 5715 5716 bool hasFeature(StringRef Feature) const override { 5717 return llvm::StringSwitch<bool>(Feature) 5718 .Case("hexagon", true) 5719 .Case("hvx", HasHVX) 5720 .Case("hvx-double", HasHVXDouble) 5721 .Default(false); 5722 } 5723 5724 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5725 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5726 const override; 5727 5728 bool handleTargetFeatures(std::vector<std::string> &Features, 5729 DiagnosticsEngine &Diags) override; 5730 5731 BuiltinVaListKind getBuiltinVaListKind() const override { 5732 return TargetInfo::CharPtrBuiltinVaList; 5733 } 5734 ArrayRef<const char *> getGCCRegNames() const override; 5735 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5736 const char *getClobbers() const override { 5737 return ""; 5738 } 5739 5740 static const char *getHexagonCPUSuffix(StringRef Name) { 5741 return llvm::StringSwitch<const char*>(Name) 5742 .Case("hexagonv4", "4") 5743 .Case("hexagonv5", "5") 5744 .Case("hexagonv55", "55") 5745 .Case("hexagonv60", "60") 5746 .Default(nullptr); 5747 } 5748 5749 bool setCPU(const std::string &Name) override { 5750 if (!getHexagonCPUSuffix(Name)) 5751 return false; 5752 CPU = Name; 5753 return true; 5754 } 5755 5756 int getEHDataRegisterNumber(unsigned RegNo) const override { 5757 return RegNo < 2 ? RegNo : -1; 5758 } 5759 }; 5760 5761 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5762 MacroBuilder &Builder) const { 5763 Builder.defineMacro("__qdsp6__", "1"); 5764 Builder.defineMacro("__hexagon__", "1"); 5765 5766 if (CPU == "hexagonv4") { 5767 Builder.defineMacro("__HEXAGON_V4__"); 5768 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5769 if (Opts.HexagonQdsp6Compat) { 5770 Builder.defineMacro("__QDSP6_V4__"); 5771 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5772 } 5773 } else if (CPU == "hexagonv5") { 5774 Builder.defineMacro("__HEXAGON_V5__"); 5775 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5776 if(Opts.HexagonQdsp6Compat) { 5777 Builder.defineMacro("__QDSP6_V5__"); 5778 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5779 } 5780 } else if (CPU == "hexagonv60") { 5781 Builder.defineMacro("__HEXAGON_V60__"); 5782 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5783 Builder.defineMacro("__QDSP6_V60__"); 5784 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5785 } 5786 } 5787 5788 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5789 DiagnosticsEngine &Diags) { 5790 for (auto &F : Features) { 5791 if (F == "+hvx") 5792 HasHVX = true; 5793 else if (F == "-hvx") 5794 HasHVX = HasHVXDouble = false; 5795 else if (F == "+hvx-double") 5796 HasHVX = HasHVXDouble = true; 5797 else if (F == "-hvx-double") 5798 HasHVXDouble = false; 5799 } 5800 return true; 5801 } 5802 5803 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5804 DiagnosticsEngine &Diags, StringRef CPU, 5805 const std::vector<std::string> &FeaturesVec) const { 5806 // Default for v60: -hvx, -hvx-double. 5807 Features["hvx"] = false; 5808 Features["hvx-double"] = false; 5809 5810 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5811 } 5812 5813 5814 const char *const HexagonTargetInfo::GCCRegNames[] = { 5815 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5816 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5817 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5818 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5819 "p0", "p1", "p2", "p3", 5820 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5821 }; 5822 5823 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5824 return llvm::makeArrayRef(GCCRegNames); 5825 } 5826 5827 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5828 { { "sp" }, "r29" }, 5829 { { "fp" }, "r30" }, 5830 { { "lr" }, "r31" }, 5831 }; 5832 5833 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5834 return llvm::makeArrayRef(GCCRegAliases); 5835 } 5836 5837 5838 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5839 #define BUILTIN(ID, TYPE, ATTRS) \ 5840 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5841 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5842 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5843 #include "clang/Basic/BuiltinsHexagon.def" 5844 }; 5845 5846 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5847 class SparcTargetInfo : public TargetInfo { 5848 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5849 static const char * const GCCRegNames[]; 5850 bool SoftFloat; 5851 public: 5852 SparcTargetInfo(const llvm::Triple &Triple) 5853 : TargetInfo(Triple), SoftFloat(false) {} 5854 5855 bool handleTargetFeatures(std::vector<std::string> &Features, 5856 DiagnosticsEngine &Diags) override { 5857 // The backend doesn't actually handle soft float yet, but in case someone 5858 // is using the support for the front end continue to support it. 5859 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5860 if (Feature != Features.end()) { 5861 SoftFloat = true; 5862 Features.erase(Feature); 5863 } 5864 return true; 5865 } 5866 void getTargetDefines(const LangOptions &Opts, 5867 MacroBuilder &Builder) const override { 5868 DefineStd(Builder, "sparc", Opts); 5869 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5870 5871 if (SoftFloat) 5872 Builder.defineMacro("SOFT_FLOAT", "1"); 5873 } 5874 5875 bool hasFeature(StringRef Feature) const override { 5876 return llvm::StringSwitch<bool>(Feature) 5877 .Case("softfloat", SoftFloat) 5878 .Case("sparc", true) 5879 .Default(false); 5880 } 5881 5882 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5883 // FIXME: Implement! 5884 return None; 5885 } 5886 BuiltinVaListKind getBuiltinVaListKind() const override { 5887 return TargetInfo::VoidPtrBuiltinVaList; 5888 } 5889 ArrayRef<const char *> getGCCRegNames() const override; 5890 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5891 bool validateAsmConstraint(const char *&Name, 5892 TargetInfo::ConstraintInfo &info) const override { 5893 // FIXME: Implement! 5894 switch (*Name) { 5895 case 'I': // Signed 13-bit constant 5896 case 'J': // Zero 5897 case 'K': // 32-bit constant with the low 12 bits clear 5898 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5899 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5900 case 'N': // Same as 'K' but zext (required for SIMode) 5901 case 'O': // The constant 4096 5902 return true; 5903 } 5904 return false; 5905 } 5906 const char *getClobbers() const override { 5907 // FIXME: Implement! 5908 return ""; 5909 } 5910 5911 // No Sparc V7 for now, the backend doesn't support it anyway. 5912 enum CPUKind { 5913 CK_GENERIC, 5914 CK_V8, 5915 CK_SUPERSPARC, 5916 CK_SPARCLITE, 5917 CK_F934, 5918 CK_HYPERSPARC, 5919 CK_SPARCLITE86X, 5920 CK_SPARCLET, 5921 CK_TSC701, 5922 CK_V9, 5923 CK_ULTRASPARC, 5924 CK_ULTRASPARC3, 5925 CK_NIAGARA, 5926 CK_NIAGARA2, 5927 CK_NIAGARA3, 5928 CK_NIAGARA4 5929 } CPU = CK_GENERIC; 5930 5931 enum CPUGeneration { 5932 CG_V8, 5933 CG_V9, 5934 }; 5935 5936 CPUGeneration getCPUGeneration(CPUKind Kind) const { 5937 switch (Kind) { 5938 case CK_GENERIC: 5939 case CK_V8: 5940 case CK_SUPERSPARC: 5941 case CK_SPARCLITE: 5942 case CK_F934: 5943 case CK_HYPERSPARC: 5944 case CK_SPARCLITE86X: 5945 case CK_SPARCLET: 5946 case CK_TSC701: 5947 return CG_V8; 5948 case CK_V9: 5949 case CK_ULTRASPARC: 5950 case CK_ULTRASPARC3: 5951 case CK_NIAGARA: 5952 case CK_NIAGARA2: 5953 case CK_NIAGARA3: 5954 case CK_NIAGARA4: 5955 return CG_V9; 5956 } 5957 llvm_unreachable("Unexpected CPU kind"); 5958 } 5959 5960 CPUKind getCPUKind(StringRef Name) const { 5961 return llvm::StringSwitch<CPUKind>(Name) 5962 .Case("v8", CK_V8) 5963 .Case("supersparc", CK_SUPERSPARC) 5964 .Case("sparclite", CK_SPARCLITE) 5965 .Case("f934", CK_F934) 5966 .Case("hypersparc", CK_HYPERSPARC) 5967 .Case("sparclite86x", CK_SPARCLITE86X) 5968 .Case("sparclet", CK_SPARCLET) 5969 .Case("tsc701", CK_TSC701) 5970 .Case("v9", CK_V9) 5971 .Case("ultrasparc", CK_ULTRASPARC) 5972 .Case("ultrasparc3", CK_ULTRASPARC3) 5973 .Case("niagara", CK_NIAGARA) 5974 .Case("niagara2", CK_NIAGARA2) 5975 .Case("niagara3", CK_NIAGARA3) 5976 .Case("niagara4", CK_NIAGARA4) 5977 .Default(CK_GENERIC); 5978 } 5979 5980 bool setCPU(const std::string &Name) override { 5981 CPU = getCPUKind(Name); 5982 return CPU != CK_GENERIC; 5983 } 5984 }; 5985 5986 const char * const SparcTargetInfo::GCCRegNames[] = { 5987 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5988 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5989 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5990 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5991 }; 5992 5993 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5994 return llvm::makeArrayRef(GCCRegNames); 5995 } 5996 5997 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5998 { { "g0" }, "r0" }, 5999 { { "g1" }, "r1" }, 6000 { { "g2" }, "r2" }, 6001 { { "g3" }, "r3" }, 6002 { { "g4" }, "r4" }, 6003 { { "g5" }, "r5" }, 6004 { { "g6" }, "r6" }, 6005 { { "g7" }, "r7" }, 6006 { { "o0" }, "r8" }, 6007 { { "o1" }, "r9" }, 6008 { { "o2" }, "r10" }, 6009 { { "o3" }, "r11" }, 6010 { { "o4" }, "r12" }, 6011 { { "o5" }, "r13" }, 6012 { { "o6", "sp" }, "r14" }, 6013 { { "o7" }, "r15" }, 6014 { { "l0" }, "r16" }, 6015 { { "l1" }, "r17" }, 6016 { { "l2" }, "r18" }, 6017 { { "l3" }, "r19" }, 6018 { { "l4" }, "r20" }, 6019 { { "l5" }, "r21" }, 6020 { { "l6" }, "r22" }, 6021 { { "l7" }, "r23" }, 6022 { { "i0" }, "r24" }, 6023 { { "i1" }, "r25" }, 6024 { { "i2" }, "r26" }, 6025 { { "i3" }, "r27" }, 6026 { { "i4" }, "r28" }, 6027 { { "i5" }, "r29" }, 6028 { { "i6", "fp" }, "r30" }, 6029 { { "i7" }, "r31" }, 6030 }; 6031 6032 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6033 return llvm::makeArrayRef(GCCRegAliases); 6034 } 6035 6036 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6037 class SparcV8TargetInfo : public SparcTargetInfo { 6038 public: 6039 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6040 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6041 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6042 switch (getTriple().getOS()) { 6043 default: 6044 SizeType = UnsignedInt; 6045 IntPtrType = SignedInt; 6046 PtrDiffType = SignedInt; 6047 break; 6048 case llvm::Triple::NetBSD: 6049 case llvm::Triple::OpenBSD: 6050 SizeType = UnsignedLong; 6051 IntPtrType = SignedLong; 6052 PtrDiffType = SignedLong; 6053 break; 6054 } 6055 } 6056 6057 void getTargetDefines(const LangOptions &Opts, 6058 MacroBuilder &Builder) const override { 6059 SparcTargetInfo::getTargetDefines(Opts, Builder); 6060 switch (getCPUGeneration(CPU)) { 6061 case CG_V8: 6062 Builder.defineMacro("__sparcv8"); 6063 if (getTriple().getOS() != llvm::Triple::Solaris) 6064 Builder.defineMacro("__sparcv8__"); 6065 break; 6066 case CG_V9: 6067 Builder.defineMacro("__sparcv9"); 6068 if (getTriple().getOS() != llvm::Triple::Solaris) { 6069 Builder.defineMacro("__sparcv9__"); 6070 Builder.defineMacro("__sparc_v9__"); 6071 } 6072 break; 6073 } 6074 } 6075 }; 6076 6077 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6078 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6079 public: 6080 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6081 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6082 BigEndian = false; 6083 } 6084 }; 6085 6086 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6087 class SparcV9TargetInfo : public SparcTargetInfo { 6088 public: 6089 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6090 // FIXME: Support Sparc quad-precision long double? 6091 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6092 // This is an LP64 platform. 6093 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6094 6095 // OpenBSD uses long long for int64_t and intmax_t. 6096 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6097 IntMaxType = SignedLongLong; 6098 else 6099 IntMaxType = SignedLong; 6100 Int64Type = IntMaxType; 6101 6102 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6103 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6104 LongDoubleWidth = 128; 6105 LongDoubleAlign = 128; 6106 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6107 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6108 } 6109 6110 void getTargetDefines(const LangOptions &Opts, 6111 MacroBuilder &Builder) const override { 6112 SparcTargetInfo::getTargetDefines(Opts, Builder); 6113 Builder.defineMacro("__sparcv9"); 6114 Builder.defineMacro("__arch64__"); 6115 // Solaris doesn't need these variants, but the BSDs do. 6116 if (getTriple().getOS() != llvm::Triple::Solaris) { 6117 Builder.defineMacro("__sparc64__"); 6118 Builder.defineMacro("__sparc_v9__"); 6119 Builder.defineMacro("__sparcv9__"); 6120 } 6121 } 6122 6123 bool setCPU(const std::string &Name) override { 6124 if (!SparcTargetInfo::setCPU(Name)) 6125 return false; 6126 return getCPUGeneration(CPU) == CG_V9; 6127 } 6128 }; 6129 6130 class SystemZTargetInfo : public TargetInfo { 6131 static const Builtin::Info BuiltinInfo[]; 6132 static const char *const GCCRegNames[]; 6133 std::string CPU; 6134 bool HasTransactionalExecution; 6135 bool HasVector; 6136 6137 public: 6138 SystemZTargetInfo(const llvm::Triple &Triple) 6139 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6140 HasVector(false) { 6141 IntMaxType = SignedLong; 6142 Int64Type = SignedLong; 6143 TLSSupported = true; 6144 IntWidth = IntAlign = 32; 6145 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6146 PointerWidth = PointerAlign = 64; 6147 LongDoubleWidth = 128; 6148 LongDoubleAlign = 64; 6149 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6150 DefaultAlignForAttributeAligned = 64; 6151 MinGlobalAlign = 16; 6152 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6153 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6154 } 6155 void getTargetDefines(const LangOptions &Opts, 6156 MacroBuilder &Builder) const override { 6157 Builder.defineMacro("__s390__"); 6158 Builder.defineMacro("__s390x__"); 6159 Builder.defineMacro("__zarch__"); 6160 Builder.defineMacro("__LONG_DOUBLE_128__"); 6161 6162 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6163 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6164 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6165 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6166 6167 if (HasTransactionalExecution) 6168 Builder.defineMacro("__HTM__"); 6169 if (Opts.ZVector) 6170 Builder.defineMacro("__VEC__", "10301"); 6171 } 6172 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6173 return llvm::makeArrayRef(BuiltinInfo, 6174 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6175 } 6176 6177 ArrayRef<const char *> getGCCRegNames() const override; 6178 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6179 // No aliases. 6180 return None; 6181 } 6182 bool validateAsmConstraint(const char *&Name, 6183 TargetInfo::ConstraintInfo &info) const override; 6184 const char *getClobbers() const override { 6185 // FIXME: Is this really right? 6186 return ""; 6187 } 6188 BuiltinVaListKind getBuiltinVaListKind() const override { 6189 return TargetInfo::SystemZBuiltinVaList; 6190 } 6191 bool setCPU(const std::string &Name) override { 6192 CPU = Name; 6193 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6194 .Case("z10", true) 6195 .Case("z196", true) 6196 .Case("zEC12", true) 6197 .Case("z13", true) 6198 .Default(false); 6199 6200 return CPUKnown; 6201 } 6202 bool 6203 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6204 StringRef CPU, 6205 const std::vector<std::string> &FeaturesVec) const override { 6206 if (CPU == "zEC12") 6207 Features["transactional-execution"] = true; 6208 if (CPU == "z13") { 6209 Features["transactional-execution"] = true; 6210 Features["vector"] = true; 6211 } 6212 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6213 } 6214 6215 bool handleTargetFeatures(std::vector<std::string> &Features, 6216 DiagnosticsEngine &Diags) override { 6217 HasTransactionalExecution = false; 6218 for (const auto &Feature : Features) { 6219 if (Feature == "+transactional-execution") 6220 HasTransactionalExecution = true; 6221 else if (Feature == "+vector") 6222 HasVector = true; 6223 } 6224 // If we use the vector ABI, vector types are 64-bit aligned. 6225 if (HasVector) { 6226 MaxVectorAlign = 64; 6227 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6228 "-v128:64-a:8:16-n32:64"; 6229 } 6230 return true; 6231 } 6232 6233 bool hasFeature(StringRef Feature) const override { 6234 return llvm::StringSwitch<bool>(Feature) 6235 .Case("systemz", true) 6236 .Case("htm", HasTransactionalExecution) 6237 .Case("vx", HasVector) 6238 .Default(false); 6239 } 6240 6241 StringRef getABI() const override { 6242 if (HasVector) 6243 return "vector"; 6244 return ""; 6245 } 6246 6247 bool useFloat128ManglingForLongDouble() const override { 6248 return true; 6249 } 6250 }; 6251 6252 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6253 #define BUILTIN(ID, TYPE, ATTRS) \ 6254 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6255 #include "clang/Basic/BuiltinsSystemZ.def" 6256 }; 6257 6258 const char *const SystemZTargetInfo::GCCRegNames[] = { 6259 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6260 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6261 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6262 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6263 }; 6264 6265 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6266 return llvm::makeArrayRef(GCCRegNames); 6267 } 6268 6269 bool SystemZTargetInfo:: 6270 validateAsmConstraint(const char *&Name, 6271 TargetInfo::ConstraintInfo &Info) const { 6272 switch (*Name) { 6273 default: 6274 return false; 6275 6276 case 'a': // Address register 6277 case 'd': // Data register (equivalent to 'r') 6278 case 'f': // Floating-point register 6279 Info.setAllowsRegister(); 6280 return true; 6281 6282 case 'I': // Unsigned 8-bit constant 6283 case 'J': // Unsigned 12-bit constant 6284 case 'K': // Signed 16-bit constant 6285 case 'L': // Signed 20-bit displacement (on all targets we support) 6286 case 'M': // 0x7fffffff 6287 return true; 6288 6289 case 'Q': // Memory with base and unsigned 12-bit displacement 6290 case 'R': // Likewise, plus an index 6291 case 'S': // Memory with base and signed 20-bit displacement 6292 case 'T': // Likewise, plus an index 6293 Info.setAllowsMemory(); 6294 return true; 6295 } 6296 } 6297 6298 class MSP430TargetInfo : public TargetInfo { 6299 static const char *const GCCRegNames[]; 6300 6301 public: 6302 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6303 BigEndian = false; 6304 TLSSupported = false; 6305 IntWidth = 16; 6306 IntAlign = 16; 6307 LongWidth = 32; 6308 LongLongWidth = 64; 6309 LongAlign = LongLongAlign = 16; 6310 PointerWidth = 16; 6311 PointerAlign = 16; 6312 SuitableAlign = 16; 6313 SizeType = UnsignedInt; 6314 IntMaxType = SignedLongLong; 6315 IntPtrType = SignedInt; 6316 PtrDiffType = SignedInt; 6317 SigAtomicType = SignedLong; 6318 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6319 } 6320 void getTargetDefines(const LangOptions &Opts, 6321 MacroBuilder &Builder) const override { 6322 Builder.defineMacro("MSP430"); 6323 Builder.defineMacro("__MSP430__"); 6324 // FIXME: defines for different 'flavours' of MCU 6325 } 6326 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6327 // FIXME: Implement. 6328 return None; 6329 } 6330 bool hasFeature(StringRef Feature) const override { 6331 return Feature == "msp430"; 6332 } 6333 ArrayRef<const char *> getGCCRegNames() const override; 6334 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6335 // No aliases. 6336 return None; 6337 } 6338 bool validateAsmConstraint(const char *&Name, 6339 TargetInfo::ConstraintInfo &info) const override { 6340 // FIXME: implement 6341 switch (*Name) { 6342 case 'K': // the constant 1 6343 case 'L': // constant -1^20 .. 1^19 6344 case 'M': // constant 1-4: 6345 return true; 6346 } 6347 // No target constraints for now. 6348 return false; 6349 } 6350 const char *getClobbers() const override { 6351 // FIXME: Is this really right? 6352 return ""; 6353 } 6354 BuiltinVaListKind getBuiltinVaListKind() const override { 6355 // FIXME: implement 6356 return TargetInfo::CharPtrBuiltinVaList; 6357 } 6358 }; 6359 6360 const char *const MSP430TargetInfo::GCCRegNames[] = { 6361 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6362 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6363 6364 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6365 return llvm::makeArrayRef(GCCRegNames); 6366 } 6367 6368 // LLVM and Clang cannot be used directly to output native binaries for 6369 // target, but is used to compile C code to llvm bitcode with correct 6370 // type and alignment information. 6371 // 6372 // TCE uses the llvm bitcode as input and uses it for generating customized 6373 // target processor and program binary. TCE co-design environment is 6374 // publicly available in http://tce.cs.tut.fi 6375 6376 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6377 3, // opencl_global 6378 4, // opencl_local 6379 5, // opencl_constant 6380 // FIXME: generic has to be added to the target 6381 0, // opencl_generic 6382 0, // cuda_device 6383 0, // cuda_constant 6384 0 // cuda_shared 6385 }; 6386 6387 class TCETargetInfo : public TargetInfo { 6388 public: 6389 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6390 TLSSupported = false; 6391 IntWidth = 32; 6392 LongWidth = LongLongWidth = 32; 6393 PointerWidth = 32; 6394 IntAlign = 32; 6395 LongAlign = LongLongAlign = 32; 6396 PointerAlign = 32; 6397 SuitableAlign = 32; 6398 SizeType = UnsignedInt; 6399 IntMaxType = SignedLong; 6400 IntPtrType = SignedInt; 6401 PtrDiffType = SignedInt; 6402 FloatWidth = 32; 6403 FloatAlign = 32; 6404 DoubleWidth = 32; 6405 DoubleAlign = 32; 6406 LongDoubleWidth = 32; 6407 LongDoubleAlign = 32; 6408 FloatFormat = &llvm::APFloat::IEEEsingle; 6409 DoubleFormat = &llvm::APFloat::IEEEsingle; 6410 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6411 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6412 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6413 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6414 UseAddrSpaceMapMangling = true; 6415 } 6416 6417 void getTargetDefines(const LangOptions &Opts, 6418 MacroBuilder &Builder) const override { 6419 DefineStd(Builder, "tce", Opts); 6420 Builder.defineMacro("__TCE__"); 6421 Builder.defineMacro("__TCE_V1__"); 6422 } 6423 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6424 6425 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6426 const char *getClobbers() const override { return ""; } 6427 BuiltinVaListKind getBuiltinVaListKind() const override { 6428 return TargetInfo::VoidPtrBuiltinVaList; 6429 } 6430 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6431 bool validateAsmConstraint(const char *&Name, 6432 TargetInfo::ConstraintInfo &info) const override { 6433 return true; 6434 } 6435 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6436 return None; 6437 } 6438 }; 6439 6440 class BPFTargetInfo : public TargetInfo { 6441 public: 6442 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6443 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6444 SizeType = UnsignedLong; 6445 PtrDiffType = SignedLong; 6446 IntPtrType = SignedLong; 6447 IntMaxType = SignedLong; 6448 Int64Type = SignedLong; 6449 RegParmMax = 5; 6450 if (Triple.getArch() == llvm::Triple::bpfeb) { 6451 BigEndian = true; 6452 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6453 } else { 6454 BigEndian = false; 6455 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6456 } 6457 MaxAtomicPromoteWidth = 64; 6458 MaxAtomicInlineWidth = 64; 6459 TLSSupported = false; 6460 } 6461 void getTargetDefines(const LangOptions &Opts, 6462 MacroBuilder &Builder) const override { 6463 DefineStd(Builder, "bpf", Opts); 6464 Builder.defineMacro("__BPF__"); 6465 } 6466 bool hasFeature(StringRef Feature) const override { 6467 return Feature == "bpf"; 6468 } 6469 6470 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6471 const char *getClobbers() const override { 6472 return ""; 6473 } 6474 BuiltinVaListKind getBuiltinVaListKind() const override { 6475 return TargetInfo::VoidPtrBuiltinVaList; 6476 } 6477 ArrayRef<const char *> getGCCRegNames() const override { 6478 return None; 6479 } 6480 bool validateAsmConstraint(const char *&Name, 6481 TargetInfo::ConstraintInfo &info) const override { 6482 return true; 6483 } 6484 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6485 return None; 6486 } 6487 }; 6488 6489 class MipsTargetInfoBase : public TargetInfo { 6490 virtual void setDataLayoutString() = 0; 6491 6492 static const Builtin::Info BuiltinInfo[]; 6493 std::string CPU; 6494 bool IsMips16; 6495 bool IsMicromips; 6496 bool IsNan2008; 6497 bool IsSingleFloat; 6498 enum MipsFloatABI { 6499 HardFloat, SoftFloat 6500 } FloatABI; 6501 enum DspRevEnum { 6502 NoDSP, DSP1, DSP2 6503 } DspRev; 6504 bool HasMSA; 6505 6506 protected: 6507 bool HasFP64; 6508 std::string ABI; 6509 6510 public: 6511 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6512 const std::string &CPUStr) 6513 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6514 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6515 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6516 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6517 } 6518 6519 bool isNaN2008Default() const { 6520 return CPU == "mips32r6" || CPU == "mips64r6"; 6521 } 6522 6523 bool isFP64Default() const { 6524 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6525 } 6526 6527 bool isNan2008() const override { 6528 return IsNan2008; 6529 } 6530 6531 StringRef getABI() const override { return ABI; } 6532 bool setCPU(const std::string &Name) override { 6533 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6534 getTriple().getArch() == llvm::Triple::mipsel; 6535 CPU = Name; 6536 return llvm::StringSwitch<bool>(Name) 6537 .Case("mips1", IsMips32) 6538 .Case("mips2", IsMips32) 6539 .Case("mips3", true) 6540 .Case("mips4", true) 6541 .Case("mips5", true) 6542 .Case("mips32", IsMips32) 6543 .Case("mips32r2", IsMips32) 6544 .Case("mips32r3", IsMips32) 6545 .Case("mips32r5", IsMips32) 6546 .Case("mips32r6", IsMips32) 6547 .Case("mips64", true) 6548 .Case("mips64r2", true) 6549 .Case("mips64r3", true) 6550 .Case("mips64r5", true) 6551 .Case("mips64r6", true) 6552 .Case("octeon", true) 6553 .Case("p5600", true) 6554 .Default(false); 6555 } 6556 const std::string& getCPU() const { return CPU; } 6557 bool 6558 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6559 StringRef CPU, 6560 const std::vector<std::string> &FeaturesVec) const override { 6561 if (CPU == "octeon") 6562 Features["mips64r2"] = Features["cnmips"] = true; 6563 else 6564 Features[CPU] = true; 6565 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6566 } 6567 6568 void getTargetDefines(const LangOptions &Opts, 6569 MacroBuilder &Builder) const override { 6570 Builder.defineMacro("__mips__"); 6571 Builder.defineMacro("_mips"); 6572 if (Opts.GNUMode) 6573 Builder.defineMacro("mips"); 6574 6575 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6576 6577 switch (FloatABI) { 6578 case HardFloat: 6579 Builder.defineMacro("__mips_hard_float", Twine(1)); 6580 break; 6581 case SoftFloat: 6582 Builder.defineMacro("__mips_soft_float", Twine(1)); 6583 break; 6584 } 6585 6586 if (IsSingleFloat) 6587 Builder.defineMacro("__mips_single_float", Twine(1)); 6588 6589 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6590 Builder.defineMacro("_MIPS_FPSET", 6591 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6592 6593 if (IsMips16) 6594 Builder.defineMacro("__mips16", Twine(1)); 6595 6596 if (IsMicromips) 6597 Builder.defineMacro("__mips_micromips", Twine(1)); 6598 6599 if (IsNan2008) 6600 Builder.defineMacro("__mips_nan2008", Twine(1)); 6601 6602 switch (DspRev) { 6603 default: 6604 break; 6605 case DSP1: 6606 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6607 Builder.defineMacro("__mips_dsp", Twine(1)); 6608 break; 6609 case DSP2: 6610 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6611 Builder.defineMacro("__mips_dspr2", Twine(1)); 6612 Builder.defineMacro("__mips_dsp", Twine(1)); 6613 break; 6614 } 6615 6616 if (HasMSA) 6617 Builder.defineMacro("__mips_msa", Twine(1)); 6618 6619 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6620 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6621 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6622 6623 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6624 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6625 6626 // These shouldn't be defined for MIPS-I but there's no need to check 6627 // for that since MIPS-I isn't supported. 6628 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6629 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6630 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6631 } 6632 6633 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6634 return llvm::makeArrayRef(BuiltinInfo, 6635 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6636 } 6637 bool hasFeature(StringRef Feature) const override { 6638 return llvm::StringSwitch<bool>(Feature) 6639 .Case("mips", true) 6640 .Case("fp64", HasFP64) 6641 .Default(false); 6642 } 6643 BuiltinVaListKind getBuiltinVaListKind() const override { 6644 return TargetInfo::VoidPtrBuiltinVaList; 6645 } 6646 ArrayRef<const char *> getGCCRegNames() const override { 6647 static const char *const GCCRegNames[] = { 6648 // CPU register names 6649 // Must match second column of GCCRegAliases 6650 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6651 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6652 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6653 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6654 // Floating point register names 6655 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6656 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6657 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6658 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6659 // Hi/lo and condition register names 6660 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6661 "$fcc5","$fcc6","$fcc7", 6662 // MSA register names 6663 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6664 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6665 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6666 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6667 // MSA control register names 6668 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6669 "$msarequest", "$msamap", "$msaunmap" 6670 }; 6671 return llvm::makeArrayRef(GCCRegNames); 6672 } 6673 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6674 bool validateAsmConstraint(const char *&Name, 6675 TargetInfo::ConstraintInfo &Info) const override { 6676 switch (*Name) { 6677 default: 6678 return false; 6679 case 'r': // CPU registers. 6680 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6681 case 'y': // Equivalent to "r", backward compatibility only. 6682 case 'f': // floating-point registers. 6683 case 'c': // $25 for indirect jumps 6684 case 'l': // lo register 6685 case 'x': // hilo register pair 6686 Info.setAllowsRegister(); 6687 return true; 6688 case 'I': // Signed 16-bit constant 6689 case 'J': // Integer 0 6690 case 'K': // Unsigned 16-bit constant 6691 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6692 case 'M': // Constants not loadable via lui, addiu, or ori 6693 case 'N': // Constant -1 to -65535 6694 case 'O': // A signed 15-bit constant 6695 case 'P': // A constant between 1 go 65535 6696 return true; 6697 case 'R': // An address that can be used in a non-macro load or store 6698 Info.setAllowsMemory(); 6699 return true; 6700 case 'Z': 6701 if (Name[1] == 'C') { // An address usable by ll, and sc. 6702 Info.setAllowsMemory(); 6703 Name++; // Skip over 'Z'. 6704 return true; 6705 } 6706 return false; 6707 } 6708 } 6709 6710 std::string convertConstraint(const char *&Constraint) const override { 6711 std::string R; 6712 switch (*Constraint) { 6713 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6714 if (Constraint[1] == 'C') { 6715 R = std::string("^") + std::string(Constraint, 2); 6716 Constraint++; 6717 return R; 6718 } 6719 break; 6720 } 6721 return TargetInfo::convertConstraint(Constraint); 6722 } 6723 6724 const char *getClobbers() const override { 6725 // In GCC, $1 is not widely used in generated code (it's used only in a few 6726 // specific situations), so there is no real need for users to add it to 6727 // the clobbers list if they want to use it in their inline assembly code. 6728 // 6729 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6730 // code generation, so using it in inline assembly without adding it to the 6731 // clobbers list can cause conflicts between the inline assembly code and 6732 // the surrounding generated code. 6733 // 6734 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6735 // operands, which will conflict with the ".set at" assembler option (which 6736 // we use only for inline assembly, in order to maintain compatibility with 6737 // GCC) and will also conflict with the user's usage of $1. 6738 // 6739 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6740 // register for generated code is to automatically clobber $1 for all inline 6741 // assembly code. 6742 // 6743 // FIXME: We should automatically clobber $1 only for inline assembly code 6744 // which actually uses it. This would allow LLVM to use $1 for inline 6745 // assembly operands if the user's assembly code doesn't use it. 6746 return "~{$1}"; 6747 } 6748 6749 bool handleTargetFeatures(std::vector<std::string> &Features, 6750 DiagnosticsEngine &Diags) override { 6751 IsMips16 = false; 6752 IsMicromips = false; 6753 IsNan2008 = isNaN2008Default(); 6754 IsSingleFloat = false; 6755 FloatABI = HardFloat; 6756 DspRev = NoDSP; 6757 HasFP64 = isFP64Default(); 6758 6759 for (const auto &Feature : Features) { 6760 if (Feature == "+single-float") 6761 IsSingleFloat = true; 6762 else if (Feature == "+soft-float") 6763 FloatABI = SoftFloat; 6764 else if (Feature == "+mips16") 6765 IsMips16 = true; 6766 else if (Feature == "+micromips") 6767 IsMicromips = true; 6768 else if (Feature == "+dsp") 6769 DspRev = std::max(DspRev, DSP1); 6770 else if (Feature == "+dspr2") 6771 DspRev = std::max(DspRev, DSP2); 6772 else if (Feature == "+msa") 6773 HasMSA = true; 6774 else if (Feature == "+fp64") 6775 HasFP64 = true; 6776 else if (Feature == "-fp64") 6777 HasFP64 = false; 6778 else if (Feature == "+nan2008") 6779 IsNan2008 = true; 6780 else if (Feature == "-nan2008") 6781 IsNan2008 = false; 6782 } 6783 6784 setDataLayoutString(); 6785 6786 return true; 6787 } 6788 6789 int getEHDataRegisterNumber(unsigned RegNo) const override { 6790 if (RegNo == 0) return 4; 6791 if (RegNo == 1) return 5; 6792 return -1; 6793 } 6794 6795 bool isCLZForZeroUndef() const override { return false; } 6796 }; 6797 6798 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6799 #define BUILTIN(ID, TYPE, ATTRS) \ 6800 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6801 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6802 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6803 #include "clang/Basic/BuiltinsMips.def" 6804 }; 6805 6806 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6807 public: 6808 Mips32TargetInfoBase(const llvm::Triple &Triple) 6809 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6810 SizeType = UnsignedInt; 6811 PtrDiffType = SignedInt; 6812 Int64Type = SignedLongLong; 6813 IntMaxType = Int64Type; 6814 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6815 } 6816 bool setABI(const std::string &Name) override { 6817 if (Name == "o32" || Name == "eabi") { 6818 ABI = Name; 6819 return true; 6820 } 6821 return false; 6822 } 6823 void getTargetDefines(const LangOptions &Opts, 6824 MacroBuilder &Builder) const override { 6825 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6826 6827 Builder.defineMacro("__mips", "32"); 6828 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6829 6830 const std::string& CPUStr = getCPU(); 6831 if (CPUStr == "mips32") 6832 Builder.defineMacro("__mips_isa_rev", "1"); 6833 else if (CPUStr == "mips32r2") 6834 Builder.defineMacro("__mips_isa_rev", "2"); 6835 else if (CPUStr == "mips32r3") 6836 Builder.defineMacro("__mips_isa_rev", "3"); 6837 else if (CPUStr == "mips32r5") 6838 Builder.defineMacro("__mips_isa_rev", "5"); 6839 else if (CPUStr == "mips32r6") 6840 Builder.defineMacro("__mips_isa_rev", "6"); 6841 6842 if (ABI == "o32") { 6843 Builder.defineMacro("__mips_o32"); 6844 Builder.defineMacro("_ABIO32", "1"); 6845 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6846 } 6847 else if (ABI == "eabi") 6848 Builder.defineMacro("__mips_eabi"); 6849 else 6850 llvm_unreachable("Invalid ABI for Mips32."); 6851 } 6852 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6853 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6854 { { "at" }, "$1" }, 6855 { { "v0" }, "$2" }, 6856 { { "v1" }, "$3" }, 6857 { { "a0" }, "$4" }, 6858 { { "a1" }, "$5" }, 6859 { { "a2" }, "$6" }, 6860 { { "a3" }, "$7" }, 6861 { { "t0" }, "$8" }, 6862 { { "t1" }, "$9" }, 6863 { { "t2" }, "$10" }, 6864 { { "t3" }, "$11" }, 6865 { { "t4" }, "$12" }, 6866 { { "t5" }, "$13" }, 6867 { { "t6" }, "$14" }, 6868 { { "t7" }, "$15" }, 6869 { { "s0" }, "$16" }, 6870 { { "s1" }, "$17" }, 6871 { { "s2" }, "$18" }, 6872 { { "s3" }, "$19" }, 6873 { { "s4" }, "$20" }, 6874 { { "s5" }, "$21" }, 6875 { { "s6" }, "$22" }, 6876 { { "s7" }, "$23" }, 6877 { { "t8" }, "$24" }, 6878 { { "t9" }, "$25" }, 6879 { { "k0" }, "$26" }, 6880 { { "k1" }, "$27" }, 6881 { { "gp" }, "$28" }, 6882 { { "sp","$sp" }, "$29" }, 6883 { { "fp","$fp" }, "$30" }, 6884 { { "ra" }, "$31" } 6885 }; 6886 return llvm::makeArrayRef(GCCRegAliases); 6887 } 6888 }; 6889 6890 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6891 void setDataLayoutString() override { 6892 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6893 } 6894 6895 public: 6896 Mips32EBTargetInfo(const llvm::Triple &Triple) 6897 : Mips32TargetInfoBase(Triple) { 6898 } 6899 void getTargetDefines(const LangOptions &Opts, 6900 MacroBuilder &Builder) const override { 6901 DefineStd(Builder, "MIPSEB", Opts); 6902 Builder.defineMacro("_MIPSEB"); 6903 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6904 } 6905 }; 6906 6907 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6908 void setDataLayoutString() override { 6909 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6910 } 6911 6912 public: 6913 Mips32ELTargetInfo(const llvm::Triple &Triple) 6914 : Mips32TargetInfoBase(Triple) { 6915 BigEndian = false; 6916 } 6917 void getTargetDefines(const LangOptions &Opts, 6918 MacroBuilder &Builder) const override { 6919 DefineStd(Builder, "MIPSEL", Opts); 6920 Builder.defineMacro("_MIPSEL"); 6921 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6922 } 6923 }; 6924 6925 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6926 public: 6927 Mips64TargetInfoBase(const llvm::Triple &Triple) 6928 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6929 LongDoubleWidth = LongDoubleAlign = 128; 6930 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6931 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6932 LongDoubleWidth = LongDoubleAlign = 64; 6933 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6934 } 6935 setN64ABITypes(); 6936 SuitableAlign = 128; 6937 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6938 } 6939 6940 void setN64ABITypes() { 6941 LongWidth = LongAlign = 64; 6942 PointerWidth = PointerAlign = 64; 6943 SizeType = UnsignedLong; 6944 PtrDiffType = SignedLong; 6945 Int64Type = SignedLong; 6946 IntMaxType = Int64Type; 6947 } 6948 6949 void setN32ABITypes() { 6950 LongWidth = LongAlign = 32; 6951 PointerWidth = PointerAlign = 32; 6952 SizeType = UnsignedInt; 6953 PtrDiffType = SignedInt; 6954 Int64Type = SignedLongLong; 6955 IntMaxType = Int64Type; 6956 } 6957 6958 bool setABI(const std::string &Name) override { 6959 if (Name == "n32") { 6960 setN32ABITypes(); 6961 ABI = Name; 6962 return true; 6963 } 6964 if (Name == "n64") { 6965 setN64ABITypes(); 6966 ABI = Name; 6967 return true; 6968 } 6969 return false; 6970 } 6971 6972 void getTargetDefines(const LangOptions &Opts, 6973 MacroBuilder &Builder) const override { 6974 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6975 6976 Builder.defineMacro("__mips", "64"); 6977 Builder.defineMacro("__mips64"); 6978 Builder.defineMacro("__mips64__"); 6979 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6980 6981 const std::string& CPUStr = getCPU(); 6982 if (CPUStr == "mips64") 6983 Builder.defineMacro("__mips_isa_rev", "1"); 6984 else if (CPUStr == "mips64r2") 6985 Builder.defineMacro("__mips_isa_rev", "2"); 6986 else if (CPUStr == "mips64r3") 6987 Builder.defineMacro("__mips_isa_rev", "3"); 6988 else if (CPUStr == "mips64r5") 6989 Builder.defineMacro("__mips_isa_rev", "5"); 6990 else if (CPUStr == "mips64r6") 6991 Builder.defineMacro("__mips_isa_rev", "6"); 6992 6993 if (ABI == "n32") { 6994 Builder.defineMacro("__mips_n32"); 6995 Builder.defineMacro("_ABIN32", "2"); 6996 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6997 } 6998 else if (ABI == "n64") { 6999 Builder.defineMacro("__mips_n64"); 7000 Builder.defineMacro("_ABI64", "3"); 7001 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7002 } 7003 else 7004 llvm_unreachable("Invalid ABI for Mips64."); 7005 7006 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7007 } 7008 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7009 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7010 { { "at" }, "$1" }, 7011 { { "v0" }, "$2" }, 7012 { { "v1" }, "$3" }, 7013 { { "a0" }, "$4" }, 7014 { { "a1" }, "$5" }, 7015 { { "a2" }, "$6" }, 7016 { { "a3" }, "$7" }, 7017 { { "a4" }, "$8" }, 7018 { { "a5" }, "$9" }, 7019 { { "a6" }, "$10" }, 7020 { { "a7" }, "$11" }, 7021 { { "t0" }, "$12" }, 7022 { { "t1" }, "$13" }, 7023 { { "t2" }, "$14" }, 7024 { { "t3" }, "$15" }, 7025 { { "s0" }, "$16" }, 7026 { { "s1" }, "$17" }, 7027 { { "s2" }, "$18" }, 7028 { { "s3" }, "$19" }, 7029 { { "s4" }, "$20" }, 7030 { { "s5" }, "$21" }, 7031 { { "s6" }, "$22" }, 7032 { { "s7" }, "$23" }, 7033 { { "t8" }, "$24" }, 7034 { { "t9" }, "$25" }, 7035 { { "k0" }, "$26" }, 7036 { { "k1" }, "$27" }, 7037 { { "gp" }, "$28" }, 7038 { { "sp","$sp" }, "$29" }, 7039 { { "fp","$fp" }, "$30" }, 7040 { { "ra" }, "$31" } 7041 }; 7042 return llvm::makeArrayRef(GCCRegAliases); 7043 } 7044 7045 bool hasInt128Type() const override { return true; } 7046 }; 7047 7048 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7049 void setDataLayoutString() override { 7050 if (ABI == "n32") 7051 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7052 else 7053 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7054 7055 } 7056 7057 public: 7058 Mips64EBTargetInfo(const llvm::Triple &Triple) 7059 : Mips64TargetInfoBase(Triple) {} 7060 void getTargetDefines(const LangOptions &Opts, 7061 MacroBuilder &Builder) const override { 7062 DefineStd(Builder, "MIPSEB", Opts); 7063 Builder.defineMacro("_MIPSEB"); 7064 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7065 } 7066 }; 7067 7068 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7069 void setDataLayoutString() override { 7070 if (ABI == "n32") 7071 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7072 else 7073 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7074 } 7075 public: 7076 Mips64ELTargetInfo(const llvm::Triple &Triple) 7077 : Mips64TargetInfoBase(Triple) { 7078 // Default ABI is n64. 7079 BigEndian = false; 7080 } 7081 void getTargetDefines(const LangOptions &Opts, 7082 MacroBuilder &Builder) const override { 7083 DefineStd(Builder, "MIPSEL", Opts); 7084 Builder.defineMacro("_MIPSEL"); 7085 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7086 } 7087 }; 7088 7089 class PNaClTargetInfo : public TargetInfo { 7090 public: 7091 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7092 BigEndian = false; 7093 this->UserLabelPrefix = ""; 7094 this->LongAlign = 32; 7095 this->LongWidth = 32; 7096 this->PointerAlign = 32; 7097 this->PointerWidth = 32; 7098 this->IntMaxType = TargetInfo::SignedLongLong; 7099 this->Int64Type = TargetInfo::SignedLongLong; 7100 this->DoubleAlign = 64; 7101 this->LongDoubleWidth = 64; 7102 this->LongDoubleAlign = 64; 7103 this->SizeType = TargetInfo::UnsignedInt; 7104 this->PtrDiffType = TargetInfo::SignedInt; 7105 this->IntPtrType = TargetInfo::SignedInt; 7106 this->RegParmMax = 0; // Disallow regparm 7107 } 7108 7109 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7110 Builder.defineMacro("__le32__"); 7111 Builder.defineMacro("__pnacl__"); 7112 } 7113 void getTargetDefines(const LangOptions &Opts, 7114 MacroBuilder &Builder) const override { 7115 getArchDefines(Opts, Builder); 7116 } 7117 bool hasFeature(StringRef Feature) const override { 7118 return Feature == "pnacl"; 7119 } 7120 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7121 BuiltinVaListKind getBuiltinVaListKind() const override { 7122 return TargetInfo::PNaClABIBuiltinVaList; 7123 } 7124 ArrayRef<const char *> getGCCRegNames() const override; 7125 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7126 bool validateAsmConstraint(const char *&Name, 7127 TargetInfo::ConstraintInfo &Info) const override { 7128 return false; 7129 } 7130 7131 const char *getClobbers() const override { 7132 return ""; 7133 } 7134 }; 7135 7136 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7137 return None; 7138 } 7139 7140 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7141 return None; 7142 } 7143 7144 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7145 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7146 public: 7147 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7148 Mips32ELTargetInfo(Triple) { 7149 } 7150 7151 BuiltinVaListKind getBuiltinVaListKind() const override { 7152 return TargetInfo::PNaClABIBuiltinVaList; 7153 } 7154 }; 7155 7156 class Le64TargetInfo : public TargetInfo { 7157 static const Builtin::Info BuiltinInfo[]; 7158 7159 public: 7160 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7161 BigEndian = false; 7162 NoAsmVariants = true; 7163 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7164 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7165 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7166 } 7167 7168 void getTargetDefines(const LangOptions &Opts, 7169 MacroBuilder &Builder) const override { 7170 DefineStd(Builder, "unix", Opts); 7171 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7172 Builder.defineMacro("__ELF__"); 7173 } 7174 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7175 return llvm::makeArrayRef(BuiltinInfo, 7176 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7177 } 7178 BuiltinVaListKind getBuiltinVaListKind() const override { 7179 return TargetInfo::PNaClABIBuiltinVaList; 7180 } 7181 const char *getClobbers() const override { return ""; } 7182 ArrayRef<const char *> getGCCRegNames() const override { 7183 return None; 7184 } 7185 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7186 return None; 7187 } 7188 bool validateAsmConstraint(const char *&Name, 7189 TargetInfo::ConstraintInfo &Info) const override { 7190 return false; 7191 } 7192 7193 bool hasProtectedVisibility() const override { return false; } 7194 }; 7195 7196 class WebAssemblyTargetInfo : public TargetInfo { 7197 static const Builtin::Info BuiltinInfo[]; 7198 7199 enum SIMDEnum { 7200 NoSIMD, 7201 SIMD128, 7202 } SIMDLevel; 7203 7204 public: 7205 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7206 : TargetInfo(T), SIMDLevel(NoSIMD) { 7207 BigEndian = false; 7208 NoAsmVariants = true; 7209 SuitableAlign = 128; 7210 LargeArrayMinWidth = 128; 7211 LargeArrayAlign = 128; 7212 SimdDefaultAlign = 128; 7213 SigAtomicType = SignedLong; 7214 LongDoubleWidth = LongDoubleAlign = 128; 7215 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7216 } 7217 7218 protected: 7219 void getTargetDefines(const LangOptions &Opts, 7220 MacroBuilder &Builder) const override { 7221 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7222 if (SIMDLevel >= SIMD128) 7223 Builder.defineMacro("__wasm_simd128__"); 7224 } 7225 7226 private: 7227 bool 7228 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7229 StringRef CPU, 7230 const std::vector<std::string> &FeaturesVec) const override { 7231 if (CPU == "bleeding-edge") 7232 Features["simd128"] = true; 7233 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7234 } 7235 bool hasFeature(StringRef Feature) const final { 7236 return llvm::StringSwitch<bool>(Feature) 7237 .Case("simd128", SIMDLevel >= SIMD128) 7238 .Default(false); 7239 } 7240 bool handleTargetFeatures(std::vector<std::string> &Features, 7241 DiagnosticsEngine &Diags) final { 7242 for (const auto &Feature : Features) { 7243 if (Feature == "+simd128") { 7244 SIMDLevel = std::max(SIMDLevel, SIMD128); 7245 continue; 7246 } 7247 if (Feature == "-simd128") { 7248 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7249 continue; 7250 } 7251 7252 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7253 << "-target-feature"; 7254 return false; 7255 } 7256 return true; 7257 } 7258 bool setCPU(const std::string &Name) final { 7259 return llvm::StringSwitch<bool>(Name) 7260 .Case("mvp", true) 7261 .Case("bleeding-edge", true) 7262 .Case("generic", true) 7263 .Default(false); 7264 } 7265 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7266 return llvm::makeArrayRef(BuiltinInfo, 7267 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7268 } 7269 BuiltinVaListKind getBuiltinVaListKind() const final { 7270 return VoidPtrBuiltinVaList; 7271 } 7272 ArrayRef<const char *> getGCCRegNames() const final { 7273 return None; 7274 } 7275 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7276 return None; 7277 } 7278 bool 7279 validateAsmConstraint(const char *&Name, 7280 TargetInfo::ConstraintInfo &Info) const final { 7281 return false; 7282 } 7283 const char *getClobbers() const final { return ""; } 7284 bool isCLZForZeroUndef() const final { return false; } 7285 bool hasInt128Type() const final { return true; } 7286 IntType getIntTypeByWidth(unsigned BitWidth, 7287 bool IsSigned) const final { 7288 // WebAssembly prefers long long for explicitly 64-bit integers. 7289 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7290 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7291 } 7292 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7293 bool IsSigned) const final { 7294 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7295 return BitWidth == 64 7296 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7297 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7298 } 7299 }; 7300 7301 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7302 #define BUILTIN(ID, TYPE, ATTRS) \ 7303 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7304 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7305 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7306 #include "clang/Basic/BuiltinsWebAssembly.def" 7307 }; 7308 7309 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7310 public: 7311 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7312 : WebAssemblyTargetInfo(T) { 7313 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7314 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128"; 7315 } 7316 7317 protected: 7318 void getTargetDefines(const LangOptions &Opts, 7319 MacroBuilder &Builder) const override { 7320 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7321 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7322 } 7323 }; 7324 7325 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7326 public: 7327 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7328 : WebAssemblyTargetInfo(T) { 7329 LongAlign = LongWidth = 64; 7330 PointerAlign = PointerWidth = 64; 7331 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7332 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 7333 } 7334 7335 protected: 7336 void getTargetDefines(const LangOptions &Opts, 7337 MacroBuilder &Builder) const override { 7338 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7339 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7340 } 7341 }; 7342 7343 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7344 #define BUILTIN(ID, TYPE, ATTRS) \ 7345 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7346 #include "clang/Basic/BuiltinsLe64.def" 7347 }; 7348 7349 static const unsigned SPIRAddrSpaceMap[] = { 7350 1, // opencl_global 7351 3, // opencl_local 7352 2, // opencl_constant 7353 4, // opencl_generic 7354 0, // cuda_device 7355 0, // cuda_constant 7356 0 // cuda_shared 7357 }; 7358 class SPIRTargetInfo : public TargetInfo { 7359 public: 7360 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7361 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7362 "SPIR target must use unknown OS"); 7363 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7364 "SPIR target must use unknown environment type"); 7365 BigEndian = false; 7366 TLSSupported = false; 7367 LongWidth = LongAlign = 64; 7368 AddrSpaceMap = &SPIRAddrSpaceMap; 7369 UseAddrSpaceMapMangling = true; 7370 // Define available target features 7371 // These must be defined in sorted order! 7372 NoAsmVariants = true; 7373 } 7374 void getTargetDefines(const LangOptions &Opts, 7375 MacroBuilder &Builder) const override { 7376 DefineStd(Builder, "SPIR", Opts); 7377 } 7378 bool hasFeature(StringRef Feature) const override { 7379 return Feature == "spir"; 7380 } 7381 7382 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7383 const char *getClobbers() const override { return ""; } 7384 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7385 bool validateAsmConstraint(const char *&Name, 7386 TargetInfo::ConstraintInfo &info) const override { 7387 return true; 7388 } 7389 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7390 return None; 7391 } 7392 BuiltinVaListKind getBuiltinVaListKind() const override { 7393 return TargetInfo::VoidPtrBuiltinVaList; 7394 } 7395 7396 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7397 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7398 : CCCR_Warning; 7399 } 7400 7401 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7402 return CC_SpirFunction; 7403 } 7404 }; 7405 7406 class SPIR32TargetInfo : public SPIRTargetInfo { 7407 public: 7408 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7409 PointerWidth = PointerAlign = 32; 7410 SizeType = TargetInfo::UnsignedInt; 7411 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7412 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7413 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7414 } 7415 void getTargetDefines(const LangOptions &Opts, 7416 MacroBuilder &Builder) const override { 7417 DefineStd(Builder, "SPIR32", Opts); 7418 } 7419 }; 7420 7421 class SPIR64TargetInfo : public SPIRTargetInfo { 7422 public: 7423 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7424 PointerWidth = PointerAlign = 64; 7425 SizeType = TargetInfo::UnsignedLong; 7426 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7427 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7428 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7429 } 7430 void getTargetDefines(const LangOptions &Opts, 7431 MacroBuilder &Builder) const override { 7432 DefineStd(Builder, "SPIR64", Opts); 7433 } 7434 }; 7435 7436 class XCoreTargetInfo : public TargetInfo { 7437 static const Builtin::Info BuiltinInfo[]; 7438 public: 7439 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7440 BigEndian = false; 7441 NoAsmVariants = true; 7442 LongLongAlign = 32; 7443 SuitableAlign = 32; 7444 DoubleAlign = LongDoubleAlign = 32; 7445 SizeType = UnsignedInt; 7446 PtrDiffType = SignedInt; 7447 IntPtrType = SignedInt; 7448 WCharType = UnsignedChar; 7449 WIntType = UnsignedInt; 7450 UseZeroLengthBitfieldAlignment = true; 7451 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7452 "-f64:32-a:0:32-n32"; 7453 } 7454 void getTargetDefines(const LangOptions &Opts, 7455 MacroBuilder &Builder) const override { 7456 Builder.defineMacro("__XS1B__"); 7457 } 7458 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7459 return llvm::makeArrayRef(BuiltinInfo, 7460 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7461 } 7462 BuiltinVaListKind getBuiltinVaListKind() const override { 7463 return TargetInfo::VoidPtrBuiltinVaList; 7464 } 7465 const char *getClobbers() const override { 7466 return ""; 7467 } 7468 ArrayRef<const char *> getGCCRegNames() const override { 7469 static const char * const GCCRegNames[] = { 7470 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7471 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7472 }; 7473 return llvm::makeArrayRef(GCCRegNames); 7474 } 7475 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7476 return None; 7477 } 7478 bool validateAsmConstraint(const char *&Name, 7479 TargetInfo::ConstraintInfo &Info) const override { 7480 return false; 7481 } 7482 int getEHDataRegisterNumber(unsigned RegNo) const override { 7483 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7484 return (RegNo < 2)? RegNo : -1; 7485 } 7486 }; 7487 7488 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7489 #define BUILTIN(ID, TYPE, ATTRS) \ 7490 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7491 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7492 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7493 #include "clang/Basic/BuiltinsXCore.def" 7494 }; 7495 7496 // x86_32 Android target 7497 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7498 public: 7499 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7500 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7501 SuitableAlign = 32; 7502 LongDoubleWidth = 64; 7503 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7504 } 7505 }; 7506 7507 // x86_64 Android target 7508 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7509 public: 7510 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7511 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7512 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7513 } 7514 7515 bool useFloat128ManglingForLongDouble() const override { 7516 return true; 7517 } 7518 }; 7519 } // end anonymous namespace 7520 7521 //===----------------------------------------------------------------------===// 7522 // Driver code 7523 //===----------------------------------------------------------------------===// 7524 7525 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7526 llvm::Triple::OSType os = Triple.getOS(); 7527 7528 switch (Triple.getArch()) { 7529 default: 7530 return nullptr; 7531 7532 case llvm::Triple::xcore: 7533 return new XCoreTargetInfo(Triple); 7534 7535 case llvm::Triple::hexagon: 7536 return new HexagonTargetInfo(Triple); 7537 7538 case llvm::Triple::aarch64: 7539 if (Triple.isOSDarwin()) 7540 return new DarwinAArch64TargetInfo(Triple); 7541 7542 switch (os) { 7543 case llvm::Triple::CloudABI: 7544 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7545 case llvm::Triple::FreeBSD: 7546 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7547 case llvm::Triple::Linux: 7548 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7549 case llvm::Triple::NetBSD: 7550 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7551 default: 7552 return new AArch64leTargetInfo(Triple); 7553 } 7554 7555 case llvm::Triple::aarch64_be: 7556 switch (os) { 7557 case llvm::Triple::FreeBSD: 7558 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7559 case llvm::Triple::Linux: 7560 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7561 case llvm::Triple::NetBSD: 7562 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7563 default: 7564 return new AArch64beTargetInfo(Triple); 7565 } 7566 7567 case llvm::Triple::arm: 7568 case llvm::Triple::thumb: 7569 if (Triple.isOSBinFormatMachO()) 7570 return new DarwinARMTargetInfo(Triple); 7571 7572 switch (os) { 7573 case llvm::Triple::Linux: 7574 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7575 case llvm::Triple::FreeBSD: 7576 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7577 case llvm::Triple::NetBSD: 7578 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7579 case llvm::Triple::OpenBSD: 7580 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7581 case llvm::Triple::Bitrig: 7582 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7583 case llvm::Triple::RTEMS: 7584 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7585 case llvm::Triple::NaCl: 7586 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7587 case llvm::Triple::Win32: 7588 switch (Triple.getEnvironment()) { 7589 case llvm::Triple::Cygnus: 7590 return new CygwinARMTargetInfo(Triple); 7591 case llvm::Triple::GNU: 7592 return new MinGWARMTargetInfo(Triple); 7593 case llvm::Triple::Itanium: 7594 return new ItaniumWindowsARMleTargetInfo(Triple); 7595 case llvm::Triple::MSVC: 7596 default: // Assume MSVC for unknown environments 7597 return new MicrosoftARMleTargetInfo(Triple); 7598 } 7599 default: 7600 return new ARMleTargetInfo(Triple); 7601 } 7602 7603 case llvm::Triple::armeb: 7604 case llvm::Triple::thumbeb: 7605 if (Triple.isOSDarwin()) 7606 return new DarwinARMTargetInfo(Triple); 7607 7608 switch (os) { 7609 case llvm::Triple::Linux: 7610 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7611 case llvm::Triple::FreeBSD: 7612 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7613 case llvm::Triple::NetBSD: 7614 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7615 case llvm::Triple::OpenBSD: 7616 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7617 case llvm::Triple::Bitrig: 7618 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7619 case llvm::Triple::RTEMS: 7620 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7621 case llvm::Triple::NaCl: 7622 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7623 default: 7624 return new ARMbeTargetInfo(Triple); 7625 } 7626 7627 case llvm::Triple::bpfeb: 7628 case llvm::Triple::bpfel: 7629 return new BPFTargetInfo(Triple); 7630 7631 case llvm::Triple::msp430: 7632 return new MSP430TargetInfo(Triple); 7633 7634 case llvm::Triple::mips: 7635 switch (os) { 7636 case llvm::Triple::Linux: 7637 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7638 case llvm::Triple::RTEMS: 7639 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7640 case llvm::Triple::FreeBSD: 7641 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7642 case llvm::Triple::NetBSD: 7643 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7644 default: 7645 return new Mips32EBTargetInfo(Triple); 7646 } 7647 7648 case llvm::Triple::mipsel: 7649 switch (os) { 7650 case llvm::Triple::Linux: 7651 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7652 case llvm::Triple::RTEMS: 7653 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7654 case llvm::Triple::FreeBSD: 7655 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7656 case llvm::Triple::NetBSD: 7657 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7658 case llvm::Triple::NaCl: 7659 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7660 default: 7661 return new Mips32ELTargetInfo(Triple); 7662 } 7663 7664 case llvm::Triple::mips64: 7665 switch (os) { 7666 case llvm::Triple::Linux: 7667 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7668 case llvm::Triple::RTEMS: 7669 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7670 case llvm::Triple::FreeBSD: 7671 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7672 case llvm::Triple::NetBSD: 7673 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7674 case llvm::Triple::OpenBSD: 7675 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7676 default: 7677 return new Mips64EBTargetInfo(Triple); 7678 } 7679 7680 case llvm::Triple::mips64el: 7681 switch (os) { 7682 case llvm::Triple::Linux: 7683 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7684 case llvm::Triple::RTEMS: 7685 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7686 case llvm::Triple::FreeBSD: 7687 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7688 case llvm::Triple::NetBSD: 7689 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7690 case llvm::Triple::OpenBSD: 7691 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7692 default: 7693 return new Mips64ELTargetInfo(Triple); 7694 } 7695 7696 case llvm::Triple::le32: 7697 switch (os) { 7698 case llvm::Triple::NaCl: 7699 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7700 default: 7701 return nullptr; 7702 } 7703 7704 case llvm::Triple::le64: 7705 return new Le64TargetInfo(Triple); 7706 7707 case llvm::Triple::ppc: 7708 if (Triple.isOSDarwin()) 7709 return new DarwinPPC32TargetInfo(Triple); 7710 switch (os) { 7711 case llvm::Triple::Linux: 7712 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7713 case llvm::Triple::FreeBSD: 7714 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7715 case llvm::Triple::NetBSD: 7716 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7717 case llvm::Triple::OpenBSD: 7718 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7719 case llvm::Triple::RTEMS: 7720 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7721 default: 7722 return new PPC32TargetInfo(Triple); 7723 } 7724 7725 case llvm::Triple::ppc64: 7726 if (Triple.isOSDarwin()) 7727 return new DarwinPPC64TargetInfo(Triple); 7728 switch (os) { 7729 case llvm::Triple::Linux: 7730 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7731 case llvm::Triple::Lv2: 7732 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7733 case llvm::Triple::FreeBSD: 7734 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7735 case llvm::Triple::NetBSD: 7736 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7737 default: 7738 return new PPC64TargetInfo(Triple); 7739 } 7740 7741 case llvm::Triple::ppc64le: 7742 switch (os) { 7743 case llvm::Triple::Linux: 7744 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7745 case llvm::Triple::NetBSD: 7746 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7747 default: 7748 return new PPC64TargetInfo(Triple); 7749 } 7750 7751 case llvm::Triple::nvptx: 7752 return new NVPTX32TargetInfo(Triple); 7753 case llvm::Triple::nvptx64: 7754 return new NVPTX64TargetInfo(Triple); 7755 7756 case llvm::Triple::amdgcn: 7757 case llvm::Triple::r600: 7758 return new AMDGPUTargetInfo(Triple); 7759 7760 case llvm::Triple::sparc: 7761 switch (os) { 7762 case llvm::Triple::Linux: 7763 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7764 case llvm::Triple::Solaris: 7765 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7766 case llvm::Triple::NetBSD: 7767 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7768 case llvm::Triple::OpenBSD: 7769 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7770 case llvm::Triple::RTEMS: 7771 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7772 default: 7773 return new SparcV8TargetInfo(Triple); 7774 } 7775 7776 // The 'sparcel' architecture copies all the above cases except for Solaris. 7777 case llvm::Triple::sparcel: 7778 switch (os) { 7779 case llvm::Triple::Linux: 7780 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7781 case llvm::Triple::NetBSD: 7782 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7783 case llvm::Triple::OpenBSD: 7784 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7785 case llvm::Triple::RTEMS: 7786 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7787 default: 7788 return new SparcV8elTargetInfo(Triple); 7789 } 7790 7791 case llvm::Triple::sparcv9: 7792 switch (os) { 7793 case llvm::Triple::Linux: 7794 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7795 case llvm::Triple::Solaris: 7796 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7797 case llvm::Triple::NetBSD: 7798 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7799 case llvm::Triple::OpenBSD: 7800 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7801 case llvm::Triple::FreeBSD: 7802 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7803 default: 7804 return new SparcV9TargetInfo(Triple); 7805 } 7806 7807 case llvm::Triple::systemz: 7808 switch (os) { 7809 case llvm::Triple::Linux: 7810 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7811 default: 7812 return new SystemZTargetInfo(Triple); 7813 } 7814 7815 case llvm::Triple::tce: 7816 return new TCETargetInfo(Triple); 7817 7818 case llvm::Triple::x86: 7819 if (Triple.isOSDarwin()) 7820 return new DarwinI386TargetInfo(Triple); 7821 7822 switch (os) { 7823 case llvm::Triple::CloudABI: 7824 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7825 case llvm::Triple::Linux: { 7826 switch (Triple.getEnvironment()) { 7827 default: 7828 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7829 case llvm::Triple::Android: 7830 return new AndroidX86_32TargetInfo(Triple); 7831 } 7832 } 7833 case llvm::Triple::DragonFly: 7834 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7835 case llvm::Triple::NetBSD: 7836 return new NetBSDI386TargetInfo(Triple); 7837 case llvm::Triple::OpenBSD: 7838 return new OpenBSDI386TargetInfo(Triple); 7839 case llvm::Triple::Bitrig: 7840 return new BitrigI386TargetInfo(Triple); 7841 case llvm::Triple::FreeBSD: 7842 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7843 case llvm::Triple::KFreeBSD: 7844 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7845 case llvm::Triple::Minix: 7846 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7847 case llvm::Triple::Solaris: 7848 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7849 case llvm::Triple::Win32: { 7850 switch (Triple.getEnvironment()) { 7851 case llvm::Triple::Cygnus: 7852 return new CygwinX86_32TargetInfo(Triple); 7853 case llvm::Triple::GNU: 7854 return new MinGWX86_32TargetInfo(Triple); 7855 case llvm::Triple::Itanium: 7856 case llvm::Triple::MSVC: 7857 default: // Assume MSVC for unknown environments 7858 return new MicrosoftX86_32TargetInfo(Triple); 7859 } 7860 } 7861 case llvm::Triple::Haiku: 7862 return new HaikuX86_32TargetInfo(Triple); 7863 case llvm::Triple::RTEMS: 7864 return new RTEMSX86_32TargetInfo(Triple); 7865 case llvm::Triple::NaCl: 7866 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7867 case llvm::Triple::ELFIAMCU: 7868 return new MCUX86_32TargetInfo(Triple); 7869 default: 7870 return new X86_32TargetInfo(Triple); 7871 } 7872 7873 case llvm::Triple::x86_64: 7874 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7875 return new DarwinX86_64TargetInfo(Triple); 7876 7877 switch (os) { 7878 case llvm::Triple::CloudABI: 7879 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7880 case llvm::Triple::Linux: { 7881 switch (Triple.getEnvironment()) { 7882 default: 7883 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7884 case llvm::Triple::Android: 7885 return new AndroidX86_64TargetInfo(Triple); 7886 } 7887 } 7888 case llvm::Triple::DragonFly: 7889 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7890 case llvm::Triple::NetBSD: 7891 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7892 case llvm::Triple::OpenBSD: 7893 return new OpenBSDX86_64TargetInfo(Triple); 7894 case llvm::Triple::Bitrig: 7895 return new BitrigX86_64TargetInfo(Triple); 7896 case llvm::Triple::FreeBSD: 7897 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7898 case llvm::Triple::KFreeBSD: 7899 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7900 case llvm::Triple::Solaris: 7901 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7902 case llvm::Triple::Win32: { 7903 switch (Triple.getEnvironment()) { 7904 case llvm::Triple::Cygnus: 7905 return new CygwinX86_64TargetInfo(Triple); 7906 case llvm::Triple::GNU: 7907 return new MinGWX86_64TargetInfo(Triple); 7908 case llvm::Triple::MSVC: 7909 default: // Assume MSVC for unknown environments 7910 return new MicrosoftX86_64TargetInfo(Triple); 7911 } 7912 } 7913 case llvm::Triple::NaCl: 7914 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7915 case llvm::Triple::PS4: 7916 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7917 default: 7918 return new X86_64TargetInfo(Triple); 7919 } 7920 7921 case llvm::Triple::spir: { 7922 if (Triple.getOS() != llvm::Triple::UnknownOS || 7923 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7924 return nullptr; 7925 return new SPIR32TargetInfo(Triple); 7926 } 7927 case llvm::Triple::spir64: { 7928 if (Triple.getOS() != llvm::Triple::UnknownOS || 7929 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7930 return nullptr; 7931 return new SPIR64TargetInfo(Triple); 7932 } 7933 case llvm::Triple::wasm32: 7934 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7935 return nullptr; 7936 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7937 case llvm::Triple::wasm64: 7938 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7939 return nullptr; 7940 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7941 } 7942 } 7943 7944 /// CreateTargetInfo - Return the target info object for the specified target 7945 /// options. 7946 TargetInfo * 7947 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7948 const std::shared_ptr<TargetOptions> &Opts) { 7949 llvm::Triple Triple(Opts->Triple); 7950 7951 // Construct the target 7952 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7953 if (!Target) { 7954 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7955 return nullptr; 7956 } 7957 Target->TargetOpts = Opts; 7958 7959 // Set the target CPU if specified. 7960 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7961 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7962 return nullptr; 7963 } 7964 7965 // Set the target ABI if specified. 7966 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7967 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7968 return nullptr; 7969 } 7970 7971 // Set the fp math unit. 7972 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7973 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7974 return nullptr; 7975 } 7976 7977 // Compute the default target features, we need the target to handle this 7978 // because features may have dependencies on one another. 7979 llvm::StringMap<bool> Features; 7980 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7981 Opts->FeaturesAsWritten)) 7982 return nullptr; 7983 7984 // Add the features to the compile options. 7985 Opts->Features.clear(); 7986 for (const auto &F : Features) 7987 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7988 7989 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7990 return nullptr; 7991 7992 return Target.release(); 7993 } 7994