1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the XCore implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
16 #include "XCore.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameLowering.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 
36 #define GET_REGINFO_TARGET_DESC
37 #include "XCoreGenRegisterInfo.inc"
38 
39 using namespace llvm;
40 
41 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
42   : XCoreGenRegisterInfo(), TII(tii) {
43 }
44 
45 // helper functions
46 static inline bool isImmUs(unsigned val) {
47   return val <= 11;
48 }
49 
50 static inline bool isImmU6(unsigned val) {
51   return val < (1 << 6);
52 }
53 
54 static inline bool isImmU16(unsigned val) {
55   return val < (1 << 16);
56 }
57 
58 static const unsigned XCore_ArgRegs[] = {
59   XCore::R0, XCore::R1, XCore::R2, XCore::R3
60 };
61 
62 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
63 {
64   return XCore_ArgRegs;
65 }
66 
67 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
68 {
69   return array_lengthof(XCore_ArgRegs);
70 }
71 
72 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
73   return MF.getMMI().hasDebugInfo() ||
74     MF.getFunction()->needsUnwindTableEntry();
75 }
76 
77 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
78                                                                          const {
79   static const unsigned CalleeSavedRegs[] = {
80     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
81     XCore::R8, XCore::R9, XCore::R10, XCore::LR,
82     0
83   };
84   return CalleeSavedRegs;
85 }
86 
87 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
88   BitVector Reserved(getNumRegs());
89   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
90 
91   Reserved.set(XCore::CP);
92   Reserved.set(XCore::DP);
93   Reserved.set(XCore::SP);
94   Reserved.set(XCore::LR);
95   if (TFI->hasFP(MF)) {
96     Reserved.set(XCore::R10);
97   }
98   return Reserved;
99 }
100 
101 bool
102 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
103   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
104 
105   // TODO can we estimate stack size?
106   return TFI->hasFP(MF);
107 }
108 
109 bool
110 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
111   return false;
112 }
113 
114 // This function eliminates ADJCALLSTACKDOWN,
115 // ADJCALLSTACKUP pseudo instructions
116 void XCoreRegisterInfo::
117 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
118                               MachineBasicBlock::iterator I) const {
119   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
120 
121   if (!TFI->hasReservedCallFrame(MF)) {
122     // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
123     // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
124     MachineInstr *Old = I;
125     uint64_t Amount = Old->getOperand(0).getImm();
126     if (Amount != 0) {
127       // We need to keep the stack aligned properly.  To do this, we round the
128       // amount of space needed for the outgoing arguments up to the next
129       // alignment boundary.
130       unsigned Align = TFI->getStackAlignment();
131       Amount = (Amount+Align-1)/Align*Align;
132 
133       assert(Amount%4 == 0);
134       Amount /= 4;
135 
136       bool isU6 = isImmU6(Amount);
137       if (!isU6 && !isImmU16(Amount)) {
138         // FIX could emit multiple instructions in this case.
139 #ifndef NDEBUG
140         errs() << "eliminateCallFramePseudoInstr size too big: "
141                << Amount << "\n";
142 #endif
143         llvm_unreachable(0);
144       }
145 
146       MachineInstr *New;
147       if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
148         int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
149         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
150           .addImm(Amount);
151       } else {
152         assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
153         int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
154         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
155           .addImm(Amount);
156       }
157 
158       // Replace the pseudo instruction with a new instruction...
159       MBB.insert(I, New);
160     }
161   }
162 
163   MBB.erase(I);
164 }
165 
166 void
167 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
168                                        int SPAdj, RegScavenger *RS) const {
169   assert(SPAdj == 0 && "Unexpected");
170   MachineInstr &MI = *II;
171   DebugLoc dl = MI.getDebugLoc();
172   unsigned i = 0;
173 
174   while (!MI.getOperand(i).isFI()) {
175     ++i;
176     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
177   }
178 
179   MachineOperand &FrameOp = MI.getOperand(i);
180   int FrameIndex = FrameOp.getIndex();
181 
182   MachineFunction &MF = *MI.getParent()->getParent();
183   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
184   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
185   int StackSize = MF.getFrameInfo()->getStackSize();
186 
187   #ifndef NDEBUG
188   DEBUG(errs() << "\nFunction         : "
189         << MF.getFunction()->getName() << "\n");
190   DEBUG(errs() << "<--------->\n");
191   DEBUG(MI.print(errs()));
192   DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
193   DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
194   DEBUG(errs() << "StackSize          : " << StackSize << "\n");
195   #endif
196 
197   Offset += StackSize;
198 
199   unsigned FrameReg = getFrameRegister(MF);
200 
201   // Special handling of DBG_VALUE instructions.
202   if (MI.isDebugValue()) {
203     MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
204     MI.getOperand(i+1).ChangeToImmediate(Offset);
205     return;
206   }
207 
208   // fold constant into offset.
209   Offset += MI.getOperand(i + 1).getImm();
210   MI.getOperand(i + 1).ChangeToImmediate(0);
211 
212   assert(Offset%4 == 0 && "Misaligned stack offset");
213 
214   DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
215 
216   Offset/=4;
217 
218   bool FP = TFI->hasFP(MF);
219 
220   unsigned Reg = MI.getOperand(0).getReg();
221   bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
222 
223   assert(XCore::GRRegsRegisterClass->contains(Reg) &&
224          "Unexpected register operand");
225 
226   MachineBasicBlock &MBB = *MI.getParent();
227 
228   if (FP) {
229     bool isUs = isImmUs(Offset);
230 
231     if (!isUs) {
232       if (!RS)
233         report_fatal_error("eliminateFrameIndex Frame size too big: " +
234                            Twine(Offset));
235       unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
236                                                  SPAdj);
237       loadConstant(MBB, II, ScratchReg, Offset, dl);
238       switch (MI.getOpcode()) {
239       case XCore::LDWFI:
240         BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
241               .addReg(FrameReg)
242               .addReg(ScratchReg, RegState::Kill);
243         break;
244       case XCore::STWFI:
245         BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
246               .addReg(Reg, getKillRegState(isKill))
247               .addReg(FrameReg)
248               .addReg(ScratchReg, RegState::Kill);
249         break;
250       case XCore::LDAWFI:
251         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
252               .addReg(FrameReg)
253               .addReg(ScratchReg, RegState::Kill);
254         break;
255       default:
256         llvm_unreachable("Unexpected Opcode");
257       }
258     } else {
259       switch (MI.getOpcode()) {
260       case XCore::LDWFI:
261         BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
262               .addReg(FrameReg)
263               .addImm(Offset);
264         break;
265       case XCore::STWFI:
266         BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
267               .addReg(Reg, getKillRegState(isKill))
268               .addReg(FrameReg)
269               .addImm(Offset);
270         break;
271       case XCore::LDAWFI:
272         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
273               .addReg(FrameReg)
274               .addImm(Offset);
275         break;
276       default:
277         llvm_unreachable("Unexpected Opcode");
278       }
279     }
280   } else {
281     bool isU6 = isImmU6(Offset);
282     if (!isU6 && !isImmU16(Offset))
283       report_fatal_error("eliminateFrameIndex Frame size too big: " +
284                          Twine(Offset));
285 
286     switch (MI.getOpcode()) {
287     int NewOpcode;
288     case XCore::LDWFI:
289       NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
290       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
291             .addImm(Offset);
292       break;
293     case XCore::STWFI:
294       NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
295       BuildMI(MBB, II, dl, TII.get(NewOpcode))
296             .addReg(Reg, getKillRegState(isKill))
297             .addImm(Offset);
298       break;
299     case XCore::LDAWFI:
300       NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
301       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
302             .addImm(Offset);
303       break;
304     default:
305       llvm_unreachable("Unexpected Opcode");
306     }
307   }
308   // Erase old instruction.
309   MBB.erase(II);
310 }
311 
312 void XCoreRegisterInfo::
313 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
314             unsigned DstReg, int64_t Value, DebugLoc dl) const {
315   // TODO use mkmsk if possible.
316   if (!isImmU16(Value)) {
317     // TODO use constant pool.
318     report_fatal_error("loadConstant value too big " + Twine(Value));
319   }
320   int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
321   BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
322 }
323 
324 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
325   return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
326 }
327 
328 int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
329   return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
330 }
331 
332 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
333   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
334 
335   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
336 }
337 
338 unsigned XCoreRegisterInfo::getRARegister() const {
339   return XCore::LR;
340 }
341