1//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the XCore instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14// Uses of CP, DP are not currently reflected in the patterns, since 15// having a physical register as an operand prevents loop hoisting and 16// since the value of these registers never changes during the life of the 17// function. 18 19//===----------------------------------------------------------------------===// 20// Instruction format superclass. 21//===----------------------------------------------------------------------===// 22 23include "XCoreInstrFormats.td" 24 25//===----------------------------------------------------------------------===// 26// XCore specific DAG Nodes. 27// 28 29// Call 30def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33 SDNPVariadic]>; 34 35def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>; 37 38def SDT_XCoreEhRet : SDTypeProfile<0, 2, 39 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 40def XCoreEhRet : SDNode<"XCoreISD::EH_RETURN", SDT_XCoreEhRet, 41 [SDNPHasChain, SDNPOptInGlue]>; 42 43def SDT_XCoreBR_JT : SDTypeProfile<0, 2, 44 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 45 46def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 47 [SDNPHasChain]>; 48 49def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 50 [SDNPHasChain]>; 51 52def SDT_XCoreAddress : SDTypeProfile<1, 1, 53 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 54 55def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 56 []>; 57 58def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 59 []>; 60 61def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 62 []>; 63 64def frametoargsoffset : SDNode<"XCoreISD::FRAME_TO_ARGS_OFFSET", SDTIntLeaf, 65 []>; 66 67def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 68def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 69 [SDNPHasChain, SDNPMayStore]>; 70 71def SDT_XCoreLdwsp : SDTypeProfile<1, 1, [SDTCisInt<1>]>; 72def XCoreLdwsp : SDNode<"XCoreISD::LDWSP", SDT_XCoreLdwsp, 73 [SDNPHasChain, SDNPMayLoad]>; 74 75// These are target-independent nodes, but have target-specific formats. 76def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 77 SDTCisVT<1, i32> ]>; 78def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 79 SDTCisVT<1, i32> ]>; 80 81def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 82 [SDNPHasChain, SDNPOutGlue]>; 83def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 84 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 85 86def SDT_XCoreMEMBARRIER : SDTypeProfile<0, 0, []>; 87 88def XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER, 89 [SDNPHasChain]>; 90 91//===----------------------------------------------------------------------===// 92// Instruction Pattern Stuff 93//===----------------------------------------------------------------------===// 94 95def div4_xform : SDNodeXForm<imm, [{ 96 // Transformation function: imm/4 97 assert(N->getZExtValue() % 4 == 0); 98 return getI32Imm(N->getZExtValue()/4, SDLoc(N)); 99}]>; 100 101def msksize_xform : SDNodeXForm<imm, [{ 102 // Transformation function: get the size of a mask 103 assert(isMask_32(N->getZExtValue())); 104 // look for the first non-zero bit 105 return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()), 106 SDLoc(N)); 107}]>; 108 109def neg_xform : SDNodeXForm<imm, [{ 110 // Transformation function: -imm 111 uint32_t value = N->getZExtValue(); 112 return getI32Imm(-value, SDLoc(N)); 113}]>; 114 115def bpwsub_xform : SDNodeXForm<imm, [{ 116 // Transformation function: 32-imm 117 uint32_t value = N->getZExtValue(); 118 return getI32Imm(32 - value, SDLoc(N)); 119}]>; 120 121def div4neg_xform : SDNodeXForm<imm, [{ 122 // Transformation function: -imm/4 123 uint32_t value = N->getZExtValue(); 124 assert(-value % 4 == 0); 125 return getI32Imm(-value/4, SDLoc(N)); 126}]>; 127 128def immUs4Neg : PatLeaf<(imm), [{ 129 uint32_t value = (uint32_t)N->getZExtValue(); 130 return (-value)%4 == 0 && (-value)/4 <= 11; 131}]>; 132 133def immUs4 : PatLeaf<(imm), [{ 134 uint32_t value = (uint32_t)N->getZExtValue(); 135 return value%4 == 0 && value/4 <= 11; 136}]>; 137 138def immUsNeg : PatLeaf<(imm), [{ 139 return -((uint32_t)N->getZExtValue()) <= 11; 140}]>; 141 142def immUs : PatLeaf<(imm), [{ 143 return (uint32_t)N->getZExtValue() <= 11; 144}]>; 145 146def immU6 : PatLeaf<(imm), [{ 147 return (uint32_t)N->getZExtValue() < (1 << 6); 148}]>; 149 150def immU16 : PatLeaf<(imm), [{ 151 return (uint32_t)N->getZExtValue() < (1 << 16); 152}]>; 153 154def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 155 156def immBitp : PatLeaf<(imm), [{ 157 uint32_t value = (uint32_t)N->getZExtValue(); 158 return (value >= 1 && value <= 8) 159 || value == 16 160 || value == 24 161 || value == 32; 162}]>; 163 164def immBpwSubBitp : PatLeaf<(imm), [{ 165 uint32_t value = (uint32_t)N->getZExtValue(); 166 return (value >= 24 && value <= 31) 167 || value == 16 168 || value == 8 169 || value == 0; 170}]>; 171 172def lda16f : PatFrag<(ops node:$addr, node:$offset), 173 (add node:$addr, (shl node:$offset, 1))>; 174def lda16b : PatFrag<(ops node:$addr, node:$offset), 175 (sub node:$addr, (shl node:$offset, 1))>; 176def ldawf : PatFrag<(ops node:$addr, node:$offset), 177 (add node:$addr, (shl node:$offset, 2))>; 178def ldawb : PatFrag<(ops node:$addr, node:$offset), 179 (sub node:$addr, (shl node:$offset, 2))>; 180 181// Instruction operand types 182def pcrel_imm : Operand<i32>; 183def pcrel_imm_neg : Operand<i32> { 184 let DecoderMethod = "DecodeNegImmOperand"; 185} 186def brtarget : Operand<OtherVT>; 187def brtarget_neg : Operand<OtherVT> { 188 let DecoderMethod = "DecodeNegImmOperand"; 189} 190 191// Addressing modes 192def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 193 194// Address operands 195def MEMii : Operand<i32> { 196 let MIOperandInfo = (ops i32imm, i32imm); 197} 198 199// Jump tables. 200def InlineJT : Operand<i32> { 201 let PrintMethod = "printInlineJT"; 202} 203 204def InlineJT32 : Operand<i32> { 205 let PrintMethod = "printInlineJT32"; 206} 207 208//===----------------------------------------------------------------------===// 209// Instruction Class Templates 210//===----------------------------------------------------------------------===// 211 212// Three operand short 213 214multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 215 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 216 !strconcat(OpcStr, " $dst, $b, $c"), 217 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 218 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 219 !strconcat(OpcStr, " $dst, $b, $c"), 220 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 221} 222 223multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 224 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 225 !strconcat(OpcStr, " $dst, $b, $c"), []>; 226 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 227 !strconcat(OpcStr, " $dst, $b, $c"), []>; 228} 229 230multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 231 SDNode OpNode> { 232 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 233 !strconcat(OpcStr, " $dst, $b, $c"), 234 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 235 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 236 !strconcat(OpcStr, " $dst, $b, $c"), 237 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 238} 239 240class F3R<bits<5> opc, string OpcStr, SDNode OpNode> : 241 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 242 !strconcat(OpcStr, " $dst, $b, $c"), 243 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 244 245class F3R_np<bits<5> opc, string OpcStr> : 246 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 247 !strconcat(OpcStr, " $dst, $b, $c"), []>; 248// Three operand long 249 250/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 251multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 252 SDNode OpNode> { 253 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 254 !strconcat(OpcStr, " $dst, $b, $c"), 255 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 256 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 257 !strconcat(OpcStr, " $dst, $b, $c"), 258 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 259} 260 261/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 262multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 263 SDNode OpNode> { 264 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 265 !strconcat(OpcStr, " $dst, $b, $c"), 266 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 267 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 268 !strconcat(OpcStr, " $dst, $b, $c"), 269 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 270} 271 272class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> : 273 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 274 !strconcat(OpcStr, " $dst, $b, $c"), 275 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 276 277// Register - U6 278// Operand register - U6 279multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> { 280 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 281 !strconcat(OpcStr, " $a, $b"), []>; 282 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 283 !strconcat(OpcStr, " $a, $b"), []>; 284} 285 286multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { 287 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 288 !strconcat(OpcStr, " $a, $b"), []>; 289 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 290 !strconcat(OpcStr, " $a, $b"), []>; 291} 292 293 294// U6 295multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> { 296 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 297 [(OpNode immU6:$a)]>; 298 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 299 [(OpNode immU16:$a)]>; 300} 301 302multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> { 303 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 304 [(Int immU6:$a)]>; 305 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 306 [(Int immU16:$a)]>; 307} 308 309multiclass FU6_LU6_np<bits<10> opc, string OpcStr> { 310 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 311 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 312} 313 314// Two operand short 315 316class F2R_np<bits<6> opc, string OpcStr> : 317 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), 318 !strconcat(OpcStr, " $dst, $b"), []>; 319 320// Two operand long 321 322//===----------------------------------------------------------------------===// 323// Pseudo Instructions 324//===----------------------------------------------------------------------===// 325 326let Defs = [SP], Uses = [SP] in { 327def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt, i32imm:$amt2), 328 "# ADJCALLSTACKDOWN $amt, $amt2", 329 [(callseq_start timm:$amt, timm:$amt2)]>; 330def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 331 "# ADJCALLSTACKUP $amt1", 332 [(callseq_end timm:$amt1, timm:$amt2)]>; 333} 334 335let isReMaterializable = 1 in 336def FRAME_TO_ARGS_OFFSET : PseudoInstXCore<(outs GRRegs:$dst), (ins), 337 "# FRAME_TO_ARGS_OFFSET $dst", 338 [(set GRRegs:$dst, (frametoargsoffset))]>; 339 340let isReturn = 1, isTerminator = 1, isBarrier = 1 in 341def EH_RETURN : PseudoInstXCore<(outs), (ins GRRegs:$s, GRRegs:$handler), 342 "# EH_RETURN $s, $handler", 343 [(XCoreEhRet GRRegs:$s, GRRegs:$handler)]>; 344 345def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 346 "# LDWFI $dst, $addr", 347 [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 348 349def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 350 "# LDAWFI $dst, $addr", 351 [(set GRRegs:$dst, ADDRspii:$addr)]>; 352 353def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 354 "# STWFI $src, $addr", 355 [(store GRRegs:$src, ADDRspii:$addr)]>; 356 357// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 358// instruction selection into a branch sequence. 359let usesCustomInserter = 1 in { 360 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 361 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 362 "# SELECT_CC PSEUDO!", 363 [(set GRRegs:$dst, 364 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 365} 366 367let hasSideEffects = 1 in 368def Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER", 369 [(XCoreMemBarrier)]>; 370 371//===----------------------------------------------------------------------===// 372// Instructions 373//===----------------------------------------------------------------------===// 374 375// Three operand short 376defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; 377defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; 378let hasSideEffects = 0 in { 379defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; 380def LSS_3r : F3R_np<0b11000, "lss">; 381def LSU_3r : F3R_np<0b11001, "lsu">; 382} 383def AND_3r : F3R<0b00111, "and", and>; 384def OR_3r : F3R<0b01000, "or", or>; 385 386let mayLoad=1 in { 387def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst), 388 (ins GRRegs:$addr, GRRegs:$offset), 389 "ldw $dst, $addr[$offset]", []>; 390 391def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst), 392 (ins GRRegs:$addr, i32imm:$offset), 393 "ldw $dst, $addr[$offset]", []>; 394 395def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst), 396 (ins GRRegs:$addr, GRRegs:$offset), 397 "ld16s $dst, $addr[$offset]", []>; 398 399def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), 400 (ins GRRegs:$addr, GRRegs:$offset), 401 "ld8u $dst, $addr[$offset]", []>; 402} 403 404let mayStore=1 in { 405def STW_l3r : _FL3R<0b000001100, (outs), 406 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 407 "stw $val, $addr[$offset]", []>; 408 409def STW_2rus : _F2RUS<0b00000, (outs), 410 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 411 "stw $val, $addr[$offset]", []>; 412} 413 414defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; 415defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; 416 417// The first operand is treated as an immediate since it refers to a register 418// number in another thread. 419def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), 420 "set t[$c]:r$a, $b", []>; 421 422// Three operand long 423def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), 424 (ins GRRegs:$addr, GRRegs:$offset), 425 "ldaw $dst, $addr[$offset]", 426 [(set GRRegs:$dst, 427 (ldawf GRRegs:$addr, GRRegs:$offset))]>; 428 429let hasSideEffects = 0 in 430def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), 431 (ins GRRegs:$addr, i32imm:$offset), 432 "ldaw $dst, $addr[$offset]", []>; 433 434def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), 435 (ins GRRegs:$addr, GRRegs:$offset), 436 "ldaw $dst, $addr[-$offset]", 437 [(set GRRegs:$dst, 438 (ldawb GRRegs:$addr, GRRegs:$offset))]>; 439 440let hasSideEffects = 0 in 441def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), 442 (ins GRRegs:$addr, i32imm:$offset), 443 "ldaw $dst, $addr[-$offset]", []>; 444 445def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst), 446 (ins GRRegs:$addr, GRRegs:$offset), 447 "lda16 $dst, $addr[$offset]", 448 [(set GRRegs:$dst, 449 (lda16f GRRegs:$addr, GRRegs:$offset))]>; 450 451def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst), 452 (ins GRRegs:$addr, GRRegs:$offset), 453 "lda16 $dst, $addr[-$offset]", 454 [(set GRRegs:$dst, 455 (lda16b GRRegs:$addr, GRRegs:$offset))]>; 456 457def MUL_l3r : FL3R<0b001111100, "mul", mul>; 458// Instructions which may trap are marked as side effecting. 459let hasSideEffects = 1 in { 460def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>; 461def DIVU_l3r : FL3R<0b010011100, "divu", udiv>; 462def REMS_l3r : FL3R<0b110001100, "rems", srem>; 463def REMU_l3r : FL3R<0b110011100, "remu", urem>; 464} 465def XOR_l3r : FL3R<0b000011100, "xor", xor>; 466defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>; 467 468let Constraints = "$src1 = $dst" in 469def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), 470 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 471 "crc32 $dst, $src2, $src3", 472 [(set GRRegs:$dst, 473 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 474 GRRegs:$src3))]>; 475 476let mayStore=1 in { 477def ST16_l3r : _FL3R<0b100001100, (outs), 478 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 479 "st16 $val, $addr[$offset]", []>; 480 481def ST8_l3r : _FL3R<0b100011100, (outs), 482 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 483 "st8 $val, $addr[$offset]", []>; 484} 485 486def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), 487 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", 488 []>; 489 490def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), 491 (ins GRRegs:$a, GRRegs:$b, i32imm:$c), 492 "outpw res[$b], $a, $c", []>; 493 494// Four operand long 495let Constraints = "$e = $a,$f = $b" in { 496def MACCU_l4r : _FL4RSrcDstSrcDst< 497 0b000001, (outs GRRegs:$a, GRRegs:$b), 498 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; 499 500def MACCS_l4r : _FL4RSrcDstSrcDst< 501 0b000010, (outs GRRegs:$a, GRRegs:$b), 502 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; 503} 504 505let Constraints = "$e = $b" in 506def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), 507 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), 508 "crc8 $b, $a, $c, $d", []>; 509 510// Five operand long 511 512def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2), 513 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 514 "ladd $dst2, $dst1, $src1, $src2, $src3", 515 []>; 516 517def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2), 518 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 519 "lsub $dst2, $dst1, $src1, $src2, $src3", []>; 520 521def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2), 522 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 523 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>; 524 525// Six operand long 526 527def LMUL_l6r : _FL6R< 528 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2), 529 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 530 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>; 531 532// Register - U6 533 534//let Uses = [DP] in ... 535let hasSideEffects = 0, isReMaterializable = 1 in 536def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 537 "ldaw $a, dp[$b]", []>; 538 539let isReMaterializable = 1 in 540def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 541 "ldaw $a, dp[$b]", 542 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 543 544let mayLoad=1 in 545def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 546 "ldw $a, dp[$b]", []>; 547 548def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 549 "ldw $a, dp[$b]", 550 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>; 551 552let mayStore=1 in 553def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 554 "stw $a, dp[$b]", []>; 555 556def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 557 "stw $a, dp[$b]", 558 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 559 560//let Uses = [CP] in .. 561let mayLoad = 1, isReMaterializable = 1, hasSideEffects = 0 in { 562def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), 563 "ldw $a, cp[$b]", []>; 564def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), 565 "ldw $a, cp[$b]", 566 [(set RRegs:$a, (load (cprelwrapper tglobaladdr:$b)))]>; 567} 568 569let Uses = [SP] in { 570let mayStore=1 in { 571def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 572 "stw $a, sp[$b]", 573 [(XCoreStwsp RRegs:$a, immU6:$b)]>; 574 575def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 576 "stw $a, sp[$b]", 577 [(XCoreStwsp RRegs:$a, immU16:$b)]>; 578} 579 580let mayLoad=1 in { 581def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 582 "ldw $a, sp[$b]", 583 [(set RRegs:$a, (XCoreLdwsp immU6:$b))]>; 584 585def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 586 "ldw $a, sp[$b]", 587 [(set RRegs:$a, (XCoreLdwsp immU16:$b))]>; 588} 589 590let hasSideEffects = 0 in { 591def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 592 "ldaw $a, sp[$b]", []>; 593 594def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 595 "ldaw $a, sp[$b]", []>; 596} 597} 598 599let isReMaterializable = 1 in { 600def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 601 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>; 602 603def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 604 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>; 605} 606 607def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 608 "setc res[$a], $b", 609 [(int_xcore_setc GRRegs:$a, immU6:$b)]>; 610 611def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 612 "setc res[$a], $b", 613 [(int_xcore_setc GRRegs:$a, immU16:$b)]>; 614 615// Operand register - U6 616let isBranch = 1, isTerminator = 1 in { 617defm BRFT: FRU6_LRU6_branch<0b011100, "bt">; 618defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; 619defm BRFF: FRU6_LRU6_branch<0b011110, "bf">; 620defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; 621} 622 623// U6 624let Defs = [SP], Uses = [SP] in { 625let hasSideEffects = 0 in 626defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; 627 628let mayStore = 1 in 629defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; 630 631let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 632defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; 633} 634} 635 636let hasSideEffects = 0 in 637defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; 638 639let Uses = [R11], isCall=1 in 640defm BLAT : FU6_LU6_np<0b0111001101, "blat">; 641 642let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 643def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 644 645def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 646 647def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 648 649def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 650} 651 652//let Uses = [CP] in ... 653let Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in 654def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 655 []>; 656 657let Defs = [R11], isReMaterializable = 1 in 658def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 659 [(set R11, (cprelwrapper tglobaladdr:$a))]>; 660 661let Defs = [R11] in 662defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">; 663 664defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; 665 666defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; 667 668// setsr may cause a branch if it is used to enable events. clrsr may 669// branch if it is executed while events are enabled. 670let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 671 isCodeGenOnly = 1 in { 672defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; 673defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; 674} 675 676defm KCALL : FU6_LU6_np<0b0111001111, "kcall">; 677 678let Uses = [SP], Defs = [SP], mayStore = 1 in 679defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">; 680 681let Uses = [SP], Defs = [SP], mayLoad = 1 in 682defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; 683 684// U10 685 686let Defs = [R11], isReMaterializable = 1 in { 687let hasSideEffects = 0 in 688def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>; 689 690def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 691 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 692 693let hasSideEffects = 0 in 694def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a", 695 []>; 696 697let hasSideEffects = 0 in 698def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a), 699 "ldap r11, $a", 700 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 701 702let isCodeGenOnly = 1 in 703def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 704 [(set R11, (pcrelwrapper tblockaddress:$a))]>; 705} 706 707let isCall=1, 708// All calls clobber the link register and the non-callee-saved registers: 709Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 710def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 711 712def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 713 714def BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 715 []>; 716 717def BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 718 [(XCoreBranchLink tglobaladdr:$a)]>; 719 720def BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 721 722def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 723} 724 725let Defs = [R11], mayLoad = 1, isReMaterializable = 1, 726 hasSideEffects = 0 in { 727def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; 728 729def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", 730 []>; 731} 732 733// Two operand short 734def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b), 735 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; 736 737def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b), 738 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 739 740let Constraints = "$src1 = $dst" in { 741def SEXT_rus : 742 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 743 "sext $dst, $src2", 744 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 745 immBitp:$src2))]>; 746 747def SEXT_2r : 748 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 749 "sext $dst, $src2", 750 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; 751 752def ZEXT_rus : 753 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 754 "zext $dst, $src2", 755 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 756 immBitp:$src2))]>; 757 758def ZEXT_2r : 759 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 760 "zext $dst, $src2", 761 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; 762 763def ANDNOT_2r : 764 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 765 "andnot $dst, $src2", 766 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 767} 768 769let isReMaterializable = 1, hasSideEffects = 0 in 770def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), 771 "mkmsk $dst, $size", []>; 772 773def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size), 774 "mkmsk $dst, $size", 775 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; 776 777def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type), 778 "getr $dst, $type", 779 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 780 781def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r), 782 "getts $dst, res[$r]", 783 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 784 785def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val), 786 "setpt res[$r], $val", 787 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 788 789def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val), 790 "outct res[$r], $val", 791 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 792 793def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val), 794 "outct res[$r], $val", 795 [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 796 797def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val), 798 "outt res[$r], $val", 799 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 800 801def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val), 802 "out res[$r], $val", 803 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 804 805let Constraints = "$src = $dst" in 806def OUTSHR_2r : 807 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 808 "outshr res[$r], $src", 809 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; 810 811def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r), 812 "inct $dst, res[$r]", 813 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 814 815def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r), 816 "int $dst, res[$r]", 817 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 818 819def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r), 820 "in $dst, res[$r]", 821 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 822 823let Constraints = "$src = $dst" in 824def INSHR_2r : 825 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 826 "inshr $dst, res[$r]", 827 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; 828 829def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val), 830 "chkct res[$r], $val", 831 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 832 833def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val), 834 "chkct res[$r], $val", 835 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 836 837def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src), 838 "testct $dst, res[$src]", 839 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 840 841def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src), 842 "testwct $dst, res[$src]", 843 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 844 845def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), 846 "setd res[$r], $val", 847 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 848 849def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 850 "setpsc res[$src1], $src2", 851 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 852 853def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), 854 "getst $dst, res[$r]", 855 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 856 857def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t), 858 "init t[$t]:sp, $src", 859 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 860 861def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t), 862 "init t[$t]:pc, $src", 863 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 864 865def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t), 866 "init t[$t]:cp, $src", 867 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 868 869def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t), 870 "init t[$t]:dp, $src", 871 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 872 873def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src), 874 "peek $dst, res[$src]", 875 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 876 877def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src), 878 "endin $dst, res[$src]", 879 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 880 881def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b), 882 "eef $a, res[$b]", []>; 883 884def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b), 885 "eet $a, res[$b]", []>; 886 887def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b), 888 "tsetmr r$a, $b", []>; 889 890// Two operand long 891def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src), 892 "bitrev $dst, $src", 893 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 894 895def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), 896 "byterev $dst, $src", 897 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 898 899def CLZ_l2r : _FL2R<0b0000111000, (outs GRRegs:$dst), (ins GRRegs:$src), 900 "clz $dst, $src", 901 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 902 903def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src), 904 "getd $dst, res[$src]", []>; 905 906def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src), 907 "getn $dst, res[$src]", []>; 908 909def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val), 910 "setc res[$r], $val", 911 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 912 913def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val), 914 "settw res[$r], $val", 915 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 916 917def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src), 918 "get $dst, ps[$src]", 919 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 920 921def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 922 "set ps[$src1], $src2", 923 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 924 925def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t), 926 "init t[$t]:lr, $src", 927 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 928 929def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2), 930 "setclk res[$src1], $src2", 931 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 932 933def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 934 "setn res[$src1], $src2", []>; 935 936def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 937 "setrdy res[$src1], $src2", 938 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 939 940def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src), 941 "testlcl $dst, res[$src]", []>; 942 943// One operand short 944def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a), 945 "msync res[$a]", 946 [(int_xcore_msync GRRegs:$a)]>; 947def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a), 948 "mjoin res[$a]", 949 [(int_xcore_mjoin GRRegs:$a)]>; 950 951let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 952def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a), 953 "bau $a", 954 [(brind GRRegs:$a)]>; 955 956let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 957def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 958 "bru $i\n$t", 959 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 960 961let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 962def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 963 "bru $i\n$t", 964 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 965 966let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 967def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; 968 969let Defs=[SP], hasSideEffects=0 in 970def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; 971 972let hasSideEffects=0 in 973def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; 974 975let hasSideEffects=0 in 976def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; 977 978let hasCtrlDep = 1 in 979def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), 980 "ecallt $a", 981 []>; 982 983let hasCtrlDep = 1 in 984def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), 985 "ecallf $a", 986 []>; 987 988let isCall=1, 989// All calls clobber the link register and the non-callee-saved registers: 990Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 991def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), 992 "bla $a", 993 [(XCoreBranchLink GRRegs:$a)]>; 994} 995 996def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a), 997 "syncr res[$a]", 998 [(int_xcore_syncr GRRegs:$a)]>; 999 1000def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a), 1001 "freer res[$a]", 1002 [(int_xcore_freer GRRegs:$a)]>; 1003 1004let Uses=[R11] in { 1005def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a), 1006 "setv res[$a], r11", 1007 [(int_xcore_setv GRRegs:$a, R11)]>; 1008 1009def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a), 1010 "setev res[$a], r11", 1011 [(int_xcore_setev GRRegs:$a, R11)]>; 1012} 1013 1014def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>; 1015 1016def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", 1017 [(int_xcore_edu GRRegs:$a)]>; 1018 1019def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a), 1020 "eeu res[$a]", 1021 [(int_xcore_eeu GRRegs:$a)]>; 1022 1023def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>; 1024 1025def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>; 1026 1027def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>; 1028 1029def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>; 1030 1031def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", 1032 [(int_xcore_clrpt GRRegs:$a)]>; 1033 1034// Zero operand short 1035 1036def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>; 1037 1038def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>; 1039 1040let Defs = [SP], Uses = [SP] in 1041def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>; 1042 1043let Defs = [SP] in 1044def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>; 1045 1046def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>; 1047 1048def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>; 1049 1050let Defs = [R11] in { 1051def GETID_0R : _F0R<0b0001001110, (outs), (ins), 1052 "get r11, id", 1053 [(set R11, (int_xcore_getid))]>; 1054 1055def GETED_0R : _F0R<0b0000111110, (outs), (ins), 1056 "get r11, ed", 1057 [(set R11, (int_xcore_geted))]>; 1058 1059def GETET_0R : _F0R<0b0000111111, (outs), (ins), 1060 "get r11, et", 1061 [(set R11, (int_xcore_getet))]>; 1062 1063def GETKEP_0R : _F0R<0b0001001111, (outs), (ins), 1064 "get r11, kep", []>; 1065 1066def GETKSP_0R : _F0R<0b0001011100, (outs), (ins), 1067 "get r11, ksp", []>; 1068} 1069 1070let Defs = [SP] in 1071def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>; 1072 1073let Uses = [SP], mayLoad = 1 in { 1074def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>; 1075 1076def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>; 1077 1078def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>; 1079 1080def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>; 1081} 1082 1083let Uses=[R11] in 1084def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>; 1085 1086def SSYNC_0r : _F0R<0b0000001110, (outs), (ins), 1087 "ssync", 1088 [(int_xcore_ssync)]>; 1089 1090let Uses = [SP], mayStore = 1 in { 1091def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>; 1092 1093def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>; 1094 1095def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>; 1096 1097def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>; 1098} 1099 1100let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1101 hasSideEffects = 1 in 1102def WAITEU_0R : _F0R<0b0000001100, (outs), (ins), 1103 "waiteu", 1104 [(brind (int_xcore_waitevent))]>; 1105 1106//===----------------------------------------------------------------------===// 1107// Non-Instruction Patterns 1108//===----------------------------------------------------------------------===// 1109 1110def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>; 1111 1112/// sext_inreg 1113def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1114def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1115def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1116 1117/// loads 1118def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1119 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1120def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1121 1122def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1123 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1124def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1125 1126def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1127 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1128def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1129 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1130def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1131 1132/// anyext 1133def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1134 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1135def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1136def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1137 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1138def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1139 1140/// stores 1141def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1142 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1143def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1144 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1145 1146def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1147 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1148def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1149 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1150 1151def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1152 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1153def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1154 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1155def : Pat<(store GRRegs:$val, GRRegs:$addr), 1156 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1157 1158/// cttz 1159def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1160 1161/// trap 1162def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1163 1164/// 1165/// branch patterns 1166/// 1167 1168// unconditional branch 1169def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1170 1171// direct match equal/notequal zero brcond 1172def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1173 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1174def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1175 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1176 1177def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1178 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1179def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1180 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1181def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1182 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1183def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1184 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1185def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1186 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1187def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1188 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1189 1190// generic brcond pattern 1191def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1192 1193 1194/// 1195/// Select patterns 1196/// 1197 1198// direct match equal/notequal zero select 1199def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1200 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1201 1202def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1203 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1204 1205def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1206 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1207def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1208 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1209def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1210 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1211def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1212 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1213def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1214 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1215def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1216 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1217 1218/// 1219/// setcc patterns, only matched when none of the above brcond 1220/// patterns match 1221/// 1222 1223// setcc 2 register operands 1224def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1225 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1226def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1227 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1228 1229def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1230 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1231def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1232 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1233 1234def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1235 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1236def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1237 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1238 1239def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1240 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1241def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1242 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1243 1244def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1245 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1246 1247def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1248 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1249 1250// setcc reg/imm operands 1251def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1252 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1253def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1254 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1255 1256// misc 1257def : Pat<(add GRRegs:$addr, immUs4:$offset), 1258 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1259 1260def : Pat<(sub GRRegs:$addr, immUs4:$offset), 1261 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1262 1263def : Pat<(and GRRegs:$val, immMskBitp:$mask), 1264 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1265 1266// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1267def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1268 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1269 1270def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1271 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1272 1273/// 1274/// Some peepholes 1275/// 1276 1277def : Pat<(mul GRRegs:$src, 3), 1278 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1279 1280def : Pat<(mul GRRegs:$src, 5), 1281 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1282 1283def : Pat<(mul GRRegs:$src, -3), 1284 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1285 1286// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1287def : Pat<(sra GRRegs:$src, 31), 1288 (ASHR_l2rus GRRegs:$src, 32)>; 1289 1290def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1291 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1292 1293// setge X, 0 is canonicalized to setgt X, -1 1294def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1295 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1296 1297def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1298 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1299 1300def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1301 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1302 1303def : Pat<(setgt GRRegs:$lhs, -1), 1304 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1305 1306def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1307 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1308 1309def : Pat<(load (cprelwrapper tconstpool:$b)), 1310 (LDWCP_lru6 tconstpool:$b)>; 1311 1312def : Pat<(cprelwrapper tconstpool:$b), 1313 (LDAWCP_lu6 tconstpool:$b)>; 1314