1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 17 #include "X86.h" 18 #include "X86TargetMachine.h" 19 #include "llvm/Analysis/TargetTransformInfo.h" 20 #include "llvm/IR/IntrinsicInst.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Target/CostTable.h" 23 #include "llvm/Target/TargetLowering.h" 24 using namespace llvm; 25 26 #define DEBUG_TYPE "x86tti" 27 28 // Declare the pass initialization routine locally as target-specific passes 29 // don't have a target-wide initialization entry point, and so we rely on the 30 // pass constructor initialization. 31 namespace llvm { 32 void initializeX86TTIPass(PassRegistry &); 33 } 34 35 namespace { 36 37 class X86TTI final : public ImmutablePass, public TargetTransformInfo { 38 const X86Subtarget *ST; 39 const X86TargetLowering *TLI; 40 41 /// Estimate the overhead of scalarizing an instruction. Insert and Extract 42 /// are set if the result needs to be inserted and/or extracted from vectors. 43 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const; 44 45 public: 46 X86TTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) { 47 llvm_unreachable("This pass cannot be directly constructed"); 48 } 49 50 X86TTI(const X86TargetMachine *TM) 51 : ImmutablePass(ID), ST(TM->getSubtargetImpl()), 52 TLI(TM->getSubtargetImpl()->getTargetLowering()) { 53 initializeX86TTIPass(*PassRegistry::getPassRegistry()); 54 } 55 56 void initializePass() override { 57 pushTTIStack(this); 58 } 59 60 void getAnalysisUsage(AnalysisUsage &AU) const override { 61 TargetTransformInfo::getAnalysisUsage(AU); 62 } 63 64 /// Pass identification. 65 static char ID; 66 67 /// Provide necessary pointer adjustments for the two base classes. 68 void *getAdjustedAnalysisPointer(const void *ID) override { 69 if (ID == &TargetTransformInfo::ID) 70 return (TargetTransformInfo*)this; 71 return this; 72 } 73 74 /// \name Scalar TTI Implementations 75 /// @{ 76 PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override; 77 78 /// @} 79 80 /// \name Vector TTI Implementations 81 /// @{ 82 83 unsigned getNumberOfRegisters(bool Vector) const override; 84 unsigned getRegisterBitWidth(bool Vector) const override; 85 unsigned getMaxInterleaveFactor() const override; 86 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind, 87 OperandValueKind, OperandValueProperties, 88 OperandValueProperties) const override; 89 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, 90 int Index, Type *SubTp) const override; 91 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, 92 Type *Src) const override; 93 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 94 Type *CondTy) const override; 95 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, 96 unsigned Index) const override; 97 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 98 unsigned AddressSpace) const override; 99 100 unsigned getAddressComputationCost(Type *PtrTy, 101 bool IsComplex) const override; 102 103 unsigned getReductionCost(unsigned Opcode, Type *Ty, 104 bool IsPairwiseForm) const override; 105 106 unsigned getIntImmCost(int64_t) const; 107 108 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override; 109 110 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 111 Type *Ty) const override; 112 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 113 Type *Ty) const override; 114 bool isLegalMaskedLoad (Type *DataType, int Consecutive) const override; 115 bool isLegalMaskedStore(Type *DataType, int Consecutive) const override; 116 117 /// @} 118 }; 119 120 } // end anonymous namespace 121 122 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti", 123 "X86 Target Transform Info", true, true, false) 124 char X86TTI::ID = 0; 125 126 ImmutablePass * 127 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) { 128 return new X86TTI(TM); 129 } 130 131 132 //===----------------------------------------------------------------------===// 133 // 134 // X86 cost model. 135 // 136 //===----------------------------------------------------------------------===// 137 138 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const { 139 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 140 // TODO: Currently the __builtin_popcount() implementation using SSE3 141 // instructions is inefficient. Once the problem is fixed, we should 142 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 143 return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software; 144 } 145 146 unsigned X86TTI::getNumberOfRegisters(bool Vector) const { 147 if (Vector && !ST->hasSSE1()) 148 return 0; 149 150 if (ST->is64Bit()) { 151 if (Vector && ST->hasAVX512()) 152 return 32; 153 return 16; 154 } 155 return 8; 156 } 157 158 unsigned X86TTI::getRegisterBitWidth(bool Vector) const { 159 if (Vector) { 160 if (ST->hasAVX512()) return 512; 161 if (ST->hasAVX()) return 256; 162 if (ST->hasSSE1()) return 128; 163 return 0; 164 } 165 166 if (ST->is64Bit()) 167 return 64; 168 return 32; 169 170 } 171 172 unsigned X86TTI::getMaxInterleaveFactor() const { 173 if (ST->isAtom()) 174 return 1; 175 176 // Sandybridge and Haswell have multiple execution ports and pipelined 177 // vector units. 178 if (ST->hasAVX()) 179 return 4; 180 181 return 2; 182 } 183 184 unsigned X86TTI::getArithmeticInstrCost( 185 unsigned Opcode, Type *Ty, OperandValueKind Op1Info, 186 OperandValueKind Op2Info, OperandValueProperties Opd1PropInfo, 187 OperandValueProperties Opd2PropInfo) const { 188 // Legalize the type. 189 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty); 190 191 int ISD = TLI->InstructionOpcodeToISD(Opcode); 192 assert(ISD && "Invalid opcode"); 193 194 if (ISD == ISD::SDIV && 195 Op2Info == TargetTransformInfo::OK_UniformConstantValue && 196 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 197 // On X86, vector signed division by constants power-of-two are 198 // normally expanded to the sequence SRA + SRL + ADD + SRA. 199 // The OperandValue properties many not be same as that of previous 200 // operation;conservatively assume OP_None. 201 unsigned Cost = 202 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 203 TargetTransformInfo::OP_None, 204 TargetTransformInfo::OP_None); 205 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 206 TargetTransformInfo::OP_None, 207 TargetTransformInfo::OP_None); 208 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 209 TargetTransformInfo::OP_None, 210 TargetTransformInfo::OP_None); 211 212 return Cost; 213 } 214 215 static const CostTblEntry<MVT::SimpleValueType> 216 AVX2UniformConstCostTable[] = { 217 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 218 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 219 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 220 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 221 }; 222 223 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 224 ST->hasAVX2()) { 225 int Idx = CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second); 226 if (Idx != -1) 227 return LT.first * AVX2UniformConstCostTable[Idx].Cost; 228 } 229 230 static const CostTblEntry<MVT::SimpleValueType> AVX512CostTable[] = { 231 { ISD::SHL, MVT::v16i32, 1 }, 232 { ISD::SRL, MVT::v16i32, 1 }, 233 { ISD::SRA, MVT::v16i32, 1 }, 234 { ISD::SHL, MVT::v8i64, 1 }, 235 { ISD::SRL, MVT::v8i64, 1 }, 236 { ISD::SRA, MVT::v8i64, 1 }, 237 }; 238 239 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = { 240 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 241 // customize them to detect the cases where shift amount is a scalar one. 242 { ISD::SHL, MVT::v4i32, 1 }, 243 { ISD::SRL, MVT::v4i32, 1 }, 244 { ISD::SRA, MVT::v4i32, 1 }, 245 { ISD::SHL, MVT::v8i32, 1 }, 246 { ISD::SRL, MVT::v8i32, 1 }, 247 { ISD::SRA, MVT::v8i32, 1 }, 248 { ISD::SHL, MVT::v2i64, 1 }, 249 { ISD::SRL, MVT::v2i64, 1 }, 250 { ISD::SHL, MVT::v4i64, 1 }, 251 { ISD::SRL, MVT::v4i64, 1 }, 252 253 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence. 254 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized. 255 256 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized. 257 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized. 258 259 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized. 260 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized. 261 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized. 262 263 // Vectorizing division is a bad idea. See the SSE2 table for more comments. 264 { ISD::SDIV, MVT::v32i8, 32*20 }, 265 { ISD::SDIV, MVT::v16i16, 16*20 }, 266 { ISD::SDIV, MVT::v8i32, 8*20 }, 267 { ISD::SDIV, MVT::v4i64, 4*20 }, 268 { ISD::UDIV, MVT::v32i8, 32*20 }, 269 { ISD::UDIV, MVT::v16i16, 16*20 }, 270 { ISD::UDIV, MVT::v8i32, 8*20 }, 271 { ISD::UDIV, MVT::v4i64, 4*20 }, 272 }; 273 274 if (ST->hasAVX512()) { 275 int Idx = CostTableLookup(AVX512CostTable, ISD, LT.second); 276 if (Idx != -1) 277 return LT.first * AVX512CostTable[Idx].Cost; 278 } 279 // Look for AVX2 lowering tricks. 280 if (ST->hasAVX2()) { 281 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 282 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 283 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 284 // On AVX2, a packed v16i16 shift left by a constant build_vector 285 // is lowered into a vector multiply (vpmullw). 286 return LT.first; 287 288 int Idx = CostTableLookup(AVX2CostTable, ISD, LT.second); 289 if (Idx != -1) 290 return LT.first * AVX2CostTable[Idx].Cost; 291 } 292 293 static const CostTblEntry<MVT::SimpleValueType> 294 SSE2UniformConstCostTable[] = { 295 // We don't correctly identify costs of casts because they are marked as 296 // custom. 297 // Constant splats are cheaper for the following instructions. 298 { ISD::SHL, MVT::v16i8, 1 }, // psllw. 299 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 300 { ISD::SHL, MVT::v4i32, 1 }, // pslld 301 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 302 303 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. 304 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 305 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 306 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 307 308 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 309 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 310 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 311 312 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 313 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 314 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 315 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 316 }; 317 318 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 319 ST->hasSSE2()) { 320 // pmuldq sequence. 321 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 322 return LT.first * 15; 323 324 int Idx = CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second); 325 if (Idx != -1) 326 return LT.first * SSE2UniformConstCostTable[Idx].Cost; 327 } 328 329 if (ISD == ISD::SHL && 330 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 331 EVT VT = LT.second; 332 if ((VT == MVT::v8i16 && ST->hasSSE2()) || 333 (VT == MVT::v4i32 && ST->hasSSE41())) 334 // Vector shift left by non uniform constant can be lowered 335 // into vector multiply (pmullw/pmulld). 336 return LT.first; 337 if (VT == MVT::v4i32 && ST->hasSSE2()) 338 // A vector shift left by non uniform constant is converted 339 // into a vector multiply; the new multiply is eventually 340 // lowered into a sequence of shuffles and 2 x pmuludq. 341 ISD = ISD::MUL; 342 } 343 344 static const CostTblEntry<MVT::SimpleValueType> SSE2CostTable[] = { 345 // We don't correctly identify costs of casts because they are marked as 346 // custom. 347 // For some cases, where the shift amount is a scalar we would be able 348 // to generate better code. Unfortunately, when this is the case the value 349 // (the splat) will get hoisted out of the loop, thereby making it invisible 350 // to ISel. The cost model must return worst case assumptions because it is 351 // used for vectorization and we don't want to make vectorized code worse 352 // than scalar code. 353 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence. 354 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized. 355 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 356 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized. 357 { ISD::SHL, MVT::v4i64, 4*10 }, // Scalarized. 358 359 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized. 360 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized. 361 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized. 362 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized. 363 364 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized. 365 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized. 366 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized. 367 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized. 368 369 // It is not a good idea to vectorize division. We have to scalarize it and 370 // in the process we will often end up having to spilling regular 371 // registers. The overhead of division is going to dominate most kernels 372 // anyways so try hard to prevent vectorization of division - it is 373 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 374 // to hide "20 cycles" for each lane. 375 { ISD::SDIV, MVT::v16i8, 16*20 }, 376 { ISD::SDIV, MVT::v8i16, 8*20 }, 377 { ISD::SDIV, MVT::v4i32, 4*20 }, 378 { ISD::SDIV, MVT::v2i64, 2*20 }, 379 { ISD::UDIV, MVT::v16i8, 16*20 }, 380 { ISD::UDIV, MVT::v8i16, 8*20 }, 381 { ISD::UDIV, MVT::v4i32, 4*20 }, 382 { ISD::UDIV, MVT::v2i64, 2*20 }, 383 }; 384 385 if (ST->hasSSE2()) { 386 int Idx = CostTableLookup(SSE2CostTable, ISD, LT.second); 387 if (Idx != -1) 388 return LT.first * SSE2CostTable[Idx].Cost; 389 } 390 391 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTable[] = { 392 // We don't have to scalarize unsupported ops. We can issue two half-sized 393 // operations and we only need to extract the upper YMM half. 394 // Two ops + 1 extract + 1 insert = 4. 395 { ISD::MUL, MVT::v16i16, 4 }, 396 { ISD::MUL, MVT::v8i32, 4 }, 397 { ISD::SUB, MVT::v8i32, 4 }, 398 { ISD::ADD, MVT::v8i32, 4 }, 399 { ISD::SUB, MVT::v4i64, 4 }, 400 { ISD::ADD, MVT::v4i64, 4 }, 401 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 402 // are lowered as a series of long multiplies(3), shifts(4) and adds(2) 403 // Because we believe v4i64 to be a legal type, we must also include the 404 // split factor of two in the cost table. Therefore, the cost here is 18 405 // instead of 9. 406 { ISD::MUL, MVT::v4i64, 18 }, 407 }; 408 409 // Look for AVX1 lowering tricks. 410 if (ST->hasAVX() && !ST->hasAVX2()) { 411 EVT VT = LT.second; 412 413 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a 414 // sequence of extract + two vector multiply + insert. 415 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) && 416 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) 417 ISD = ISD::MUL; 418 419 int Idx = CostTableLookup(AVX1CostTable, ISD, VT); 420 if (Idx != -1) 421 return LT.first * AVX1CostTable[Idx].Cost; 422 } 423 424 // Custom lowering of vectors. 425 static const CostTblEntry<MVT::SimpleValueType> CustomLowered[] = { 426 // A v2i64/v4i64 and multiply is custom lowered as a series of long 427 // multiplies(3), shifts(4) and adds(2). 428 { ISD::MUL, MVT::v2i64, 9 }, 429 { ISD::MUL, MVT::v4i64, 9 }, 430 }; 431 int Idx = CostTableLookup(CustomLowered, ISD, LT.second); 432 if (Idx != -1) 433 return LT.first * CustomLowered[Idx].Cost; 434 435 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle, 436 // 2x pmuludq, 2x shuffle. 437 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() && 438 !ST->hasSSE41()) 439 return LT.first * 6; 440 441 // Fallback to the default implementation. 442 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info, 443 Op2Info); 444 } 445 446 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index, 447 Type *SubTp) const { 448 // We only estimate the cost of reverse and alternate shuffles. 449 if (Kind != SK_Reverse && Kind != SK_Alternate) 450 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp); 451 452 if (Kind == SK_Reverse) { 453 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp); 454 unsigned Cost = 1; 455 if (LT.second.getSizeInBits() > 128) 456 Cost = 3; // Extract + insert + copy. 457 458 // Multiple by the number of parts. 459 return Cost * LT.first; 460 } 461 462 if (Kind == SK_Alternate) { 463 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 464 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 465 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp); 466 467 // The backend knows how to generate a single VEX.256 version of 468 // instruction VPBLENDW if the target supports AVX2. 469 if (ST->hasAVX2() && LT.second == MVT::v16i16) 470 return LT.first; 471 472 static const CostTblEntry<MVT::SimpleValueType> AVXAltShuffleTbl[] = { 473 {ISD::VECTOR_SHUFFLE, MVT::v4i64, 1}, // vblendpd 474 {ISD::VECTOR_SHUFFLE, MVT::v4f64, 1}, // vblendpd 475 476 {ISD::VECTOR_SHUFFLE, MVT::v8i32, 1}, // vblendps 477 {ISD::VECTOR_SHUFFLE, MVT::v8f32, 1}, // vblendps 478 479 // This shuffle is custom lowered into a sequence of: 480 // 2x vextractf128 , 2x vpblendw , 1x vinsertf128 481 {ISD::VECTOR_SHUFFLE, MVT::v16i16, 5}, 482 483 // This shuffle is custom lowered into a long sequence of: 484 // 2x vextractf128 , 4x vpshufb , 2x vpor , 1x vinsertf128 485 {ISD::VECTOR_SHUFFLE, MVT::v32i8, 9} 486 }; 487 488 if (ST->hasAVX()) { 489 int Idx = CostTableLookup(AVXAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second); 490 if (Idx != -1) 491 return LT.first * AVXAltShuffleTbl[Idx].Cost; 492 } 493 494 static const CostTblEntry<MVT::SimpleValueType> SSE41AltShuffleTbl[] = { 495 // These are lowered into movsd. 496 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 497 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 498 499 // packed float vectors with four elements are lowered into BLENDI dag 500 // nodes. A v4i32/v4f32 BLENDI generates a single 'blendps'/'blendpd'. 501 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, 502 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, 503 504 // This shuffle generates a single pshufw. 505 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, 506 507 // There is no instruction that matches a v16i8 alternate shuffle. 508 // The backend will expand it into the sequence 'pshufb + pshufb + or'. 509 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3} 510 }; 511 512 if (ST->hasSSE41()) { 513 int Idx = CostTableLookup(SSE41AltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second); 514 if (Idx != -1) 515 return LT.first * SSE41AltShuffleTbl[Idx].Cost; 516 } 517 518 static const CostTblEntry<MVT::SimpleValueType> SSSE3AltShuffleTbl[] = { 519 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, // movsd 520 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd 521 522 // SSE3 doesn't have 'blendps'. The following shuffles are expanded into 523 // the sequence 'shufps + pshufd' 524 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, 525 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, 526 527 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 3}, // pshufb + pshufb + or 528 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3} // pshufb + pshufb + or 529 }; 530 531 if (ST->hasSSSE3()) { 532 int Idx = CostTableLookup(SSSE3AltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second); 533 if (Idx != -1) 534 return LT.first * SSSE3AltShuffleTbl[Idx].Cost; 535 } 536 537 static const CostTblEntry<MVT::SimpleValueType> SSEAltShuffleTbl[] = { 538 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, // movsd 539 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd 540 541 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, // shufps + pshufd 542 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd 543 544 // This is expanded into a long sequence of four extract + four insert. 545 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 8}, // 4 x pextrw + 4 pinsrw. 546 547 // 8 x (pinsrw + pextrw + and + movb + movzb + or) 548 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 48} 549 }; 550 551 // Fall-back (SSE3 and SSE2). 552 int Idx = CostTableLookup(SSEAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second); 553 if (Idx != -1) 554 return LT.first * SSEAltShuffleTbl[Idx].Cost; 555 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp); 556 } 557 558 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp); 559 } 560 561 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const { 562 int ISD = TLI->InstructionOpcodeToISD(Opcode); 563 assert(ISD && "Invalid opcode"); 564 565 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src); 566 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst); 567 568 static const TypeConversionCostTblEntry<MVT::SimpleValueType> 569 SSE2ConvTbl[] = { 570 // These are somewhat magic numbers justified by looking at the output of 571 // Intel's IACA, running some kernels and making sure when we take 572 // legalization into account the throughput will be overestimated. 573 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 574 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 575 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 576 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 577 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 578 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 579 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 580 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 581 // There are faster sequences for float conversions. 582 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 583 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 584 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 585 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 586 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 587 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, 588 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 589 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 590 }; 591 592 if (ST->hasSSE2() && !ST->hasAVX()) { 593 int Idx = 594 ConvertCostTableLookup(SSE2ConvTbl, ISD, LTDest.second, LTSrc.second); 595 if (Idx != -1) 596 return LTSrc.first * SSE2ConvTbl[Idx].Cost; 597 } 598 599 static const TypeConversionCostTblEntry<MVT::SimpleValueType> 600 AVX512ConversionTbl[] = { 601 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 602 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 603 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 604 { ISD::FP_ROUND, MVT::v16f32, MVT::v8f64, 3 }, 605 606 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 607 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 608 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 609 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 610 { ISD::TRUNCATE, MVT::v16i32, MVT::v8i64, 4 }, 611 612 // v16i1 -> v16i32 - load + broadcast 613 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 614 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 615 616 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 617 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 618 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 619 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 620 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i32, 3 }, 621 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i32, 3 }, 622 623 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 624 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 625 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 626 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 627 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 628 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 629 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 630 }; 631 632 if (ST->hasAVX512()) { 633 int Idx = ConvertCostTableLookup(AVX512ConversionTbl, ISD, LTDest.second, 634 LTSrc.second); 635 if (Idx != -1) 636 return AVX512ConversionTbl[Idx].Cost; 637 } 638 EVT SrcTy = TLI->getValueType(Src); 639 EVT DstTy = TLI->getValueType(Dst); 640 641 // The function getSimpleVT only handles simple value types. 642 if (!SrcTy.isSimple() || !DstTy.isSimple()) 643 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 644 645 static const TypeConversionCostTblEntry<MVT::SimpleValueType> 646 AVX2ConversionTbl[] = { 647 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 648 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 649 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 650 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 651 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 652 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 653 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 654 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 655 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 656 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 657 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 658 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 659 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 660 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 661 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 662 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 663 664 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 665 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 666 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 667 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 668 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 669 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 670 671 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 672 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 673 674 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 675 }; 676 677 static const TypeConversionCostTblEntry<MVT::SimpleValueType> 678 AVXConversionTbl[] = { 679 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 680 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 681 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 682 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 683 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 684 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 685 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 686 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 687 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 688 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 689 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 690 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 691 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 692 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 693 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 694 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 695 696 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 697 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 698 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 699 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 700 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 701 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 702 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 703 704 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 705 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 706 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 707 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 708 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 709 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 710 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 711 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 712 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 713 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 714 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 715 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 716 717 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 718 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 719 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 720 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 721 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 722 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 723 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 724 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 725 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 726 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 727 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 728 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 729 // The generic code to compute the scalar overhead is currently broken. 730 // Workaround this limitation by estimating the scalarization overhead 731 // here. We have roughly 10 instructions per scalar element. 732 // Multiply that by the vector width. 733 // FIXME: remove that when PR19268 is fixed. 734 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 735 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 4*10 }, 736 737 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 738 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 739 // This node is expanded into scalarized operations but BasicTTI is overly 740 // optimistic estimating its cost. It computes 3 per element (one 741 // vector-extract, one scalar conversion and one vector-insert). The 742 // problem is that the inserts form a read-modify-write chain so latency 743 // should be factored in too. Inflating the cost per element by 1. 744 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 745 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 746 }; 747 748 if (ST->hasAVX2()) { 749 int Idx = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 750 DstTy.getSimpleVT(), SrcTy.getSimpleVT()); 751 if (Idx != -1) 752 return AVX2ConversionTbl[Idx].Cost; 753 } 754 755 if (ST->hasAVX()) { 756 int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(), 757 SrcTy.getSimpleVT()); 758 if (Idx != -1) 759 return AVXConversionTbl[Idx].Cost; 760 } 761 762 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 763 } 764 765 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 766 Type *CondTy) const { 767 // Legalize the type. 768 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy); 769 770 MVT MTy = LT.second; 771 772 int ISD = TLI->InstructionOpcodeToISD(Opcode); 773 assert(ISD && "Invalid opcode"); 774 775 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTbl[] = { 776 { ISD::SETCC, MVT::v2f64, 1 }, 777 { ISD::SETCC, MVT::v4f32, 1 }, 778 { ISD::SETCC, MVT::v2i64, 1 }, 779 { ISD::SETCC, MVT::v4i32, 1 }, 780 { ISD::SETCC, MVT::v8i16, 1 }, 781 { ISD::SETCC, MVT::v16i8, 1 }, 782 }; 783 784 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTbl[] = { 785 { ISD::SETCC, MVT::v4f64, 1 }, 786 { ISD::SETCC, MVT::v8f32, 1 }, 787 // AVX1 does not support 8-wide integer compare. 788 { ISD::SETCC, MVT::v4i64, 4 }, 789 { ISD::SETCC, MVT::v8i32, 4 }, 790 { ISD::SETCC, MVT::v16i16, 4 }, 791 { ISD::SETCC, MVT::v32i8, 4 }, 792 }; 793 794 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTbl[] = { 795 { ISD::SETCC, MVT::v4i64, 1 }, 796 { ISD::SETCC, MVT::v8i32, 1 }, 797 { ISD::SETCC, MVT::v16i16, 1 }, 798 { ISD::SETCC, MVT::v32i8, 1 }, 799 }; 800 801 static const CostTblEntry<MVT::SimpleValueType> AVX512CostTbl[] = { 802 { ISD::SETCC, MVT::v8i64, 1 }, 803 { ISD::SETCC, MVT::v16i32, 1 }, 804 { ISD::SETCC, MVT::v8f64, 1 }, 805 { ISD::SETCC, MVT::v16f32, 1 }, 806 }; 807 808 if (ST->hasAVX512()) { 809 int Idx = CostTableLookup(AVX512CostTbl, ISD, MTy); 810 if (Idx != -1) 811 return LT.first * AVX512CostTbl[Idx].Cost; 812 } 813 814 if (ST->hasAVX2()) { 815 int Idx = CostTableLookup(AVX2CostTbl, ISD, MTy); 816 if (Idx != -1) 817 return LT.first * AVX2CostTbl[Idx].Cost; 818 } 819 820 if (ST->hasAVX()) { 821 int Idx = CostTableLookup(AVX1CostTbl, ISD, MTy); 822 if (Idx != -1) 823 return LT.first * AVX1CostTbl[Idx].Cost; 824 } 825 826 if (ST->hasSSE42()) { 827 int Idx = CostTableLookup(SSE42CostTbl, ISD, MTy); 828 if (Idx != -1) 829 return LT.first * SSE42CostTbl[Idx].Cost; 830 } 831 832 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy); 833 } 834 835 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val, 836 unsigned Index) const { 837 assert(Val->isVectorTy() && "This must be a vector type"); 838 839 if (Index != -1U) { 840 // Legalize the type. 841 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val); 842 843 // This type is legalized to a scalar type. 844 if (!LT.second.isVector()) 845 return 0; 846 847 // The type may be split. Normalize the index to the new type. 848 unsigned Width = LT.second.getVectorNumElements(); 849 Index = Index % Width; 850 851 // Floating point scalars are already located in index #0. 852 if (Val->getScalarType()->isFloatingPointTy() && Index == 0) 853 return 0; 854 } 855 856 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index); 857 } 858 859 unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert, 860 bool Extract) const { 861 assert (Ty->isVectorTy() && "Can only scalarize vectors"); 862 unsigned Cost = 0; 863 864 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) { 865 if (Insert) 866 Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i); 867 if (Extract) 868 Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i); 869 } 870 871 return Cost; 872 } 873 874 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 875 unsigned AddressSpace) const { 876 // Handle non-power-of-two vectors such as <3 x float> 877 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 878 unsigned NumElem = VTy->getVectorNumElements(); 879 880 // Handle a few common cases: 881 // <3 x float> 882 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 883 // Cost = 64 bit store + extract + 32 bit store. 884 return 3; 885 886 // <3 x double> 887 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 888 // Cost = 128 bit store + unpack + 64 bit store. 889 return 3; 890 891 // Assume that all other non-power-of-two numbers are scalarized. 892 if (!isPowerOf2_32(NumElem)) { 893 unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode, 894 VTy->getScalarType(), 895 Alignment, 896 AddressSpace); 897 unsigned SplitCost = getScalarizationOverhead(Src, 898 Opcode == Instruction::Load, 899 Opcode==Instruction::Store); 900 return NumElem * Cost + SplitCost; 901 } 902 } 903 904 // Legalize the type. 905 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src); 906 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 907 "Invalid Opcode"); 908 909 // Each load/store unit costs 1. 910 unsigned Cost = LT.first * 1; 911 912 // On Sandybridge 256bit load/stores are double pumped 913 // (but not on Haswell). 914 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2()) 915 Cost*=2; 916 917 return Cost; 918 } 919 920 unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const { 921 // Address computations in vectorized code with non-consecutive addresses will 922 // likely result in more instructions compared to scalar code where the 923 // computation can more often be merged into the index mode. The resulting 924 // extra micro-ops can significantly decrease throughput. 925 unsigned NumVectorInstToHideOverhead = 10; 926 927 if (Ty->isVectorTy() && IsComplex) 928 return NumVectorInstToHideOverhead; 929 930 return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex); 931 } 932 933 unsigned X86TTI::getReductionCost(unsigned Opcode, Type *ValTy, 934 bool IsPairwise) const { 935 936 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy); 937 938 MVT MTy = LT.second; 939 940 int ISD = TLI->InstructionOpcodeToISD(Opcode); 941 assert(ISD && "Invalid opcode"); 942 943 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 944 // and make it as the cost. 945 946 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblPairWise[] = { 947 { ISD::FADD, MVT::v2f64, 2 }, 948 { ISD::FADD, MVT::v4f32, 4 }, 949 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 950 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 951 { ISD::ADD, MVT::v8i16, 5 }, 952 }; 953 954 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblPairWise[] = { 955 { ISD::FADD, MVT::v4f32, 4 }, 956 { ISD::FADD, MVT::v4f64, 5 }, 957 { ISD::FADD, MVT::v8f32, 7 }, 958 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 959 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 960 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 961 { ISD::ADD, MVT::v8i16, 5 }, 962 { ISD::ADD, MVT::v8i32, 5 }, 963 }; 964 965 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblNoPairWise[] = { 966 { ISD::FADD, MVT::v2f64, 2 }, 967 { ISD::FADD, MVT::v4f32, 4 }, 968 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 969 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 970 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 971 }; 972 973 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblNoPairWise[] = { 974 { ISD::FADD, MVT::v4f32, 3 }, 975 { ISD::FADD, MVT::v4f64, 3 }, 976 { ISD::FADD, MVT::v8f32, 4 }, 977 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 978 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 979 { ISD::ADD, MVT::v4i64, 3 }, 980 { ISD::ADD, MVT::v8i16, 4 }, 981 { ISD::ADD, MVT::v8i32, 5 }, 982 }; 983 984 if (IsPairwise) { 985 if (ST->hasAVX()) { 986 int Idx = CostTableLookup(AVX1CostTblPairWise, ISD, MTy); 987 if (Idx != -1) 988 return LT.first * AVX1CostTblPairWise[Idx].Cost; 989 } 990 991 if (ST->hasSSE42()) { 992 int Idx = CostTableLookup(SSE42CostTblPairWise, ISD, MTy); 993 if (Idx != -1) 994 return LT.first * SSE42CostTblPairWise[Idx].Cost; 995 } 996 } else { 997 if (ST->hasAVX()) { 998 int Idx = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy); 999 if (Idx != -1) 1000 return LT.first * AVX1CostTblNoPairWise[Idx].Cost; 1001 } 1002 1003 if (ST->hasSSE42()) { 1004 int Idx = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy); 1005 if (Idx != -1) 1006 return LT.first * SSE42CostTblNoPairWise[Idx].Cost; 1007 } 1008 } 1009 1010 return TargetTransformInfo::getReductionCost(Opcode, ValTy, IsPairwise); 1011 } 1012 1013 /// \brief Calculate the cost of materializing a 64-bit value. This helper 1014 /// method might only calculate a fraction of a larger immediate. Therefore it 1015 /// is valid to return a cost of ZERO. 1016 unsigned X86TTI::getIntImmCost(int64_t Val) const { 1017 if (Val == 0) 1018 return TCC_Free; 1019 1020 if (isInt<32>(Val)) 1021 return TCC_Basic; 1022 1023 return 2 * TCC_Basic; 1024 } 1025 1026 unsigned X86TTI::getIntImmCost(const APInt &Imm, Type *Ty) const { 1027 assert(Ty->isIntegerTy()); 1028 1029 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1030 if (BitSize == 0) 1031 return ~0U; 1032 1033 // Never hoist constants larger than 128bit, because this might lead to 1034 // incorrect code generation or assertions in codegen. 1035 // Fixme: Create a cost model for types larger than i128 once the codegen 1036 // issues have been fixed. 1037 if (BitSize > 128) 1038 return TCC_Free; 1039 1040 if (Imm == 0) 1041 return TCC_Free; 1042 1043 // Sign-extend all constants to a multiple of 64-bit. 1044 APInt ImmVal = Imm; 1045 if (BitSize & 0x3f) 1046 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU); 1047 1048 // Split the constant into 64-bit chunks and calculate the cost for each 1049 // chunk. 1050 unsigned Cost = 0; 1051 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 1052 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 1053 int64_t Val = Tmp.getSExtValue(); 1054 Cost += getIntImmCost(Val); 1055 } 1056 // We need at least one instruction to materialze the constant. 1057 return std::max(1U, Cost); 1058 } 1059 1060 unsigned X86TTI::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 1061 Type *Ty) const { 1062 assert(Ty->isIntegerTy()); 1063 1064 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1065 // There is no cost model for constants with a bit size of 0. Return TCC_Free 1066 // here, so that constant hoisting will ignore this constant. 1067 if (BitSize == 0) 1068 return TCC_Free; 1069 1070 unsigned ImmIdx = ~0U; 1071 switch (Opcode) { 1072 default: return TCC_Free; 1073 case Instruction::GetElementPtr: 1074 // Always hoist the base address of a GetElementPtr. This prevents the 1075 // creation of new constants for every base constant that gets constant 1076 // folded with the offset. 1077 if (Idx == 0) 1078 return 2 * TCC_Basic; 1079 return TCC_Free; 1080 case Instruction::Store: 1081 ImmIdx = 0; 1082 break; 1083 case Instruction::Add: 1084 case Instruction::Sub: 1085 case Instruction::Mul: 1086 case Instruction::UDiv: 1087 case Instruction::SDiv: 1088 case Instruction::URem: 1089 case Instruction::SRem: 1090 case Instruction::And: 1091 case Instruction::Or: 1092 case Instruction::Xor: 1093 case Instruction::ICmp: 1094 ImmIdx = 1; 1095 break; 1096 // Always return TCC_Free for the shift value of a shift instruction. 1097 case Instruction::Shl: 1098 case Instruction::LShr: 1099 case Instruction::AShr: 1100 if (Idx == 1) 1101 return TCC_Free; 1102 break; 1103 case Instruction::Trunc: 1104 case Instruction::ZExt: 1105 case Instruction::SExt: 1106 case Instruction::IntToPtr: 1107 case Instruction::PtrToInt: 1108 case Instruction::BitCast: 1109 case Instruction::PHI: 1110 case Instruction::Call: 1111 case Instruction::Select: 1112 case Instruction::Ret: 1113 case Instruction::Load: 1114 break; 1115 } 1116 1117 if (Idx == ImmIdx) { 1118 unsigned NumConstants = (BitSize + 63) / 64; 1119 unsigned Cost = X86TTI::getIntImmCost(Imm, Ty); 1120 return (Cost <= NumConstants * TCC_Basic) 1121 ? static_cast<unsigned>(TCC_Free) 1122 : Cost; 1123 } 1124 1125 return X86TTI::getIntImmCost(Imm, Ty); 1126 } 1127 1128 unsigned X86TTI::getIntImmCost(Intrinsic::ID IID, unsigned Idx, 1129 const APInt &Imm, Type *Ty) const { 1130 assert(Ty->isIntegerTy()); 1131 1132 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1133 // There is no cost model for constants with a bit size of 0. Return TCC_Free 1134 // here, so that constant hoisting will ignore this constant. 1135 if (BitSize == 0) 1136 return TCC_Free; 1137 1138 switch (IID) { 1139 default: return TCC_Free; 1140 case Intrinsic::sadd_with_overflow: 1141 case Intrinsic::uadd_with_overflow: 1142 case Intrinsic::ssub_with_overflow: 1143 case Intrinsic::usub_with_overflow: 1144 case Intrinsic::smul_with_overflow: 1145 case Intrinsic::umul_with_overflow: 1146 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 1147 return TCC_Free; 1148 break; 1149 case Intrinsic::experimental_stackmap: 1150 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 1151 return TCC_Free; 1152 break; 1153 case Intrinsic::experimental_patchpoint_void: 1154 case Intrinsic::experimental_patchpoint_i64: 1155 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 1156 return TCC_Free; 1157 break; 1158 } 1159 return X86TTI::getIntImmCost(Imm, Ty); 1160 } 1161 1162 bool X86TTI::isLegalMaskedLoad(Type *DataTy, int Consecutive) const { 1163 int DataWidth = DataTy->getPrimitiveSizeInBits(); 1164 1165 // Todo: AVX512 allows gather/scatter, works with strided and random as well 1166 if ((DataWidth < 32) || (Consecutive == 0)) 1167 return false; 1168 if (ST->hasAVX512() || ST->hasAVX2()) 1169 return true; 1170 return false; 1171 } 1172 1173 bool X86TTI::isLegalMaskedStore(Type *DataType, int Consecutive) const { 1174 return isLegalMaskedLoad(DataType, Consecutive); 1175 } 1176 1177