1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63                           cl::desc("Clearance between two register writes "
64                                    "for inserting XOR to avoid partial "
65                                    "register update"),
66                           cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69                   cl::desc("How many idle instructions we would like before "
70                            "certain undef register reads"),
71                   cl::init(64), cl::Hidden);
72 
73 enum {
74   // Select which memory operand is being unfolded.
75   // (stored in bits 0 - 3)
76   TB_INDEX_0    = 0,
77   TB_INDEX_1    = 1,
78   TB_INDEX_2    = 2,
79   TB_INDEX_3    = 3,
80   TB_INDEX_4    = 4,
81   TB_INDEX_MASK = 0xf,
82 
83   // Do not insert the reverse map (MemOp -> RegOp) into the table.
84   // This may be needed because there is a many -> one mapping.
85   TB_NO_REVERSE   = 1 << 4,
86 
87   // Do not insert the forward map (RegOp -> MemOp) into the table.
88   // This is needed for Native Client, which prohibits branch
89   // instructions from using a memory operand.
90   TB_NO_FORWARD   = 1 << 5,
91 
92   TB_FOLDED_LOAD  = 1 << 6,
93   TB_FOLDED_STORE = 1 << 7,
94 
95   // Minimum alignment required for load/store.
96   // Used for RegOp->MemOp conversion.
97   // (stored in bits 8 - 15)
98   TB_ALIGN_SHIFT = 8,
99   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
100   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
101   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
102   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
103   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
104 };
105 
106 struct X86MemoryFoldTableEntry {
107   uint16_t RegOp;
108   uint16_t MemOp;
109   uint16_t Flags;
110 };
111 
112 // Pin the vtable to this file.
113 void X86InstrInfo::anchor() {}
114 
115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117                                                : X86::ADJCALLSTACKDOWN32),
118                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119                                                : X86::ADJCALLSTACKUP32),
120                       X86::CATCHRET,
121                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122       Subtarget(STI), RI(STI.getTargetTriple()) {
123 
124   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125     { X86::ADC32ri,     X86::ADC32mi,    0 },
126     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
127     { X86::ADC32rr,     X86::ADC32mr,    0 },
128     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
129     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
130     { X86::ADC64rr,     X86::ADC64mr,    0 },
131     { X86::ADD16ri,     X86::ADD16mi,    0 },
132     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
133     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
134     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
135     { X86::ADD16rr,     X86::ADD16mr,    0 },
136     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
137     { X86::ADD32ri,     X86::ADD32mi,    0 },
138     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
139     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
140     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
141     { X86::ADD32rr,     X86::ADD32mr,    0 },
142     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
143     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
144     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
145     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
146     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
147     { X86::ADD64rr,     X86::ADD64mr,    0 },
148     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
149     { X86::ADD8ri,      X86::ADD8mi,     0 },
150     { X86::ADD8rr,      X86::ADD8mr,     0 },
151     { X86::AND16ri,     X86::AND16mi,    0 },
152     { X86::AND16ri8,    X86::AND16mi8,   0 },
153     { X86::AND16rr,     X86::AND16mr,    0 },
154     { X86::AND32ri,     X86::AND32mi,    0 },
155     { X86::AND32ri8,    X86::AND32mi8,   0 },
156     { X86::AND32rr,     X86::AND32mr,    0 },
157     { X86::AND64ri32,   X86::AND64mi32,  0 },
158     { X86::AND64ri8,    X86::AND64mi8,   0 },
159     { X86::AND64rr,     X86::AND64mr,    0 },
160     { X86::AND8ri,      X86::AND8mi,     0 },
161     { X86::AND8rr,      X86::AND8mr,     0 },
162     { X86::DEC16r,      X86::DEC16m,     0 },
163     { X86::DEC32r,      X86::DEC32m,     0 },
164     { X86::DEC64r,      X86::DEC64m,     0 },
165     { X86::DEC8r,       X86::DEC8m,      0 },
166     { X86::INC16r,      X86::INC16m,     0 },
167     { X86::INC32r,      X86::INC32m,     0 },
168     { X86::INC64r,      X86::INC64m,     0 },
169     { X86::INC8r,       X86::INC8m,      0 },
170     { X86::NEG16r,      X86::NEG16m,     0 },
171     { X86::NEG32r,      X86::NEG32m,     0 },
172     { X86::NEG64r,      X86::NEG64m,     0 },
173     { X86::NEG8r,       X86::NEG8m,      0 },
174     { X86::NOT16r,      X86::NOT16m,     0 },
175     { X86::NOT32r,      X86::NOT32m,     0 },
176     { X86::NOT64r,      X86::NOT64m,     0 },
177     { X86::NOT8r,       X86::NOT8m,      0 },
178     { X86::OR16ri,      X86::OR16mi,     0 },
179     { X86::OR16ri8,     X86::OR16mi8,    0 },
180     { X86::OR16rr,      X86::OR16mr,     0 },
181     { X86::OR32ri,      X86::OR32mi,     0 },
182     { X86::OR32ri8,     X86::OR32mi8,    0 },
183     { X86::OR32rr,      X86::OR32mr,     0 },
184     { X86::OR64ri32,    X86::OR64mi32,   0 },
185     { X86::OR64ri8,     X86::OR64mi8,    0 },
186     { X86::OR64rr,      X86::OR64mr,     0 },
187     { X86::OR8ri,       X86::OR8mi,      0 },
188     { X86::OR8rr,       X86::OR8mr,      0 },
189     { X86::ROL16r1,     X86::ROL16m1,    0 },
190     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
191     { X86::ROL16ri,     X86::ROL16mi,    0 },
192     { X86::ROL32r1,     X86::ROL32m1,    0 },
193     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
194     { X86::ROL32ri,     X86::ROL32mi,    0 },
195     { X86::ROL64r1,     X86::ROL64m1,    0 },
196     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
197     { X86::ROL64ri,     X86::ROL64mi,    0 },
198     { X86::ROL8r1,      X86::ROL8m1,     0 },
199     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
200     { X86::ROL8ri,      X86::ROL8mi,     0 },
201     { X86::ROR16r1,     X86::ROR16m1,    0 },
202     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
203     { X86::ROR16ri,     X86::ROR16mi,    0 },
204     { X86::ROR32r1,     X86::ROR32m1,    0 },
205     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
206     { X86::ROR32ri,     X86::ROR32mi,    0 },
207     { X86::ROR64r1,     X86::ROR64m1,    0 },
208     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
209     { X86::ROR64ri,     X86::ROR64mi,    0 },
210     { X86::ROR8r1,      X86::ROR8m1,     0 },
211     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
212     { X86::ROR8ri,      X86::ROR8mi,     0 },
213     { X86::SAR16r1,     X86::SAR16m1,    0 },
214     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
215     { X86::SAR16ri,     X86::SAR16mi,    0 },
216     { X86::SAR32r1,     X86::SAR32m1,    0 },
217     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
218     { X86::SAR32ri,     X86::SAR32mi,    0 },
219     { X86::SAR64r1,     X86::SAR64m1,    0 },
220     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
221     { X86::SAR64ri,     X86::SAR64mi,    0 },
222     { X86::SAR8r1,      X86::SAR8m1,     0 },
223     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
224     { X86::SAR8ri,      X86::SAR8mi,     0 },
225     { X86::SBB32ri,     X86::SBB32mi,    0 },
226     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
227     { X86::SBB32rr,     X86::SBB32mr,    0 },
228     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
229     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
230     { X86::SBB64rr,     X86::SBB64mr,    0 },
231     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
232     { X86::SHL16ri,     X86::SHL16mi,    0 },
233     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
234     { X86::SHL32ri,     X86::SHL32mi,    0 },
235     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
236     { X86::SHL64ri,     X86::SHL64mi,    0 },
237     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
238     { X86::SHL8ri,      X86::SHL8mi,     0 },
239     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
240     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
241     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
242     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
243     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
244     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
245     { X86::SHR16r1,     X86::SHR16m1,    0 },
246     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
247     { X86::SHR16ri,     X86::SHR16mi,    0 },
248     { X86::SHR32r1,     X86::SHR32m1,    0 },
249     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
250     { X86::SHR32ri,     X86::SHR32mi,    0 },
251     { X86::SHR64r1,     X86::SHR64m1,    0 },
252     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
253     { X86::SHR64ri,     X86::SHR64mi,    0 },
254     { X86::SHR8r1,      X86::SHR8m1,     0 },
255     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
256     { X86::SHR8ri,      X86::SHR8mi,     0 },
257     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
258     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
259     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
260     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
261     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
262     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
263     { X86::SUB16ri,     X86::SUB16mi,    0 },
264     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
265     { X86::SUB16rr,     X86::SUB16mr,    0 },
266     { X86::SUB32ri,     X86::SUB32mi,    0 },
267     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
268     { X86::SUB32rr,     X86::SUB32mr,    0 },
269     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
270     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
271     { X86::SUB64rr,     X86::SUB64mr,    0 },
272     { X86::SUB8ri,      X86::SUB8mi,     0 },
273     { X86::SUB8rr,      X86::SUB8mr,     0 },
274     { X86::XOR16ri,     X86::XOR16mi,    0 },
275     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
276     { X86::XOR16rr,     X86::XOR16mr,    0 },
277     { X86::XOR32ri,     X86::XOR32mi,    0 },
278     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
279     { X86::XOR32rr,     X86::XOR32mr,    0 },
280     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
281     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
282     { X86::XOR64rr,     X86::XOR64mr,    0 },
283     { X86::XOR8ri,      X86::XOR8mi,     0 },
284     { X86::XOR8rr,      X86::XOR8mr,     0 }
285   };
286 
287   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
288     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
289                   Entry.RegOp, Entry.MemOp,
290                   // Index 0, folded load and store, no alignment requirement.
291                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
292   }
293 
294   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
295     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
296     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
297     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
298     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
299     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
300     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
301     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
302     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
303     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
304     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
305     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
306     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
307     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
308     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
309     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
310     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
311     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
312     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
313     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
314     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
315     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
316     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
317     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
318     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
319     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
320     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
321     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
322     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
323     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
324     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
325     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
326     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
327     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
328     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
329     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
330     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
331     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
332     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
333     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
334     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
336     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
337     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
338     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
339     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
340     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
341     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
342     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
343     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
344     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
345     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
346     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
347     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
348     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
349     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
350     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
351     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
352     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
353     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
354     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
355     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
356     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
357     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
358     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
359     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
360     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
361     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
362     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
363     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
364     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
365     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
366     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
367     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
368     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
369     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
370     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
371     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
372     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
373     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
374     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
375     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
376 
377     // AVX 128-bit versions of foldable instructions
378     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
379     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
380     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
381     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
382     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
383     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
384     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
386     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
387     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
388     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
389     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
390     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
391 
392     // AVX 256-bit foldable instructions
393     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
394     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
395     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
396     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
397     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
398     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
399 
400     // AVX-512 foldable instructions
401     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
403     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
404     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
405     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
406     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
407     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
408     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
409     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
410     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
411     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
412 
413     // AVX-512 foldable instructions (256-bit versions)
414     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
415     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
416     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
417     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
418     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
419     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
420     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
421     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
422     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
423     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
424 
425     // AVX-512 foldable instructions (128-bit versions)
426     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
427     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
428     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
429     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
430     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
431     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
432     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
433     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
434     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
435     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
436 
437     // F16C foldable instructions
438     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
439     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
440   };
441 
442   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
443     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
444                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
445   }
446 
447   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
448     { X86::BSF16rr,         X86::BSF16rm,             0 },
449     { X86::BSF32rr,         X86::BSF32rm,             0 },
450     { X86::BSF64rr,         X86::BSF64rm,             0 },
451     { X86::BSR16rr,         X86::BSR16rm,             0 },
452     { X86::BSR32rr,         X86::BSR32rm,             0 },
453     { X86::BSR64rr,         X86::BSR64rm,             0 },
454     { X86::CMP16rr,         X86::CMP16rm,             0 },
455     { X86::CMP32rr,         X86::CMP32rm,             0 },
456     { X86::CMP64rr,         X86::CMP64rm,             0 },
457     { X86::CMP8rr,          X86::CMP8rm,              0 },
458     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
459     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
460     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
461     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
462     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
463     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
464     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
465     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
466     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
467     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
468     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
469     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
470     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
471     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
472     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
473     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
474     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
475     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
476     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
477     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
478     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
479     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
480     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
481     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
482     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
483     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
484     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
485     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
486     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
487     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
488     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
489     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
490     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
491     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
492     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
493     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
494     { X86::MOV16rr,         X86::MOV16rm,             0 },
495     { X86::MOV32rr,         X86::MOV32rm,             0 },
496     { X86::MOV64rr,         X86::MOV64rm,             0 },
497     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
498     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
499     { X86::MOV8rr,          X86::MOV8rm,              0 },
500     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
501     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
502     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
503     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
504     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
505     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
506     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
507     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
508     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
509     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
510     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
511     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
512     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
513     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
514     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
515     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
516     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
517     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
518     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
519     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
520     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
521     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
522     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
523     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
524     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
525     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
526     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
527     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
528     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
529     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
530     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
531     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
532     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
533     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
534     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
535     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
536     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
537     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
538     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
539     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
540     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
541     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
542     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
543     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
544     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
545     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
546     { X86::RCPSSr,          X86::RCPSSm,              0 },
547     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
548     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
549     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
550     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
551     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
552     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
553     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
554     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
555     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
556     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
557     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
558     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
559     { X86::TEST16rr,        X86::TEST16rm,            0 },
560     { X86::TEST32rr,        X86::TEST32rm,            0 },
561     { X86::TEST64rr,        X86::TEST64rm,            0 },
562     { X86::TEST8rr,         X86::TEST8rm,             0 },
563     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
564     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
565     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
566 
567     // MMX version of foldable instructions
568     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
569     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
570     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
571     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
572     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
573     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
574     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
575     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
576     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
577     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
578 
579     // 3DNow! version of foldable instructions
580     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
581     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
582     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
583     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
584     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
585     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
586     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
587 
588     // AVX 128-bit versions of foldable instructions
589     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
590     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
591     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
592     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
593     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
594     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
595     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
596     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
597     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
598     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
599     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
600     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
601     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
602     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
603     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
604     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
605     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
606     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
607     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
608     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
609     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
610     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
611     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
612     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
613     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
614     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
615     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
616     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
617     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
618     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
619     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
620     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
621     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
622     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
623     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
624     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
625     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
626     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
627     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
628     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
629     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
630     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
631     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
632     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
633     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
634     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
635     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
636     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
637     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
638     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
639     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
640     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
641     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
642     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
643     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
644     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
645     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
646     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
647     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
648     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
649     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
650     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
651     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
652     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
653     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
654     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
655     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
656     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
657     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
658     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
659     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
660     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
661     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
662 
663     // AVX 256-bit foldable instructions
664     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
665     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
666     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
667     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
668     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
669     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
670     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
671     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
672     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
673     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
674     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
675     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
676     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
677     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
678     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
679     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
680     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
681     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
682     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
683     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
684     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
685     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
686     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
687     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
688     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
689     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
690     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
691 
692     // AVX2 foldable instructions
693 
694     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
695     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
696     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
697     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
698     // so they don't need an equivalent limitation.
699     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
700     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
701     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
702     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
703     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
704     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
705     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
706     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
707     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
708     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
709     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
710     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
711     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
712     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
713     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
714     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
715     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
716     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
717     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
718     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
719     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
720     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
721     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
722     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
723     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
724     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
725     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
726     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
727     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
728     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
729     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
730 
731     // XOP foldable instructions
732     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
733     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
734     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
735     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
736     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
737     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
738     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
739     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
740     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
741     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
742     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
743     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
744     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
745     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
746     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
747     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
748     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
749     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
750     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
751     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
752     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
753     { X86::VPROTBri,           X86::VPROTBmi,         0 },
754     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
755     { X86::VPROTDri,           X86::VPROTDmi,         0 },
756     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
757     { X86::VPROTQri,           X86::VPROTQmi,         0 },
758     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
759     { X86::VPROTWri,           X86::VPROTWmi,         0 },
760     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
761     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
762     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
763     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
764     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
765     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
766     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
767     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
768     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
769 
770     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
771     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
772     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
773     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
774     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
775     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
776     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
777     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
778     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
779     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
780     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
781     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
782     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
783     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
784     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
785     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
786     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
787     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
788     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
789     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
790     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
791     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
792     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
793     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
794     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
795     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
796     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
797     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
798     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
799     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
800     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
801     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
802     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
803     { X86::RORX32ri,        X86::RORX32mi,            0 },
804     { X86::RORX64ri,        X86::RORX64mi,            0 },
805     { X86::SARX32rr,        X86::SARX32rm,            0 },
806     { X86::SARX64rr,        X86::SARX64rm,            0 },
807     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
808     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
809     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
810     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
811     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
812     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
813     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
814     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
815     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
816     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
817     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
818 
819     // AVX-512 foldable instructions
820     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
821     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
822     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
823     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
824     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
825     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
826     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
827     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
828     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
829     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
830     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
831     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
832     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
833     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
834     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
835     { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm,     TB_NO_REVERSE },
836     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
837     { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm,     TB_NO_REVERSE },
838 
839     // AVX-512 foldable instructions (256-bit versions)
840     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
841     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
842     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
843     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
844     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
845     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
846     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
847     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
848     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
849     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
850     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
851     { X86::VBROADCASTSSZ256r_s,  X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
852     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
853     { X86::VBROADCASTSDZ256r_s,  X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
854 
855     // AVX-512 foldable instructions (128-bit versions)
856     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
857     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
858     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
859     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
860     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
861     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
862     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
863     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
864     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
865     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
866     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
867     { X86::VBROADCASTSSZ128r_s,  X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
868     // F16C foldable instructions
869     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
870     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
871 
872     // AES foldable instructions
873     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
874     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
875     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
876     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
877   };
878 
879   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
880     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
881                   Entry.RegOp, Entry.MemOp,
882                   // Index 1, folded load
883                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
884   }
885 
886   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
887     { X86::ADC32rr,         X86::ADC32rm,       0 },
888     { X86::ADC64rr,         X86::ADC64rm,       0 },
889     { X86::ADD16rr,         X86::ADD16rm,       0 },
890     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
891     { X86::ADD32rr,         X86::ADD32rm,       0 },
892     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
893     { X86::ADD64rr,         X86::ADD64rm,       0 },
894     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
895     { X86::ADD8rr,          X86::ADD8rm,        0 },
896     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
897     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
898     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
899     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
900     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
901     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
902     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
903     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
904     { X86::AND16rr,         X86::AND16rm,       0 },
905     { X86::AND32rr,         X86::AND32rm,       0 },
906     { X86::AND64rr,         X86::AND64rm,       0 },
907     { X86::AND8rr,          X86::AND8rm,        0 },
908     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
909     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
910     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
911     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
912     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
913     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
914     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
915     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
916     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
917     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
918     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
919     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
920     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
921     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
922     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
923     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
924     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
925     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
926     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
927     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
928     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
929     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
930     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
931     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
932     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
933     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
934     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
935     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
936     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
937     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
938     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
939     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
940     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
941     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
942     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
943     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
944     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
945     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
946     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
947     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
948     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
949     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
950     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
951     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
952     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
953     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
954     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
955     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
956     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
957     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
958     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
959     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
960     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
961     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
962     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
963     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
964     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
965     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
966     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
967     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
968     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
969     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
970     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
971     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
972     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
973     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
974     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
975     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
976     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
977     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
978 
979     // Do not fold Fs* scalar logical op loads because there are no scalar
980     // load variants for these instructions. When folded, the load is required
981     // to be 128-bits, so the load size would not match.
982 
983     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
984     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
985     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
986     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
987     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
988     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
989     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
990     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
991     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
992     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
993     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
994     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
995     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
996     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
997     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
998     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
999     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
1000     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
1001     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
1002     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
1003     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
1004     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
1005     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
1006     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
1007     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
1008     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
1009     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
1010     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1011     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
1012     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1013     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1014     { X86::MINSDrr,         X86::MINSDrm,       0 },
1015     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1016     { X86::MINSSrr,         X86::MINSSrm,       0 },
1017     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1018     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1019     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1020     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1021     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1022     { X86::MULSDrr,         X86::MULSDrm,       0 },
1023     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1024     { X86::MULSSrr,         X86::MULSSrm,       0 },
1025     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1026     { X86::OR16rr,          X86::OR16rm,        0 },
1027     { X86::OR32rr,          X86::OR32rm,        0 },
1028     { X86::OR64rr,          X86::OR64rm,        0 },
1029     { X86::OR8rr,           X86::OR8rm,         0 },
1030     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1031     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1032     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1033     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1034     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1035     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1036     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1037     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1038     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1039     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1040     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1041     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1042     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1043     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1044     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1045     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1046     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1047     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1048     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1049     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1050     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1051     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1052     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1053     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1054     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1055     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1056     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1057     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1058     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1059     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1060     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1061     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1062     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1063     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1064     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1065     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1066     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1067     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1068     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1069     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1070     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1071     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1072     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1073     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1074     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1075     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1076     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1077     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1078     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1079     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1080     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1081     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1082     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1083     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1084     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1085     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1086     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1087     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1088     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1089     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1090     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1091     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1092     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1093     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1094     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1095     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1096     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1097     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1098     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1099     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1100     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1101     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1102     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1103     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1104     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1105     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1106     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1107     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1108     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1109     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1110     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1111     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1112     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1113     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1114     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1115     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1116     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1117     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1118     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1119     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1120     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1121     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1122     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1123     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1124     { X86::SBB32rr,         X86::SBB32rm,       0 },
1125     { X86::SBB64rr,         X86::SBB64rm,       0 },
1126     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1127     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1128     { X86::SUB16rr,         X86::SUB16rm,       0 },
1129     { X86::SUB32rr,         X86::SUB32rm,       0 },
1130     { X86::SUB64rr,         X86::SUB64rm,       0 },
1131     { X86::SUB8rr,          X86::SUB8rm,        0 },
1132     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1133     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1134     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1135     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1136     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1137     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1138     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1139     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1140     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1141     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1142     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1143     { X86::XOR16rr,         X86::XOR16rm,       0 },
1144     { X86::XOR32rr,         X86::XOR32rm,       0 },
1145     { X86::XOR64rr,         X86::XOR64rm,       0 },
1146     { X86::XOR8rr,          X86::XOR8rm,        0 },
1147     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1148     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1149 
1150     // MMX version of foldable instructions
1151     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1152     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1153     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1154     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1155     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1156     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1157     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1158     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1159     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1160     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1161     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1162     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1163     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1164     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1165     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1166     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1167     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1168     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1169     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1170     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1171     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1172     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1173     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1174     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1175     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1176     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1177     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1178     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1179     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1180     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1181     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1182     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1183     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1184     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1185     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1186     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1187     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1188     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1189     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1190     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1191     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1192     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1193     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1194     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1195     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1196     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1197     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1198     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1199     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1200     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1201     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1202     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1203     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1204     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1205     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1206     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1207     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1208     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1209     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1210     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1211     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1212     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1213     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1214     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1215     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1216     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1217     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1218     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1219     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1220     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1221 
1222     // 3DNow! version of foldable instructions
1223     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1224     { X86::PFACCrr,           X86::PFACCrm,           0 },
1225     { X86::PFADDrr,           X86::PFADDrm,           0 },
1226     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1227     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1228     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1229     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1230     { X86::PFMINrr,           X86::PFMINrm,           0 },
1231     { X86::PFMULrr,           X86::PFMULrm,           0 },
1232     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1233     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1234     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1235     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1236     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1237     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1238     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1239     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1240 
1241     // AVX 128-bit versions of foldable instructions
1242     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1243     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1244     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1245     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1246     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1247     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1248     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1249     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1250     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1251     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1252     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1253     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1254     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1255     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1256     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1257     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1258     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1259     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1260     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1261     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1262     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1263     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1264     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1265     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1266     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1267     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1268     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1269     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1270     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1271     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1272     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1273     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1274     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1275     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1276     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1277     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1278     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1279     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1280     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1281     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1282     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1283     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1284     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1285     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1286     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1287     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1288     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1289     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1290     // Do not fold VFs* loads because there are no scalar load variants for
1291     // these instructions. When folded, the load is required to be 128-bits, so
1292     // the load size would not match.
1293     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1294     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1295     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1296     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1297     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1298     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1299     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1300     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1301     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1302     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1303     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1304     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1305     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1306     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1307     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1308     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1309     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1310     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1311     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1312     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1313     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1314     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1315     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1316     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1317     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1318     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1319     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1320     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1321     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1322     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1323     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1324     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1325     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1326     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1327     { X86::VORPDrr,           X86::VORPDrm,            0 },
1328     { X86::VORPSrr,           X86::VORPSrm,            0 },
1329     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1330     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1331     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1332     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1333     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1334     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1335     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1336     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1337     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1338     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1339     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1340     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1341     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1342     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1343     { X86::VPANDrr,           X86::VPANDrm,            0 },
1344     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1345     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1346     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1347     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1348     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1349     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1350     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1351     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1352     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1353     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1354     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1355     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1356     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1357     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1358     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1359     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1360     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1361     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1362     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1363     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1364     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1365     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1366     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1367     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1368     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1369     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1370     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1371     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1372     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1373     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1374     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1375     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1376     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1377     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1378     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1379     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1380     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1381     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1382     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1383     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1384     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1385     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1386     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1387     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1388     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1389     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1390     { X86::VPORrr,            X86::VPORrm,             0 },
1391     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1392     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1393     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1394     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1395     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1396     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1397     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1398     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1399     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1400     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1401     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1402     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1403     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1404     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1405     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1406     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1407     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1408     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1409     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1410     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1411     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1412     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1413     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1414     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1415     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1416     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1417     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1418     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1419     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1420     { X86::VPXORrr,           X86::VPXORrm,            0 },
1421     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1422     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1423     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1424     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1425     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1426     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1427     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1428     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1429     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1430     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1431     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1432     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1433     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1434     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1435     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1436     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1437 
1438     // AVX 256-bit foldable instructions
1439     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1440     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1441     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1442     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1443     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1444     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1445     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1446     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1447     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1448     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1449     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1450     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1451     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1452     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1453     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1454     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1455     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1456     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1457     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1458     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1459     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1460     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1461     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1462     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1463     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1464     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1465     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1466     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1467     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1468     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1469     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1470     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1471     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1472     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1473     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1474     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1475     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1476     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1477     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1478     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1479     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1480     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1481     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1482 
1483     // AVX2 foldable instructions
1484     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1485     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1486     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1487     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1488     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1489     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1490     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1491     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1492     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1493     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1494     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1495     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1496     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1497     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1498     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1499     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1500     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1501     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1502     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1503     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1504     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1505     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1506     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1507     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1508     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1509     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1510     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1511     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1512     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1513     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1514     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1515     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1516     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1517     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1518     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1519     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1520     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1521     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1522     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1523     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1524     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1525     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1526     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1527     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1528     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1529     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1530     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1531     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1532     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1533     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1534     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1535     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1536     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1537     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1538     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1539     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1540     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1541     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1542     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1543     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1544     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1545     { X86::VPORYrr,           X86::VPORYrm,            0 },
1546     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1547     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1548     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1549     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1550     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1551     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1552     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1553     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1554     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1555     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1556     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1557     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1558     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1559     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1560     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1561     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1562     { X86::VPSRAVD_Intrr,     X86::VPSRAVD_Intrm,      0 },
1563     { X86::VPSRAVD_IntYrr,    X86::VPSRAVD_IntYrm,     0 },
1564     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1565     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1566     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1567     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1568     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1569     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1570     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1571     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1572     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1573     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1574     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1575     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1576     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1577     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1578     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1579     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1580     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1581     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1582     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1583     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1584     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1585     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1586     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1587     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1588 
1589     // FMA4 foldable patterns
1590     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1591     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1592     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1593     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1594     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_NONE },
1595     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_NONE },
1596     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1597     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1598     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1599     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1600     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_NONE },
1601     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_NONE },
1602     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1603     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1604     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1605     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1606     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_NONE },
1607     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_NONE },
1608     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1609     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1610     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1611     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1612     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_NONE },
1613     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_NONE },
1614     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1615     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1616     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_NONE },
1617     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_NONE },
1618     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1619     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1620     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_NONE },
1621     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_NONE },
1622 
1623     // XOP foldable instructions
1624     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1625     { X86::VPCMOVrrrY,        X86::VPCMOVrmrY,          0 },
1626     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1627     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1628     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1629     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1630     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1631     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1632     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1633     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1634     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1635     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1636     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1637     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1638     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1639     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1640     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1641     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1642     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1643     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1644     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1645     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1646     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1647     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1648     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1649     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1650     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1651     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1652     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1653     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1654     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1655     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1656     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1657     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1658     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1659     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1660     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1661     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1662     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1663 
1664     // BMI/BMI2 foldable instructions
1665     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1666     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1667     { X86::MULX32rr,          X86::MULX32rm,            0 },
1668     { X86::MULX64rr,          X86::MULX64rm,            0 },
1669     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1670     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1671     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1672     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1673 
1674     // ADX foldable instructions
1675     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1676     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1677     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1678     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1679 
1680     // AVX-512 foldable instructions
1681     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1682     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1683     { X86::VADDSSZrr,         X86::VADDSSZrm,           0 },
1684     { X86::VADDSSZrr_Int,     X86::VADDSSZrm_Int,       0 },
1685     { X86::VADDSDZrr,         X86::VADDSDZrm,           0 },
1686     { X86::VADDSDZrr_Int,     X86::VADDSDZrm_Int,       0 },
1687     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1688     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1689     { X86::VSUBSSZrr,         X86::VSUBSSZrm,           0 },
1690     { X86::VSUBSSZrr_Int,     X86::VSUBSSZrm_Int,       0 },
1691     { X86::VSUBSDZrr,         X86::VSUBSDZrm,           0 },
1692     { X86::VSUBSDZrr_Int,     X86::VSUBSDZrm_Int,       0 },
1693     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1694     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1695     { X86::VMULSSZrr,         X86::VMULSSZrm,           0 },
1696     { X86::VMULSSZrr_Int,     X86::VMULSSZrm_Int,       0 },
1697     { X86::VMULSDZrr,         X86::VMULSDZrm,           0 },
1698     { X86::VMULSDZrr_Int,     X86::VMULSDZrm_Int,       0 },
1699     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1700     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1701     { X86::VDIVSSZrr,         X86::VDIVSSZrm,           0 },
1702     { X86::VDIVSSZrr_Int,     X86::VDIVSSZrm_Int,       0 },
1703     { X86::VDIVSDZrr,         X86::VDIVSDZrm,           0 },
1704     { X86::VDIVSDZrr_Int,     X86::VDIVSDZrm_Int,       0 },
1705     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1706     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1707     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1708     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1709     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1710     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1711     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1712     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1713     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1714     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1715     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1716     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1717     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1718     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1719     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1720     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1721     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1722     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1723     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1724     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1725     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1726     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1727     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1728     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1729     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1730     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1731     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1732     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1733     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1734     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1735     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1736 
1737     // AVX-512{F,VL} foldable instructions
1738     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1739     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1740     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1741 
1742     // AVX-512{F,VL} foldable instructions
1743     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1744     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1745     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1746     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1747 
1748     // AES foldable instructions
1749     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1750     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1751     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1752     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1753     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1754     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1755     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1756     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1757 
1758     // SHA foldable instructions
1759     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1760     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1761     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1762     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1763     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1764     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1765     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1766   };
1767 
1768   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1769     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1770                   Entry.RegOp, Entry.MemOp,
1771                   // Index 2, folded load
1772                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1773   }
1774 
1775   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1776     // FMA foldable instructions
1777     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1778     { X86::VFMADDSSr231r_Int,     X86::VFMADDSSr231m_Int,     TB_ALIGN_NONE },
1779     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1780     { X86::VFMADDSDr231r_Int,     X86::VFMADDSDr231m_Int,     TB_ALIGN_NONE },
1781     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1782     { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     TB_ALIGN_NONE },
1783     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1784     { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     TB_ALIGN_NONE },
1785     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1786     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     TB_ALIGN_NONE },
1787     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1788     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     TB_ALIGN_NONE },
1789 
1790     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1791     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1792     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1793     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1794     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1795     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1796     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1797     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1798     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1799     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1800     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1801     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1802 
1803     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1804     { X86::VFNMADDSSr231r_Int,    X86::VFNMADDSSr231m_Int,    TB_ALIGN_NONE },
1805     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1806     { X86::VFNMADDSDr231r_Int,    X86::VFNMADDSDr231m_Int,    TB_ALIGN_NONE },
1807     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1808     { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    TB_ALIGN_NONE },
1809     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1810     { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    TB_ALIGN_NONE },
1811     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1812     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    TB_ALIGN_NONE },
1813     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1814     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    TB_ALIGN_NONE },
1815 
1816     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1817     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1818     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1819     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1820     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1821     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1822     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1823     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1824     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1825     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1826     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1827     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1828 
1829     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1830     { X86::VFMSUBSSr231r_Int,     X86::VFMSUBSSr231m_Int,     TB_ALIGN_NONE },
1831     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1832     { X86::VFMSUBSDr231r_Int,     X86::VFMSUBSDr231m_Int,     TB_ALIGN_NONE },
1833     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1834     { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     TB_ALIGN_NONE },
1835     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1836     { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     TB_ALIGN_NONE },
1837     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1838     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     TB_ALIGN_NONE },
1839     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1840     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     TB_ALIGN_NONE },
1841 
1842     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1843     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1844     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1845     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1846     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1847     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1848     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1849     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1850     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1851     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1852     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1853     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1854 
1855     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1856     { X86::VFNMSUBSSr231r_Int,    X86::VFNMSUBSSr231m_Int,    TB_ALIGN_NONE },
1857     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1858     { X86::VFNMSUBSDr231r_Int,    X86::VFNMSUBSDr231m_Int,    TB_ALIGN_NONE },
1859     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1860     { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    TB_ALIGN_NONE },
1861     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1862     { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    TB_ALIGN_NONE },
1863     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1864     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    TB_ALIGN_NONE },
1865     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1866     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    TB_ALIGN_NONE },
1867 
1868     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1869     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1870     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1871     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1872     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1873     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1874     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1875     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1876     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1877     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1878     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1879     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1880 
1881     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1882     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1883     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1884     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1885     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1886     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1887     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1888     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1889     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1890     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1891     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1892     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1893 
1894     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1895     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1896     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1897     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1898     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1899     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1900     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1901     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1902     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1903     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1904     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1905     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1906 
1907     // FMA4 foldable patterns
1908     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
1909     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
1910     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
1911     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
1912     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_NONE },
1913     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_NONE },
1914     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
1915     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
1916     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
1917     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
1918     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_NONE },
1919     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_NONE },
1920     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
1921     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
1922     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
1923     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
1924     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_NONE },
1925     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_NONE },
1926     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
1927     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
1928     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
1929     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
1930     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_NONE },
1931     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_NONE },
1932     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
1933     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
1934     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_NONE },
1935     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_NONE },
1936     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
1937     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
1938     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_NONE },
1939     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_NONE },
1940 
1941     // XOP foldable instructions
1942     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
1943     { X86::VPCMOVrrrY,            X86::VPCMOVrrmY,            0 },
1944     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1945     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1946     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1947     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1948     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
1949 
1950     // AVX-512 VPERMI instructions with 3 source operands.
1951     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1952     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1953     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1954     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1955     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1956     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1957     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1958     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1959     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1960     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1961     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1962     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1963     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1964      // AVX-512 arithmetic instructions
1965     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1966     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1967     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1968     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1969     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1970     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1971     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1972     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1973     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1974     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1975     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1976     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1977     // AVX-512{F,VL} arithmetic instructions 256-bit
1978     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1979     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1980     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1981     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1982     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1983     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1984     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1985     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1986     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1987     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1988     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1989     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1990     // AVX-512{F,VL} arithmetic instructions 128-bit
1991     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1992     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1993     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1994     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1995     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1996     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1997     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1998     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1999     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
2000     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
2001     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
2002     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
2003   };
2004 
2005   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
2006     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2007                   Entry.RegOp, Entry.MemOp,
2008                   // Index 3, folded load
2009                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
2010   }
2011 
2012   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
2013      // AVX-512 foldable instructions
2014     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
2015     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
2016     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
2017     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
2018     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
2019     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
2020     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
2021     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
2022     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
2023     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
2024     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
2025     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
2026     // AVX-512{F,VL} foldable instructions 256-bit
2027     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
2028     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
2029     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
2030     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
2031     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
2032     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
2033     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
2034     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
2035     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
2036     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2037     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2038     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2039     // AVX-512{F,VL} foldable instructions 128-bit
2040     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2041     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2042     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2043     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2044     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2045     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2046     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2047     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2048     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2049     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2050     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2051     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
2052   };
2053 
2054   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2055     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2056                   Entry.RegOp, Entry.MemOp,
2057                   // Index 4, folded load
2058                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2059   }
2060 }
2061 
2062 void
2063 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2064                             MemOp2RegOpTableType &M2RTable,
2065                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
2066     if ((Flags & TB_NO_FORWARD) == 0) {
2067       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2068       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2069     }
2070     if ((Flags & TB_NO_REVERSE) == 0) {
2071       assert(!M2RTable.count(MemOp) &&
2072            "Duplicated entries in unfolding maps?");
2073       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2074     }
2075 }
2076 
2077 bool
2078 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2079                                     unsigned &SrcReg, unsigned &DstReg,
2080                                     unsigned &SubIdx) const {
2081   switch (MI.getOpcode()) {
2082   default: break;
2083   case X86::MOVSX16rr8:
2084   case X86::MOVZX16rr8:
2085   case X86::MOVSX32rr8:
2086   case X86::MOVZX32rr8:
2087   case X86::MOVSX64rr8:
2088     if (!Subtarget.is64Bit())
2089       // It's not always legal to reference the low 8-bit of the larger
2090       // register in 32-bit mode.
2091       return false;
2092   case X86::MOVSX32rr16:
2093   case X86::MOVZX32rr16:
2094   case X86::MOVSX64rr16:
2095   case X86::MOVSX64rr32: {
2096     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2097       // Be conservative.
2098       return false;
2099     SrcReg = MI.getOperand(1).getReg();
2100     DstReg = MI.getOperand(0).getReg();
2101     switch (MI.getOpcode()) {
2102     default: llvm_unreachable("Unreachable!");
2103     case X86::MOVSX16rr8:
2104     case X86::MOVZX16rr8:
2105     case X86::MOVSX32rr8:
2106     case X86::MOVZX32rr8:
2107     case X86::MOVSX64rr8:
2108       SubIdx = X86::sub_8bit;
2109       break;
2110     case X86::MOVSX32rr16:
2111     case X86::MOVZX32rr16:
2112     case X86::MOVSX64rr16:
2113       SubIdx = X86::sub_16bit;
2114       break;
2115     case X86::MOVSX64rr32:
2116       SubIdx = X86::sub_32bit;
2117       break;
2118     }
2119     return true;
2120   }
2121   }
2122   return false;
2123 }
2124 
2125 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2126   const MachineFunction *MF = MI.getParent()->getParent();
2127   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2128 
2129   if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2130       MI.getOpcode() == getCallFrameDestroyOpcode()) {
2131     unsigned StackAlign = TFI->getStackAlignment();
2132     int SPAdj =
2133         (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
2134 
2135     SPAdj -= MI.getOperand(1).getImm();
2136 
2137     if (MI.getOpcode() == getCallFrameSetupOpcode())
2138       return SPAdj;
2139     else
2140       return -SPAdj;
2141   }
2142 
2143   // To know whether a call adjusts the stack, we need information
2144   // that is bound to the following ADJCALLSTACKUP pseudo.
2145   // Look for the next ADJCALLSTACKUP that follows the call.
2146   if (MI.isCall()) {
2147     const MachineBasicBlock *MBB = MI.getParent();
2148     auto I = ++MachineBasicBlock::const_iterator(MI);
2149     for (auto E = MBB->end(); I != E; ++I) {
2150       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2151           I->isCall())
2152         break;
2153     }
2154 
2155     // If we could not find a frame destroy opcode, then it has already
2156     // been simplified, so we don't care.
2157     if (I->getOpcode() != getCallFrameDestroyOpcode())
2158       return 0;
2159 
2160     return -(I->getOperand(1).getImm());
2161   }
2162 
2163   // Currently handle only PUSHes we can reasonably expect to see
2164   // in call sequences
2165   switch (MI.getOpcode()) {
2166   default:
2167     return 0;
2168   case X86::PUSH32i8:
2169   case X86::PUSH32r:
2170   case X86::PUSH32rmm:
2171   case X86::PUSH32rmr:
2172   case X86::PUSHi32:
2173     return 4;
2174   case X86::PUSH64i8:
2175   case X86::PUSH64r:
2176   case X86::PUSH64rmm:
2177   case X86::PUSH64rmr:
2178   case X86::PUSH64i32:
2179     return 8;
2180   }
2181 }
2182 
2183 /// Return true and the FrameIndex if the specified
2184 /// operand and follow operands form a reference to the stack frame.
2185 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
2186                                   int &FrameIndex) const {
2187   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2188       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2189       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2190       MI.getOperand(Op + X86::AddrDisp).isImm() &&
2191       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2192       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2193       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2194     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
2195     return true;
2196   }
2197   return false;
2198 }
2199 
2200 static bool isFrameLoadOpcode(int Opcode) {
2201   switch (Opcode) {
2202   default:
2203     return false;
2204   case X86::MOV8rm:
2205   case X86::MOV16rm:
2206   case X86::MOV32rm:
2207   case X86::MOV64rm:
2208   case X86::LD_Fp64m:
2209   case X86::MOVSSrm:
2210   case X86::MOVSDrm:
2211   case X86::MOVAPSrm:
2212   case X86::MOVUPSrm:
2213   case X86::MOVAPDrm:
2214   case X86::MOVUPDrm:
2215   case X86::MOVDQArm:
2216   case X86::MOVDQUrm:
2217   case X86::VMOVSSrm:
2218   case X86::VMOVSDrm:
2219   case X86::VMOVAPSrm:
2220   case X86::VMOVUPSrm:
2221   case X86::VMOVAPDrm:
2222   case X86::VMOVUPDrm:
2223   case X86::VMOVDQArm:
2224   case X86::VMOVDQUrm:
2225   case X86::VMOVUPSYrm:
2226   case X86::VMOVAPSYrm:
2227   case X86::VMOVUPDYrm:
2228   case X86::VMOVAPDYrm:
2229   case X86::VMOVDQUYrm:
2230   case X86::VMOVDQAYrm:
2231   case X86::MMX_MOVD64rm:
2232   case X86::MMX_MOVQ64rm:
2233   case X86::VMOVSSZrm:
2234   case X86::VMOVSDZrm:
2235   case X86::VMOVAPSZrm:
2236   case X86::VMOVAPSZ128rm:
2237   case X86::VMOVAPSZ256rm:
2238   case X86::VMOVUPSZrm:
2239   case X86::VMOVUPSZ128rm:
2240   case X86::VMOVUPSZ256rm:
2241   case X86::VMOVAPDZrm:
2242   case X86::VMOVAPDZ128rm:
2243   case X86::VMOVAPDZ256rm:
2244   case X86::VMOVUPDZrm:
2245   case X86::VMOVUPDZ128rm:
2246   case X86::VMOVUPDZ256rm:
2247   case X86::VMOVDQA32Zrm:
2248   case X86::VMOVDQA32Z128rm:
2249   case X86::VMOVDQA32Z256rm:
2250   case X86::VMOVDQU32Zrm:
2251   case X86::VMOVDQU32Z128rm:
2252   case X86::VMOVDQU32Z256rm:
2253   case X86::VMOVDQA64Zrm:
2254   case X86::VMOVDQA64Z128rm:
2255   case X86::VMOVDQA64Z256rm:
2256   case X86::VMOVDQU64Zrm:
2257   case X86::VMOVDQU64Z128rm:
2258   case X86::VMOVDQU64Z256rm:
2259   case X86::VMOVDQU8Zrm:
2260   case X86::VMOVDQU8Z128rm:
2261   case X86::VMOVDQU8Z256rm:
2262   case X86::VMOVDQU16Zrm:
2263   case X86::VMOVDQU16Z128rm:
2264   case X86::VMOVDQU16Z256rm:
2265   case X86::KMOVBkm:
2266   case X86::KMOVWkm:
2267   case X86::KMOVDkm:
2268   case X86::KMOVQkm:
2269     return true;
2270   }
2271 }
2272 
2273 static bool isFrameStoreOpcode(int Opcode) {
2274   switch (Opcode) {
2275   default: break;
2276   case X86::MOV8mr:
2277   case X86::MOV16mr:
2278   case X86::MOV32mr:
2279   case X86::MOV64mr:
2280   case X86::ST_FpP64m:
2281   case X86::MOVSSmr:
2282   case X86::MOVSDmr:
2283   case X86::MOVAPSmr:
2284   case X86::MOVUPSmr:
2285   case X86::MOVAPDmr:
2286   case X86::MOVUPDmr:
2287   case X86::MOVDQAmr:
2288   case X86::MOVDQUmr:
2289   case X86::VMOVSSmr:
2290   case X86::VMOVSDmr:
2291   case X86::VMOVAPSmr:
2292   case X86::VMOVUPSmr:
2293   case X86::VMOVAPDmr:
2294   case X86::VMOVUPDmr:
2295   case X86::VMOVDQAmr:
2296   case X86::VMOVDQUmr:
2297   case X86::VMOVUPSYmr:
2298   case X86::VMOVAPSYmr:
2299   case X86::VMOVUPDYmr:
2300   case X86::VMOVAPDYmr:
2301   case X86::VMOVDQUYmr:
2302   case X86::VMOVDQAYmr:
2303   case X86::VMOVSSZmr:
2304   case X86::VMOVSDZmr:
2305   case X86::VMOVUPSZmr:
2306   case X86::VMOVUPSZ128mr:
2307   case X86::VMOVUPSZ256mr:
2308   case X86::VMOVAPSZmr:
2309   case X86::VMOVAPSZ128mr:
2310   case X86::VMOVAPSZ256mr:
2311   case X86::VMOVUPDZmr:
2312   case X86::VMOVUPDZ128mr:
2313   case X86::VMOVUPDZ256mr:
2314   case X86::VMOVAPDZmr:
2315   case X86::VMOVAPDZ128mr:
2316   case X86::VMOVAPDZ256mr:
2317   case X86::VMOVDQA32Zmr:
2318   case X86::VMOVDQA32Z128mr:
2319   case X86::VMOVDQA32Z256mr:
2320   case X86::VMOVDQU32Zmr:
2321   case X86::VMOVDQU32Z128mr:
2322   case X86::VMOVDQU32Z256mr:
2323   case X86::VMOVDQA64Zmr:
2324   case X86::VMOVDQA64Z128mr:
2325   case X86::VMOVDQA64Z256mr:
2326   case X86::VMOVDQU64Zmr:
2327   case X86::VMOVDQU64Z128mr:
2328   case X86::VMOVDQU64Z256mr:
2329   case X86::VMOVDQU8Zmr:
2330   case X86::VMOVDQU8Z128mr:
2331   case X86::VMOVDQU8Z256mr:
2332   case X86::VMOVDQU16Zmr:
2333   case X86::VMOVDQU16Z128mr:
2334   case X86::VMOVDQU16Z256mr:
2335   case X86::MMX_MOVD64mr:
2336   case X86::MMX_MOVQ64mr:
2337   case X86::MMX_MOVNTQmr:
2338   case X86::KMOVBmk:
2339   case X86::KMOVWmk:
2340   case X86::KMOVDmk:
2341   case X86::KMOVQmk:
2342     return true;
2343   }
2344   return false;
2345 }
2346 
2347 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
2348                                            int &FrameIndex) const {
2349   if (isFrameLoadOpcode(MI.getOpcode()))
2350     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2351       return MI.getOperand(0).getReg();
2352   return 0;
2353 }
2354 
2355 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
2356                                                  int &FrameIndex) const {
2357   if (isFrameLoadOpcode(MI.getOpcode())) {
2358     unsigned Reg;
2359     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2360       return Reg;
2361     // Check for post-frame index elimination operations
2362     const MachineMemOperand *Dummy;
2363     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2364   }
2365   return 0;
2366 }
2367 
2368 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
2369                                           int &FrameIndex) const {
2370   if (isFrameStoreOpcode(MI.getOpcode()))
2371     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2372         isFrameOperand(MI, 0, FrameIndex))
2373       return MI.getOperand(X86::AddrNumOperands).getReg();
2374   return 0;
2375 }
2376 
2377 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
2378                                                 int &FrameIndex) const {
2379   if (isFrameStoreOpcode(MI.getOpcode())) {
2380     unsigned Reg;
2381     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2382       return Reg;
2383     // Check for post-frame index elimination operations
2384     const MachineMemOperand *Dummy;
2385     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2386   }
2387   return 0;
2388 }
2389 
2390 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2391 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2392   // Don't waste compile time scanning use-def chains of physregs.
2393   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2394     return false;
2395   bool isPICBase = false;
2396   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2397          E = MRI.def_instr_end(); I != E; ++I) {
2398     MachineInstr *DefMI = &*I;
2399     if (DefMI->getOpcode() != X86::MOVPC32r)
2400       return false;
2401     assert(!isPICBase && "More than one PIC base?");
2402     isPICBase = true;
2403   }
2404   return isPICBase;
2405 }
2406 
2407 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2408                                                      AliasAnalysis *AA) const {
2409   switch (MI.getOpcode()) {
2410   default: break;
2411   case X86::MOV8rm:
2412   case X86::MOV16rm:
2413   case X86::MOV32rm:
2414   case X86::MOV64rm:
2415   case X86::LD_Fp64m:
2416   case X86::MOVSSrm:
2417   case X86::MOVSDrm:
2418   case X86::MOVAPSrm:
2419   case X86::MOVUPSrm:
2420   case X86::MOVAPDrm:
2421   case X86::MOVDQArm:
2422   case X86::MOVDQUrm:
2423   case X86::VMOVSSrm:
2424   case X86::VMOVSDrm:
2425   case X86::VMOVAPSrm:
2426   case X86::VMOVUPSrm:
2427   case X86::VMOVAPDrm:
2428   case X86::VMOVDQArm:
2429   case X86::VMOVDQUrm:
2430   case X86::VMOVAPSYrm:
2431   case X86::VMOVUPSYrm:
2432   case X86::VMOVAPDYrm:
2433   case X86::VMOVDQAYrm:
2434   case X86::VMOVDQUYrm:
2435   case X86::MMX_MOVD64rm:
2436   case X86::MMX_MOVQ64rm:
2437   case X86::FsVMOVAPSrm:
2438   case X86::FsVMOVAPDrm:
2439   case X86::FsMOVAPSrm:
2440   case X86::FsMOVAPDrm:
2441   // AVX-512
2442   case X86::VMOVAPDZ128rm:
2443   case X86::VMOVAPDZ256rm:
2444   case X86::VMOVAPDZrm:
2445   case X86::VMOVAPSZ128rm:
2446   case X86::VMOVAPSZ256rm:
2447   case X86::VMOVAPSZrm:
2448   case X86::VMOVDQA32Z128rm:
2449   case X86::VMOVDQA32Z256rm:
2450   case X86::VMOVDQA32Zrm:
2451   case X86::VMOVDQA64Z128rm:
2452   case X86::VMOVDQA64Z256rm:
2453   case X86::VMOVDQA64Zrm:
2454   case X86::VMOVDQU16Z128rm:
2455   case X86::VMOVDQU16Z256rm:
2456   case X86::VMOVDQU16Zrm:
2457   case X86::VMOVDQU32Z128rm:
2458   case X86::VMOVDQU32Z256rm:
2459   case X86::VMOVDQU32Zrm:
2460   case X86::VMOVDQU64Z128rm:
2461   case X86::VMOVDQU64Z256rm:
2462   case X86::VMOVDQU64Zrm:
2463   case X86::VMOVDQU8Z128rm:
2464   case X86::VMOVDQU8Z256rm:
2465   case X86::VMOVDQU8Zrm:
2466   case X86::VMOVUPSZ128rm:
2467   case X86::VMOVUPSZ256rm:
2468   case X86::VMOVUPSZrm: {
2469     // Loads from constant pools are trivially rematerializable.
2470     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2471         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2472         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2473         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2474         MI.isInvariantLoad(AA)) {
2475       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2476       if (BaseReg == 0 || BaseReg == X86::RIP)
2477         return true;
2478       // Allow re-materialization of PIC load.
2479       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
2480         return false;
2481       const MachineFunction &MF = *MI.getParent()->getParent();
2482       const MachineRegisterInfo &MRI = MF.getRegInfo();
2483       return regIsPICBase(BaseReg, MRI);
2484     }
2485     return false;
2486   }
2487 
2488   case X86::LEA32r:
2489   case X86::LEA64r: {
2490     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2491         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2492         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2493         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
2494       // lea fi#, lea GV, etc. are all rematerializable.
2495       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
2496         return true;
2497       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2498       if (BaseReg == 0)
2499         return true;
2500       // Allow re-materialization of lea PICBase + x.
2501       const MachineFunction &MF = *MI.getParent()->getParent();
2502       const MachineRegisterInfo &MRI = MF.getRegInfo();
2503       return regIsPICBase(BaseReg, MRI);
2504     }
2505     return false;
2506   }
2507   }
2508 
2509   // All other instructions marked M_REMATERIALIZABLE are always trivially
2510   // rematerializable.
2511   return true;
2512 }
2513 
2514 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2515                                          MachineBasicBlock::iterator I) const {
2516   MachineBasicBlock::iterator E = MBB.end();
2517 
2518   // For compile time consideration, if we are not able to determine the
2519   // safety after visiting 4 instructions in each direction, we will assume
2520   // it's not safe.
2521   MachineBasicBlock::iterator Iter = I;
2522   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2523     bool SeenDef = false;
2524     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2525       MachineOperand &MO = Iter->getOperand(j);
2526       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2527         SeenDef = true;
2528       if (!MO.isReg())
2529         continue;
2530       if (MO.getReg() == X86::EFLAGS) {
2531         if (MO.isUse())
2532           return false;
2533         SeenDef = true;
2534       }
2535     }
2536 
2537     if (SeenDef)
2538       // This instruction defines EFLAGS, no need to look any further.
2539       return true;
2540     ++Iter;
2541     // Skip over DBG_VALUE.
2542     while (Iter != E && Iter->isDebugValue())
2543       ++Iter;
2544   }
2545 
2546   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2547   // live in.
2548   if (Iter == E) {
2549     for (MachineBasicBlock *S : MBB.successors())
2550       if (S->isLiveIn(X86::EFLAGS))
2551         return false;
2552     return true;
2553   }
2554 
2555   MachineBasicBlock::iterator B = MBB.begin();
2556   Iter = I;
2557   for (unsigned i = 0; i < 4; ++i) {
2558     // If we make it to the beginning of the block, it's safe to clobber
2559     // EFLAGS iff EFLAGS is not live-in.
2560     if (Iter == B)
2561       return !MBB.isLiveIn(X86::EFLAGS);
2562 
2563     --Iter;
2564     // Skip over DBG_VALUE.
2565     while (Iter != B && Iter->isDebugValue())
2566       --Iter;
2567 
2568     bool SawKill = false;
2569     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2570       MachineOperand &MO = Iter->getOperand(j);
2571       // A register mask may clobber EFLAGS, but we should still look for a
2572       // live EFLAGS def.
2573       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2574         SawKill = true;
2575       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2576         if (MO.isDef()) return MO.isDead();
2577         if (MO.isKill()) SawKill = true;
2578       }
2579     }
2580 
2581     if (SawKill)
2582       // This instruction kills EFLAGS and doesn't redefine it, so
2583       // there's no need to look further.
2584       return true;
2585   }
2586 
2587   // Conservative answer.
2588   return false;
2589 }
2590 
2591 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2592                                  MachineBasicBlock::iterator I,
2593                                  unsigned DestReg, unsigned SubIdx,
2594                                  const MachineInstr &Orig,
2595                                  const TargetRegisterInfo &TRI) const {
2596   bool ClobbersEFLAGS = false;
2597   for (const MachineOperand &MO : Orig.operands()) {
2598     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2599       ClobbersEFLAGS = true;
2600       break;
2601     }
2602   }
2603 
2604   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2605     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2606     // effects.
2607     int Value;
2608     switch (Orig.getOpcode()) {
2609     case X86::MOV32r0:  Value = 0; break;
2610     case X86::MOV32r1:  Value = 1; break;
2611     case X86::MOV32r_1: Value = -1; break;
2612     default:
2613       llvm_unreachable("Unexpected instruction!");
2614     }
2615 
2616     const DebugLoc &DL = Orig.getDebugLoc();
2617     BuildMI(MBB, I, DL, get(X86::MOV32ri))
2618         .addOperand(Orig.getOperand(0))
2619         .addImm(Value);
2620   } else {
2621     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
2622     MBB.insert(I, MI);
2623   }
2624 
2625   MachineInstr &NewMI = *std::prev(I);
2626   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
2627 }
2628 
2629 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2630 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2631   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2632     MachineOperand &MO = MI.getOperand(i);
2633     if (MO.isReg() && MO.isDef() &&
2634         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2635       return true;
2636     }
2637   }
2638   return false;
2639 }
2640 
2641 /// Check whether the shift count for a machine operand is non-zero.
2642 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
2643                                               unsigned ShiftAmtOperandIdx) {
2644   // The shift count is six bits with the REX.W prefix and five bits without.
2645   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2646   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
2647   return Imm & ShiftCountMask;
2648 }
2649 
2650 /// Check whether the given shift count is appropriate
2651 /// can be represented by a LEA instruction.
2652 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2653   // Left shift instructions can be transformed into load-effective-address
2654   // instructions if we can encode them appropriately.
2655   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2656   // The SIB.scale field is two bits wide which means that we can encode any
2657   // shift amount less than 4.
2658   return ShAmt < 4 && ShAmt > 0;
2659 }
2660 
2661 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2662                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
2663                                   bool &isKill, bool &isUndef,
2664                                   MachineOperand &ImplicitOp,
2665                                   LiveVariables *LV) const {
2666   MachineFunction &MF = *MI.getParent()->getParent();
2667   const TargetRegisterClass *RC;
2668   if (AllowSP) {
2669     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2670   } else {
2671     RC = Opc != X86::LEA32r ?
2672       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2673   }
2674   unsigned SrcReg = Src.getReg();
2675 
2676   // For both LEA64 and LEA32 the register already has essentially the right
2677   // type (32-bit or 64-bit) we may just need to forbid SP.
2678   if (Opc != X86::LEA64_32r) {
2679     NewSrc = SrcReg;
2680     isKill = Src.isKill();
2681     isUndef = Src.isUndef();
2682 
2683     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2684         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2685       return false;
2686 
2687     return true;
2688   }
2689 
2690   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2691   // another we need to add 64-bit registers to the final MI.
2692   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2693     ImplicitOp = Src;
2694     ImplicitOp.setImplicit();
2695 
2696     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
2697     MachineBasicBlock::LivenessQueryResult LQR =
2698         MI.getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2699 
2700     switch (LQR) {
2701     case MachineBasicBlock::LQR_Unknown:
2702       // We can't give sane liveness flags to the instruction, abandon LEA
2703       // formation.
2704       return false;
2705     case MachineBasicBlock::LQR_Live:
2706       isKill = MI.killsRegister(SrcReg);
2707       isUndef = false;
2708       break;
2709     default:
2710       // The physreg itself is dead, so we have to use it as an <undef>.
2711       isKill = false;
2712       isUndef = true;
2713       break;
2714     }
2715   } else {
2716     // Virtual register of the wrong class, we have to create a temporary 64-bit
2717     // vreg to feed into the LEA.
2718     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2719     MachineInstr *Copy = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
2720                                  get(TargetOpcode::COPY))
2721         .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2722         .addOperand(Src);
2723 
2724     // Which is obviously going to be dead after we're done with it.
2725     isKill = true;
2726     isUndef = false;
2727 
2728     if (LV)
2729       LV->replaceKillInstruction(SrcReg, MI, *Copy);
2730   }
2731 
2732   // We've set all the parameters without issue.
2733   return true;
2734 }
2735 
2736 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2737 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2738 /// truncating back down to a 16-bit subregister.
2739 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2740     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2741     LiveVariables *LV) const {
2742   MachineBasicBlock::iterator MBBI = MI.getIterator();
2743   unsigned Dest = MI.getOperand(0).getReg();
2744   unsigned Src = MI.getOperand(1).getReg();
2745   bool isDead = MI.getOperand(0).isDead();
2746   bool isKill = MI.getOperand(1).isKill();
2747 
2748   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2749   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2750   unsigned Opc, leaInReg;
2751   if (Subtarget.is64Bit()) {
2752     Opc = X86::LEA64_32r;
2753     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2754   } else {
2755     Opc = X86::LEA32r;
2756     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2757   }
2758 
2759   // Build and insert into an implicit UNDEF value. This is OK because
2760   // well be shifting and then extracting the lower 16-bits.
2761   // This has the potential to cause partial register stall. e.g.
2762   //   movw    (%rbp,%rcx,2), %dx
2763   //   leal    -65(%rdx), %esi
2764   // But testing has shown this *does* help performance in 64-bit mode (at
2765   // least on modern x86 machines).
2766   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2767   MachineInstr *InsMI =
2768       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2769           .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2770           .addReg(Src, getKillRegState(isKill));
2771 
2772   MachineInstrBuilder MIB =
2773       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
2774   switch (MIOpc) {
2775   default: llvm_unreachable("Unreachable!");
2776   case X86::SHL16ri: {
2777     unsigned ShAmt = MI.getOperand(2).getImm();
2778     MIB.addReg(0).addImm(1ULL << ShAmt)
2779        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2780     break;
2781   }
2782   case X86::INC16r:
2783     addRegOffset(MIB, leaInReg, true, 1);
2784     break;
2785   case X86::DEC16r:
2786     addRegOffset(MIB, leaInReg, true, -1);
2787     break;
2788   case X86::ADD16ri:
2789   case X86::ADD16ri8:
2790   case X86::ADD16ri_DB:
2791   case X86::ADD16ri8_DB:
2792     addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
2793     break;
2794   case X86::ADD16rr:
2795   case X86::ADD16rr_DB: {
2796     unsigned Src2 = MI.getOperand(2).getReg();
2797     bool isKill2 = MI.getOperand(2).isKill();
2798     unsigned leaInReg2 = 0;
2799     MachineInstr *InsMI2 = nullptr;
2800     if (Src == Src2) {
2801       // ADD16rr %reg1028<kill>, %reg1028
2802       // just a single insert_subreg.
2803       addRegReg(MIB, leaInReg, true, leaInReg, false);
2804     } else {
2805       if (Subtarget.is64Bit())
2806         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2807       else
2808         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2809       // Build and insert into an implicit UNDEF value. This is OK because
2810       // well be shifting and then extracting the lower 16-bits.
2811       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2812       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2813                    .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2814                    .addReg(Src2, getKillRegState(isKill2));
2815       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2816     }
2817     if (LV && isKill2 && InsMI2)
2818       LV->replaceKillInstruction(Src2, MI, *InsMI2);
2819     break;
2820   }
2821   }
2822 
2823   MachineInstr *NewMI = MIB;
2824   MachineInstr *ExtMI =
2825       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2826           .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2827           .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2828 
2829   if (LV) {
2830     // Update live variables
2831     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2832     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2833     if (isKill)
2834       LV->replaceKillInstruction(Src, MI, *InsMI);
2835     if (isDead)
2836       LV->replaceKillInstruction(Dest, MI, *ExtMI);
2837   }
2838 
2839   return ExtMI;
2840 }
2841 
2842 /// This method must be implemented by targets that
2843 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2844 /// may be able to convert a two-address instruction into a true
2845 /// three-address instruction on demand.  This allows the X86 target (for
2846 /// example) to convert ADD and SHL instructions into LEA instructions if they
2847 /// would require register copies due to two-addressness.
2848 ///
2849 /// This method returns a null pointer if the transformation cannot be
2850 /// performed, otherwise it returns the new instruction.
2851 ///
2852 MachineInstr *
2853 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2854                                     MachineInstr &MI, LiveVariables *LV) const {
2855   // The following opcodes also sets the condition code register(s). Only
2856   // convert them to equivalent lea if the condition code register def's
2857   // are dead!
2858   if (hasLiveCondCodeDef(MI))
2859     return nullptr;
2860 
2861   MachineFunction &MF = *MI.getParent()->getParent();
2862   // All instructions input are two-addr instructions.  Get the known operands.
2863   const MachineOperand &Dest = MI.getOperand(0);
2864   const MachineOperand &Src = MI.getOperand(1);
2865 
2866   MachineInstr *NewMI = nullptr;
2867   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2868   // we have better subtarget support, enable the 16-bit LEA generation here.
2869   // 16-bit LEA is also slow on Core2.
2870   bool DisableLEA16 = true;
2871   bool is64Bit = Subtarget.is64Bit();
2872 
2873   unsigned MIOpc = MI.getOpcode();
2874   switch (MIOpc) {
2875   default: return nullptr;
2876   case X86::SHL64ri: {
2877     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
2878     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2879     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2880 
2881     // LEA can't handle RSP.
2882     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2883         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2884                                            &X86::GR64_NOSPRegClass))
2885       return nullptr;
2886 
2887     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
2888                 .addOperand(Dest)
2889                 .addReg(0)
2890                 .addImm(1ULL << ShAmt)
2891                 .addOperand(Src)
2892                 .addImm(0)
2893                 .addReg(0);
2894     break;
2895   }
2896   case X86::SHL32ri: {
2897     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
2898     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2899     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2900 
2901     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2902 
2903     // LEA can't handle ESP.
2904     bool isKill, isUndef;
2905     unsigned SrcReg;
2906     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2907     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2908                         SrcReg, isKill, isUndef, ImplicitOp, LV))
2909       return nullptr;
2910 
2911     MachineInstrBuilder MIB =
2912         BuildMI(MF, MI.getDebugLoc(), get(Opc))
2913             .addOperand(Dest)
2914             .addReg(0)
2915             .addImm(1ULL << ShAmt)
2916             .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2917             .addImm(0)
2918             .addReg(0);
2919     if (ImplicitOp.getReg() != 0)
2920       MIB.addOperand(ImplicitOp);
2921     NewMI = MIB;
2922 
2923     break;
2924   }
2925   case X86::SHL16ri: {
2926     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
2927     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2928     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2929 
2930     if (DisableLEA16)
2931       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2932                      : nullptr;
2933     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2934                 .addOperand(Dest)
2935                 .addReg(0)
2936                 .addImm(1ULL << ShAmt)
2937                 .addOperand(Src)
2938                 .addImm(0)
2939                 .addReg(0);
2940     break;
2941   }
2942   case X86::INC64r:
2943   case X86::INC32r: {
2944     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
2945     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2946       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2947     bool isKill, isUndef;
2948     unsigned SrcReg;
2949     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2950     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2951                         SrcReg, isKill, isUndef, ImplicitOp, LV))
2952       return nullptr;
2953 
2954     MachineInstrBuilder MIB =
2955         BuildMI(MF, MI.getDebugLoc(), get(Opc))
2956             .addOperand(Dest)
2957             .addReg(SrcReg,
2958                     getKillRegState(isKill) | getUndefRegState(isUndef));
2959     if (ImplicitOp.getReg() != 0)
2960       MIB.addOperand(ImplicitOp);
2961 
2962     NewMI = addOffset(MIB, 1);
2963     break;
2964   }
2965   case X86::INC16r:
2966     if (DisableLEA16)
2967       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2968                      : nullptr;
2969     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
2970     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2971                           .addOperand(Dest)
2972                           .addOperand(Src),
2973                       1);
2974     break;
2975   case X86::DEC64r:
2976   case X86::DEC32r: {
2977     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
2978     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2979       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2980 
2981     bool isKill, isUndef;
2982     unsigned SrcReg;
2983     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2984     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2985                         SrcReg, isKill, isUndef, ImplicitOp, LV))
2986       return nullptr;
2987 
2988     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2989                                   .addOperand(Dest)
2990                                   .addReg(SrcReg, getUndefRegState(isUndef) |
2991                                                       getKillRegState(isKill));
2992     if (ImplicitOp.getReg() != 0)
2993       MIB.addOperand(ImplicitOp);
2994 
2995     NewMI = addOffset(MIB, -1);
2996 
2997     break;
2998   }
2999   case X86::DEC16r:
3000     if (DisableLEA16)
3001       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3002                      : nullptr;
3003     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3004     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3005                           .addOperand(Dest)
3006                           .addOperand(Src),
3007                       -1);
3008     break;
3009   case X86::ADD64rr:
3010   case X86::ADD64rr_DB:
3011   case X86::ADD32rr:
3012   case X86::ADD32rr_DB: {
3013     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3014     unsigned Opc;
3015     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3016       Opc = X86::LEA64r;
3017     else
3018       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3019 
3020     bool isKill, isUndef;
3021     unsigned SrcReg;
3022     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3023     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3024                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3025       return nullptr;
3026 
3027     const MachineOperand &Src2 = MI.getOperand(2);
3028     bool isKill2, isUndef2;
3029     unsigned SrcReg2;
3030     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3031     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
3032                         SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
3033       return nullptr;
3034 
3035     MachineInstrBuilder MIB =
3036         BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
3037     if (ImplicitOp.getReg() != 0)
3038       MIB.addOperand(ImplicitOp);
3039     if (ImplicitOp2.getReg() != 0)
3040       MIB.addOperand(ImplicitOp2);
3041 
3042     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3043 
3044     // Preserve undefness of the operands.
3045     NewMI->getOperand(1).setIsUndef(isUndef);
3046     NewMI->getOperand(3).setIsUndef(isUndef2);
3047 
3048     if (LV && Src2.isKill())
3049       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
3050     break;
3051   }
3052   case X86::ADD16rr:
3053   case X86::ADD16rr_DB: {
3054     if (DisableLEA16)
3055       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3056                      : nullptr;
3057     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3058     unsigned Src2 = MI.getOperand(2).getReg();
3059     bool isKill2 = MI.getOperand(2).isKill();
3060     NewMI = addRegReg(
3061         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3062         Src.getReg(), Src.isKill(), Src2, isKill2);
3063 
3064     // Preserve undefness of the operands.
3065     bool isUndef = MI.getOperand(1).isUndef();
3066     bool isUndef2 = MI.getOperand(2).isUndef();
3067     NewMI->getOperand(1).setIsUndef(isUndef);
3068     NewMI->getOperand(3).setIsUndef(isUndef2);
3069 
3070     if (LV && isKill2)
3071       LV->replaceKillInstruction(Src2, MI, *NewMI);
3072     break;
3073   }
3074   case X86::ADD64ri32:
3075   case X86::ADD64ri8:
3076   case X86::ADD64ri32_DB:
3077   case X86::ADD64ri8_DB:
3078     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3079     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3080                           .addOperand(Dest)
3081                           .addOperand(Src),
3082                       MI.getOperand(2).getImm());
3083     break;
3084   case X86::ADD32ri:
3085   case X86::ADD32ri8:
3086   case X86::ADD32ri_DB:
3087   case X86::ADD32ri8_DB: {
3088     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3089     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3090 
3091     bool isKill, isUndef;
3092     unsigned SrcReg;
3093     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3094     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3095                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3096       return nullptr;
3097 
3098     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3099                                   .addOperand(Dest)
3100                                   .addReg(SrcReg, getUndefRegState(isUndef) |
3101                                                       getKillRegState(isKill));
3102     if (ImplicitOp.getReg() != 0)
3103       MIB.addOperand(ImplicitOp);
3104 
3105     NewMI = addOffset(MIB, MI.getOperand(2).getImm());
3106     break;
3107   }
3108   case X86::ADD16ri:
3109   case X86::ADD16ri8:
3110   case X86::ADD16ri_DB:
3111   case X86::ADD16ri8_DB:
3112     if (DisableLEA16)
3113       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3114                      : nullptr;
3115     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3116     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3117                           .addOperand(Dest)
3118                           .addOperand(Src),
3119                       MI.getOperand(2).getImm());
3120     break;
3121   }
3122 
3123   if (!NewMI) return nullptr;
3124 
3125   if (LV) {  // Update live variables
3126     if (Src.isKill())
3127       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
3128     if (Dest.isDead())
3129       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
3130   }
3131 
3132   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
3133   return NewMI;
3134 }
3135 
3136 /// Returns true if the given instruction opcode is FMA3.
3137 /// Otherwise, returns false.
3138 /// The second parameter is optional and is used as the second return from
3139 /// the function. It is set to true if the given instruction has FMA3 opcode
3140 /// that is used for lowering of scalar FMA intrinsics, and it is set to false
3141 /// otherwise.
3142 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3143   if (IsIntrinsic)
3144     *IsIntrinsic = false;
3145 
3146   switch (Opcode) {
3147     case X86::VFMADDSDr132r:      case X86::VFMADDSDr132m:
3148     case X86::VFMADDSSr132r:      case X86::VFMADDSSr132m:
3149     case X86::VFMSUBSDr132r:      case X86::VFMSUBSDr132m:
3150     case X86::VFMSUBSSr132r:      case X86::VFMSUBSSr132m:
3151     case X86::VFNMADDSDr132r:     case X86::VFNMADDSDr132m:
3152     case X86::VFNMADDSSr132r:     case X86::VFNMADDSSr132m:
3153     case X86::VFNMSUBSDr132r:     case X86::VFNMSUBSDr132m:
3154     case X86::VFNMSUBSSr132r:     case X86::VFNMSUBSSr132m:
3155 
3156     case X86::VFMADDSDr213r:      case X86::VFMADDSDr213m:
3157     case X86::VFMADDSSr213r:      case X86::VFMADDSSr213m:
3158     case X86::VFMSUBSDr213r:      case X86::VFMSUBSDr213m:
3159     case X86::VFMSUBSSr213r:      case X86::VFMSUBSSr213m:
3160     case X86::VFNMADDSDr213r:     case X86::VFNMADDSDr213m:
3161     case X86::VFNMADDSSr213r:     case X86::VFNMADDSSr213m:
3162     case X86::VFNMSUBSDr213r:     case X86::VFNMSUBSDr213m:
3163     case X86::VFNMSUBSSr213r:     case X86::VFNMSUBSSr213m:
3164 
3165     case X86::VFMADDSDr231r:      case X86::VFMADDSDr231m:
3166     case X86::VFMADDSSr231r:      case X86::VFMADDSSr231m:
3167     case X86::VFMSUBSDr231r:      case X86::VFMSUBSDr231m:
3168     case X86::VFMSUBSSr231r:      case X86::VFMSUBSSr231m:
3169     case X86::VFNMADDSDr231r:     case X86::VFNMADDSDr231m:
3170     case X86::VFNMADDSSr231r:     case X86::VFNMADDSSr231m:
3171     case X86::VFNMSUBSDr231r:     case X86::VFNMSUBSDr231m:
3172     case X86::VFNMSUBSSr231r:     case X86::VFNMSUBSSr231m:
3173 
3174     case X86::VFMADDSUBPDr132r:   case X86::VFMADDSUBPDr132m:
3175     case X86::VFMADDSUBPSr132r:   case X86::VFMADDSUBPSr132m:
3176     case X86::VFMSUBADDPDr132r:   case X86::VFMSUBADDPDr132m:
3177     case X86::VFMSUBADDPSr132r:   case X86::VFMSUBADDPSr132m:
3178     case X86::VFMADDSUBPDr132rY:  case X86::VFMADDSUBPDr132mY:
3179     case X86::VFMADDSUBPSr132rY:  case X86::VFMADDSUBPSr132mY:
3180     case X86::VFMSUBADDPDr132rY:  case X86::VFMSUBADDPDr132mY:
3181     case X86::VFMSUBADDPSr132rY:  case X86::VFMSUBADDPSr132mY:
3182 
3183     case X86::VFMADDPDr132r:      case X86::VFMADDPDr132m:
3184     case X86::VFMADDPSr132r:      case X86::VFMADDPSr132m:
3185     case X86::VFMSUBPDr132r:      case X86::VFMSUBPDr132m:
3186     case X86::VFMSUBPSr132r:      case X86::VFMSUBPSr132m:
3187     case X86::VFNMADDPDr132r:     case X86::VFNMADDPDr132m:
3188     case X86::VFNMADDPSr132r:     case X86::VFNMADDPSr132m:
3189     case X86::VFNMSUBPDr132r:     case X86::VFNMSUBPDr132m:
3190     case X86::VFNMSUBPSr132r:     case X86::VFNMSUBPSr132m:
3191     case X86::VFMADDPDr132rY:     case X86::VFMADDPDr132mY:
3192     case X86::VFMADDPSr132rY:     case X86::VFMADDPSr132mY:
3193     case X86::VFMSUBPDr132rY:     case X86::VFMSUBPDr132mY:
3194     case X86::VFMSUBPSr132rY:     case X86::VFMSUBPSr132mY:
3195     case X86::VFNMADDPDr132rY:    case X86::VFNMADDPDr132mY:
3196     case X86::VFNMADDPSr132rY:    case X86::VFNMADDPSr132mY:
3197     case X86::VFNMSUBPDr132rY:    case X86::VFNMSUBPDr132mY:
3198     case X86::VFNMSUBPSr132rY:    case X86::VFNMSUBPSr132mY:
3199 
3200     case X86::VFMADDSUBPDr213r:   case X86::VFMADDSUBPDr213m:
3201     case X86::VFMADDSUBPSr213r:   case X86::VFMADDSUBPSr213m:
3202     case X86::VFMSUBADDPDr213r:   case X86::VFMSUBADDPDr213m:
3203     case X86::VFMSUBADDPSr213r:   case X86::VFMSUBADDPSr213m:
3204     case X86::VFMADDSUBPDr213rY:  case X86::VFMADDSUBPDr213mY:
3205     case X86::VFMADDSUBPSr213rY:  case X86::VFMADDSUBPSr213mY:
3206     case X86::VFMSUBADDPDr213rY:  case X86::VFMSUBADDPDr213mY:
3207     case X86::VFMSUBADDPSr213rY:  case X86::VFMSUBADDPSr213mY:
3208 
3209     case X86::VFMADDPDr213r:      case X86::VFMADDPDr213m:
3210     case X86::VFMADDPSr213r:      case X86::VFMADDPSr213m:
3211     case X86::VFMSUBPDr213r:      case X86::VFMSUBPDr213m:
3212     case X86::VFMSUBPSr213r:      case X86::VFMSUBPSr213m:
3213     case X86::VFNMADDPDr213r:     case X86::VFNMADDPDr213m:
3214     case X86::VFNMADDPSr213r:     case X86::VFNMADDPSr213m:
3215     case X86::VFNMSUBPDr213r:     case X86::VFNMSUBPDr213m:
3216     case X86::VFNMSUBPSr213r:     case X86::VFNMSUBPSr213m:
3217     case X86::VFMADDPDr213rY:     case X86::VFMADDPDr213mY:
3218     case X86::VFMADDPSr213rY:     case X86::VFMADDPSr213mY:
3219     case X86::VFMSUBPDr213rY:     case X86::VFMSUBPDr213mY:
3220     case X86::VFMSUBPSr213rY:     case X86::VFMSUBPSr213mY:
3221     case X86::VFNMADDPDr213rY:    case X86::VFNMADDPDr213mY:
3222     case X86::VFNMADDPSr213rY:    case X86::VFNMADDPSr213mY:
3223     case X86::VFNMSUBPDr213rY:    case X86::VFNMSUBPDr213mY:
3224     case X86::VFNMSUBPSr213rY:    case X86::VFNMSUBPSr213mY:
3225 
3226     case X86::VFMADDSUBPDr231r:   case X86::VFMADDSUBPDr231m:
3227     case X86::VFMADDSUBPSr231r:   case X86::VFMADDSUBPSr231m:
3228     case X86::VFMSUBADDPDr231r:   case X86::VFMSUBADDPDr231m:
3229     case X86::VFMSUBADDPSr231r:   case X86::VFMSUBADDPSr231m:
3230     case X86::VFMADDSUBPDr231rY:  case X86::VFMADDSUBPDr231mY:
3231     case X86::VFMADDSUBPSr231rY:  case X86::VFMADDSUBPSr231mY:
3232     case X86::VFMSUBADDPDr231rY:  case X86::VFMSUBADDPDr231mY:
3233     case X86::VFMSUBADDPSr231rY:  case X86::VFMSUBADDPSr231mY:
3234 
3235     case X86::VFMADDPDr231r:      case X86::VFMADDPDr231m:
3236     case X86::VFMADDPSr231r:      case X86::VFMADDPSr231m:
3237     case X86::VFMSUBPDr231r:      case X86::VFMSUBPDr231m:
3238     case X86::VFMSUBPSr231r:      case X86::VFMSUBPSr231m:
3239     case X86::VFNMADDPDr231r:     case X86::VFNMADDPDr231m:
3240     case X86::VFNMADDPSr231r:     case X86::VFNMADDPSr231m:
3241     case X86::VFNMSUBPDr231r:     case X86::VFNMSUBPDr231m:
3242     case X86::VFNMSUBPSr231r:     case X86::VFNMSUBPSr231m:
3243     case X86::VFMADDPDr231rY:     case X86::VFMADDPDr231mY:
3244     case X86::VFMADDPSr231rY:     case X86::VFMADDPSr231mY:
3245     case X86::VFMSUBPDr231rY:     case X86::VFMSUBPDr231mY:
3246     case X86::VFMSUBPSr231rY:     case X86::VFMSUBPSr231mY:
3247     case X86::VFNMADDPDr231rY:    case X86::VFNMADDPDr231mY:
3248     case X86::VFNMADDPSr231rY:    case X86::VFNMADDPSr231mY:
3249     case X86::VFNMSUBPDr231rY:    case X86::VFNMSUBPDr231mY:
3250     case X86::VFNMSUBPSr231rY:    case X86::VFNMSUBPSr231mY:
3251       return true;
3252 
3253     case X86::VFMADDSDr132r_Int:  case X86::VFMADDSDr132m_Int:
3254     case X86::VFMADDSSr132r_Int:  case X86::VFMADDSSr132m_Int:
3255     case X86::VFMSUBSDr132r_Int:  case X86::VFMSUBSDr132m_Int:
3256     case X86::VFMSUBSSr132r_Int:  case X86::VFMSUBSSr132m_Int:
3257     case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3258     case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3259     case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3260     case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3261 
3262     case X86::VFMADDSDr213r_Int:  case X86::VFMADDSDr213m_Int:
3263     case X86::VFMADDSSr213r_Int:  case X86::VFMADDSSr213m_Int:
3264     case X86::VFMSUBSDr213r_Int:  case X86::VFMSUBSDr213m_Int:
3265     case X86::VFMSUBSSr213r_Int:  case X86::VFMSUBSSr213m_Int:
3266     case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3267     case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3268     case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3269     case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3270 
3271     case X86::VFMADDSDr231r_Int:  case X86::VFMADDSDr231m_Int:
3272     case X86::VFMADDSSr231r_Int:  case X86::VFMADDSSr231m_Int:
3273     case X86::VFMSUBSDr231r_Int:  case X86::VFMSUBSDr231m_Int:
3274     case X86::VFMSUBSSr231r_Int:  case X86::VFMSUBSSr231m_Int:
3275     case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3276     case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3277     case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3278     case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3279       if (IsIntrinsic)
3280         *IsIntrinsic = true;
3281       return true;
3282     default:
3283       return false;
3284   }
3285   llvm_unreachable("Opcode not handled by the switch");
3286 }
3287 
3288 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
3289                                                    unsigned OpIdx1,
3290                                                    unsigned OpIdx2) const {
3291   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3292     if (NewMI)
3293       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3294     return MI;
3295   };
3296 
3297   switch (MI.getOpcode()) {
3298   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3299   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3300   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3301   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3302   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3303   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3304     unsigned Opc;
3305     unsigned Size;
3306     switch (MI.getOpcode()) {
3307     default: llvm_unreachable("Unreachable!");
3308     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3309     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3310     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3311     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3312     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3313     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3314     }
3315     unsigned Amt = MI.getOperand(3).getImm();
3316     auto &WorkingMI = cloneIfNew(MI);
3317     WorkingMI.setDesc(get(Opc));
3318     WorkingMI.getOperand(3).setImm(Size - Amt);
3319     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3320                                                    OpIdx1, OpIdx2);
3321   }
3322   case X86::BLENDPDrri:
3323   case X86::BLENDPSrri:
3324   case X86::PBLENDWrri:
3325   case X86::VBLENDPDrri:
3326   case X86::VBLENDPSrri:
3327   case X86::VBLENDPDYrri:
3328   case X86::VBLENDPSYrri:
3329   case X86::VPBLENDDrri:
3330   case X86::VPBLENDWrri:
3331   case X86::VPBLENDDYrri:
3332   case X86::VPBLENDWYrri:{
3333     unsigned Mask;
3334     switch (MI.getOpcode()) {
3335     default: llvm_unreachable("Unreachable!");
3336     case X86::BLENDPDrri:    Mask = 0x03; break;
3337     case X86::BLENDPSrri:    Mask = 0x0F; break;
3338     case X86::PBLENDWrri:    Mask = 0xFF; break;
3339     case X86::VBLENDPDrri:   Mask = 0x03; break;
3340     case X86::VBLENDPSrri:   Mask = 0x0F; break;
3341     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
3342     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
3343     case X86::VPBLENDDrri:   Mask = 0x0F; break;
3344     case X86::VPBLENDWrri:   Mask = 0xFF; break;
3345     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
3346     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
3347     }
3348     // Only the least significant bits of Imm are used.
3349     unsigned Imm = MI.getOperand(3).getImm() & Mask;
3350     auto &WorkingMI = cloneIfNew(MI);
3351     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3352     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3353                                                    OpIdx1, OpIdx2);
3354   }
3355   case X86::PCLMULQDQrr:
3356   case X86::VPCLMULQDQrr:{
3357     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3358     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3359     unsigned Imm = MI.getOperand(3).getImm();
3360     unsigned Src1Hi = Imm & 0x01;
3361     unsigned Src2Hi = Imm & 0x10;
3362     auto &WorkingMI = cloneIfNew(MI);
3363     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3364     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3365                                                    OpIdx1, OpIdx2);
3366   }
3367   case X86::CMPPDrri:
3368   case X86::CMPPSrri:
3369   case X86::VCMPPDrri:
3370   case X86::VCMPPSrri:
3371   case X86::VCMPPDYrri:
3372   case X86::VCMPPSYrri: {
3373     // Float comparison can be safely commuted for
3374     // Ordered/Unordered/Equal/NotEqual tests
3375     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3376     switch (Imm) {
3377     case 0x00: // EQUAL
3378     case 0x03: // UNORDERED
3379     case 0x04: // NOT EQUAL
3380     case 0x07: // ORDERED
3381       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3382     default:
3383       return nullptr;
3384     }
3385   }
3386   case X86::VPCOMBri: case X86::VPCOMUBri:
3387   case X86::VPCOMDri: case X86::VPCOMUDri:
3388   case X86::VPCOMQri: case X86::VPCOMUQri:
3389   case X86::VPCOMWri: case X86::VPCOMUWri: {
3390     // Flip comparison mode immediate (if necessary).
3391     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3392     switch (Imm) {
3393     case 0x00: Imm = 0x02; break; // LT -> GT
3394     case 0x01: Imm = 0x03; break; // LE -> GE
3395     case 0x02: Imm = 0x00; break; // GT -> LT
3396     case 0x03: Imm = 0x01; break; // GE -> LE
3397     case 0x04: // EQ
3398     case 0x05: // NE
3399     case 0x06: // FALSE
3400     case 0x07: // TRUE
3401     default:
3402       break;
3403     }
3404     auto &WorkingMI = cloneIfNew(MI);
3405     WorkingMI.getOperand(3).setImm(Imm);
3406     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3407                                                    OpIdx1, OpIdx2);
3408   }
3409   case X86::VPERM2F128rr:
3410   case X86::VPERM2I128rr: {
3411     // Flip permute source immediate.
3412     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3413     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3414     unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3415     auto &WorkingMI = cloneIfNew(MI);
3416     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3417     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3418                                                    OpIdx1, OpIdx2);
3419   }
3420   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3421   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3422   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3423   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3424   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3425   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3426   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3427   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3428   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3429   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3430   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3431   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3432   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3433   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3434   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3435   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3436     unsigned Opc;
3437     switch (MI.getOpcode()) {
3438     default: llvm_unreachable("Unreachable!");
3439     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3440     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3441     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3442     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3443     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3444     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3445     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3446     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3447     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3448     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3449     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3450     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3451     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3452     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3453     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3454     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3455     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3456     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3457     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3458     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3459     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3460     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3461     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3462     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3463     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3464     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3465     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3466     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3467     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3468     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3469     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3470     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3471     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3472     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3473     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3474     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3475     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3476     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3477     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3478     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3479     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3480     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3481     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3482     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3483     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3484     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3485     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3486     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3487     }
3488     auto &WorkingMI = cloneIfNew(MI);
3489     WorkingMI.setDesc(get(Opc));
3490     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3491                                                    OpIdx1, OpIdx2);
3492   }
3493   default:
3494     if (isFMA3(MI.getOpcode())) {
3495       unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3496       if (Opc == 0)
3497         return nullptr;
3498       auto &WorkingMI = cloneIfNew(MI);
3499       WorkingMI.setDesc(get(Opc));
3500       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3501                                                      OpIdx1, OpIdx2);
3502     }
3503 
3504     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3505   }
3506 }
3507 
3508 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr &MI,
3509                                              unsigned &SrcOpIdx1,
3510                                              unsigned &SrcOpIdx2) const {
3511 
3512   unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3513 
3514   // Only the first RegOpsNum operands are commutable.
3515   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3516   // that the operand is not specified/fixed.
3517   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3518       (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3519     return false;
3520   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3521       (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3522     return false;
3523 
3524   // Look for two different register operands assumed to be commutable
3525   // regardless of the FMA opcode. The FMA opcode is adjusted later.
3526   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3527       SrcOpIdx2 == CommuteAnyOperandIndex) {
3528     unsigned CommutableOpIdx1 = SrcOpIdx1;
3529     unsigned CommutableOpIdx2 = SrcOpIdx2;
3530 
3531     // At least one of operands to be commuted is not specified and
3532     // this method is free to choose appropriate commutable operands.
3533     if (SrcOpIdx1 == SrcOpIdx2)
3534       // Both of operands are not fixed. By default set one of commutable
3535       // operands to the last register operand of the instruction.
3536       CommutableOpIdx2 = RegOpsNum;
3537     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3538       // Only one of operands is not fixed.
3539       CommutableOpIdx2 = SrcOpIdx1;
3540 
3541     // CommutableOpIdx2 is well defined now. Let's choose another commutable
3542     // operand and assign its index to CommutableOpIdx1.
3543     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
3544     for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3545       // The commuted operands must have different registers.
3546       // Otherwise, the commute transformation does not change anything and
3547       // is useless then.
3548       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
3549         break;
3550     }
3551 
3552     // No appropriate commutable operands were found.
3553     if (CommutableOpIdx1 == 0)
3554       return false;
3555 
3556     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3557     // to return those values.
3558     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3559                               CommutableOpIdx1, CommutableOpIdx2))
3560       return false;
3561   }
3562 
3563   // Check if we can adjust the opcode to preserve the semantics when
3564   // commute the register operands.
3565   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3566 }
3567 
3568 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3569     MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) const {
3570   unsigned Opc = MI.getOpcode();
3571 
3572   // Define the array that holds FMA opcodes in groups
3573   // of 3 opcodes(132, 213, 231) in each group.
3574   static const uint16_t RegularOpcodeGroups[][3] = {
3575     { X86::VFMADDSSr132r,   X86::VFMADDSSr213r,   X86::VFMADDSSr231r  },
3576     { X86::VFMADDSDr132r,   X86::VFMADDSDr213r,   X86::VFMADDSDr231r  },
3577     { X86::VFMADDPSr132r,   X86::VFMADDPSr213r,   X86::VFMADDPSr231r  },
3578     { X86::VFMADDPDr132r,   X86::VFMADDPDr213r,   X86::VFMADDPDr231r  },
3579     { X86::VFMADDPSr132rY,  X86::VFMADDPSr213rY,  X86::VFMADDPSr231rY },
3580     { X86::VFMADDPDr132rY,  X86::VFMADDPDr213rY,  X86::VFMADDPDr231rY },
3581     { X86::VFMADDSSr132m,   X86::VFMADDSSr213m,   X86::VFMADDSSr231m  },
3582     { X86::VFMADDSDr132m,   X86::VFMADDSDr213m,   X86::VFMADDSDr231m  },
3583     { X86::VFMADDPSr132m,   X86::VFMADDPSr213m,   X86::VFMADDPSr231m  },
3584     { X86::VFMADDPDr132m,   X86::VFMADDPDr213m,   X86::VFMADDPDr231m  },
3585     { X86::VFMADDPSr132mY,  X86::VFMADDPSr213mY,  X86::VFMADDPSr231mY },
3586     { X86::VFMADDPDr132mY,  X86::VFMADDPDr213mY,  X86::VFMADDPDr231mY },
3587 
3588     { X86::VFMSUBSSr132r,   X86::VFMSUBSSr213r,   X86::VFMSUBSSr231r  },
3589     { X86::VFMSUBSDr132r,   X86::VFMSUBSDr213r,   X86::VFMSUBSDr231r  },
3590     { X86::VFMSUBPSr132r,   X86::VFMSUBPSr213r,   X86::VFMSUBPSr231r  },
3591     { X86::VFMSUBPDr132r,   X86::VFMSUBPDr213r,   X86::VFMSUBPDr231r  },
3592     { X86::VFMSUBPSr132rY,  X86::VFMSUBPSr213rY,  X86::VFMSUBPSr231rY },
3593     { X86::VFMSUBPDr132rY,  X86::VFMSUBPDr213rY,  X86::VFMSUBPDr231rY },
3594     { X86::VFMSUBSSr132m,   X86::VFMSUBSSr213m,   X86::VFMSUBSSr231m  },
3595     { X86::VFMSUBSDr132m,   X86::VFMSUBSDr213m,   X86::VFMSUBSDr231m  },
3596     { X86::VFMSUBPSr132m,   X86::VFMSUBPSr213m,   X86::VFMSUBPSr231m  },
3597     { X86::VFMSUBPDr132m,   X86::VFMSUBPDr213m,   X86::VFMSUBPDr231m  },
3598     { X86::VFMSUBPSr132mY,  X86::VFMSUBPSr213mY,  X86::VFMSUBPSr231mY },
3599     { X86::VFMSUBPDr132mY,  X86::VFMSUBPDr213mY,  X86::VFMSUBPDr231mY },
3600 
3601     { X86::VFNMADDSSr132r,  X86::VFNMADDSSr213r,  X86::VFNMADDSSr231r  },
3602     { X86::VFNMADDSDr132r,  X86::VFNMADDSDr213r,  X86::VFNMADDSDr231r  },
3603     { X86::VFNMADDPSr132r,  X86::VFNMADDPSr213r,  X86::VFNMADDPSr231r  },
3604     { X86::VFNMADDPDr132r,  X86::VFNMADDPDr213r,  X86::VFNMADDPDr231r  },
3605     { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3606     { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3607     { X86::VFNMADDSSr132m,  X86::VFNMADDSSr213m,  X86::VFNMADDSSr231m  },
3608     { X86::VFNMADDSDr132m,  X86::VFNMADDSDr213m,  X86::VFNMADDSDr231m  },
3609     { X86::VFNMADDPSr132m,  X86::VFNMADDPSr213m,  X86::VFNMADDPSr231m  },
3610     { X86::VFNMADDPDr132m,  X86::VFNMADDPDr213m,  X86::VFNMADDPDr231m  },
3611     { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3612     { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3613 
3614     { X86::VFNMSUBSSr132r,  X86::VFNMSUBSSr213r,  X86::VFNMSUBSSr231r  },
3615     { X86::VFNMSUBSDr132r,  X86::VFNMSUBSDr213r,  X86::VFNMSUBSDr231r  },
3616     { X86::VFNMSUBPSr132r,  X86::VFNMSUBPSr213r,  X86::VFNMSUBPSr231r  },
3617     { X86::VFNMSUBPDr132r,  X86::VFNMSUBPDr213r,  X86::VFNMSUBPDr231r  },
3618     { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3619     { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3620     { X86::VFNMSUBSSr132m,  X86::VFNMSUBSSr213m,  X86::VFNMSUBSSr231m  },
3621     { X86::VFNMSUBSDr132m,  X86::VFNMSUBSDr213m,  X86::VFNMSUBSDr231m  },
3622     { X86::VFNMSUBPSr132m,  X86::VFNMSUBPSr213m,  X86::VFNMSUBPSr231m  },
3623     { X86::VFNMSUBPDr132m,  X86::VFNMSUBPDr213m,  X86::VFNMSUBPDr231m  },
3624     { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3625     { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3626 
3627     { X86::VFMADDSUBPSr132r,  X86::VFMADDSUBPSr213r,  X86::VFMADDSUBPSr231r  },
3628     { X86::VFMADDSUBPDr132r,  X86::VFMADDSUBPDr213r,  X86::VFMADDSUBPDr231r  },
3629     { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3630     { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3631     { X86::VFMADDSUBPSr132m,  X86::VFMADDSUBPSr213m,  X86::VFMADDSUBPSr231m  },
3632     { X86::VFMADDSUBPDr132m,  X86::VFMADDSUBPDr213m,  X86::VFMADDSUBPDr231m  },
3633     { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3634     { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3635 
3636     { X86::VFMSUBADDPSr132r,  X86::VFMSUBADDPSr213r,  X86::VFMSUBADDPSr231r  },
3637     { X86::VFMSUBADDPDr132r,  X86::VFMSUBADDPDr213r,  X86::VFMSUBADDPDr231r  },
3638     { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3639     { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3640     { X86::VFMSUBADDPSr132m,  X86::VFMSUBADDPSr213m,  X86::VFMSUBADDPSr231m  },
3641     { X86::VFMSUBADDPDr132m,  X86::VFMSUBADDPDr213m,  X86::VFMSUBADDPDr231m  },
3642     { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3643     { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3644   };
3645 
3646   // Define the array that holds FMA*_Int opcodes in groups
3647   // of 3 opcodes(132, 213, 231) in each group.
3648   static const uint16_t IntrinOpcodeGroups[][3] = {
3649     { X86::VFMADDSSr132r_Int,  X86::VFMADDSSr213r_Int,  X86::VFMADDSSr231r_Int },
3650     { X86::VFMADDSDr132r_Int,  X86::VFMADDSDr213r_Int,  X86::VFMADDSDr231r_Int },
3651     { X86::VFMADDSSr132m_Int,  X86::VFMADDSSr213m_Int,  X86::VFMADDSSr231m_Int },
3652     { X86::VFMADDSDr132m_Int,  X86::VFMADDSDr213m_Int,  X86::VFMADDSDr231m_Int },
3653 
3654     { X86::VFMSUBSSr132r_Int,  X86::VFMSUBSSr213r_Int,  X86::VFMSUBSSr231r_Int },
3655     { X86::VFMSUBSDr132r_Int,  X86::VFMSUBSDr213r_Int,  X86::VFMSUBSDr231r_Int },
3656     { X86::VFMSUBSSr132m_Int,  X86::VFMSUBSSr213m_Int,  X86::VFMSUBSSr231m_Int },
3657     { X86::VFMSUBSDr132m_Int,  X86::VFMSUBSDr213m_Int,  X86::VFMSUBSDr231m_Int },
3658 
3659     { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3660     { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3661     { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3662     { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3663 
3664     { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3665     { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3666     { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3667     { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3668   };
3669 
3670   const unsigned Form132Index = 0;
3671   const unsigned Form213Index = 1;
3672   const unsigned Form231Index = 2;
3673   const unsigned FormsNum = 3;
3674 
3675   bool IsIntrinOpcode;
3676   isFMA3(Opc, &IsIntrinOpcode);
3677 
3678   size_t GroupsNum;
3679   const uint16_t (*OpcodeGroups)[3];
3680   if (IsIntrinOpcode) {
3681     GroupsNum = array_lengthof(IntrinOpcodeGroups);
3682     OpcodeGroups = IntrinOpcodeGroups;
3683   } else {
3684     GroupsNum = array_lengthof(RegularOpcodeGroups);
3685     OpcodeGroups = RegularOpcodeGroups;
3686   }
3687 
3688   const uint16_t *FoundOpcodesGroup = nullptr;
3689   size_t FormIndex;
3690 
3691   // Look for the input opcode in the corresponding opcodes table.
3692   for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3693          ++GroupIndex) {
3694     for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
3695       if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3696         FoundOpcodesGroup = OpcodeGroups[GroupIndex];
3697         break;
3698       }
3699     }
3700   }
3701 
3702   // The input opcode does not match with any of the opcodes from the tables.
3703   // The unsupported FMA opcode must be added to one of the two opcode groups
3704   // defined above.
3705   assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
3706 
3707   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3708   if (SrcOpIdx1 > SrcOpIdx2)
3709     std::swap(SrcOpIdx1, SrcOpIdx2);
3710 
3711   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3712   // analysis. The commute optimization is legal only if all users of FMA*_Int
3713   // use only the lowest element of the FMA*_Int instruction. Such analysis are
3714   // not implemented yet. So, just return 0 in that case.
3715   // When such analysis are available this place will be the right place for
3716   // calling it.
3717   if (IsIntrinOpcode && SrcOpIdx1 == 1)
3718     return 0;
3719 
3720   unsigned Case;
3721   if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
3722     Case = 0;
3723   else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3724     Case = 1;
3725   else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3726     Case = 2;
3727   else
3728     return 0;
3729 
3730   // Define the FMA forms mapping array that helps to map input FMA form
3731   // to output FMA form to preserve the operation semantics after
3732   // commuting the operands.
3733   static const unsigned FormMapping[][3] = {
3734     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3735     // FMA132 A, C, b; ==> FMA231 C, A, b;
3736     // FMA213 B, A, c; ==> FMA213 A, B, c;
3737     // FMA231 C, A, b; ==> FMA132 A, C, b;
3738     { Form231Index, Form213Index, Form132Index },
3739     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3740     // FMA132 A, c, B; ==> FMA132 B, c, A;
3741     // FMA213 B, a, C; ==> FMA231 C, a, B;
3742     // FMA231 C, a, B; ==> FMA213 B, a, C;
3743     { Form132Index, Form231Index, Form213Index },
3744     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3745     // FMA132 a, C, B; ==> FMA213 a, B, C;
3746     // FMA213 b, A, C; ==> FMA132 b, C, A;
3747     // FMA231 c, A, B; ==> FMA231 c, B, A;
3748     { Form213Index, Form132Index, Form231Index }
3749   };
3750 
3751   // Everything is ready, just adjust the FMA opcode and return it.
3752   FormIndex = FormMapping[Case][FormIndex];
3753   return FoundOpcodesGroup[FormIndex];
3754 }
3755 
3756 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
3757                                          unsigned &SrcOpIdx2) const {
3758   switch (MI.getOpcode()) {
3759   case X86::CMPPDrri:
3760   case X86::CMPPSrri:
3761   case X86::VCMPPDrri:
3762   case X86::VCMPPSrri:
3763   case X86::VCMPPDYrri:
3764   case X86::VCMPPSYrri: {
3765     // Float comparison can be safely commuted for
3766     // Ordered/Unordered/Equal/NotEqual tests
3767     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3768     switch (Imm) {
3769     case 0x00: // EQUAL
3770     case 0x03: // UNORDERED
3771     case 0x04: // NOT EQUAL
3772     case 0x07: // ORDERED
3773       // The indices of the commutable operands are 1 and 2.
3774       // Assign them to the returned operand indices here.
3775       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3776     }
3777     return false;
3778   }
3779   default:
3780     if (isFMA3(MI.getOpcode()))
3781       return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3782     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3783   }
3784   return false;
3785 }
3786 
3787 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3788   switch (BrOpc) {
3789   default: return X86::COND_INVALID;
3790   case X86::JE_1:  return X86::COND_E;
3791   case X86::JNE_1: return X86::COND_NE;
3792   case X86::JL_1:  return X86::COND_L;
3793   case X86::JLE_1: return X86::COND_LE;
3794   case X86::JG_1:  return X86::COND_G;
3795   case X86::JGE_1: return X86::COND_GE;
3796   case X86::JB_1:  return X86::COND_B;
3797   case X86::JBE_1: return X86::COND_BE;
3798   case X86::JA_1:  return X86::COND_A;
3799   case X86::JAE_1: return X86::COND_AE;
3800   case X86::JS_1:  return X86::COND_S;
3801   case X86::JNS_1: return X86::COND_NS;
3802   case X86::JP_1:  return X86::COND_P;
3803   case X86::JNP_1: return X86::COND_NP;
3804   case X86::JO_1:  return X86::COND_O;
3805   case X86::JNO_1: return X86::COND_NO;
3806   }
3807 }
3808 
3809 /// Return condition code of a SET opcode.
3810 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3811   switch (Opc) {
3812   default: return X86::COND_INVALID;
3813   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3814   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3815   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3816   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3817   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3818   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3819   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3820   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3821   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3822   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3823   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3824   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3825   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3826   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3827   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3828   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3829   }
3830 }
3831 
3832 /// Return condition code of a CMov opcode.
3833 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3834   switch (Opc) {
3835   default: return X86::COND_INVALID;
3836   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3837   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3838     return X86::COND_A;
3839   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3840   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3841     return X86::COND_AE;
3842   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3843   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3844     return X86::COND_B;
3845   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3846   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3847     return X86::COND_BE;
3848   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3849   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3850     return X86::COND_E;
3851   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3852   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3853     return X86::COND_G;
3854   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3855   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3856     return X86::COND_GE;
3857   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3858   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3859     return X86::COND_L;
3860   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3861   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3862     return X86::COND_LE;
3863   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3864   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3865     return X86::COND_NE;
3866   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3867   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3868     return X86::COND_NO;
3869   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3870   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3871     return X86::COND_NP;
3872   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3873   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3874     return X86::COND_NS;
3875   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3876   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3877     return X86::COND_O;
3878   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3879   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3880     return X86::COND_P;
3881   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3882   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3883     return X86::COND_S;
3884   }
3885 }
3886 
3887 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3888   switch (CC) {
3889   default: llvm_unreachable("Illegal condition code!");
3890   case X86::COND_E:  return X86::JE_1;
3891   case X86::COND_NE: return X86::JNE_1;
3892   case X86::COND_L:  return X86::JL_1;
3893   case X86::COND_LE: return X86::JLE_1;
3894   case X86::COND_G:  return X86::JG_1;
3895   case X86::COND_GE: return X86::JGE_1;
3896   case X86::COND_B:  return X86::JB_1;
3897   case X86::COND_BE: return X86::JBE_1;
3898   case X86::COND_A:  return X86::JA_1;
3899   case X86::COND_AE: return X86::JAE_1;
3900   case X86::COND_S:  return X86::JS_1;
3901   case X86::COND_NS: return X86::JNS_1;
3902   case X86::COND_P:  return X86::JP_1;
3903   case X86::COND_NP: return X86::JNP_1;
3904   case X86::COND_O:  return X86::JO_1;
3905   case X86::COND_NO: return X86::JNO_1;
3906   }
3907 }
3908 
3909 /// Return the inverse of the specified condition,
3910 /// e.g. turning COND_E to COND_NE.
3911 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3912   switch (CC) {
3913   default: llvm_unreachable("Illegal condition code!");
3914   case X86::COND_E:  return X86::COND_NE;
3915   case X86::COND_NE: return X86::COND_E;
3916   case X86::COND_L:  return X86::COND_GE;
3917   case X86::COND_LE: return X86::COND_G;
3918   case X86::COND_G:  return X86::COND_LE;
3919   case X86::COND_GE: return X86::COND_L;
3920   case X86::COND_B:  return X86::COND_AE;
3921   case X86::COND_BE: return X86::COND_A;
3922   case X86::COND_A:  return X86::COND_BE;
3923   case X86::COND_AE: return X86::COND_B;
3924   case X86::COND_S:  return X86::COND_NS;
3925   case X86::COND_NS: return X86::COND_S;
3926   case X86::COND_P:  return X86::COND_NP;
3927   case X86::COND_NP: return X86::COND_P;
3928   case X86::COND_O:  return X86::COND_NO;
3929   case X86::COND_NO: return X86::COND_O;
3930   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
3931   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
3932   }
3933 }
3934 
3935 /// Assuming the flags are set by MI(a,b), return the condition code if we
3936 /// modify the instructions such that flags are set by MI(b,a).
3937 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3938   switch (CC) {
3939   default: return X86::COND_INVALID;
3940   case X86::COND_E:  return X86::COND_E;
3941   case X86::COND_NE: return X86::COND_NE;
3942   case X86::COND_L:  return X86::COND_G;
3943   case X86::COND_LE: return X86::COND_GE;
3944   case X86::COND_G:  return X86::COND_L;
3945   case X86::COND_GE: return X86::COND_LE;
3946   case X86::COND_B:  return X86::COND_A;
3947   case X86::COND_BE: return X86::COND_AE;
3948   case X86::COND_A:  return X86::COND_B;
3949   case X86::COND_AE: return X86::COND_BE;
3950   }
3951 }
3952 
3953 /// Return a set opcode for the given condition and
3954 /// whether it has memory operand.
3955 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3956   static const uint16_t Opc[16][2] = {
3957     { X86::SETAr,  X86::SETAm  },
3958     { X86::SETAEr, X86::SETAEm },
3959     { X86::SETBr,  X86::SETBm  },
3960     { X86::SETBEr, X86::SETBEm },
3961     { X86::SETEr,  X86::SETEm  },
3962     { X86::SETGr,  X86::SETGm  },
3963     { X86::SETGEr, X86::SETGEm },
3964     { X86::SETLr,  X86::SETLm  },
3965     { X86::SETLEr, X86::SETLEm },
3966     { X86::SETNEr, X86::SETNEm },
3967     { X86::SETNOr, X86::SETNOm },
3968     { X86::SETNPr, X86::SETNPm },
3969     { X86::SETNSr, X86::SETNSm },
3970     { X86::SETOr,  X86::SETOm  },
3971     { X86::SETPr,  X86::SETPm  },
3972     { X86::SETSr,  X86::SETSm  }
3973   };
3974 
3975   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3976   return Opc[CC][HasMemoryOperand ? 1 : 0];
3977 }
3978 
3979 /// Return a cmov opcode for the given condition,
3980 /// register size in bytes, and operand type.
3981 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3982                               bool HasMemoryOperand) {
3983   static const uint16_t Opc[32][3] = {
3984     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3985     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3986     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3987     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3988     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3989     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3990     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3991     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3992     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3993     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3994     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3995     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3996     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3997     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3998     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3999     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
4000     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
4001     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
4002     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
4003     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
4004     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
4005     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
4006     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
4007     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
4008     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
4009     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
4010     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
4011     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
4012     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
4013     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
4014     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
4015     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
4016   };
4017 
4018   assert(CC < 16 && "Can only handle standard cond codes");
4019   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
4020   switch(RegBytes) {
4021   default: llvm_unreachable("Illegal register size!");
4022   case 2: return Opc[Idx][0];
4023   case 4: return Opc[Idx][1];
4024   case 8: return Opc[Idx][2];
4025   }
4026 }
4027 
4028 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
4029   if (!MI.isTerminator()) return false;
4030 
4031   // Conditional branch is a special case.
4032   if (MI.isBranch() && !MI.isBarrier())
4033     return true;
4034   if (!MI.isPredicable())
4035     return true;
4036   return !isPredicated(MI);
4037 }
4038 
4039 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
4040 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
4041 // fallthrough MBB cannot be identified.
4042 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
4043                                             MachineBasicBlock *TBB) {
4044   // Look for non-EHPad successors other than TBB. If we find exactly one, it
4045   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
4046   // and fallthrough MBB. If we find more than one, we cannot identify the
4047   // fallthrough MBB and should return nullptr.
4048   MachineBasicBlock *FallthroughBB = nullptr;
4049   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
4050     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
4051       continue;
4052     // Return a nullptr if we found more than one fallthrough successor.
4053     if (FallthroughBB && FallthroughBB != TBB)
4054       return nullptr;
4055     FallthroughBB = *SI;
4056   }
4057   return FallthroughBB;
4058 }
4059 
4060 bool X86InstrInfo::AnalyzeBranchImpl(
4061     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
4062     SmallVectorImpl<MachineOperand> &Cond,
4063     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
4064 
4065   // Start from the bottom of the block and work up, examining the
4066   // terminator instructions.
4067   MachineBasicBlock::iterator I = MBB.end();
4068   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
4069   while (I != MBB.begin()) {
4070     --I;
4071     if (I->isDebugValue())
4072       continue;
4073 
4074     // Working from the bottom, when we see a non-terminator instruction, we're
4075     // done.
4076     if (!isUnpredicatedTerminator(*I))
4077       break;
4078 
4079     // A terminator that isn't a branch can't easily be handled by this
4080     // analysis.
4081     if (!I->isBranch())
4082       return true;
4083 
4084     // Handle unconditional branches.
4085     if (I->getOpcode() == X86::JMP_1) {
4086       UnCondBrIter = I;
4087 
4088       if (!AllowModify) {
4089         TBB = I->getOperand(0).getMBB();
4090         continue;
4091       }
4092 
4093       // If the block has any instructions after a JMP, delete them.
4094       while (std::next(I) != MBB.end())
4095         std::next(I)->eraseFromParent();
4096 
4097       Cond.clear();
4098       FBB = nullptr;
4099 
4100       // Delete the JMP if it's equivalent to a fall-through.
4101       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
4102         TBB = nullptr;
4103         I->eraseFromParent();
4104         I = MBB.end();
4105         UnCondBrIter = MBB.end();
4106         continue;
4107       }
4108 
4109       // TBB is used to indicate the unconditional destination.
4110       TBB = I->getOperand(0).getMBB();
4111       continue;
4112     }
4113 
4114     // Handle conditional branches.
4115     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
4116     if (BranchCode == X86::COND_INVALID)
4117       return true;  // Can't handle indirect branch.
4118 
4119     // Working from the bottom, handle the first conditional branch.
4120     if (Cond.empty()) {
4121       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4122       if (AllowModify && UnCondBrIter != MBB.end() &&
4123           MBB.isLayoutSuccessor(TargetBB)) {
4124         // If we can modify the code and it ends in something like:
4125         //
4126         //     jCC L1
4127         //     jmp L2
4128         //   L1:
4129         //     ...
4130         //   L2:
4131         //
4132         // Then we can change this to:
4133         //
4134         //     jnCC L2
4135         //   L1:
4136         //     ...
4137         //   L2:
4138         //
4139         // Which is a bit more efficient.
4140         // We conditionally jump to the fall-through block.
4141         BranchCode = GetOppositeBranchCondition(BranchCode);
4142         unsigned JNCC = GetCondBranchFromCond(BranchCode);
4143         MachineBasicBlock::iterator OldInst = I;
4144 
4145         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
4146           .addMBB(UnCondBrIter->getOperand(0).getMBB());
4147         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
4148           .addMBB(TargetBB);
4149 
4150         OldInst->eraseFromParent();
4151         UnCondBrIter->eraseFromParent();
4152 
4153         // Restart the analysis.
4154         UnCondBrIter = MBB.end();
4155         I = MBB.end();
4156         continue;
4157       }
4158 
4159       FBB = TBB;
4160       TBB = I->getOperand(0).getMBB();
4161       Cond.push_back(MachineOperand::CreateImm(BranchCode));
4162       CondBranches.push_back(&*I);
4163       continue;
4164     }
4165 
4166     // Handle subsequent conditional branches. Only handle the case where all
4167     // conditional branches branch to the same destination and their condition
4168     // opcodes fit one of the special multi-branch idioms.
4169     assert(Cond.size() == 1);
4170     assert(TBB);
4171 
4172     // If the conditions are the same, we can leave them alone.
4173     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
4174     auto NewTBB = I->getOperand(0).getMBB();
4175     if (OldBranchCode == BranchCode && TBB == NewTBB)
4176       continue;
4177 
4178     // If they differ, see if they fit one of the known patterns. Theoretically,
4179     // we could handle more patterns here, but we shouldn't expect to see them
4180     // if instruction selection has done a reasonable job.
4181     if (TBB == NewTBB &&
4182                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4183                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
4184       BranchCode = X86::COND_NE_OR_P;
4185     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4186                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4187       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4188         return true;
4189 
4190       // X86::COND_E_AND_NP usually has two different branch destinations.
4191       //
4192       // JP B1
4193       // JE B2
4194       // JMP B1
4195       // B1:
4196       // B2:
4197       //
4198       // Here this condition branches to B2 only if NP && E. It has another
4199       // equivalent form:
4200       //
4201       // JNE B1
4202       // JNP B2
4203       // JMP B1
4204       // B1:
4205       // B2:
4206       //
4207       // Similarly it branches to B2 only if E && NP. That is why this condition
4208       // is named with COND_E_AND_NP.
4209       BranchCode = X86::COND_E_AND_NP;
4210     } else
4211       return true;
4212 
4213     // Update the MachineOperand.
4214     Cond[0].setImm(BranchCode);
4215     CondBranches.push_back(&*I);
4216   }
4217 
4218   return false;
4219 }
4220 
4221 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
4222                                  MachineBasicBlock *&TBB,
4223                                  MachineBasicBlock *&FBB,
4224                                  SmallVectorImpl<MachineOperand> &Cond,
4225                                  bool AllowModify) const {
4226   SmallVector<MachineInstr *, 4> CondBranches;
4227   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4228 }
4229 
4230 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
4231                                           MachineBranchPredicate &MBP,
4232                                           bool AllowModify) const {
4233   using namespace std::placeholders;
4234 
4235   SmallVector<MachineOperand, 4> Cond;
4236   SmallVector<MachineInstr *, 4> CondBranches;
4237   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4238                         AllowModify))
4239     return true;
4240 
4241   if (Cond.size() != 1)
4242     return true;
4243 
4244   assert(MBP.TrueDest && "expected!");
4245 
4246   if (!MBP.FalseDest)
4247     MBP.FalseDest = MBB.getNextNode();
4248 
4249   const TargetRegisterInfo *TRI = &getRegisterInfo();
4250 
4251   MachineInstr *ConditionDef = nullptr;
4252   bool SingleUseCondition = true;
4253 
4254   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4255     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4256       ConditionDef = &*I;
4257       break;
4258     }
4259 
4260     if (I->readsRegister(X86::EFLAGS, TRI))
4261       SingleUseCondition = false;
4262   }
4263 
4264   if (!ConditionDef)
4265     return true;
4266 
4267   if (SingleUseCondition) {
4268     for (auto *Succ : MBB.successors())
4269       if (Succ->isLiveIn(X86::EFLAGS))
4270         SingleUseCondition = false;
4271   }
4272 
4273   MBP.ConditionDef = ConditionDef;
4274   MBP.SingleUseCondition = SingleUseCondition;
4275 
4276   // Currently we only recognize the simple pattern:
4277   //
4278   //   test %reg, %reg
4279   //   je %label
4280   //
4281   const unsigned TestOpcode =
4282       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4283 
4284   if (ConditionDef->getOpcode() == TestOpcode &&
4285       ConditionDef->getNumOperands() == 3 &&
4286       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4287       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4288     MBP.LHS = ConditionDef->getOperand(0);
4289     MBP.RHS = MachineOperand::CreateImm(0);
4290     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4291                         ? MachineBranchPredicate::PRED_NE
4292                         : MachineBranchPredicate::PRED_EQ;
4293     return false;
4294   }
4295 
4296   return true;
4297 }
4298 
4299 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
4300   MachineBasicBlock::iterator I = MBB.end();
4301   unsigned Count = 0;
4302 
4303   while (I != MBB.begin()) {
4304     --I;
4305     if (I->isDebugValue())
4306       continue;
4307     if (I->getOpcode() != X86::JMP_1 &&
4308         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4309       break;
4310     // Remove the branch.
4311     I->eraseFromParent();
4312     I = MBB.end();
4313     ++Count;
4314   }
4315 
4316   return Count;
4317 }
4318 
4319 unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4320                                     MachineBasicBlock *TBB,
4321                                     MachineBasicBlock *FBB,
4322                                     ArrayRef<MachineOperand> Cond,
4323                                     const DebugLoc &DL) const {
4324   // Shouldn't be a fall through.
4325   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
4326   assert((Cond.size() == 1 || Cond.size() == 0) &&
4327          "X86 branch conditions have one component!");
4328 
4329   if (Cond.empty()) {
4330     // Unconditional branch?
4331     assert(!FBB && "Unconditional branch with multiple successors!");
4332     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4333     return 1;
4334   }
4335 
4336   // If FBB is null, it is implied to be a fall-through block.
4337   bool FallThru = FBB == nullptr;
4338 
4339   // Conditional branch.
4340   unsigned Count = 0;
4341   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4342   switch (CC) {
4343   case X86::COND_NE_OR_P:
4344     // Synthesize NE_OR_P with two branches.
4345     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4346     ++Count;
4347     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4348     ++Count;
4349     break;
4350   case X86::COND_E_AND_NP:
4351     // Use the next block of MBB as FBB if it is null.
4352     if (FBB == nullptr) {
4353       FBB = getFallThroughMBB(&MBB, TBB);
4354       assert(FBB && "MBB cannot be the last block in function when the false "
4355                     "body is a fall-through.");
4356     }
4357     // Synthesize COND_E_AND_NP with two branches.
4358     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4359     ++Count;
4360     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4361     ++Count;
4362     break;
4363   default: {
4364     unsigned Opc = GetCondBranchFromCond(CC);
4365     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4366     ++Count;
4367   }
4368   }
4369   if (!FallThru) {
4370     // Two-way Conditional branch. Insert the second branch.
4371     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4372     ++Count;
4373   }
4374   return Count;
4375 }
4376 
4377 bool X86InstrInfo::
4378 canInsertSelect(const MachineBasicBlock &MBB,
4379                 ArrayRef<MachineOperand> Cond,
4380                 unsigned TrueReg, unsigned FalseReg,
4381                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4382   // Not all subtargets have cmov instructions.
4383   if (!Subtarget.hasCMov())
4384     return false;
4385   if (Cond.size() != 1)
4386     return false;
4387   // We cannot do the composite conditions, at least not in SSA form.
4388   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4389     return false;
4390 
4391   // Check register classes.
4392   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4393   const TargetRegisterClass *RC =
4394     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4395   if (!RC)
4396     return false;
4397 
4398   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4399   if (X86::GR16RegClass.hasSubClassEq(RC) ||
4400       X86::GR32RegClass.hasSubClassEq(RC) ||
4401       X86::GR64RegClass.hasSubClassEq(RC)) {
4402     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4403     // Bridge. Probably Ivy Bridge as well.
4404     CondCycles = 2;
4405     TrueCycles = 2;
4406     FalseCycles = 2;
4407     return true;
4408   }
4409 
4410   // Can't do vectors.
4411   return false;
4412 }
4413 
4414 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4415                                 MachineBasicBlock::iterator I,
4416                                 const DebugLoc &DL, unsigned DstReg,
4417                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4418                                 unsigned FalseReg) const {
4419   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4420   assert(Cond.size() == 1 && "Invalid Cond array");
4421   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4422                                  MRI.getRegClass(DstReg)->getSize(),
4423                                  false /*HasMemoryOperand*/);
4424   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4425 }
4426 
4427 /// Test if the given register is a physical h register.
4428 static bool isHReg(unsigned Reg) {
4429   return X86::GR8_ABCD_HRegClass.contains(Reg);
4430 }
4431 
4432 // Try and copy between VR128/VR64 and GR64 registers.
4433 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
4434                                         const X86Subtarget &Subtarget) {
4435 
4436   // SrcReg(VR128) -> DestReg(GR64)
4437   // SrcReg(VR64)  -> DestReg(GR64)
4438   // SrcReg(GR64)  -> DestReg(VR128)
4439   // SrcReg(GR64)  -> DestReg(VR64)
4440 
4441   bool HasAVX = Subtarget.hasAVX();
4442   bool HasAVX512 = Subtarget.hasAVX512();
4443   if (X86::GR64RegClass.contains(DestReg)) {
4444     if (X86::VR128XRegClass.contains(SrcReg))
4445       // Copy from a VR128 register to a GR64 register.
4446       return HasAVX512 ? X86::VMOVPQIto64Zrr :
4447              HasAVX    ? X86::VMOVPQIto64rr  :
4448                          X86::MOVPQIto64rr;
4449     if (X86::VR64RegClass.contains(SrcReg))
4450       // Copy from a VR64 register to a GR64 register.
4451       return X86::MMX_MOVD64from64rr;
4452   } else if (X86::GR64RegClass.contains(SrcReg)) {
4453     // Copy from a GR64 register to a VR128 register.
4454     if (X86::VR128XRegClass.contains(DestReg))
4455       return HasAVX512 ? X86::VMOV64toPQIZrr :
4456              HasAVX    ? X86::VMOV64toPQIrr  :
4457                          X86::MOV64toPQIrr;
4458     // Copy from a GR64 register to a VR64 register.
4459     if (X86::VR64RegClass.contains(DestReg))
4460       return X86::MMX_MOVD64to64rr;
4461   }
4462 
4463   // SrcReg(FR32) -> DestReg(GR32)
4464   // SrcReg(GR32) -> DestReg(FR32)
4465 
4466   if (X86::GR32RegClass.contains(DestReg) &&
4467       X86::FR32XRegClass.contains(SrcReg))
4468     // Copy from a FR32 register to a GR32 register.
4469     return HasAVX512 ? X86::VMOVSS2DIZrr :
4470            HasAVX    ? X86::VMOVSS2DIrr  :
4471                        X86::MOVSS2DIrr;
4472 
4473   if (X86::FR32XRegClass.contains(DestReg) &&
4474       X86::GR32RegClass.contains(SrcReg))
4475     // Copy from a GR32 register to a FR32 register.
4476     return HasAVX512 ? X86::VMOVDI2SSZrr :
4477            HasAVX    ? X86::VMOVDI2SSrr  :
4478                        X86::MOVDI2SSrr;
4479   return 0;
4480 }
4481 
4482 static bool isMaskRegClass(const TargetRegisterClass *RC) {
4483   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4484   return X86::VK16RegClass.hasSubClassEq(RC);
4485 }
4486 
4487 static bool MaskRegClassContains(unsigned Reg) {
4488   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4489   return X86::VK16RegClass.contains(Reg);
4490 }
4491 
4492 static bool GRRegClassContains(unsigned Reg) {
4493   return X86::GR64RegClass.contains(Reg) ||
4494          X86::GR32RegClass.contains(Reg) ||
4495          X86::GR16RegClass.contains(Reg) ||
4496          X86::GR8RegClass.contains(Reg);
4497 }
4498 static
4499 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4500   if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4501     DestReg = getX86SubSuperRegister(DestReg, 32);
4502     return X86::KMOVBrk;
4503   }
4504   if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4505     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4506     return X86::KMOVBkr;
4507   }
4508   return 0;
4509 }
4510 
4511 static
4512 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4513   if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4514     return X86::KMOVQkk;
4515   if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4516     return X86::KMOVDrk;
4517   if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4518     return X86::KMOVQrk;
4519   if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4520     return X86::KMOVDkr;
4521   if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4522     return X86::KMOVQkr;
4523   return 0;
4524 }
4525 
4526 static
4527 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4528                                   const X86Subtarget &Subtarget)
4529 {
4530   if (Subtarget.hasDQI())
4531     if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4532       return Opc;
4533   if (Subtarget.hasBWI())
4534     if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4535       return Opc;
4536   if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
4537     if (Subtarget.hasVLX())
4538       return X86::VMOVAPSZ128rr;
4539    DestReg = get512BitSuperRegister(DestReg);
4540    SrcReg = get512BitSuperRegister(SrcReg);
4541    return X86::VMOVAPSZrr;
4542   }
4543   if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
4544     if (Subtarget.hasVLX())
4545       return X86::VMOVAPSZ256rr;
4546    DestReg = get512BitSuperRegister(DestReg);
4547    SrcReg = get512BitSuperRegister(SrcReg);
4548    return X86::VMOVAPSZrr;
4549   }
4550   if (X86::VR512RegClass.contains(DestReg, SrcReg))
4551      return X86::VMOVAPSZrr;
4552   if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
4553     return X86::KMOVWkk;
4554   if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
4555     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4556     return X86::KMOVWkr;
4557   }
4558   if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
4559     DestReg = getX86SubSuperRegister(DestReg, 32);
4560     return X86::KMOVWrk;
4561   }
4562   return 0;
4563 }
4564 
4565 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4566                                MachineBasicBlock::iterator MI,
4567                                const DebugLoc &DL, unsigned DestReg,
4568                                unsigned SrcReg, bool KillSrc) const {
4569   // First deal with the normal symmetric copies.
4570   bool HasAVX = Subtarget.hasAVX();
4571   bool HasAVX512 = Subtarget.hasAVX512();
4572   unsigned Opc = 0;
4573   if (X86::GR64RegClass.contains(DestReg, SrcReg))
4574     Opc = X86::MOV64rr;
4575   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4576     Opc = X86::MOV32rr;
4577   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4578     Opc = X86::MOV16rr;
4579   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4580     // Copying to or from a physical H register on x86-64 requires a NOREX
4581     // move.  Otherwise use a normal move.
4582     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4583         Subtarget.is64Bit()) {
4584       Opc = X86::MOV8rr_NOREX;
4585       // Both operands must be encodable without an REX prefix.
4586       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4587              "8-bit H register can not be copied outside GR8_NOREX");
4588     } else
4589       Opc = X86::MOV8rr;
4590   }
4591   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4592     Opc = X86::MMX_MOVQ64rr;
4593   else if (HasAVX512)
4594     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
4595   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4596     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4597   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4598     Opc = X86::VMOVAPSYrr;
4599   if (!Opc)
4600     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4601 
4602   if (Opc) {
4603     BuildMI(MBB, MI, DL, get(Opc), DestReg)
4604       .addReg(SrcReg, getKillRegState(KillSrc));
4605     return;
4606   }
4607 
4608   bool FromEFLAGS = SrcReg == X86::EFLAGS;
4609   bool ToEFLAGS = DestReg == X86::EFLAGS;
4610   int Reg = FromEFLAGS ? DestReg : SrcReg;
4611   bool is32 = X86::GR32RegClass.contains(Reg);
4612   bool is64 = X86::GR64RegClass.contains(Reg);
4613 
4614   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4615     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4616     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4617     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4618     int Pop = is64 ? X86::POP64r : X86::POP32r;
4619     int PopF = is64 ? X86::POPF64 : X86::POPF32;
4620     int AX = is64 ? X86::RAX : X86::EAX;
4621 
4622     if (!Subtarget.hasLAHFSAHF()) {
4623       assert(Subtarget.is64Bit() &&
4624              "Not having LAHF/SAHF only happens on 64-bit.");
4625       // Moving EFLAGS to / from another register requires a push and a pop.
4626       // Notice that we have to adjust the stack if we don't want to clobber the
4627       // first frame index. See X86FrameLowering.cpp - usesTheStack.
4628       if (FromEFLAGS) {
4629         BuildMI(MBB, MI, DL, get(PushF));
4630         BuildMI(MBB, MI, DL, get(Pop), DestReg);
4631       }
4632       if (ToEFLAGS) {
4633         BuildMI(MBB, MI, DL, get(Push))
4634             .addReg(SrcReg, getKillRegState(KillSrc));
4635         BuildMI(MBB, MI, DL, get(PopF));
4636       }
4637       return;
4638     }
4639 
4640     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4641     // inefficient. Instead:
4642     //   - Save the overflow flag OF into AL using SETO, and restore it using a
4643     //     signed 8-bit addition of AL and INT8_MAX.
4644     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4645     //     using LAHF/SAHF.
4646     //   - When RAX/EAX is live and isn't the destination register, make sure it
4647     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4648     //     the flags.
4649     // This approach is ~2.25x faster than using PUSHF/POPF.
4650     //
4651     // This is still somewhat inefficient because we don't know which flags are
4652     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4653     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4654     //
4655     // PUSHF/POPF is also potentially incorrect because it affects other flags
4656     // such as TF/IF/DF, which LLVM doesn't model.
4657     //
4658     // Notice that we have to adjust the stack if we don't want to clobber the
4659     // first frame index.
4660     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
4661 
4662     const TargetRegisterInfo *TRI = &getRegisterInfo();
4663     MachineBasicBlock::LivenessQueryResult LQR =
4664         MBB.computeRegisterLiveness(TRI, AX, MI);
4665     // We do not want to save and restore AX if we do not have to.
4666     // Moreover, if we do so whereas AX is dead, we would need to set
4667     // an undef flag on the use of AX, otherwise the verifier will
4668     // complain that we read an undef value.
4669     // We do not want to change the behavior of the machine verifier
4670     // as this is usually wrong to read an undef value.
4671     if (MachineBasicBlock::LQR_Unknown == LQR) {
4672       LivePhysRegs LPR(TRI);
4673       LPR.addLiveOuts(MBB);
4674       MachineBasicBlock::iterator I = MBB.end();
4675       while (I != MI) {
4676         --I;
4677         LPR.stepBackward(*I);
4678       }
4679       // AX contains the top most register in the aliasing hierarchy.
4680       // It may not be live, but one of its aliases may be.
4681       for (MCRegAliasIterator AI(AX, TRI, true);
4682            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4683         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4684                                 : MachineBasicBlock::LQR_Dead;
4685     }
4686     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4687     if (!AXDead)
4688       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4689     if (FromEFLAGS) {
4690       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4691       BuildMI(MBB, MI, DL, get(X86::LAHF));
4692       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
4693     }
4694     if (ToEFLAGS) {
4695       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4696       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4697           .addReg(X86::AL)
4698           .addImm(INT8_MAX);
4699       BuildMI(MBB, MI, DL, get(X86::SAHF));
4700     }
4701     if (!AXDead)
4702       BuildMI(MBB, MI, DL, get(Pop), AX);
4703     return;
4704   }
4705 
4706   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4707                << " to " << RI.getName(DestReg) << '\n');
4708   llvm_unreachable("Cannot emit physreg copy instruction");
4709 }
4710 
4711 static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4712                                           bool load) {
4713   switch (RC->getSize()) {
4714   default:
4715     llvm_unreachable("Unknown spill size");
4716   case 2:
4717     return load ? X86::KMOVWkm : X86::KMOVWmk;
4718   case 4:
4719     return load ? X86::KMOVDkm : X86::KMOVDmk;
4720   case 8:
4721     return load ? X86::KMOVQkm : X86::KMOVQmk;
4722   }
4723 }
4724 
4725 static unsigned getLoadStoreRegOpcode(unsigned Reg,
4726                                       const TargetRegisterClass *RC,
4727                                       bool isStackAligned,
4728                                       const X86Subtarget &STI,
4729                                       bool load) {
4730   if (STI.hasAVX512()) {
4731     if (isMaskRegClass(RC))
4732       return getLoadStoreMaskRegOpcode(RC, load);
4733     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
4734       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
4735     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
4736       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
4737     if (X86::VR512RegClass.hasSubClassEq(RC))
4738       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4739   }
4740 
4741   bool HasAVX = STI.hasAVX();
4742   switch (RC->getSize()) {
4743   default:
4744     llvm_unreachable("Unknown spill size");
4745   case 1:
4746     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4747     if (STI.is64Bit())
4748       // Copying to or from a physical H register on x86-64 requires a NOREX
4749       // move.  Otherwise use a normal move.
4750       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4751         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4752     return load ? X86::MOV8rm : X86::MOV8mr;
4753   case 2:
4754     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4755     return load ? X86::MOV16rm : X86::MOV16mr;
4756   case 4:
4757     if (X86::GR32RegClass.hasSubClassEq(RC))
4758       return load ? X86::MOV32rm : X86::MOV32mr;
4759     if (X86::FR32RegClass.hasSubClassEq(RC))
4760       return load ?
4761         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4762         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4763     if (X86::RFP32RegClass.hasSubClassEq(RC))
4764       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4765     llvm_unreachable("Unknown 4-byte regclass");
4766   case 8:
4767     if (X86::GR64RegClass.hasSubClassEq(RC))
4768       return load ? X86::MOV64rm : X86::MOV64mr;
4769     if (X86::FR64RegClass.hasSubClassEq(RC))
4770       return load ?
4771         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4772         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4773     if (X86::VR64RegClass.hasSubClassEq(RC))
4774       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4775     if (X86::RFP64RegClass.hasSubClassEq(RC))
4776       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4777     llvm_unreachable("Unknown 8-byte regclass");
4778   case 10:
4779     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4780     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4781   case 16: {
4782     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4783             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
4784     // If stack is realigned we can use aligned stores.
4785     if (X86::VR128RegClass.hasSubClassEq(RC)) {
4786       if (isStackAligned)
4787         return load ? (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
4788                     : (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4789       else
4790         return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
4791                     : (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4792     }
4793     assert(STI.hasVLX() && "Using extended register requires VLX");
4794     if (isStackAligned)
4795       return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr;
4796     else
4797       return load ? X86::VMOVUPSZ128rm : X86::VMOVUPSZ128mr;
4798   }
4799   case 32:
4800     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4801             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
4802     // If stack is realigned we can use aligned stores.
4803     if (X86::VR256RegClass.hasSubClassEq(RC)) {
4804       if (isStackAligned)
4805         return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4806       else
4807         return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4808     }
4809     assert(STI.hasVLX() && "Using extended register requires VLX");
4810     if (isStackAligned)
4811       return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr;
4812     else
4813       return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
4814   case 64:
4815     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4816     assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
4817     if (isStackAligned)
4818       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4819     else
4820       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4821   }
4822 }
4823 
4824 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
4825                                          int64_t &Offset,
4826                                          const TargetRegisterInfo *TRI) const {
4827   const MCInstrDesc &Desc = MemOp.getDesc();
4828   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
4829   if (MemRefBegin < 0)
4830     return false;
4831 
4832   MemRefBegin += X86II::getOperandBias(Desc);
4833 
4834   MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
4835   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4836     return false;
4837 
4838   BaseReg = BaseMO.getReg();
4839   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4840     return false;
4841 
4842   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4843       X86::NoRegister)
4844     return false;
4845 
4846   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
4847 
4848   // Displacement can be symbolic
4849   if (!DispMO.isImm())
4850     return false;
4851 
4852   Offset = DispMO.getImm();
4853 
4854   return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4855          X86::NoRegister;
4856 }
4857 
4858 static unsigned getStoreRegOpcode(unsigned SrcReg,
4859                                   const TargetRegisterClass *RC,
4860                                   bool isStackAligned,
4861                                   const X86Subtarget &STI) {
4862   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4863 }
4864 
4865 
4866 static unsigned getLoadRegOpcode(unsigned DestReg,
4867                                  const TargetRegisterClass *RC,
4868                                  bool isStackAligned,
4869                                  const X86Subtarget &STI) {
4870   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4871 }
4872 
4873 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4874                                        MachineBasicBlock::iterator MI,
4875                                        unsigned SrcReg, bool isKill, int FrameIdx,
4876                                        const TargetRegisterClass *RC,
4877                                        const TargetRegisterInfo *TRI) const {
4878   const MachineFunction &MF = *MBB.getParent();
4879   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4880          "Stack slot too small for store");
4881   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4882   bool isAligned =
4883       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4884       RI.canRealignStack(MF);
4885   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4886   DebugLoc DL = MBB.findDebugLoc(MI);
4887   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4888     .addReg(SrcReg, getKillRegState(isKill));
4889 }
4890 
4891 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4892                                   bool isKill,
4893                                   SmallVectorImpl<MachineOperand> &Addr,
4894                                   const TargetRegisterClass *RC,
4895                                   MachineInstr::mmo_iterator MMOBegin,
4896                                   MachineInstr::mmo_iterator MMOEnd,
4897                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
4898   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4899   bool isAligned = MMOBegin != MMOEnd &&
4900                    (*MMOBegin)->getAlignment() >= Alignment;
4901   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4902   DebugLoc DL;
4903   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4904   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4905     MIB.addOperand(Addr[i]);
4906   MIB.addReg(SrcReg, getKillRegState(isKill));
4907   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4908   NewMIs.push_back(MIB);
4909 }
4910 
4911 
4912 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4913                                         MachineBasicBlock::iterator MI,
4914                                         unsigned DestReg, int FrameIdx,
4915                                         const TargetRegisterClass *RC,
4916                                         const TargetRegisterInfo *TRI) const {
4917   const MachineFunction &MF = *MBB.getParent();
4918   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4919   bool isAligned =
4920       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4921       RI.canRealignStack(MF);
4922   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4923   DebugLoc DL = MBB.findDebugLoc(MI);
4924   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4925 }
4926 
4927 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4928                                  SmallVectorImpl<MachineOperand> &Addr,
4929                                  const TargetRegisterClass *RC,
4930                                  MachineInstr::mmo_iterator MMOBegin,
4931                                  MachineInstr::mmo_iterator MMOEnd,
4932                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
4933   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4934   bool isAligned = MMOBegin != MMOEnd &&
4935                    (*MMOBegin)->getAlignment() >= Alignment;
4936   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4937   DebugLoc DL;
4938   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4939   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4940     MIB.addOperand(Addr[i]);
4941   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4942   NewMIs.push_back(MIB);
4943 }
4944 
4945 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
4946                                   unsigned &SrcReg2, int &CmpMask,
4947                                   int &CmpValue) const {
4948   switch (MI.getOpcode()) {
4949   default: break;
4950   case X86::CMP64ri32:
4951   case X86::CMP64ri8:
4952   case X86::CMP32ri:
4953   case X86::CMP32ri8:
4954   case X86::CMP16ri:
4955   case X86::CMP16ri8:
4956   case X86::CMP8ri:
4957     SrcReg = MI.getOperand(0).getReg();
4958     SrcReg2 = 0;
4959     CmpMask = ~0;
4960     CmpValue = MI.getOperand(1).getImm();
4961     return true;
4962   // A SUB can be used to perform comparison.
4963   case X86::SUB64rm:
4964   case X86::SUB32rm:
4965   case X86::SUB16rm:
4966   case X86::SUB8rm:
4967     SrcReg = MI.getOperand(1).getReg();
4968     SrcReg2 = 0;
4969     CmpMask = ~0;
4970     CmpValue = 0;
4971     return true;
4972   case X86::SUB64rr:
4973   case X86::SUB32rr:
4974   case X86::SUB16rr:
4975   case X86::SUB8rr:
4976     SrcReg = MI.getOperand(1).getReg();
4977     SrcReg2 = MI.getOperand(2).getReg();
4978     CmpMask = ~0;
4979     CmpValue = 0;
4980     return true;
4981   case X86::SUB64ri32:
4982   case X86::SUB64ri8:
4983   case X86::SUB32ri:
4984   case X86::SUB32ri8:
4985   case X86::SUB16ri:
4986   case X86::SUB16ri8:
4987   case X86::SUB8ri:
4988     SrcReg = MI.getOperand(1).getReg();
4989     SrcReg2 = 0;
4990     CmpMask = ~0;
4991     CmpValue = MI.getOperand(2).getImm();
4992     return true;
4993   case X86::CMP64rr:
4994   case X86::CMP32rr:
4995   case X86::CMP16rr:
4996   case X86::CMP8rr:
4997     SrcReg = MI.getOperand(0).getReg();
4998     SrcReg2 = MI.getOperand(1).getReg();
4999     CmpMask = ~0;
5000     CmpValue = 0;
5001     return true;
5002   case X86::TEST8rr:
5003   case X86::TEST16rr:
5004   case X86::TEST32rr:
5005   case X86::TEST64rr:
5006     SrcReg = MI.getOperand(0).getReg();
5007     if (MI.getOperand(1).getReg() != SrcReg)
5008       return false;
5009     // Compare against zero.
5010     SrcReg2 = 0;
5011     CmpMask = ~0;
5012     CmpValue = 0;
5013     return true;
5014   }
5015   return false;
5016 }
5017 
5018 /// Check whether the first instruction, whose only
5019 /// purpose is to update flags, can be made redundant.
5020 /// CMPrr can be made redundant by SUBrr if the operands are the same.
5021 /// This function can be extended later on.
5022 /// SrcReg, SrcRegs: register operands for FlagI.
5023 /// ImmValue: immediate for FlagI if it takes an immediate.
5024 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
5025                                         unsigned SrcReg2, int ImmValue,
5026                                         MachineInstr &OI) {
5027   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
5028        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
5029        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
5030        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
5031       ((OI.getOperand(1).getReg() == SrcReg &&
5032         OI.getOperand(2).getReg() == SrcReg2) ||
5033        (OI.getOperand(1).getReg() == SrcReg2 &&
5034         OI.getOperand(2).getReg() == SrcReg)))
5035     return true;
5036 
5037   if (((FlagI.getOpcode() == X86::CMP64ri32 &&
5038         OI.getOpcode() == X86::SUB64ri32) ||
5039        (FlagI.getOpcode() == X86::CMP64ri8 &&
5040         OI.getOpcode() == X86::SUB64ri8) ||
5041        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
5042        (FlagI.getOpcode() == X86::CMP32ri8 &&
5043         OI.getOpcode() == X86::SUB32ri8) ||
5044        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
5045        (FlagI.getOpcode() == X86::CMP16ri8 &&
5046         OI.getOpcode() == X86::SUB16ri8) ||
5047        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
5048       OI.getOperand(1).getReg() == SrcReg &&
5049       OI.getOperand(2).getImm() == ImmValue)
5050     return true;
5051   return false;
5052 }
5053 
5054 /// Check whether the definition can be converted
5055 /// to remove a comparison against zero.
5056 inline static bool isDefConvertible(MachineInstr &MI) {
5057   switch (MI.getOpcode()) {
5058   default: return false;
5059 
5060   // The shift instructions only modify ZF if their shift count is non-zero.
5061   // N.B.: The processor truncates the shift count depending on the encoding.
5062   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
5063   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
5064      return getTruncatedShiftCount(MI, 2) != 0;
5065 
5066   // Some left shift instructions can be turned into LEA instructions but only
5067   // if their flags aren't used. Avoid transforming such instructions.
5068   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
5069     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
5070     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
5071     return ShAmt != 0;
5072   }
5073 
5074   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
5075   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
5076      return getTruncatedShiftCount(MI, 3) != 0;
5077 
5078   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
5079   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
5080   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
5081   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
5082   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
5083   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
5084   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
5085   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
5086   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
5087   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
5088   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
5089   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
5090   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
5091   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
5092   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
5093   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
5094   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
5095   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
5096   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
5097   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
5098   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
5099   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
5100   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
5101   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
5102   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
5103   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
5104   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
5105   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
5106   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
5107   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
5108   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
5109   case X86::ADC32ri:   case X86::ADC32ri8:
5110   case X86::ADC32rr:   case X86::ADC64ri32:
5111   case X86::ADC64ri8:  case X86::ADC64rr:
5112   case X86::SBB32ri:   case X86::SBB32ri8:
5113   case X86::SBB32rr:   case X86::SBB64ri32:
5114   case X86::SBB64ri8:  case X86::SBB64rr:
5115   case X86::ANDN32rr:  case X86::ANDN32rm:
5116   case X86::ANDN64rr:  case X86::ANDN64rm:
5117   case X86::BEXTR32rr: case X86::BEXTR64rr:
5118   case X86::BEXTR32rm: case X86::BEXTR64rm:
5119   case X86::BLSI32rr:  case X86::BLSI32rm:
5120   case X86::BLSI64rr:  case X86::BLSI64rm:
5121   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5122   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5123   case X86::BLSR32rr:  case X86::BLSR32rm:
5124   case X86::BLSR64rr:  case X86::BLSR64rm:
5125   case X86::BZHI32rr:  case X86::BZHI32rm:
5126   case X86::BZHI64rr:  case X86::BZHI64rm:
5127   case X86::LZCNT16rr: case X86::LZCNT16rm:
5128   case X86::LZCNT32rr: case X86::LZCNT32rm:
5129   case X86::LZCNT64rr: case X86::LZCNT64rm:
5130   case X86::POPCNT16rr:case X86::POPCNT16rm:
5131   case X86::POPCNT32rr:case X86::POPCNT32rm:
5132   case X86::POPCNT64rr:case X86::POPCNT64rm:
5133   case X86::TZCNT16rr: case X86::TZCNT16rm:
5134   case X86::TZCNT32rr: case X86::TZCNT32rm:
5135   case X86::TZCNT64rr: case X86::TZCNT64rm:
5136     return true;
5137   }
5138 }
5139 
5140 /// Check whether the use can be converted to remove a comparison against zero.
5141 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5142   switch (MI.getOpcode()) {
5143   default: return X86::COND_INVALID;
5144   case X86::LZCNT16rr: case X86::LZCNT16rm:
5145   case X86::LZCNT32rr: case X86::LZCNT32rm:
5146   case X86::LZCNT64rr: case X86::LZCNT64rm:
5147     return X86::COND_B;
5148   case X86::POPCNT16rr:case X86::POPCNT16rm:
5149   case X86::POPCNT32rr:case X86::POPCNT32rm:
5150   case X86::POPCNT64rr:case X86::POPCNT64rm:
5151     return X86::COND_E;
5152   case X86::TZCNT16rr: case X86::TZCNT16rm:
5153   case X86::TZCNT32rr: case X86::TZCNT32rm:
5154   case X86::TZCNT64rr: case X86::TZCNT64rm:
5155     return X86::COND_B;
5156   }
5157 }
5158 
5159 /// Check if there exists an earlier instruction that
5160 /// operates on the same source operands and sets flags in the same way as
5161 /// Compare; remove Compare if possible.
5162 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5163                                         unsigned SrcReg2, int CmpMask,
5164                                         int CmpValue,
5165                                         const MachineRegisterInfo *MRI) const {
5166   // Check whether we can replace SUB with CMP.
5167   unsigned NewOpcode = 0;
5168   switch (CmpInstr.getOpcode()) {
5169   default: break;
5170   case X86::SUB64ri32:
5171   case X86::SUB64ri8:
5172   case X86::SUB32ri:
5173   case X86::SUB32ri8:
5174   case X86::SUB16ri:
5175   case X86::SUB16ri8:
5176   case X86::SUB8ri:
5177   case X86::SUB64rm:
5178   case X86::SUB32rm:
5179   case X86::SUB16rm:
5180   case X86::SUB8rm:
5181   case X86::SUB64rr:
5182   case X86::SUB32rr:
5183   case X86::SUB16rr:
5184   case X86::SUB8rr: {
5185     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
5186       return false;
5187     // There is no use of the destination register, we can replace SUB with CMP.
5188     switch (CmpInstr.getOpcode()) {
5189     default: llvm_unreachable("Unreachable!");
5190     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
5191     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
5192     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
5193     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
5194     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
5195     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
5196     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
5197     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
5198     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5199     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
5200     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
5201     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
5202     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
5203     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
5204     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
5205     }
5206     CmpInstr.setDesc(get(NewOpcode));
5207     CmpInstr.RemoveOperand(0);
5208     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5209     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5210         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5211       return false;
5212   }
5213   }
5214 
5215   // Get the unique definition of SrcReg.
5216   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5217   if (!MI) return false;
5218 
5219   // CmpInstr is the first instruction of the BB.
5220   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5221 
5222   // If we are comparing against zero, check whether we can use MI to update
5223   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5224   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
5225   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
5226     return false;
5227 
5228   // If we have a use of the source register between the def and our compare
5229   // instruction we can eliminate the compare iff the use sets EFLAGS in the
5230   // right way.
5231   bool ShouldUpdateCC = false;
5232   X86::CondCode NewCC = X86::COND_INVALID;
5233   if (IsCmpZero && !isDefConvertible(*MI)) {
5234     // Scan forward from the use until we hit the use we're looking for or the
5235     // compare instruction.
5236     for (MachineBasicBlock::iterator J = MI;; ++J) {
5237       // Do we have a convertible instruction?
5238       NewCC = isUseDefConvertible(*J);
5239       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5240           J->getOperand(1).getReg() == SrcReg) {
5241         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5242         ShouldUpdateCC = true; // Update CC later on.
5243         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5244         // with the new def.
5245         Def = J;
5246         MI = &*Def;
5247         break;
5248       }
5249 
5250       if (J == I)
5251         return false;
5252     }
5253   }
5254 
5255   // We are searching for an earlier instruction that can make CmpInstr
5256   // redundant and that instruction will be saved in Sub.
5257   MachineInstr *Sub = nullptr;
5258   const TargetRegisterInfo *TRI = &getRegisterInfo();
5259 
5260   // We iterate backward, starting from the instruction before CmpInstr and
5261   // stop when reaching the definition of a source register or done with the BB.
5262   // RI points to the instruction before CmpInstr.
5263   // If the definition is in this basic block, RE points to the definition;
5264   // otherwise, RE is the rend of the basic block.
5265   MachineBasicBlock::reverse_iterator
5266       RI = MachineBasicBlock::reverse_iterator(I),
5267       RE = CmpInstr.getParent() == MI->getParent()
5268                ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5269                : CmpInstr.getParent()->rend();
5270   MachineInstr *Movr0Inst = nullptr;
5271   for (; RI != RE; ++RI) {
5272     MachineInstr &Instr = *RI;
5273     // Check whether CmpInstr can be made redundant by the current instruction.
5274     if (!IsCmpZero &&
5275         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5276       Sub = &Instr;
5277       break;
5278     }
5279 
5280     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5281         Instr.readsRegister(X86::EFLAGS, TRI)) {
5282       // This instruction modifies or uses EFLAGS.
5283 
5284       // MOV32r0 etc. are implemented with xor which clobbers condition code.
5285       // They are safe to move up, if the definition to EFLAGS is dead and
5286       // earlier instructions do not read or write EFLAGS.
5287       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5288           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5289         Movr0Inst = &Instr;
5290         continue;
5291       }
5292 
5293       // We can't remove CmpInstr.
5294       return false;
5295     }
5296   }
5297 
5298   // Return false if no candidates exist.
5299   if (!IsCmpZero && !Sub)
5300     return false;
5301 
5302   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5303                     Sub->getOperand(2).getReg() == SrcReg);
5304 
5305   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5306   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5307   // If we are done with the basic block, we need to check whether EFLAGS is
5308   // live-out.
5309   bool IsSafe = false;
5310   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5311   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
5312   for (++I; I != E; ++I) {
5313     const MachineInstr &Instr = *I;
5314     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5315     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5316     // We should check the usage if this instruction uses and updates EFLAGS.
5317     if (!UseEFLAGS && ModifyEFLAGS) {
5318       // It is safe to remove CmpInstr if EFLAGS is updated again.
5319       IsSafe = true;
5320       break;
5321     }
5322     if (!UseEFLAGS && !ModifyEFLAGS)
5323       continue;
5324 
5325     // EFLAGS is used by this instruction.
5326     X86::CondCode OldCC = X86::COND_INVALID;
5327     bool OpcIsSET = false;
5328     if (IsCmpZero || IsSwapped) {
5329       // We decode the condition code from opcode.
5330       if (Instr.isBranch())
5331         OldCC = getCondFromBranchOpc(Instr.getOpcode());
5332       else {
5333         OldCC = getCondFromSETOpc(Instr.getOpcode());
5334         if (OldCC != X86::COND_INVALID)
5335           OpcIsSET = true;
5336         else
5337           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
5338       }
5339       if (OldCC == X86::COND_INVALID) return false;
5340     }
5341     if (IsCmpZero) {
5342       switch (OldCC) {
5343       default: break;
5344       case X86::COND_A: case X86::COND_AE:
5345       case X86::COND_B: case X86::COND_BE:
5346       case X86::COND_G: case X86::COND_GE:
5347       case X86::COND_L: case X86::COND_LE:
5348       case X86::COND_O: case X86::COND_NO:
5349         // CF and OF are used, we can't perform this optimization.
5350         return false;
5351       }
5352 
5353       // If we're updating the condition code check if we have to reverse the
5354       // condition.
5355       if (ShouldUpdateCC)
5356         switch (OldCC) {
5357         default:
5358           return false;
5359         case X86::COND_E:
5360           break;
5361         case X86::COND_NE:
5362           NewCC = GetOppositeBranchCondition(NewCC);
5363           break;
5364         }
5365     } else if (IsSwapped) {
5366       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5367       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5368       // We swap the condition code and synthesize the new opcode.
5369       NewCC = getSwappedCondition(OldCC);
5370       if (NewCC == X86::COND_INVALID) return false;
5371     }
5372 
5373     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
5374       // Synthesize the new opcode.
5375       bool HasMemoryOperand = Instr.hasOneMemOperand();
5376       unsigned NewOpc;
5377       if (Instr.isBranch())
5378         NewOpc = GetCondBranchFromCond(NewCC);
5379       else if(OpcIsSET)
5380         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5381       else {
5382         unsigned DstReg = Instr.getOperand(0).getReg();
5383         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5384                                  HasMemoryOperand);
5385       }
5386 
5387       // Push the MachineInstr to OpsToUpdate.
5388       // If it is safe to remove CmpInstr, the condition code of these
5389       // instructions will be modified.
5390       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5391     }
5392     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5393       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5394       IsSafe = true;
5395       break;
5396     }
5397   }
5398 
5399   // If EFLAGS is not killed nor re-defined, we should check whether it is
5400   // live-out. If it is live-out, do not optimize.
5401   if ((IsCmpZero || IsSwapped) && !IsSafe) {
5402     MachineBasicBlock *MBB = CmpInstr.getParent();
5403     for (MachineBasicBlock *Successor : MBB->successors())
5404       if (Successor->isLiveIn(X86::EFLAGS))
5405         return false;
5406   }
5407 
5408   // The instruction to be updated is either Sub or MI.
5409   Sub = IsCmpZero ? MI : Sub;
5410   // Move Movr0Inst to the appropriate place before Sub.
5411   if (Movr0Inst) {
5412     // Look backwards until we find a def that doesn't use the current EFLAGS.
5413     Def = Sub;
5414     MachineBasicBlock::reverse_iterator
5415       InsertI = MachineBasicBlock::reverse_iterator(++Def),
5416                 InsertE = Sub->getParent()->rend();
5417     for (; InsertI != InsertE; ++InsertI) {
5418       MachineInstr *Instr = &*InsertI;
5419       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5420           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5421         Sub->getParent()->remove(Movr0Inst);
5422         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5423                                    Movr0Inst);
5424         break;
5425       }
5426     }
5427     if (InsertI == InsertE)
5428       return false;
5429   }
5430 
5431   // Make sure Sub instruction defines EFLAGS and mark the def live.
5432   unsigned i = 0, e = Sub->getNumOperands();
5433   for (; i != e; ++i) {
5434     MachineOperand &MO = Sub->getOperand(i);
5435     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5436       MO.setIsDead(false);
5437       break;
5438     }
5439   }
5440   assert(i != e && "Unable to locate a def EFLAGS operand");
5441 
5442   CmpInstr.eraseFromParent();
5443 
5444   // Modify the condition code of instructions in OpsToUpdate.
5445   for (auto &Op : OpsToUpdate)
5446     Op.first->setDesc(get(Op.second));
5447   return true;
5448 }
5449 
5450 /// Try to remove the load by folding it to a register
5451 /// operand at the use. We fold the load instructions if load defines a virtual
5452 /// register, the virtual register is used once in the same BB, and the
5453 /// instructions in-between do not load or store, and have no side effects.
5454 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
5455                                               const MachineRegisterInfo *MRI,
5456                                               unsigned &FoldAsLoadDefReg,
5457                                               MachineInstr *&DefMI) const {
5458   if (FoldAsLoadDefReg == 0)
5459     return nullptr;
5460   // To be conservative, if there exists another load, clear the load candidate.
5461   if (MI.mayLoad()) {
5462     FoldAsLoadDefReg = 0;
5463     return nullptr;
5464   }
5465 
5466   // Check whether we can move DefMI here.
5467   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5468   assert(DefMI);
5469   bool SawStore = false;
5470   if (!DefMI->isSafeToMove(nullptr, SawStore))
5471     return nullptr;
5472 
5473   // Collect information about virtual register operands of MI.
5474   unsigned SrcOperandId = 0;
5475   bool FoundSrcOperand = false;
5476   for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5477     MachineOperand &MO = MI.getOperand(i);
5478     if (!MO.isReg())
5479       continue;
5480     unsigned Reg = MO.getReg();
5481     if (Reg != FoldAsLoadDefReg)
5482       continue;
5483     // Do not fold if we have a subreg use or a def or multiple uses.
5484     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5485       return nullptr;
5486 
5487     SrcOperandId = i;
5488     FoundSrcOperand = true;
5489   }
5490   if (!FoundSrcOperand)
5491     return nullptr;
5492 
5493   // Check whether we can fold the def into SrcOperandId.
5494   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
5495     FoldAsLoadDefReg = 0;
5496     return FoldMI;
5497   }
5498 
5499   return nullptr;
5500 }
5501 
5502 /// Expand a single-def pseudo instruction to a two-addr
5503 /// instruction with two undef reads of the register being defined.
5504 /// This is used for mapping:
5505 ///   %xmm4 = V_SET0
5506 /// to:
5507 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5508 ///
5509 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5510                              const MCInstrDesc &Desc) {
5511   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5512   unsigned Reg = MIB->getOperand(0).getReg();
5513   MIB->setDesc(Desc);
5514 
5515   // MachineInstr::addOperand() will insert explicit operands before any
5516   // implicit operands.
5517   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5518   // But we don't trust that.
5519   assert(MIB->getOperand(1).getReg() == Reg &&
5520          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5521   return true;
5522 }
5523 
5524 /// Expand a single-def pseudo instruction to a two-addr
5525 /// instruction with two %k0 reads.
5526 /// This is used for mapping:
5527 ///   %k4 = K_SET1
5528 /// to:
5529 ///   %k4 = KXNORrr %k0, %k0
5530 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5531                             const MCInstrDesc &Desc, unsigned Reg) {
5532   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5533   MIB->setDesc(Desc);
5534   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5535   return true;
5536 }
5537 
5538 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5539                           bool MinusOne) {
5540   MachineBasicBlock &MBB = *MIB->getParent();
5541   DebugLoc DL = MIB->getDebugLoc();
5542   unsigned Reg = MIB->getOperand(0).getReg();
5543 
5544   // Insert the XOR.
5545   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5546       .addReg(Reg, RegState::Undef)
5547       .addReg(Reg, RegState::Undef);
5548 
5549   // Turn the pseudo into an INC or DEC.
5550   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5551   MIB.addReg(Reg);
5552 
5553   return true;
5554 }
5555 
5556 bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5557   MachineBasicBlock &MBB = *MIB->getParent();
5558   DebugLoc DL = MIB->getDebugLoc();
5559   int64_t Imm = MIB->getOperand(1).getImm();
5560   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5561   MachineBasicBlock::iterator I = MIB.getInstr();
5562 
5563   int StackAdjustment;
5564 
5565   if (Subtarget.is64Bit()) {
5566     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5567            MIB->getOpcode() == X86::MOV32ImmSExti8);
5568 
5569     // Can't use push/pop lowering if the function might write to the red zone.
5570     X86MachineFunctionInfo *X86FI =
5571         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5572     if (X86FI->getUsesRedZone()) {
5573       MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5574                                                                : X86::MOV64ri));
5575       return true;
5576     }
5577 
5578     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5579     // widen the register if necessary.
5580     StackAdjustment = 8;
5581     BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5582     MIB->setDesc(get(X86::POP64r));
5583     MIB->getOperand(0)
5584         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5585   } else {
5586     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5587     StackAdjustment = 4;
5588     BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5589     MIB->setDesc(get(X86::POP32r));
5590   }
5591 
5592   // Build CFI if necessary.
5593   MachineFunction &MF = *MBB.getParent();
5594   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5595   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5596   bool NeedsDwarfCFI =
5597       !IsWin64Prologue &&
5598       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5599   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5600   if (EmitCFI) {
5601     TFL->BuildCFI(MBB, I, DL,
5602         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5603     TFL->BuildCFI(MBB, std::next(I), DL,
5604         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5605   }
5606 
5607   return true;
5608 }
5609 
5610 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5611 // code sequence is needed for other targets.
5612 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5613                                  const TargetInstrInfo &TII) {
5614   MachineBasicBlock &MBB = *MIB->getParent();
5615   DebugLoc DL = MIB->getDebugLoc();
5616   unsigned Reg = MIB->getOperand(0).getReg();
5617   const GlobalValue *GV =
5618       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5619   auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
5620   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5621       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
5622   MachineBasicBlock::iterator I = MIB.getInstr();
5623 
5624   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5625       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5626       .addMemOperand(MMO);
5627   MIB->setDebugLoc(DL);
5628   MIB->setDesc(TII.get(X86::MOV64rm));
5629   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5630 }
5631 
5632 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
5633   bool HasAVX = Subtarget.hasAVX();
5634   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5635   switch (MI.getOpcode()) {
5636   case X86::MOV32r0:
5637     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
5638   case X86::MOV32r1:
5639     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5640   case X86::MOV32r_1:
5641     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
5642   case X86::MOV32ImmSExti8:
5643   case X86::MOV64ImmSExti8:
5644     return ExpandMOVImmSExti8(MIB);
5645   case X86::SETB_C8r:
5646     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
5647   case X86::SETB_C16r:
5648     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
5649   case X86::SETB_C32r:
5650     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
5651   case X86::SETB_C64r:
5652     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
5653   case X86::V_SET0:
5654   case X86::FsFLD0SS:
5655   case X86::FsFLD0SD:
5656     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
5657   case X86::AVX_SET0:
5658     assert(HasAVX && "AVX not supported");
5659     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
5660   case X86::AVX512_128_SET0:
5661     return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5662   case X86::AVX512_256_SET0:
5663     return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
5664   case X86::AVX512_512_SET0:
5665     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5666   case X86::V_SETALLONES:
5667     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5668   case X86::AVX2_SETALLONES:
5669     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5670   case X86::AVX512_512_SETALLONES: {
5671     unsigned Reg = MIB->getOperand(0).getReg();
5672     MIB->setDesc(get(X86::VPTERNLOGDZrri));
5673     // VPTERNLOGD needs 3 register inputs and an immediate.
5674     // 0xff will return 1s for any input.
5675     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5676        .addReg(Reg, RegState::Undef).addImm(0xff);
5677     return true;
5678   }
5679   case X86::TEST8ri_NOREX:
5680     MI.setDesc(get(X86::TEST8ri));
5681     return true;
5682   case X86::MOV32ri64:
5683     MI.setDesc(get(X86::MOV32ri));
5684     return true;
5685 
5686   // KNL does not recognize dependency-breaking idioms for mask registers,
5687   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5688   // Using %k0 as the undef input register is a performance heuristic based
5689   // on the assumption that %k0 is used less frequently than the other mask
5690   // registers, since it is not usable as a write mask.
5691   // FIXME: A more advanced approach would be to choose the best input mask
5692   // register based on context.
5693   case X86::KSET0B:
5694   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5695   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5696   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
5697   case X86::KSET1B:
5698   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5699   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5700   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
5701   case TargetOpcode::LOAD_STACK_GUARD:
5702     expandLoadStackGuard(MIB, *this);
5703     return true;
5704   }
5705   return false;
5706 }
5707 
5708 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5709                         int PtrOffset = 0) {
5710   unsigned NumAddrOps = MOs.size();
5711 
5712   if (NumAddrOps < 4) {
5713     // FrameIndex only - add an immediate offset (whether its zero or not).
5714     for (unsigned i = 0; i != NumAddrOps; ++i)
5715       MIB.addOperand(MOs[i]);
5716     addOffset(MIB, PtrOffset);
5717   } else {
5718     // General Memory Addressing - we need to add any offset to an existing
5719     // offset.
5720     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5721     for (unsigned i = 0; i != NumAddrOps; ++i) {
5722       const MachineOperand &MO = MOs[i];
5723       if (i == 3 && PtrOffset != 0) {
5724         MIB.addDisp(MO, PtrOffset);
5725       } else {
5726         MIB.addOperand(MO);
5727       }
5728     }
5729   }
5730 }
5731 
5732 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5733                                      ArrayRef<MachineOperand> MOs,
5734                                      MachineBasicBlock::iterator InsertPt,
5735                                      MachineInstr &MI,
5736                                      const TargetInstrInfo &TII) {
5737   // Create the base instruction with the memory operand as the first part.
5738   // Omit the implicit operands, something BuildMI can't do.
5739   MachineInstr *NewMI =
5740       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5741   MachineInstrBuilder MIB(MF, NewMI);
5742   addOperands(MIB, MOs);
5743 
5744   // Loop over the rest of the ri operands, converting them over.
5745   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5746   for (unsigned i = 0; i != NumOps; ++i) {
5747     MachineOperand &MO = MI.getOperand(i + 2);
5748     MIB.addOperand(MO);
5749   }
5750   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5751     MachineOperand &MO = MI.getOperand(i);
5752     MIB.addOperand(MO);
5753   }
5754 
5755   MachineBasicBlock *MBB = InsertPt->getParent();
5756   MBB->insert(InsertPt, NewMI);
5757 
5758   return MIB;
5759 }
5760 
5761 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5762                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5763                               MachineBasicBlock::iterator InsertPt,
5764                               MachineInstr &MI, const TargetInstrInfo &TII,
5765                               int PtrOffset = 0) {
5766   // Omit the implicit operands, something BuildMI can't do.
5767   MachineInstr *NewMI =
5768       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5769   MachineInstrBuilder MIB(MF, NewMI);
5770 
5771   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5772     MachineOperand &MO = MI.getOperand(i);
5773     if (i == OpNo) {
5774       assert(MO.isReg() && "Expected to fold into reg operand!");
5775       addOperands(MIB, MOs, PtrOffset);
5776     } else {
5777       MIB.addOperand(MO);
5778     }
5779   }
5780 
5781   MachineBasicBlock *MBB = InsertPt->getParent();
5782   MBB->insert(InsertPt, NewMI);
5783 
5784   return MIB;
5785 }
5786 
5787 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5788                                 ArrayRef<MachineOperand> MOs,
5789                                 MachineBasicBlock::iterator InsertPt,
5790                                 MachineInstr &MI) {
5791   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5792                                     MI.getDebugLoc(), TII.get(Opcode));
5793   addOperands(MIB, MOs);
5794   return MIB.addImm(0);
5795 }
5796 
5797 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5798     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5799     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5800     unsigned Size, unsigned Align) const {
5801   switch (MI.getOpcode()) {
5802   case X86::INSERTPSrr:
5803   case X86::VINSERTPSrr:
5804     // Attempt to convert the load of inserted vector into a fold load
5805     // of a single float.
5806     if (OpNum == 2) {
5807       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5808       unsigned ZMask = Imm & 15;
5809       unsigned DstIdx = (Imm >> 4) & 3;
5810       unsigned SrcIdx = (Imm >> 6) & 3;
5811 
5812       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5813       if (Size <= RCSize && 4 <= Align) {
5814         int PtrOffset = SrcIdx * 4;
5815         unsigned NewImm = (DstIdx << 4) | ZMask;
5816         unsigned NewOpCode =
5817             (MI.getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5818                                                 : X86::INSERTPSrm);
5819         MachineInstr *NewMI =
5820             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5821         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5822         return NewMI;
5823       }
5824     }
5825     break;
5826   case X86::MOVHLPSrr:
5827   case X86::VMOVHLPSrr:
5828     // Move the upper 64-bits of the second operand to the lower 64-bits.
5829     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5830     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5831     if (OpNum == 2) {
5832       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5833       if (Size <= RCSize && 8 <= Align) {
5834         unsigned NewOpCode =
5835             (MI.getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5836                                                : X86::MOVLPSrm);
5837         MachineInstr *NewMI =
5838             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5839         return NewMI;
5840       }
5841     }
5842     break;
5843   };
5844 
5845   return nullptr;
5846 }
5847 
5848 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5849     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5850     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5851     unsigned Size, unsigned Align, bool AllowCommute) const {
5852   const DenseMap<unsigned,
5853                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
5854   bool isCallRegIndirect = Subtarget.callRegIndirect();
5855   bool isTwoAddrFold = false;
5856 
5857   // For CPUs that favor the register form of a call or push,
5858   // do not fold loads into calls or pushes, unless optimizing for size
5859   // aggressively.
5860   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
5861       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5862        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5863        MI.getOpcode() == X86::PUSH64r))
5864     return nullptr;
5865 
5866   unsigned NumOps = MI.getDesc().getNumOperands();
5867   bool isTwoAddr =
5868       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5869 
5870   // FIXME: AsmPrinter doesn't know how to handle
5871   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5872   if (MI.getOpcode() == X86::ADD32ri &&
5873       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5874     return nullptr;
5875 
5876   MachineInstr *NewMI = nullptr;
5877 
5878   // Attempt to fold any custom cases we have.
5879   if (MachineInstr *CustomMI =
5880           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
5881     return CustomMI;
5882 
5883   // Folding a memory location into the two-address part of a two-address
5884   // instruction is different than folding it other places.  It requires
5885   // replacing the *two* registers with the memory location.
5886   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5887       MI.getOperand(1).isReg() &&
5888       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5889     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5890     isTwoAddrFold = true;
5891   } else if (OpNum == 0) {
5892     if (MI.getOpcode() == X86::MOV32r0) {
5893       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5894       if (NewMI)
5895         return NewMI;
5896     }
5897 
5898     OpcodeTablePtr = &RegOp2MemOpTable0;
5899   } else if (OpNum == 1) {
5900     OpcodeTablePtr = &RegOp2MemOpTable1;
5901   } else if (OpNum == 2) {
5902     OpcodeTablePtr = &RegOp2MemOpTable2;
5903   } else if (OpNum == 3) {
5904     OpcodeTablePtr = &RegOp2MemOpTable3;
5905   } else if (OpNum == 4) {
5906     OpcodeTablePtr = &RegOp2MemOpTable4;
5907   }
5908 
5909   // If table selected...
5910   if (OpcodeTablePtr) {
5911     // Find the Opcode to fuse
5912     auto I = OpcodeTablePtr->find(MI.getOpcode());
5913     if (I != OpcodeTablePtr->end()) {
5914       unsigned Opcode = I->second.first;
5915       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
5916       if (Align < MinAlign)
5917         return nullptr;
5918       bool NarrowToMOV32rm = false;
5919       if (Size) {
5920         unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5921         if (Size < RCSize) {
5922           // Check if it's safe to fold the load. If the size of the object is
5923           // narrower than the load width, then it's not.
5924           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5925             return nullptr;
5926           // If this is a 64-bit load, but the spill slot is 32, then we can do
5927           // a 32-bit load which is implicitly zero-extended. This likely is
5928           // due to live interval analysis remat'ing a load from stack slot.
5929           if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5930             return nullptr;
5931           Opcode = X86::MOV32rm;
5932           NarrowToMOV32rm = true;
5933         }
5934       }
5935 
5936       if (isTwoAddrFold)
5937         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5938       else
5939         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5940 
5941       if (NarrowToMOV32rm) {
5942         // If this is the special case where we use a MOV32rm to load a 32-bit
5943         // value and zero-extend the top bits. Change the destination register
5944         // to a 32-bit one.
5945         unsigned DstReg = NewMI->getOperand(0).getReg();
5946         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
5947           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5948         else
5949           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5950       }
5951       return NewMI;
5952     }
5953   }
5954 
5955   // If the instruction and target operand are commutable, commute the
5956   // instruction and try again.
5957   if (AllowCommute) {
5958     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5959     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5960       bool HasDef = MI.getDesc().getNumDefs();
5961       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
5962       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5963       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5964       bool Tied1 =
5965           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5966       bool Tied2 =
5967           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5968 
5969       // If either of the commutable operands are tied to the destination
5970       // then we can not commute + fold.
5971       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5972           (HasDef && Reg0 == Reg2 && Tied2))
5973         return nullptr;
5974 
5975       MachineInstr *CommutedMI =
5976           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5977       if (!CommutedMI) {
5978         // Unable to commute.
5979         return nullptr;
5980       }
5981       if (CommutedMI != &MI) {
5982         // New instruction. We can't fold from this.
5983         CommutedMI->eraseFromParent();
5984         return nullptr;
5985       }
5986 
5987       // Attempt to fold with the commuted version of the instruction.
5988       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5989                                     Size, Align, /*AllowCommute=*/false);
5990       if (NewMI)
5991         return NewMI;
5992 
5993       // Folding failed again - undo the commute before returning.
5994       MachineInstr *UncommutedMI =
5995           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5996       if (!UncommutedMI) {
5997         // Unable to commute.
5998         return nullptr;
5999       }
6000       if (UncommutedMI != &MI) {
6001         // New instruction. It doesn't need to be kept.
6002         UncommutedMI->eraseFromParent();
6003         return nullptr;
6004       }
6005 
6006       // Return here to prevent duplicate fuse failure report.
6007       return nullptr;
6008     }
6009   }
6010 
6011   // No fusion
6012   if (PrintFailedFusing && !MI.isCopy())
6013     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
6014   return nullptr;
6015 }
6016 
6017 /// Return true for all instructions that only update
6018 /// the first 32 or 64-bits of the destination register and leave the rest
6019 /// unmodified. This can be used to avoid folding loads if the instructions
6020 /// only update part of the destination register, and the non-updated part is
6021 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6022 /// instructions breaks the partial register dependency and it can improve
6023 /// performance. e.g.:
6024 ///
6025 ///   movss (%rdi), %xmm0
6026 ///   cvtss2sd %xmm0, %xmm0
6027 ///
6028 /// Instead of
6029 ///   cvtss2sd (%rdi), %xmm0
6030 ///
6031 /// FIXME: This should be turned into a TSFlags.
6032 ///
6033 static bool hasPartialRegUpdate(unsigned Opcode) {
6034   switch (Opcode) {
6035   case X86::CVTSI2SSrr:
6036   case X86::CVTSI2SSrm:
6037   case X86::CVTSI2SS64rr:
6038   case X86::CVTSI2SS64rm:
6039   case X86::CVTSI2SDrr:
6040   case X86::CVTSI2SDrm:
6041   case X86::CVTSI2SD64rr:
6042   case X86::CVTSI2SD64rm:
6043   case X86::CVTSD2SSrr:
6044   case X86::CVTSD2SSrm:
6045   case X86::Int_CVTSD2SSrr:
6046   case X86::Int_CVTSD2SSrm:
6047   case X86::CVTSS2SDrr:
6048   case X86::CVTSS2SDrm:
6049   case X86::Int_CVTSS2SDrr:
6050   case X86::Int_CVTSS2SDrm:
6051   case X86::MOVHPDrm:
6052   case X86::MOVHPSrm:
6053   case X86::MOVLPDrm:
6054   case X86::MOVLPSrm:
6055   case X86::RCPSSr:
6056   case X86::RCPSSm:
6057   case X86::RCPSSr_Int:
6058   case X86::RCPSSm_Int:
6059   case X86::ROUNDSDr:
6060   case X86::ROUNDSDm:
6061   case X86::ROUNDSDr_Int:
6062   case X86::ROUNDSSr:
6063   case X86::ROUNDSSm:
6064   case X86::ROUNDSSr_Int:
6065   case X86::RSQRTSSr:
6066   case X86::RSQRTSSm:
6067   case X86::RSQRTSSr_Int:
6068   case X86::RSQRTSSm_Int:
6069   case X86::SQRTSSr:
6070   case X86::SQRTSSm:
6071   case X86::SQRTSSr_Int:
6072   case X86::SQRTSSm_Int:
6073   case X86::SQRTSDr:
6074   case X86::SQRTSDm:
6075   case X86::SQRTSDr_Int:
6076   case X86::SQRTSDm_Int:
6077     return true;
6078   }
6079 
6080   return false;
6081 }
6082 
6083 /// Inform the ExeDepsFix pass how many idle
6084 /// instructions we would like before a partial register update.
6085 unsigned X86InstrInfo::getPartialRegUpdateClearance(
6086     const MachineInstr &MI, unsigned OpNum,
6087     const TargetRegisterInfo *TRI) const {
6088   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
6089     return 0;
6090 
6091   // If MI is marked as reading Reg, the partial register update is wanted.
6092   const MachineOperand &MO = MI.getOperand(0);
6093   unsigned Reg = MO.getReg();
6094   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6095     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
6096       return 0;
6097   } else {
6098     if (MI.readsRegister(Reg, TRI))
6099       return 0;
6100   }
6101 
6102   // If any instructions in the clearance range are reading Reg, insert a
6103   // dependency breaking instruction, which is inexpensive and is likely to
6104   // be hidden in other instruction's cycles.
6105   return PartialRegUpdateClearance;
6106 }
6107 
6108 // Return true for any instruction the copies the high bits of the first source
6109 // operand into the unused high bits of the destination operand.
6110 static bool hasUndefRegUpdate(unsigned Opcode) {
6111   switch (Opcode) {
6112   case X86::VCVTSI2SSrr:
6113   case X86::VCVTSI2SSrm:
6114   case X86::Int_VCVTSI2SSrr:
6115   case X86::Int_VCVTSI2SSrm:
6116   case X86::VCVTSI2SS64rr:
6117   case X86::VCVTSI2SS64rm:
6118   case X86::Int_VCVTSI2SS64rr:
6119   case X86::Int_VCVTSI2SS64rm:
6120   case X86::VCVTSI2SDrr:
6121   case X86::VCVTSI2SDrm:
6122   case X86::Int_VCVTSI2SDrr:
6123   case X86::Int_VCVTSI2SDrm:
6124   case X86::VCVTSI2SD64rr:
6125   case X86::VCVTSI2SD64rm:
6126   case X86::Int_VCVTSI2SD64rr:
6127   case X86::Int_VCVTSI2SD64rm:
6128   case X86::VCVTSD2SSrr:
6129   case X86::VCVTSD2SSrm:
6130   case X86::Int_VCVTSD2SSrr:
6131   case X86::Int_VCVTSD2SSrm:
6132   case X86::VCVTSS2SDrr:
6133   case X86::VCVTSS2SDrm:
6134   case X86::Int_VCVTSS2SDrr:
6135   case X86::Int_VCVTSS2SDrm:
6136   case X86::VRCPSSr:
6137   case X86::VRCPSSm:
6138   case X86::VRCPSSm_Int:
6139   case X86::VROUNDSDr:
6140   case X86::VROUNDSDm:
6141   case X86::VROUNDSDr_Int:
6142   case X86::VROUNDSSr:
6143   case X86::VROUNDSSm:
6144   case X86::VROUNDSSr_Int:
6145   case X86::VRSQRTSSr:
6146   case X86::VRSQRTSSm:
6147   case X86::VRSQRTSSm_Int:
6148   case X86::VSQRTSSr:
6149   case X86::VSQRTSSm:
6150   case X86::VSQRTSSm_Int:
6151   case X86::VSQRTSDr:
6152   case X86::VSQRTSDm:
6153   case X86::VSQRTSDm_Int:
6154     // AVX-512
6155   case X86::VCVTSD2SSZrr:
6156   case X86::VCVTSD2SSZrm:
6157   case X86::VCVTSS2SDZrr:
6158   case X86::VCVTSS2SDZrm:
6159     return true;
6160   }
6161 
6162   return false;
6163 }
6164 
6165 /// Inform the ExeDepsFix pass how many idle instructions we would like before
6166 /// certain undef register reads.
6167 ///
6168 /// This catches the VCVTSI2SD family of instructions:
6169 ///
6170 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6171 ///
6172 /// We should to be careful *not* to catch VXOR idioms which are presumably
6173 /// handled specially in the pipeline:
6174 ///
6175 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6176 ///
6177 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6178 /// high bits that are passed-through are not live.
6179 unsigned
6180 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6181                                    const TargetRegisterInfo *TRI) const {
6182   if (!hasUndefRegUpdate(MI.getOpcode()))
6183     return 0;
6184 
6185   // Set the OpNum parameter to the first source operand.
6186   OpNum = 1;
6187 
6188   const MachineOperand &MO = MI.getOperand(OpNum);
6189   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
6190     return UndefRegClearance;
6191   }
6192   return 0;
6193 }
6194 
6195 void X86InstrInfo::breakPartialRegDependency(
6196     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6197   unsigned Reg = MI.getOperand(OpNum).getReg();
6198   // If MI kills this register, the false dependence is already broken.
6199   if (MI.killsRegister(Reg, TRI))
6200     return;
6201 
6202   if (X86::VR128RegClass.contains(Reg)) {
6203     // These instructions are all floating point domain, so xorps is the best
6204     // choice.
6205     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
6206     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6207         .addReg(Reg, RegState::Undef)
6208         .addReg(Reg, RegState::Undef);
6209     MI.addRegisterKilled(Reg, TRI, true);
6210   } else if (X86::VR256RegClass.contains(Reg)) {
6211     // Use vxorps to clear the full ymm register.
6212     // It wants to read and write the xmm sub-register.
6213     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
6214     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6215         .addReg(XReg, RegState::Undef)
6216         .addReg(XReg, RegState::Undef)
6217         .addReg(Reg, RegState::ImplicitDefine);
6218     MI.addRegisterKilled(Reg, TRI, true);
6219   }
6220 }
6221 
6222 MachineInstr *
6223 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6224                                     ArrayRef<unsigned> Ops,
6225                                     MachineBasicBlock::iterator InsertPt,
6226                                     int FrameIndex, LiveIntervals *LIS) const {
6227   // Check switch flag
6228   if (NoFusing)
6229     return nullptr;
6230 
6231   // Unless optimizing for size, don't fold to avoid partial
6232   // register update stalls
6233   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
6234     return nullptr;
6235 
6236   const MachineFrameInfo *MFI = MF.getFrameInfo();
6237   unsigned Size = MFI->getObjectSize(FrameIndex);
6238   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
6239   // If the function stack isn't realigned we don't want to fold instructions
6240   // that need increased alignment.
6241   if (!RI.needsStackRealignment(MF))
6242     Alignment =
6243         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
6244   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6245     unsigned NewOpc = 0;
6246     unsigned RCSize = 0;
6247     switch (MI.getOpcode()) {
6248     default: return nullptr;
6249     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
6250     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6251     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6252     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6253     }
6254     // Check if it's safe to fold the load. If the size of the object is
6255     // narrower than the load width, then it's not.
6256     if (Size < RCSize)
6257       return nullptr;
6258     // Change to CMPXXri r, 0 first.
6259     MI.setDesc(get(NewOpc));
6260     MI.getOperand(1).ChangeToImmediate(0);
6261   } else if (Ops.size() != 1)
6262     return nullptr;
6263 
6264   return foldMemoryOperandImpl(MF, MI, Ops[0],
6265                                MachineOperand::CreateFI(FrameIndex), InsertPt,
6266                                Size, Alignment, /*AllowCommute=*/true);
6267 }
6268 
6269 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6270 /// because the latter uses contents that wouldn't be defined in the folded
6271 /// version.  For instance, this transformation isn't legal:
6272 ///   movss (%rdi), %xmm0
6273 ///   addps %xmm0, %xmm0
6274 /// ->
6275 ///   addps (%rdi), %xmm0
6276 ///
6277 /// But this one is:
6278 ///   movss (%rdi), %xmm0
6279 ///   addss %xmm0, %xmm0
6280 /// ->
6281 ///   addss (%rdi), %xmm0
6282 ///
6283 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6284                                              const MachineInstr &UserMI,
6285                                              const MachineFunction &MF) {
6286   unsigned Opc = LoadMI.getOpcode();
6287   unsigned UserOpc = UserMI.getOpcode();
6288   unsigned RegSize =
6289       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6290 
6291   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
6292       RegSize > 4) {
6293     // These instructions only load 32 bits, we can't fold them if the
6294     // destination register is wider than 32 bits (4 bytes), and its user
6295     // instruction isn't scalar (SS).
6296     switch (UserOpc) {
6297     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
6298     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
6299     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6300     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
6301     case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6302     case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6303     case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6304     case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6305     case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6306     case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
6307       return false;
6308     default:
6309       return true;
6310     }
6311   }
6312 
6313   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
6314       RegSize > 8) {
6315     // These instructions only load 64 bits, we can't fold them if the
6316     // destination register is wider than 64 bits (8 bytes), and its user
6317     // instruction isn't scalar (SD).
6318     switch (UserOpc) {
6319     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6320     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6321     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6322     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
6323     case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6324     case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6325     case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6326     case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6327     case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6328     case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
6329       return false;
6330     default:
6331       return true;
6332     }
6333   }
6334 
6335   return false;
6336 }
6337 
6338 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6339     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6340     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6341     LiveIntervals *LIS) const {
6342   // If loading from a FrameIndex, fold directly from the FrameIndex.
6343   unsigned NumOps = LoadMI.getDesc().getNumOperands();
6344   int FrameIndex;
6345   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6346     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6347       return nullptr;
6348     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6349   }
6350 
6351   // Check switch flag
6352   if (NoFusing) return nullptr;
6353 
6354   // Avoid partial register update stalls unless optimizing for size.
6355   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
6356     return nullptr;
6357 
6358   // Determine the alignment of the load.
6359   unsigned Alignment = 0;
6360   if (LoadMI.hasOneMemOperand())
6361     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
6362   else
6363     switch (LoadMI.getOpcode()) {
6364     case X86::AVX512_512_SET0:
6365     case X86::AVX512_512_SETALLONES:
6366       Alignment = 64;
6367       break;
6368     case X86::AVX2_SETALLONES:
6369     case X86::AVX_SET0:
6370     case X86::AVX512_256_SET0:
6371       Alignment = 32;
6372       break;
6373     case X86::V_SET0:
6374     case X86::V_SETALLONES:
6375     case X86::AVX512_128_SET0:
6376       Alignment = 16;
6377       break;
6378     case X86::FsFLD0SD:
6379       Alignment = 8;
6380       break;
6381     case X86::FsFLD0SS:
6382       Alignment = 4;
6383       break;
6384     default:
6385       return nullptr;
6386     }
6387   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6388     unsigned NewOpc = 0;
6389     switch (MI.getOpcode()) {
6390     default: return nullptr;
6391     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6392     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6393     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6394     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6395     }
6396     // Change to CMPXXri r, 0 first.
6397     MI.setDesc(get(NewOpc));
6398     MI.getOperand(1).ChangeToImmediate(0);
6399   } else if (Ops.size() != 1)
6400     return nullptr;
6401 
6402   // Make sure the subregisters match.
6403   // Otherwise we risk changing the size of the load.
6404   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6405     return nullptr;
6406 
6407   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6408   switch (LoadMI.getOpcode()) {
6409   case X86::V_SET0:
6410   case X86::V_SETALLONES:
6411   case X86::AVX2_SETALLONES:
6412   case X86::AVX_SET0:
6413   case X86::AVX512_128_SET0:
6414   case X86::AVX512_256_SET0:
6415   case X86::AVX512_512_SET0:
6416   case X86::AVX512_512_SETALLONES:
6417   case X86::FsFLD0SD:
6418   case X86::FsFLD0SS: {
6419     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6420     // Create a constant-pool entry and operands to load from it.
6421 
6422     // Medium and large mode can't fold loads this way.
6423     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6424         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6425       return nullptr;
6426 
6427     // x86-32 PIC requires a PIC base register for constant pools.
6428     unsigned PICBase = 0;
6429     if (MF.getTarget().isPositionIndependent()) {
6430       if (Subtarget.is64Bit())
6431         PICBase = X86::RIP;
6432       else
6433         // FIXME: PICBase = getGlobalBaseReg(&MF);
6434         // This doesn't work for several reasons.
6435         // 1. GlobalBaseReg may have been spilled.
6436         // 2. It may not be live at MI.
6437         return nullptr;
6438     }
6439 
6440     // Create a constant-pool entry.
6441     MachineConstantPool &MCP = *MF.getConstantPool();
6442     Type *Ty;
6443     unsigned Opc = LoadMI.getOpcode();
6444     if (Opc == X86::FsFLD0SS)
6445       Ty = Type::getFloatTy(MF.getFunction()->getContext());
6446     else if (Opc == X86::FsFLD0SD)
6447       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
6448     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6449       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6450     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6451              Opc == X86::AVX512_256_SET0)
6452       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
6453     else
6454       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
6455 
6456     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6457                       Opc == X86::AVX512_512_SETALLONES);
6458     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6459                                     Constant::getNullValue(Ty);
6460     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6461 
6462     // Create operands to load from the constant pool entry.
6463     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6464     MOs.push_back(MachineOperand::CreateImm(1));
6465     MOs.push_back(MachineOperand::CreateReg(0, false));
6466     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6467     MOs.push_back(MachineOperand::CreateReg(0, false));
6468     break;
6469   }
6470   default: {
6471     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6472       return nullptr;
6473 
6474     // Folding a normal load. Just copy the load's address operands.
6475     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6476                LoadMI.operands_begin() + NumOps);
6477     break;
6478   }
6479   }
6480   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6481                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6482 }
6483 
6484 bool X86InstrInfo::unfoldMemoryOperand(
6485     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6486     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6487   auto I = MemOp2RegOpTable.find(MI.getOpcode());
6488   if (I == MemOp2RegOpTable.end())
6489     return false;
6490   unsigned Opc = I->second.first;
6491   unsigned Index = I->second.second & TB_INDEX_MASK;
6492   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6493   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6494   if (UnfoldLoad && !FoldedLoad)
6495     return false;
6496   UnfoldLoad &= FoldedLoad;
6497   if (UnfoldStore && !FoldedStore)
6498     return false;
6499   UnfoldStore &= FoldedStore;
6500 
6501   const MCInstrDesc &MCID = get(Opc);
6502   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6503   // TODO: Check if 32-byte or greater accesses are slow too?
6504   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6505       Subtarget.isUnalignedMem16Slow())
6506     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6507     // conservatively assume the address is unaligned. That's bad for
6508     // performance.
6509     return false;
6510   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6511   SmallVector<MachineOperand,2> BeforeOps;
6512   SmallVector<MachineOperand,2> AfterOps;
6513   SmallVector<MachineOperand,4> ImpOps;
6514   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6515     MachineOperand &Op = MI.getOperand(i);
6516     if (i >= Index && i < Index + X86::AddrNumOperands)
6517       AddrOps.push_back(Op);
6518     else if (Op.isReg() && Op.isImplicit())
6519       ImpOps.push_back(Op);
6520     else if (i < Index)
6521       BeforeOps.push_back(Op);
6522     else if (i > Index)
6523       AfterOps.push_back(Op);
6524   }
6525 
6526   // Emit the load instruction.
6527   if (UnfoldLoad) {
6528     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6529         MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
6530     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
6531     if (UnfoldStore) {
6532       // Address operands cannot be marked isKill.
6533       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6534         MachineOperand &MO = NewMIs[0]->getOperand(i);
6535         if (MO.isReg())
6536           MO.setIsKill(false);
6537       }
6538     }
6539   }
6540 
6541   // Emit the data processing instruction.
6542   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6543   MachineInstrBuilder MIB(MF, DataMI);
6544 
6545   if (FoldedStore)
6546     MIB.addReg(Reg, RegState::Define);
6547   for (MachineOperand &BeforeOp : BeforeOps)
6548     MIB.addOperand(BeforeOp);
6549   if (FoldedLoad)
6550     MIB.addReg(Reg);
6551   for (MachineOperand &AfterOp : AfterOps)
6552     MIB.addOperand(AfterOp);
6553   for (MachineOperand &ImpOp : ImpOps) {
6554     MIB.addReg(ImpOp.getReg(),
6555                getDefRegState(ImpOp.isDef()) |
6556                RegState::Implicit |
6557                getKillRegState(ImpOp.isKill()) |
6558                getDeadRegState(ImpOp.isDead()) |
6559                getUndefRegState(ImpOp.isUndef()));
6560   }
6561   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6562   switch (DataMI->getOpcode()) {
6563   default: break;
6564   case X86::CMP64ri32:
6565   case X86::CMP64ri8:
6566   case X86::CMP32ri:
6567   case X86::CMP32ri8:
6568   case X86::CMP16ri:
6569   case X86::CMP16ri8:
6570   case X86::CMP8ri: {
6571     MachineOperand &MO0 = DataMI->getOperand(0);
6572     MachineOperand &MO1 = DataMI->getOperand(1);
6573     if (MO1.getImm() == 0) {
6574       unsigned NewOpc;
6575       switch (DataMI->getOpcode()) {
6576       default: llvm_unreachable("Unreachable!");
6577       case X86::CMP64ri8:
6578       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6579       case X86::CMP32ri8:
6580       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6581       case X86::CMP16ri8:
6582       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6583       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6584       }
6585       DataMI->setDesc(get(NewOpc));
6586       MO1.ChangeToRegister(MO0.getReg(), false);
6587     }
6588   }
6589   }
6590   NewMIs.push_back(DataMI);
6591 
6592   // Emit the store instruction.
6593   if (UnfoldStore) {
6594     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6595     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6596         MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
6597     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6598   }
6599 
6600   return true;
6601 }
6602 
6603 bool
6604 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6605                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6606   if (!N->isMachineOpcode())
6607     return false;
6608 
6609   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
6610   if (I == MemOp2RegOpTable.end())
6611     return false;
6612   unsigned Opc = I->second.first;
6613   unsigned Index = I->second.second & TB_INDEX_MASK;
6614   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6615   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6616   const MCInstrDesc &MCID = get(Opc);
6617   MachineFunction &MF = DAG.getMachineFunction();
6618   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6619   unsigned NumDefs = MCID.NumDefs;
6620   std::vector<SDValue> AddrOps;
6621   std::vector<SDValue> BeforeOps;
6622   std::vector<SDValue> AfterOps;
6623   SDLoc dl(N);
6624   unsigned NumOps = N->getNumOperands();
6625   for (unsigned i = 0; i != NumOps-1; ++i) {
6626     SDValue Op = N->getOperand(i);
6627     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6628       AddrOps.push_back(Op);
6629     else if (i < Index-NumDefs)
6630       BeforeOps.push_back(Op);
6631     else if (i > Index-NumDefs)
6632       AfterOps.push_back(Op);
6633   }
6634   SDValue Chain = N->getOperand(NumOps-1);
6635   AddrOps.push_back(Chain);
6636 
6637   // Emit the load instruction.
6638   SDNode *Load = nullptr;
6639   if (FoldedLoad) {
6640     EVT VT = *RC->vt_begin();
6641     std::pair<MachineInstr::mmo_iterator,
6642               MachineInstr::mmo_iterator> MMOs =
6643       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6644                             cast<MachineSDNode>(N)->memoperands_end());
6645     if (!(*MMOs.first) &&
6646         RC == &X86::VR128RegClass &&
6647         Subtarget.isUnalignedMem16Slow())
6648       // Do not introduce a slow unaligned load.
6649       return false;
6650     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6651     // memory access is slow above.
6652     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6653     bool isAligned = (*MMOs.first) &&
6654                      (*MMOs.first)->getAlignment() >= Alignment;
6655     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
6656                               VT, MVT::Other, AddrOps);
6657     NewNodes.push_back(Load);
6658 
6659     // Preserve memory reference information.
6660     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
6661   }
6662 
6663   // Emit the data processing instruction.
6664   std::vector<EVT> VTs;
6665   const TargetRegisterClass *DstRC = nullptr;
6666   if (MCID.getNumDefs() > 0) {
6667     DstRC = getRegClass(MCID, 0, &RI, MF);
6668     VTs.push_back(*DstRC->vt_begin());
6669   }
6670   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6671     EVT VT = N->getValueType(i);
6672     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6673       VTs.push_back(VT);
6674   }
6675   if (Load)
6676     BeforeOps.push_back(SDValue(Load, 0));
6677   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6678   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6679   NewNodes.push_back(NewNode);
6680 
6681   // Emit the store instruction.
6682   if (FoldedStore) {
6683     AddrOps.pop_back();
6684     AddrOps.push_back(SDValue(NewNode, 0));
6685     AddrOps.push_back(Chain);
6686     std::pair<MachineInstr::mmo_iterator,
6687               MachineInstr::mmo_iterator> MMOs =
6688       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6689                              cast<MachineSDNode>(N)->memoperands_end());
6690     if (!(*MMOs.first) &&
6691         RC == &X86::VR128RegClass &&
6692         Subtarget.isUnalignedMem16Slow())
6693       // Do not introduce a slow unaligned store.
6694       return false;
6695     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6696     // memory access is slow above.
6697     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6698     bool isAligned = (*MMOs.first) &&
6699                      (*MMOs.first)->getAlignment() >= Alignment;
6700     SDNode *Store =
6701         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6702                            dl, MVT::Other, AddrOps);
6703     NewNodes.push_back(Store);
6704 
6705     // Preserve memory reference information.
6706     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
6707   }
6708 
6709   return true;
6710 }
6711 
6712 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6713                                       bool UnfoldLoad, bool UnfoldStore,
6714                                       unsigned *LoadRegIndex) const {
6715   auto I = MemOp2RegOpTable.find(Opc);
6716   if (I == MemOp2RegOpTable.end())
6717     return 0;
6718   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6719   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6720   if (UnfoldLoad && !FoldedLoad)
6721     return 0;
6722   if (UnfoldStore && !FoldedStore)
6723     return 0;
6724   if (LoadRegIndex)
6725     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
6726   return I->second.first;
6727 }
6728 
6729 bool
6730 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6731                                      int64_t &Offset1, int64_t &Offset2) const {
6732   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6733     return false;
6734   unsigned Opc1 = Load1->getMachineOpcode();
6735   unsigned Opc2 = Load2->getMachineOpcode();
6736   switch (Opc1) {
6737   default: return false;
6738   case X86::MOV8rm:
6739   case X86::MOV16rm:
6740   case X86::MOV32rm:
6741   case X86::MOV64rm:
6742   case X86::LD_Fp32m:
6743   case X86::LD_Fp64m:
6744   case X86::LD_Fp80m:
6745   case X86::MOVSSrm:
6746   case X86::MOVSDrm:
6747   case X86::MMX_MOVD64rm:
6748   case X86::MMX_MOVQ64rm:
6749   case X86::FsMOVAPSrm:
6750   case X86::FsMOVAPDrm:
6751   case X86::MOVAPSrm:
6752   case X86::MOVUPSrm:
6753   case X86::MOVAPDrm:
6754   case X86::MOVUPDrm:
6755   case X86::MOVDQArm:
6756   case X86::MOVDQUrm:
6757   // AVX load instructions
6758   case X86::VMOVSSrm:
6759   case X86::VMOVSDrm:
6760   case X86::FsVMOVAPSrm:
6761   case X86::FsVMOVAPDrm:
6762   case X86::VMOVAPSrm:
6763   case X86::VMOVUPSrm:
6764   case X86::VMOVAPDrm:
6765   case X86::VMOVUPDrm:
6766   case X86::VMOVDQArm:
6767   case X86::VMOVDQUrm:
6768   case X86::VMOVAPSYrm:
6769   case X86::VMOVUPSYrm:
6770   case X86::VMOVAPDYrm:
6771   case X86::VMOVUPDYrm:
6772   case X86::VMOVDQAYrm:
6773   case X86::VMOVDQUYrm:
6774   // AVX512 load instructions
6775   case X86::VMOVSSZrm:
6776   case X86::VMOVSDZrm:
6777   case X86::VMOVAPSZ128rm:
6778   case X86::VMOVUPSZ128rm:
6779   case X86::VMOVAPDZ128rm:
6780   case X86::VMOVUPDZ128rm:
6781   case X86::VMOVDQU8Z128rm:
6782   case X86::VMOVDQU16Z128rm:
6783   case X86::VMOVDQA32Z128rm:
6784   case X86::VMOVDQU32Z128rm:
6785   case X86::VMOVDQA64Z128rm:
6786   case X86::VMOVDQU64Z128rm:
6787   case X86::VMOVAPSZ256rm:
6788   case X86::VMOVUPSZ256rm:
6789   case X86::VMOVAPDZ256rm:
6790   case X86::VMOVUPDZ256rm:
6791   case X86::VMOVDQU8Z256rm:
6792   case X86::VMOVDQU16Z256rm:
6793   case X86::VMOVDQA32Z256rm:
6794   case X86::VMOVDQU32Z256rm:
6795   case X86::VMOVDQA64Z256rm:
6796   case X86::VMOVDQU64Z256rm:
6797   case X86::VMOVAPSZrm:
6798   case X86::VMOVUPSZrm:
6799   case X86::VMOVAPDZrm:
6800   case X86::VMOVUPDZrm:
6801   case X86::VMOVDQU8Zrm:
6802   case X86::VMOVDQU16Zrm:
6803   case X86::VMOVDQA32Zrm:
6804   case X86::VMOVDQU32Zrm:
6805   case X86::VMOVDQA64Zrm:
6806   case X86::VMOVDQU64Zrm:
6807   case X86::KMOVBkm:
6808   case X86::KMOVWkm:
6809   case X86::KMOVDkm:
6810   case X86::KMOVQkm:
6811     break;
6812   }
6813   switch (Opc2) {
6814   default: return false;
6815   case X86::MOV8rm:
6816   case X86::MOV16rm:
6817   case X86::MOV32rm:
6818   case X86::MOV64rm:
6819   case X86::LD_Fp32m:
6820   case X86::LD_Fp64m:
6821   case X86::LD_Fp80m:
6822   case X86::MOVSSrm:
6823   case X86::MOVSDrm:
6824   case X86::MMX_MOVD64rm:
6825   case X86::MMX_MOVQ64rm:
6826   case X86::FsMOVAPSrm:
6827   case X86::FsMOVAPDrm:
6828   case X86::MOVAPSrm:
6829   case X86::MOVUPSrm:
6830   case X86::MOVAPDrm:
6831   case X86::MOVUPDrm:
6832   case X86::MOVDQArm:
6833   case X86::MOVDQUrm:
6834   // AVX load instructions
6835   case X86::VMOVSSrm:
6836   case X86::VMOVSDrm:
6837   case X86::FsVMOVAPSrm:
6838   case X86::FsVMOVAPDrm:
6839   case X86::VMOVAPSrm:
6840   case X86::VMOVUPSrm:
6841   case X86::VMOVAPDrm:
6842   case X86::VMOVUPDrm:
6843   case X86::VMOVDQArm:
6844   case X86::VMOVDQUrm:
6845   case X86::VMOVAPSYrm:
6846   case X86::VMOVUPSYrm:
6847   case X86::VMOVAPDYrm:
6848   case X86::VMOVUPDYrm:
6849   case X86::VMOVDQAYrm:
6850   case X86::VMOVDQUYrm:
6851   // AVX512 load instructions
6852   case X86::VMOVSSZrm:
6853   case X86::VMOVSDZrm:
6854   case X86::VMOVAPSZ128rm:
6855   case X86::VMOVUPSZ128rm:
6856   case X86::VMOVAPDZ128rm:
6857   case X86::VMOVUPDZ128rm:
6858   case X86::VMOVDQU8Z128rm:
6859   case X86::VMOVDQU16Z128rm:
6860   case X86::VMOVDQA32Z128rm:
6861   case X86::VMOVDQU32Z128rm:
6862   case X86::VMOVDQA64Z128rm:
6863   case X86::VMOVDQU64Z128rm:
6864   case X86::VMOVAPSZ256rm:
6865   case X86::VMOVUPSZ256rm:
6866   case X86::VMOVAPDZ256rm:
6867   case X86::VMOVUPDZ256rm:
6868   case X86::VMOVDQU8Z256rm:
6869   case X86::VMOVDQU16Z256rm:
6870   case X86::VMOVDQA32Z256rm:
6871   case X86::VMOVDQU32Z256rm:
6872   case X86::VMOVDQA64Z256rm:
6873   case X86::VMOVDQU64Z256rm:
6874   case X86::VMOVAPSZrm:
6875   case X86::VMOVUPSZrm:
6876   case X86::VMOVAPDZrm:
6877   case X86::VMOVUPDZrm:
6878   case X86::VMOVDQU8Zrm:
6879   case X86::VMOVDQU16Zrm:
6880   case X86::VMOVDQA32Zrm:
6881   case X86::VMOVDQU32Zrm:
6882   case X86::VMOVDQA64Zrm:
6883   case X86::VMOVDQU64Zrm:
6884   case X86::KMOVBkm:
6885   case X86::KMOVWkm:
6886   case X86::KMOVDkm:
6887   case X86::KMOVQkm:
6888     break;
6889   }
6890 
6891   // Check if chain operands and base addresses match.
6892   if (Load1->getOperand(0) != Load2->getOperand(0) ||
6893       Load1->getOperand(5) != Load2->getOperand(5))
6894     return false;
6895   // Segment operands should match as well.
6896   if (Load1->getOperand(4) != Load2->getOperand(4))
6897     return false;
6898   // Scale should be 1, Index should be Reg0.
6899   if (Load1->getOperand(1) == Load2->getOperand(1) &&
6900       Load1->getOperand(2) == Load2->getOperand(2)) {
6901     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6902       return false;
6903 
6904     // Now let's examine the displacements.
6905     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6906         isa<ConstantSDNode>(Load2->getOperand(3))) {
6907       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6908       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6909       return true;
6910     }
6911   }
6912   return false;
6913 }
6914 
6915 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6916                                            int64_t Offset1, int64_t Offset2,
6917                                            unsigned NumLoads) const {
6918   assert(Offset2 > Offset1);
6919   if ((Offset2 - Offset1) / 8 > 64)
6920     return false;
6921 
6922   unsigned Opc1 = Load1->getMachineOpcode();
6923   unsigned Opc2 = Load2->getMachineOpcode();
6924   if (Opc1 != Opc2)
6925     return false;  // FIXME: overly conservative?
6926 
6927   switch (Opc1) {
6928   default: break;
6929   case X86::LD_Fp32m:
6930   case X86::LD_Fp64m:
6931   case X86::LD_Fp80m:
6932   case X86::MMX_MOVD64rm:
6933   case X86::MMX_MOVQ64rm:
6934     return false;
6935   }
6936 
6937   EVT VT = Load1->getValueType(0);
6938   switch (VT.getSimpleVT().SimpleTy) {
6939   default:
6940     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6941     // have 16 of them to play with.
6942     if (Subtarget.is64Bit()) {
6943       if (NumLoads >= 3)
6944         return false;
6945     } else if (NumLoads) {
6946       return false;
6947     }
6948     break;
6949   case MVT::i8:
6950   case MVT::i16:
6951   case MVT::i32:
6952   case MVT::i64:
6953   case MVT::f32:
6954   case MVT::f64:
6955     if (NumLoads)
6956       return false;
6957     break;
6958   }
6959 
6960   return true;
6961 }
6962 
6963 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
6964                                           MachineInstr &Second) const {
6965   // Check if this processor supports macro-fusion. Since this is a minor
6966   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6967   // proxy for SandyBridge+.
6968   if (!Subtarget.hasAVX())
6969     return false;
6970 
6971   enum {
6972     FuseTest,
6973     FuseCmp,
6974     FuseInc
6975   } FuseKind;
6976 
6977   switch (Second.getOpcode()) {
6978   default:
6979     return false;
6980   case X86::JE_1:
6981   case X86::JNE_1:
6982   case X86::JL_1:
6983   case X86::JLE_1:
6984   case X86::JG_1:
6985   case X86::JGE_1:
6986     FuseKind = FuseInc;
6987     break;
6988   case X86::JB_1:
6989   case X86::JBE_1:
6990   case X86::JA_1:
6991   case X86::JAE_1:
6992     FuseKind = FuseCmp;
6993     break;
6994   case X86::JS_1:
6995   case X86::JNS_1:
6996   case X86::JP_1:
6997   case X86::JNP_1:
6998   case X86::JO_1:
6999   case X86::JNO_1:
7000     FuseKind = FuseTest;
7001     break;
7002   }
7003   switch (First.getOpcode()) {
7004   default:
7005     return false;
7006   case X86::TEST8rr:
7007   case X86::TEST16rr:
7008   case X86::TEST32rr:
7009   case X86::TEST64rr:
7010   case X86::TEST8ri:
7011   case X86::TEST16ri:
7012   case X86::TEST32ri:
7013   case X86::TEST32i32:
7014   case X86::TEST64i32:
7015   case X86::TEST64ri32:
7016   case X86::TEST8rm:
7017   case X86::TEST16rm:
7018   case X86::TEST32rm:
7019   case X86::TEST64rm:
7020   case X86::TEST8ri_NOREX:
7021   case X86::AND16i16:
7022   case X86::AND16ri:
7023   case X86::AND16ri8:
7024   case X86::AND16rm:
7025   case X86::AND16rr:
7026   case X86::AND32i32:
7027   case X86::AND32ri:
7028   case X86::AND32ri8:
7029   case X86::AND32rm:
7030   case X86::AND32rr:
7031   case X86::AND64i32:
7032   case X86::AND64ri32:
7033   case X86::AND64ri8:
7034   case X86::AND64rm:
7035   case X86::AND64rr:
7036   case X86::AND8i8:
7037   case X86::AND8ri:
7038   case X86::AND8rm:
7039   case X86::AND8rr:
7040     return true;
7041   case X86::CMP16i16:
7042   case X86::CMP16ri:
7043   case X86::CMP16ri8:
7044   case X86::CMP16rm:
7045   case X86::CMP16rr:
7046   case X86::CMP32i32:
7047   case X86::CMP32ri:
7048   case X86::CMP32ri8:
7049   case X86::CMP32rm:
7050   case X86::CMP32rr:
7051   case X86::CMP64i32:
7052   case X86::CMP64ri32:
7053   case X86::CMP64ri8:
7054   case X86::CMP64rm:
7055   case X86::CMP64rr:
7056   case X86::CMP8i8:
7057   case X86::CMP8ri:
7058   case X86::CMP8rm:
7059   case X86::CMP8rr:
7060   case X86::ADD16i16:
7061   case X86::ADD16ri:
7062   case X86::ADD16ri8:
7063   case X86::ADD16ri8_DB:
7064   case X86::ADD16ri_DB:
7065   case X86::ADD16rm:
7066   case X86::ADD16rr:
7067   case X86::ADD16rr_DB:
7068   case X86::ADD32i32:
7069   case X86::ADD32ri:
7070   case X86::ADD32ri8:
7071   case X86::ADD32ri8_DB:
7072   case X86::ADD32ri_DB:
7073   case X86::ADD32rm:
7074   case X86::ADD32rr:
7075   case X86::ADD32rr_DB:
7076   case X86::ADD64i32:
7077   case X86::ADD64ri32:
7078   case X86::ADD64ri32_DB:
7079   case X86::ADD64ri8:
7080   case X86::ADD64ri8_DB:
7081   case X86::ADD64rm:
7082   case X86::ADD64rr:
7083   case X86::ADD64rr_DB:
7084   case X86::ADD8i8:
7085   case X86::ADD8mi:
7086   case X86::ADD8mr:
7087   case X86::ADD8ri:
7088   case X86::ADD8rm:
7089   case X86::ADD8rr:
7090   case X86::SUB16i16:
7091   case X86::SUB16ri:
7092   case X86::SUB16ri8:
7093   case X86::SUB16rm:
7094   case X86::SUB16rr:
7095   case X86::SUB32i32:
7096   case X86::SUB32ri:
7097   case X86::SUB32ri8:
7098   case X86::SUB32rm:
7099   case X86::SUB32rr:
7100   case X86::SUB64i32:
7101   case X86::SUB64ri32:
7102   case X86::SUB64ri8:
7103   case X86::SUB64rm:
7104   case X86::SUB64rr:
7105   case X86::SUB8i8:
7106   case X86::SUB8ri:
7107   case X86::SUB8rm:
7108   case X86::SUB8rr:
7109     return FuseKind == FuseCmp || FuseKind == FuseInc;
7110   case X86::INC16r:
7111   case X86::INC32r:
7112   case X86::INC64r:
7113   case X86::INC8r:
7114   case X86::DEC16r:
7115   case X86::DEC32r:
7116   case X86::DEC64r:
7117   case X86::DEC8r:
7118     return FuseKind == FuseInc;
7119   }
7120 }
7121 
7122 bool X86InstrInfo::
7123 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
7124   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
7125   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7126   Cond[0].setImm(GetOppositeBranchCondition(CC));
7127   return false;
7128 }
7129 
7130 bool X86InstrInfo::
7131 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7132   // FIXME: Return false for x87 stack register classes for now. We can't
7133   // allow any loads of these registers before FpGet_ST0_80.
7134   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
7135            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
7136 }
7137 
7138 /// Return a virtual register initialized with the
7139 /// the global base register value. Output instructions required to
7140 /// initialize the register in the function entry block, if necessary.
7141 ///
7142 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7143 ///
7144 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
7145   assert(!Subtarget.is64Bit() &&
7146          "X86-64 PIC uses RIP relative addressing");
7147 
7148   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7149   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7150   if (GlobalBaseReg != 0)
7151     return GlobalBaseReg;
7152 
7153   // Create the register. The code to initialize it is inserted
7154   // later, by the CGBR pass (below).
7155   MachineRegisterInfo &RegInfo = MF->getRegInfo();
7156   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
7157   X86FI->setGlobalBaseReg(GlobalBaseReg);
7158   return GlobalBaseReg;
7159 }
7160 
7161 // These are the replaceable SSE instructions. Some of these have Int variants
7162 // that we don't include here. We don't want to replace instructions selected
7163 // by intrinsics.
7164 static const uint16_t ReplaceableInstrs[][3] = {
7165   //PackedSingle     PackedDouble    PackedInt
7166   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
7167   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
7168   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
7169   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
7170   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
7171   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
7172   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
7173   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
7174   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
7175   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
7176   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
7177   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
7178   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
7179   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
7180   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
7181   // AVX 128-bit support
7182   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
7183   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
7184   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
7185   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
7186   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
7187   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
7188   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7189   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
7190   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
7191   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
7192   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
7193   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
7194   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
7195   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
7196   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
7197   // AVX 256-bit support
7198   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
7199   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
7200   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
7201   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
7202   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
7203   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
7204 };
7205 
7206 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7207   //PackedSingle       PackedDouble       PackedInt
7208   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7209   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7210   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7211   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7212   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7213   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7214   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7215   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7216   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7217   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7218   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7219   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7220   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7221   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7222   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7223   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7224   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7225   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7226   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7227   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
7228 };
7229 
7230 // FIXME: Some shuffle and unpack instructions have equivalents in different
7231 // domains, but they require a bit more work than just switching opcodes.
7232 
7233 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
7234   for (const uint16_t (&Row)[3] : ReplaceableInstrs)
7235     if (Row[domain-1] == opcode)
7236       return Row;
7237   return nullptr;
7238 }
7239 
7240 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
7241   for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
7242     if (Row[domain-1] == opcode)
7243       return Row;
7244   return nullptr;
7245 }
7246 
7247 std::pair<uint16_t, uint16_t>
7248 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7249   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7250   bool hasAVX2 = Subtarget.hasAVX2();
7251   uint16_t validDomains = 0;
7252   if (domain && lookup(MI.getOpcode(), domain))
7253     validDomains = 0xe;
7254   else if (domain && lookupAVX2(MI.getOpcode(), domain))
7255     validDomains = hasAVX2 ? 0xe : 0x6;
7256   return std::make_pair(domain, validDomains);
7257 }
7258 
7259 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7260   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7261   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7262   assert(dom && "Not an SSE instruction");
7263   const uint16_t *table = lookup(MI.getOpcode(), dom);
7264   if (!table) { // try the other table
7265     assert((Subtarget.hasAVX2() || Domain < 3) &&
7266            "256-bit vector operations only available in AVX2");
7267     table = lookupAVX2(MI.getOpcode(), dom);
7268   }
7269   assert(table && "Cannot change domain");
7270   MI.setDesc(get(table[Domain - 1]));
7271 }
7272 
7273 /// Return the noop instruction to use for a noop.
7274 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7275   NopInst.setOpcode(X86::NOOP);
7276 }
7277 
7278 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7279 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7280 // on the encoding lengths of the instructions generated by
7281 // getUnconditionalBranch and getTrap.
7282 void X86InstrInfo::getUnconditionalBranch(
7283     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
7284   Branch.setOpcode(X86::JMP_1);
7285   Branch.addOperand(MCOperand::createExpr(BranchTarget));
7286 }
7287 
7288 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7289 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7290 // on the encoding lengths of the instructions generated by
7291 // getUnconditionalBranch and getTrap.
7292 void X86InstrInfo::getTrap(MCInst &MI) const {
7293   MI.setOpcode(X86::TRAP);
7294 }
7295 
7296 // See getTrap and getUnconditionalBranch for conditions on the value returned
7297 // by this function.
7298 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7299   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7300   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7301   return 5;
7302 }
7303 
7304 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7305   switch (opc) {
7306   default: return false;
7307   case X86::DIVPDrm:
7308   case X86::DIVPDrr:
7309   case X86::DIVPSrm:
7310   case X86::DIVPSrr:
7311   case X86::DIVSDrm:
7312   case X86::DIVSDrm_Int:
7313   case X86::DIVSDrr:
7314   case X86::DIVSDrr_Int:
7315   case X86::DIVSSrm:
7316   case X86::DIVSSrm_Int:
7317   case X86::DIVSSrr:
7318   case X86::DIVSSrr_Int:
7319   case X86::SQRTPDm:
7320   case X86::SQRTPDr:
7321   case X86::SQRTPSm:
7322   case X86::SQRTPSr:
7323   case X86::SQRTSDm:
7324   case X86::SQRTSDm_Int:
7325   case X86::SQRTSDr:
7326   case X86::SQRTSDr_Int:
7327   case X86::SQRTSSm:
7328   case X86::SQRTSSm_Int:
7329   case X86::SQRTSSr:
7330   case X86::SQRTSSr_Int:
7331   // AVX instructions with high latency
7332   case X86::VDIVPDrm:
7333   case X86::VDIVPDrr:
7334   case X86::VDIVPDYrm:
7335   case X86::VDIVPDYrr:
7336   case X86::VDIVPSrm:
7337   case X86::VDIVPSrr:
7338   case X86::VDIVPSYrm:
7339   case X86::VDIVPSYrr:
7340   case X86::VDIVSDrm:
7341   case X86::VDIVSDrm_Int:
7342   case X86::VDIVSDrr:
7343   case X86::VDIVSDrr_Int:
7344   case X86::VDIVSSrm:
7345   case X86::VDIVSSrm_Int:
7346   case X86::VDIVSSrr:
7347   case X86::VDIVSSrr_Int:
7348   case X86::VSQRTPDm:
7349   case X86::VSQRTPDr:
7350   case X86::VSQRTPDYm:
7351   case X86::VSQRTPDYr:
7352   case X86::VSQRTPSm:
7353   case X86::VSQRTPSr:
7354   case X86::VSQRTPSYm:
7355   case X86::VSQRTPSYr:
7356   case X86::VSQRTSDm:
7357   case X86::VSQRTSDm_Int:
7358   case X86::VSQRTSDr:
7359   case X86::VSQRTSDr_Int:
7360   case X86::VSQRTSSm:
7361   case X86::VSQRTSSm_Int:
7362   case X86::VSQRTSSr:
7363   case X86::VSQRTSSr_Int:
7364   // AVX512 instructions with high latency
7365   case X86::VDIVPDZ128rm:
7366   case X86::VDIVPDZ128rmb:
7367   case X86::VDIVPDZ128rmbk:
7368   case X86::VDIVPDZ128rmbkz:
7369   case X86::VDIVPDZ128rmk:
7370   case X86::VDIVPDZ128rmkz:
7371   case X86::VDIVPDZ128rr:
7372   case X86::VDIVPDZ128rrk:
7373   case X86::VDIVPDZ128rrkz:
7374   case X86::VDIVPDZ256rm:
7375   case X86::VDIVPDZ256rmb:
7376   case X86::VDIVPDZ256rmbk:
7377   case X86::VDIVPDZ256rmbkz:
7378   case X86::VDIVPDZ256rmk:
7379   case X86::VDIVPDZ256rmkz:
7380   case X86::VDIVPDZ256rr:
7381   case X86::VDIVPDZ256rrk:
7382   case X86::VDIVPDZ256rrkz:
7383   case X86::VDIVPDZrb:
7384   case X86::VDIVPDZrbk:
7385   case X86::VDIVPDZrbkz:
7386   case X86::VDIVPDZrm:
7387   case X86::VDIVPDZrmb:
7388   case X86::VDIVPDZrmbk:
7389   case X86::VDIVPDZrmbkz:
7390   case X86::VDIVPDZrmk:
7391   case X86::VDIVPDZrmkz:
7392   case X86::VDIVPDZrr:
7393   case X86::VDIVPDZrrk:
7394   case X86::VDIVPDZrrkz:
7395   case X86::VDIVPSZ128rm:
7396   case X86::VDIVPSZ128rmb:
7397   case X86::VDIVPSZ128rmbk:
7398   case X86::VDIVPSZ128rmbkz:
7399   case X86::VDIVPSZ128rmk:
7400   case X86::VDIVPSZ128rmkz:
7401   case X86::VDIVPSZ128rr:
7402   case X86::VDIVPSZ128rrk:
7403   case X86::VDIVPSZ128rrkz:
7404   case X86::VDIVPSZ256rm:
7405   case X86::VDIVPSZ256rmb:
7406   case X86::VDIVPSZ256rmbk:
7407   case X86::VDIVPSZ256rmbkz:
7408   case X86::VDIVPSZ256rmk:
7409   case X86::VDIVPSZ256rmkz:
7410   case X86::VDIVPSZ256rr:
7411   case X86::VDIVPSZ256rrk:
7412   case X86::VDIVPSZ256rrkz:
7413   case X86::VDIVPSZrb:
7414   case X86::VDIVPSZrbk:
7415   case X86::VDIVPSZrbkz:
7416   case X86::VDIVPSZrm:
7417   case X86::VDIVPSZrmb:
7418   case X86::VDIVPSZrmbk:
7419   case X86::VDIVPSZrmbkz:
7420   case X86::VDIVPSZrmk:
7421   case X86::VDIVPSZrmkz:
7422   case X86::VDIVPSZrr:
7423   case X86::VDIVPSZrrk:
7424   case X86::VDIVPSZrrkz:
7425   case X86::VDIVSDZrm:
7426   case X86::VDIVSDZrr:
7427   case X86::VDIVSDZrm_Int:
7428   case X86::VDIVSDZrm_Intk:
7429   case X86::VDIVSDZrm_Intkz:
7430   case X86::VDIVSDZrr_Int:
7431   case X86::VDIVSDZrr_Intk:
7432   case X86::VDIVSDZrr_Intkz:
7433   case X86::VDIVSDZrrb:
7434   case X86::VDIVSDZrrbk:
7435   case X86::VDIVSDZrrbkz:
7436   case X86::VDIVSSZrm:
7437   case X86::VDIVSSZrr:
7438   case X86::VDIVSSZrm_Int:
7439   case X86::VDIVSSZrm_Intk:
7440   case X86::VDIVSSZrm_Intkz:
7441   case X86::VDIVSSZrr_Int:
7442   case X86::VDIVSSZrr_Intk:
7443   case X86::VDIVSSZrr_Intkz:
7444   case X86::VDIVSSZrrb:
7445   case X86::VDIVSSZrrbk:
7446   case X86::VDIVSSZrrbkz:
7447   case X86::VSQRTPDZ128m:
7448   case X86::VSQRTPDZ128mb:
7449   case X86::VSQRTPDZ128mbk:
7450   case X86::VSQRTPDZ128mbkz:
7451   case X86::VSQRTPDZ128mk:
7452   case X86::VSQRTPDZ128mkz:
7453   case X86::VSQRTPDZ128r:
7454   case X86::VSQRTPDZ128rk:
7455   case X86::VSQRTPDZ128rkz:
7456   case X86::VSQRTPDZ256m:
7457   case X86::VSQRTPDZ256mb:
7458   case X86::VSQRTPDZ256mbk:
7459   case X86::VSQRTPDZ256mbkz:
7460   case X86::VSQRTPDZ256mk:
7461   case X86::VSQRTPDZ256mkz:
7462   case X86::VSQRTPDZ256r:
7463   case X86::VSQRTPDZ256rk:
7464   case X86::VSQRTPDZ256rkz:
7465   case X86::VSQRTPDZm:
7466   case X86::VSQRTPDZmb:
7467   case X86::VSQRTPDZmbk:
7468   case X86::VSQRTPDZmbkz:
7469   case X86::VSQRTPDZmk:
7470   case X86::VSQRTPDZmkz:
7471   case X86::VSQRTPDZr:
7472   case X86::VSQRTPDZrb:
7473   case X86::VSQRTPDZrbk:
7474   case X86::VSQRTPDZrbkz:
7475   case X86::VSQRTPDZrk:
7476   case X86::VSQRTPDZrkz:
7477   case X86::VSQRTPSZ128m:
7478   case X86::VSQRTPSZ128mb:
7479   case X86::VSQRTPSZ128mbk:
7480   case X86::VSQRTPSZ128mbkz:
7481   case X86::VSQRTPSZ128mk:
7482   case X86::VSQRTPSZ128mkz:
7483   case X86::VSQRTPSZ128r:
7484   case X86::VSQRTPSZ128rk:
7485   case X86::VSQRTPSZ128rkz:
7486   case X86::VSQRTPSZ256m:
7487   case X86::VSQRTPSZ256mb:
7488   case X86::VSQRTPSZ256mbk:
7489   case X86::VSQRTPSZ256mbkz:
7490   case X86::VSQRTPSZ256mk:
7491   case X86::VSQRTPSZ256mkz:
7492   case X86::VSQRTPSZ256r:
7493   case X86::VSQRTPSZ256rk:
7494   case X86::VSQRTPSZ256rkz:
7495   case X86::VSQRTPSZm:
7496   case X86::VSQRTPSZmb:
7497   case X86::VSQRTPSZmbk:
7498   case X86::VSQRTPSZmbkz:
7499   case X86::VSQRTPSZmk:
7500   case X86::VSQRTPSZmkz:
7501   case X86::VSQRTPSZr:
7502   case X86::VSQRTPSZrb:
7503   case X86::VSQRTPSZrbk:
7504   case X86::VSQRTPSZrbkz:
7505   case X86::VSQRTPSZrk:
7506   case X86::VSQRTPSZrkz:
7507   case X86::VSQRTSDZm:
7508   case X86::VSQRTSDZm_Int:
7509   case X86::VSQRTSDZm_Intk:
7510   case X86::VSQRTSDZm_Intkz:
7511   case X86::VSQRTSDZr:
7512   case X86::VSQRTSDZr_Int:
7513   case X86::VSQRTSDZr_Intk:
7514   case X86::VSQRTSDZr_Intkz:
7515   case X86::VSQRTSDZrb_Int:
7516   case X86::VSQRTSDZrb_Intk:
7517   case X86::VSQRTSDZrb_Intkz:
7518   case X86::VSQRTSSZm:
7519   case X86::VSQRTSSZm_Int:
7520   case X86::VSQRTSSZm_Intk:
7521   case X86::VSQRTSSZm_Intkz:
7522   case X86::VSQRTSSZr:
7523   case X86::VSQRTSSZr_Int:
7524   case X86::VSQRTSSZr_Intk:
7525   case X86::VSQRTSSZr_Intkz:
7526   case X86::VSQRTSSZrb_Int:
7527   case X86::VSQRTSSZrb_Intk:
7528   case X86::VSQRTSSZrb_Intkz:
7529 
7530   case X86::VGATHERDPDYrm:
7531   case X86::VGATHERDPDZ128rm:
7532   case X86::VGATHERDPDZ256rm:
7533   case X86::VGATHERDPDZrm:
7534   case X86::VGATHERDPDrm:
7535   case X86::VGATHERDPSYrm:
7536   case X86::VGATHERDPSZ128rm:
7537   case X86::VGATHERDPSZ256rm:
7538   case X86::VGATHERDPSZrm:
7539   case X86::VGATHERDPSrm:
7540   case X86::VGATHERPF0DPDm:
7541   case X86::VGATHERPF0DPSm:
7542   case X86::VGATHERPF0QPDm:
7543   case X86::VGATHERPF0QPSm:
7544   case X86::VGATHERPF1DPDm:
7545   case X86::VGATHERPF1DPSm:
7546   case X86::VGATHERPF1QPDm:
7547   case X86::VGATHERPF1QPSm:
7548   case X86::VGATHERQPDYrm:
7549   case X86::VGATHERQPDZ128rm:
7550   case X86::VGATHERQPDZ256rm:
7551   case X86::VGATHERQPDZrm:
7552   case X86::VGATHERQPDrm:
7553   case X86::VGATHERQPSYrm:
7554   case X86::VGATHERQPSZ128rm:
7555   case X86::VGATHERQPSZ256rm:
7556   case X86::VGATHERQPSZrm:
7557   case X86::VGATHERQPSrm:
7558   case X86::VPGATHERDDYrm:
7559   case X86::VPGATHERDDZ128rm:
7560   case X86::VPGATHERDDZ256rm:
7561   case X86::VPGATHERDDZrm:
7562   case X86::VPGATHERDDrm:
7563   case X86::VPGATHERDQYrm:
7564   case X86::VPGATHERDQZ128rm:
7565   case X86::VPGATHERDQZ256rm:
7566   case X86::VPGATHERDQZrm:
7567   case X86::VPGATHERDQrm:
7568   case X86::VPGATHERQDYrm:
7569   case X86::VPGATHERQDZ128rm:
7570   case X86::VPGATHERQDZ256rm:
7571   case X86::VPGATHERQDZrm:
7572   case X86::VPGATHERQDrm:
7573   case X86::VPGATHERQQYrm:
7574   case X86::VPGATHERQQZ128rm:
7575   case X86::VPGATHERQQZ256rm:
7576   case X86::VPGATHERQQZrm:
7577   case X86::VPGATHERQQrm:
7578   case X86::VSCATTERDPDZ128mr:
7579   case X86::VSCATTERDPDZ256mr:
7580   case X86::VSCATTERDPDZmr:
7581   case X86::VSCATTERDPSZ128mr:
7582   case X86::VSCATTERDPSZ256mr:
7583   case X86::VSCATTERDPSZmr:
7584   case X86::VSCATTERPF0DPDm:
7585   case X86::VSCATTERPF0DPSm:
7586   case X86::VSCATTERPF0QPDm:
7587   case X86::VSCATTERPF0QPSm:
7588   case X86::VSCATTERPF1DPDm:
7589   case X86::VSCATTERPF1DPSm:
7590   case X86::VSCATTERPF1QPDm:
7591   case X86::VSCATTERPF1QPSm:
7592   case X86::VSCATTERQPDZ128mr:
7593   case X86::VSCATTERQPDZ256mr:
7594   case X86::VSCATTERQPDZmr:
7595   case X86::VSCATTERQPSZ128mr:
7596   case X86::VSCATTERQPSZ256mr:
7597   case X86::VSCATTERQPSZmr:
7598   case X86::VPSCATTERDDZ128mr:
7599   case X86::VPSCATTERDDZ256mr:
7600   case X86::VPSCATTERDDZmr:
7601   case X86::VPSCATTERDQZ128mr:
7602   case X86::VPSCATTERDQZ256mr:
7603   case X86::VPSCATTERDQZmr:
7604   case X86::VPSCATTERQDZ128mr:
7605   case X86::VPSCATTERQDZ256mr:
7606   case X86::VPSCATTERQDZmr:
7607   case X86::VPSCATTERQQZ128mr:
7608   case X86::VPSCATTERQQZ256mr:
7609   case X86::VPSCATTERQQZmr:
7610     return true;
7611   }
7612 }
7613 
7614 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7615                                          const MachineRegisterInfo *MRI,
7616                                          const MachineInstr &DefMI,
7617                                          unsigned DefIdx,
7618                                          const MachineInstr &UseMI,
7619                                          unsigned UseIdx) const {
7620   return isHighLatencyDef(DefMI.getOpcode());
7621 }
7622 
7623 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7624                                            const MachineBasicBlock *MBB) const {
7625   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7626          "Reassociation needs binary operators");
7627 
7628   // Integer binary math/logic instructions have a third source operand:
7629   // the EFLAGS register. That operand must be both defined here and never
7630   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7631   // not change anything because rearranging the operands could affect other
7632   // instructions that depend on the exact status flags (zero, sign, etc.)
7633   // that are set by using these particular operands with this operation.
7634   if (Inst.getNumOperands() == 4) {
7635     assert(Inst.getOperand(3).isReg() &&
7636            Inst.getOperand(3).getReg() == X86::EFLAGS &&
7637            "Unexpected operand in reassociable instruction");
7638     if (!Inst.getOperand(3).isDead())
7639       return false;
7640   }
7641 
7642   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7643 }
7644 
7645 // TODO: There are many more machine instruction opcodes to match:
7646 //       1. Other data types (integer, vectors)
7647 //       2. Other math / logic operations (xor, or)
7648 //       3. Other forms of the same operation (intrinsics and other variants)
7649 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7650   switch (Inst.getOpcode()) {
7651   case X86::AND8rr:
7652   case X86::AND16rr:
7653   case X86::AND32rr:
7654   case X86::AND64rr:
7655   case X86::OR8rr:
7656   case X86::OR16rr:
7657   case X86::OR32rr:
7658   case X86::OR64rr:
7659   case X86::XOR8rr:
7660   case X86::XOR16rr:
7661   case X86::XOR32rr:
7662   case X86::XOR64rr:
7663   case X86::IMUL16rr:
7664   case X86::IMUL32rr:
7665   case X86::IMUL64rr:
7666   case X86::PANDrr:
7667   case X86::PORrr:
7668   case X86::PXORrr:
7669   case X86::ANDPDrr:
7670   case X86::ANDPSrr:
7671   case X86::ORPDrr:
7672   case X86::ORPSrr:
7673   case X86::XORPDrr:
7674   case X86::XORPSrr:
7675   case X86::PADDBrr:
7676   case X86::PADDWrr:
7677   case X86::PADDDrr:
7678   case X86::PADDQrr:
7679   case X86::VPANDrr:
7680   case X86::VPANDYrr:
7681   case X86::VPANDDZ128rr:
7682   case X86::VPANDDZ256rr:
7683   case X86::VPANDDZrr:
7684   case X86::VPANDQZ128rr:
7685   case X86::VPANDQZ256rr:
7686   case X86::VPANDQZrr:
7687   case X86::VPORrr:
7688   case X86::VPORYrr:
7689   case X86::VPORDZ128rr:
7690   case X86::VPORDZ256rr:
7691   case X86::VPORDZrr:
7692   case X86::VPORQZ128rr:
7693   case X86::VPORQZ256rr:
7694   case X86::VPORQZrr:
7695   case X86::VPXORrr:
7696   case X86::VPXORYrr:
7697   case X86::VPXORDZ128rr:
7698   case X86::VPXORDZ256rr:
7699   case X86::VPXORDZrr:
7700   case X86::VPXORQZ128rr:
7701   case X86::VPXORQZ256rr:
7702   case X86::VPXORQZrr:
7703   case X86::VANDPDrr:
7704   case X86::VANDPSrr:
7705   case X86::VANDPDYrr:
7706   case X86::VANDPSYrr:
7707   case X86::VANDPDZ128rr:
7708   case X86::VANDPSZ128rr:
7709   case X86::VANDPDZ256rr:
7710   case X86::VANDPSZ256rr:
7711   case X86::VANDPDZrr:
7712   case X86::VANDPSZrr:
7713   case X86::VORPDrr:
7714   case X86::VORPSrr:
7715   case X86::VORPDYrr:
7716   case X86::VORPSYrr:
7717   case X86::VORPDZ128rr:
7718   case X86::VORPSZ128rr:
7719   case X86::VORPDZ256rr:
7720   case X86::VORPSZ256rr:
7721   case X86::VORPDZrr:
7722   case X86::VORPSZrr:
7723   case X86::VXORPDrr:
7724   case X86::VXORPSrr:
7725   case X86::VXORPDYrr:
7726   case X86::VXORPSYrr:
7727   case X86::VXORPDZ128rr:
7728   case X86::VXORPSZ128rr:
7729   case X86::VXORPDZ256rr:
7730   case X86::VXORPSZ256rr:
7731   case X86::VXORPDZrr:
7732   case X86::VXORPSZrr:
7733   case X86::KADDBrr:
7734   case X86::KADDWrr:
7735   case X86::KADDDrr:
7736   case X86::KADDQrr:
7737   case X86::KANDBrr:
7738   case X86::KANDWrr:
7739   case X86::KANDDrr:
7740   case X86::KANDQrr:
7741   case X86::KORBrr:
7742   case X86::KORWrr:
7743   case X86::KORDrr:
7744   case X86::KORQrr:
7745   case X86::KXORBrr:
7746   case X86::KXORWrr:
7747   case X86::KXORDrr:
7748   case X86::KXORQrr:
7749   case X86::VPADDBrr:
7750   case X86::VPADDWrr:
7751   case X86::VPADDDrr:
7752   case X86::VPADDQrr:
7753   case X86::VPADDBYrr:
7754   case X86::VPADDWYrr:
7755   case X86::VPADDDYrr:
7756   case X86::VPADDQYrr:
7757   case X86::VPADDBZ128rr:
7758   case X86::VPADDWZ128rr:
7759   case X86::VPADDDZ128rr:
7760   case X86::VPADDQZ128rr:
7761   case X86::VPADDBZ256rr:
7762   case X86::VPADDWZ256rr:
7763   case X86::VPADDDZ256rr:
7764   case X86::VPADDQZ256rr:
7765   case X86::VPADDBZrr:
7766   case X86::VPADDWZrr:
7767   case X86::VPADDDZrr:
7768   case X86::VPADDQZrr:
7769   case X86::VPMULLWrr:
7770   case X86::VPMULLWYrr:
7771   case X86::VPMULLWZ128rr:
7772   case X86::VPMULLWZ256rr:
7773   case X86::VPMULLWZrr:
7774   case X86::VPMULLDrr:
7775   case X86::VPMULLDYrr:
7776   case X86::VPMULLDZ128rr:
7777   case X86::VPMULLDZ256rr:
7778   case X86::VPMULLDZrr:
7779   case X86::VPMULLQZ128rr:
7780   case X86::VPMULLQZ256rr:
7781   case X86::VPMULLQZrr:
7782   // Normal min/max instructions are not commutative because of NaN and signed
7783   // zero semantics, but these are. Thus, there's no need to check for global
7784   // relaxed math; the instructions themselves have the properties we need.
7785   case X86::MAXCPDrr:
7786   case X86::MAXCPSrr:
7787   case X86::MAXCSDrr:
7788   case X86::MAXCSSrr:
7789   case X86::MINCPDrr:
7790   case X86::MINCPSrr:
7791   case X86::MINCSDrr:
7792   case X86::MINCSSrr:
7793   case X86::VMAXCPDrr:
7794   case X86::VMAXCPSrr:
7795   case X86::VMAXCPDYrr:
7796   case X86::VMAXCPSYrr:
7797   case X86::VMAXCPDZ128rr:
7798   case X86::VMAXCPSZ128rr:
7799   case X86::VMAXCPDZ256rr:
7800   case X86::VMAXCPSZ256rr:
7801   case X86::VMAXCPDZrr:
7802   case X86::VMAXCPSZrr:
7803   case X86::VMAXCSDrr:
7804   case X86::VMAXCSSrr:
7805   case X86::VMAXCSDZrr:
7806   case X86::VMAXCSSZrr:
7807   case X86::VMINCPDrr:
7808   case X86::VMINCPSrr:
7809   case X86::VMINCPDYrr:
7810   case X86::VMINCPSYrr:
7811   case X86::VMINCPDZ128rr:
7812   case X86::VMINCPSZ128rr:
7813   case X86::VMINCPDZ256rr:
7814   case X86::VMINCPSZ256rr:
7815   case X86::VMINCPDZrr:
7816   case X86::VMINCPSZrr:
7817   case X86::VMINCSDrr:
7818   case X86::VMINCSSrr:
7819   case X86::VMINCSDZrr:
7820   case X86::VMINCSSZrr:
7821     return true;
7822   case X86::ADDPDrr:
7823   case X86::ADDPSrr:
7824   case X86::ADDSDrr:
7825   case X86::ADDSSrr:
7826   case X86::MULPDrr:
7827   case X86::MULPSrr:
7828   case X86::MULSDrr:
7829   case X86::MULSSrr:
7830   case X86::VADDPDrr:
7831   case X86::VADDPSrr:
7832   case X86::VADDPDYrr:
7833   case X86::VADDPSYrr:
7834   case X86::VADDPDZ128rr:
7835   case X86::VADDPSZ128rr:
7836   case X86::VADDPDZ256rr:
7837   case X86::VADDPSZ256rr:
7838   case X86::VADDPDZrr:
7839   case X86::VADDPSZrr:
7840   case X86::VADDSDrr:
7841   case X86::VADDSSrr:
7842   case X86::VADDSDZrr:
7843   case X86::VADDSSZrr:
7844   case X86::VMULPDrr:
7845   case X86::VMULPSrr:
7846   case X86::VMULPDYrr:
7847   case X86::VMULPSYrr:
7848   case X86::VMULPDZ128rr:
7849   case X86::VMULPSZ128rr:
7850   case X86::VMULPDZ256rr:
7851   case X86::VMULPSZ256rr:
7852   case X86::VMULPDZrr:
7853   case X86::VMULPSZrr:
7854   case X86::VMULSDrr:
7855   case X86::VMULSSrr:
7856   case X86::VMULSDZrr:
7857   case X86::VMULSSZrr:
7858     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7859   default:
7860     return false;
7861   }
7862 }
7863 
7864 /// This is an architecture-specific helper function of reassociateOps.
7865 /// Set special operand attributes for new instructions after reassociation.
7866 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7867                                          MachineInstr &OldMI2,
7868                                          MachineInstr &NewMI1,
7869                                          MachineInstr &NewMI2) const {
7870   // Integer instructions define an implicit EFLAGS source register operand as
7871   // the third source (fourth total) operand.
7872   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7873     return;
7874 
7875   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7876          "Unexpected instruction type for reassociation");
7877 
7878   MachineOperand &OldOp1 = OldMI1.getOperand(3);
7879   MachineOperand &OldOp2 = OldMI2.getOperand(3);
7880   MachineOperand &NewOp1 = NewMI1.getOperand(3);
7881   MachineOperand &NewOp2 = NewMI2.getOperand(3);
7882 
7883   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7884          "Must have dead EFLAGS operand in reassociable instruction");
7885   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7886          "Must have dead EFLAGS operand in reassociable instruction");
7887 
7888   (void)OldOp1;
7889   (void)OldOp2;
7890 
7891   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7892          "Unexpected operand in reassociable instruction");
7893   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7894          "Unexpected operand in reassociable instruction");
7895 
7896   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7897   // of this pass or other passes. The EFLAGS operands must be dead in these new
7898   // instructions because the EFLAGS operands in the original instructions must
7899   // be dead in order for reassociation to occur.
7900   NewOp1.setIsDead();
7901   NewOp2.setIsDead();
7902 }
7903 
7904 std::pair<unsigned, unsigned>
7905 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7906   return std::make_pair(TF, 0u);
7907 }
7908 
7909 ArrayRef<std::pair<unsigned, const char *>>
7910 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7911   using namespace X86II;
7912   static const std::pair<unsigned, const char *> TargetFlags[] = {
7913       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7914       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7915       {MO_GOT, "x86-got"},
7916       {MO_GOTOFF, "x86-gotoff"},
7917       {MO_GOTPCREL, "x86-gotpcrel"},
7918       {MO_PLT, "x86-plt"},
7919       {MO_TLSGD, "x86-tlsgd"},
7920       {MO_TLSLD, "x86-tlsld"},
7921       {MO_TLSLDM, "x86-tlsldm"},
7922       {MO_GOTTPOFF, "x86-gottpoff"},
7923       {MO_INDNTPOFF, "x86-indntpoff"},
7924       {MO_TPOFF, "x86-tpoff"},
7925       {MO_DTPOFF, "x86-dtpoff"},
7926       {MO_NTPOFF, "x86-ntpoff"},
7927       {MO_GOTNTPOFF, "x86-gotntpoff"},
7928       {MO_DLLIMPORT, "x86-dllimport"},
7929       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7930       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7931       {MO_TLVP, "x86-tlvp"},
7932       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7933       {MO_SECREL, "x86-secrel"}};
7934   return makeArrayRef(TargetFlags);
7935 }
7936 
7937 namespace {
7938   /// Create Global Base Reg pass. This initializes the PIC
7939   /// global base register for x86-32.
7940   struct CGBR : public MachineFunctionPass {
7941     static char ID;
7942     CGBR() : MachineFunctionPass(ID) {}
7943 
7944     bool runOnMachineFunction(MachineFunction &MF) override {
7945       const X86TargetMachine *TM =
7946         static_cast<const X86TargetMachine *>(&MF.getTarget());
7947       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7948 
7949       // Don't do anything if this is 64-bit as 64-bit PIC
7950       // uses RIP relative addressing.
7951       if (STI.is64Bit())
7952         return false;
7953 
7954       // Only emit a global base reg in PIC mode.
7955       if (!TM->isPositionIndependent())
7956         return false;
7957 
7958       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7959       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7960 
7961       // If we didn't need a GlobalBaseReg, don't insert code.
7962       if (GlobalBaseReg == 0)
7963         return false;
7964 
7965       // Insert the set of GlobalBaseReg into the first MBB of the function
7966       MachineBasicBlock &FirstMBB = MF.front();
7967       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7968       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7969       MachineRegisterInfo &RegInfo = MF.getRegInfo();
7970       const X86InstrInfo *TII = STI.getInstrInfo();
7971 
7972       unsigned PC;
7973       if (STI.isPICStyleGOT())
7974         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7975       else
7976         PC = GlobalBaseReg;
7977 
7978       // Operand of MovePCtoStack is completely ignored by asm printer. It's
7979       // only used in JIT code emission as displacement to pc.
7980       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7981 
7982       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7983       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7984       if (STI.isPICStyleGOT()) {
7985         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7986         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7987           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7988                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
7989       }
7990 
7991       return true;
7992     }
7993 
7994     const char *getPassName() const override {
7995       return "X86 PIC Global Base Reg Initialization";
7996     }
7997 
7998     void getAnalysisUsage(AnalysisUsage &AU) const override {
7999       AU.setPreservesCFG();
8000       MachineFunctionPass::getAnalysisUsage(AU);
8001     }
8002   };
8003 }
8004 
8005 char CGBR::ID = 0;
8006 FunctionPass*
8007 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8008 
8009 namespace {
8010   struct LDTLSCleanup : public MachineFunctionPass {
8011     static char ID;
8012     LDTLSCleanup() : MachineFunctionPass(ID) {}
8013 
8014     bool runOnMachineFunction(MachineFunction &MF) override {
8015       if (skipFunction(*MF.getFunction()))
8016         return false;
8017 
8018       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8019       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8020         // No point folding accesses if there isn't at least two.
8021         return false;
8022       }
8023 
8024       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8025       return VisitNode(DT->getRootNode(), 0);
8026     }
8027 
8028     // Visit the dominator subtree rooted at Node in pre-order.
8029     // If TLSBaseAddrReg is non-null, then use that to replace any
8030     // TLS_base_addr instructions. Otherwise, create the register
8031     // when the first such instruction is seen, and then use it
8032     // as we encounter more instructions.
8033     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8034       MachineBasicBlock *BB = Node->getBlock();
8035       bool Changed = false;
8036 
8037       // Traverse the current block.
8038       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8039            ++I) {
8040         switch (I->getOpcode()) {
8041           case X86::TLS_base_addr32:
8042           case X86::TLS_base_addr64:
8043             if (TLSBaseAddrReg)
8044               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8045             else
8046               I = SetRegister(*I, &TLSBaseAddrReg);
8047             Changed = true;
8048             break;
8049           default:
8050             break;
8051         }
8052       }
8053 
8054       // Visit the children of this block in the dominator tree.
8055       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
8056            I != E; ++I) {
8057         Changed |= VisitNode(*I, TLSBaseAddrReg);
8058       }
8059 
8060       return Changed;
8061     }
8062 
8063     // Replace the TLS_base_addr instruction I with a copy from
8064     // TLSBaseAddrReg, returning the new instruction.
8065     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8066                                          unsigned TLSBaseAddrReg) {
8067       MachineFunction *MF = I.getParent()->getParent();
8068       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8069       const bool is64Bit = STI.is64Bit();
8070       const X86InstrInfo *TII = STI.getInstrInfo();
8071 
8072       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8073       MachineInstr *Copy =
8074           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8075                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8076               .addReg(TLSBaseAddrReg);
8077 
8078       // Erase the TLS_base_addr instruction.
8079       I.eraseFromParent();
8080 
8081       return Copy;
8082     }
8083 
8084     // Create a virtal register in *TLSBaseAddrReg, and populate it by
8085     // inserting a copy instruction after I. Returns the new instruction.
8086     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8087       MachineFunction *MF = I.getParent()->getParent();
8088       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8089       const bool is64Bit = STI.is64Bit();
8090       const X86InstrInfo *TII = STI.getInstrInfo();
8091 
8092       // Create a virtual register for the TLS base address.
8093       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8094       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8095                                                       ? &X86::GR64RegClass
8096                                                       : &X86::GR32RegClass);
8097 
8098       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
8099       MachineInstr *Next = I.getNextNode();
8100       MachineInstr *Copy =
8101           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8102                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8103               .addReg(is64Bit ? X86::RAX : X86::EAX);
8104 
8105       return Copy;
8106     }
8107 
8108     const char *getPassName() const override {
8109       return "Local Dynamic TLS Access Clean-up";
8110     }
8111 
8112     void getAnalysisUsage(AnalysisUsage &AU) const override {
8113       AU.setPreservesCFG();
8114       AU.addRequired<MachineDominatorTree>();
8115       MachineFunctionPass::getAnalysisUsage(AU);
8116     }
8117   };
8118 }
8119 
8120 char LDTLSCleanup::ID = 0;
8121 FunctionPass*
8122 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
8123