1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 x87 FPU instruction set, defining the 11// instructions, and properties of the instructions which are needed for code 12// generation, machine code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// FPStack specific DAG Nodes. 18//===----------------------------------------------------------------------===// 19 20def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, 21 SDTCisVT<1, f80>]>; 22def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, 23 SDTCisPtrTy<1>, 24 SDTCisVT<2, OtherVT>]>; 25def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, 26 SDTCisPtrTy<1>, 27 SDTCisVT<2, OtherVT>]>; 28def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, 29 SDTCisVT<2, OtherVT>]>; 30def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 31def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 32 33def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 34 35def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 36 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 37def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 38 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 39 SDNPMemOperand]>; 40def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 41 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 42def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 43 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 44 SDNPMemOperand]>; 45def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 46def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, 47 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 48def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, 49 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 50def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, 51 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 52def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 53 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 54 SDNPMemOperand]>; 55 56//===----------------------------------------------------------------------===// 57// FPStack pattern fragments 58//===----------------------------------------------------------------------===// 59 60def fpimm0 : FPImmLeaf<fAny, [{ 61 return Imm.isExactlyValue(+0.0); 62}]>; 63 64def fpimmneg0 : FPImmLeaf<fAny, [{ 65 return Imm.isExactlyValue(-0.0); 66}]>; 67 68def fpimm1 : FPImmLeaf<fAny, [{ 69 return Imm.isExactlyValue(+1.0); 70}]>; 71 72def fpimmneg1 : FPImmLeaf<fAny, [{ 73 return Imm.isExactlyValue(-1.0); 74}]>; 75 76// Some 'special' instructions - expanded after instruction selection. 77let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 79 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 81 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 83 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 85 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 87 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 89 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 91 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 93 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 95 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 96} 97 98// All FP Stack operations are represented with four instructions here. The 99// first three instructions, generated by the instruction selector, use "RFP32" 100// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 101// 64-bit or 80-bit floating point values. These sizes apply to the values, 102// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 103// copied to each other without losing information. These instructions are all 104// pseudo instructions and use the "_Fp" suffix. 105// In some cases there are additional variants with a mixture of different 106// register sizes. 107// The second instruction is defined with FPI, which is the actual instruction 108// emitted by the assembler. These use "RST" registers, although frequently 109// the actual register(s) used are implicit. These are always 80 bits. 110// The FP stackifier pass converts one to the other after register allocation 111// occurs. 112// 113// Note that the FpI instruction should have instruction selection info (e.g. 114// a pattern) and the FPI instruction should have emission info (e.g. opcode 115// encoding and asm printing info). 116 117// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 118// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 119// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 120// f80 instructions cannot use SSE and use neither of these. 121class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern, 122 InstrItinClass itin = NoItinerary> : 123 FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf32]>; 124class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern, 125 InstrItinClass itin = NoItinerary> : 126 FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf64]>; 127 128// Factoring for arithmetic. 129multiclass FPBinary_rr<SDNode OpNode> { 130// Register op register -> register 131// These are separated out because they have no reversed form. 132def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 133 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 134def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 135 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 136def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 137 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 138} 139// The FopST0 series are not included here because of the irregularities 140// in where the 'r' goes in assembly output. 141// These instructions cannot address 80-bit memory. 142multiclass FPBinary<SDNode OpNode, Format fp, string asmstring, 143 bit Forward = 1> { 144let mayLoad = 1, hasSideEffects = 1 in { 145// ST(0) = ST(0) + [mem] 146def _Fp32m : FpIf32<(outs RFP32:$dst), 147 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 148 [!if(Forward, 149 (set RFP32:$dst, 150 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 151 (set RFP32:$dst, 152 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 153def _Fp64m : FpIf64<(outs RFP64:$dst), 154 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 155 [!if(Forward, 156 (set RFP64:$dst, 157 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 158 (set RFP64:$dst, 159 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 160def _Fp64m32: FpIf64<(outs RFP64:$dst), 161 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 162 [!if(Forward, 163 (set RFP64:$dst, 164 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 165 (set RFP64:$dst, 166 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 167def _Fp80m32: FpI_<(outs RFP80:$dst), 168 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 169 [!if(Forward, 170 (set RFP80:$dst, 171 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 172 (set RFP80:$dst, 173 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 174def _Fp80m64: FpI_<(outs RFP80:$dst), 175 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 176 [!if(Forward, 177 (set RFP80:$dst, 178 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 179 (set RFP80:$dst, 180 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 181def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 182 !strconcat("f", asmstring, "{s}\t$src")>; 183def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 184 !strconcat("f", asmstring, "{l}\t$src")>; 185// ST(0) = ST(0) + [memint] 186def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 187 OneArgFPRW, 188 [!if(Forward, 189 (set RFP32:$dst, 190 (OpNode RFP32:$src1, (X86fild addr:$src2, i16))), 191 (set RFP32:$dst, 192 (OpNode (X86fild addr:$src2, i16), RFP32:$src1)))]>; 193def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 194 OneArgFPRW, 195 [!if(Forward, 196 (set RFP32:$dst, 197 (OpNode RFP32:$src1, (X86fild addr:$src2, i32))), 198 (set RFP32:$dst, 199 (OpNode (X86fild addr:$src2, i32), RFP32:$src1)))]>; 200def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 201 OneArgFPRW, 202 [!if(Forward, 203 (set RFP64:$dst, 204 (OpNode RFP64:$src1, (X86fild addr:$src2, i16))), 205 (set RFP64:$dst, 206 (OpNode (X86fild addr:$src2, i16), RFP64:$src1)))]>; 207def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 208 OneArgFPRW, 209 [!if(Forward, 210 (set RFP64:$dst, 211 (OpNode RFP64:$src1, (X86fild addr:$src2, i32))), 212 (set RFP64:$dst, 213 (OpNode (X86fild addr:$src2, i32), RFP64:$src1)))]>; 214def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 215 OneArgFPRW, 216 [!if(Forward, 217 (set RFP80:$dst, 218 (OpNode RFP80:$src1, (X86fild addr:$src2, i16))), 219 (set RFP80:$dst, 220 (OpNode (X86fild addr:$src2, i16), RFP80:$src1)))]>; 221def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 222 OneArgFPRW, 223 [!if(Forward, 224 (set RFP80:$dst, 225 (OpNode RFP80:$src1, (X86fild addr:$src2, i32))), 226 (set RFP80:$dst, 227 (OpNode (X86fild addr:$src2, i32), RFP80:$src1)))]>; 228def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 229 !strconcat("fi", asmstring, "{s}\t$src")>; 230def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 231 !strconcat("fi", asmstring, "{l}\t$src")>; 232} // mayLoad = 1, hasSideEffects = 1 233} 234 235let Defs = [FPSW] in { 236// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 237// resources. 238let hasNoSchedulingInfo = 1 in { 239defm ADD : FPBinary_rr<fadd>; 240defm SUB : FPBinary_rr<fsub>; 241defm MUL : FPBinary_rr<fmul>; 242defm DIV : FPBinary_rr<fdiv>; 243} 244 245// Sets the scheduling resources for the actual NAME#_F<size>m defintions. 246let SchedRW = [WriteFAddLd] in { 247defm ADD : FPBinary<fadd, MRM0m, "add">; 248defm SUB : FPBinary<fsub, MRM4m, "sub">; 249defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>; 250} 251 252let SchedRW = [WriteFMulLd] in { 253defm MUL : FPBinary<fmul, MRM1m, "mul">; 254} 255 256let SchedRW = [WriteFDivLd] in { 257defm DIV : FPBinary<fdiv, MRM6m, "div">; 258defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>; 259} 260} // Defs = [FPSW] 261 262class FPST0rInst<Format fp, string asm> 263 : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; 264class FPrST0Inst<Format fp, string asm> 265 : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; 266class FPrST0PInst<Format fp, string asm> 267 : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; 268 269// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 270// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 271// we have to put some 'r's in and take them out of weird places. 272let SchedRW = [WriteFAdd] in { 273def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">; 274def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">; 275def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">; 276def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">; 277def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">; 278def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">; 279def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">; 280def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; 281def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">; 282def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 283def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 284} // SchedRW 285let SchedRW = [WriteFMul] in { 286def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; 287def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; 288def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; 289} // SchedRW 290let SchedRW = [WriteFDiv] in { 291def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">; 292def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; 293def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">; 294def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">; 295def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; 296def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">; 297} // SchedRW 298 299// Unary operations. 300multiclass FPUnary<SDNode OpNode, Format fp, string asmstring, 301 InstrItinClass itin> { 302def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 303 [(set RFP32:$dst, (OpNode RFP32:$src))], itin>; 304def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 305 [(set RFP64:$dst, (OpNode RFP64:$src))], itin>; 306def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 307 [(set RFP80:$dst, (OpNode RFP80:$src))], itin>; 308def _F : FPI<0xD9, fp, (outs), (ins), asmstring, itin>; 309} 310 311let Defs = [FPSW] in { 312 313let SchedRW = [WriteVecLogic] in { 314defm CHS : FPUnary<fneg, MRM_E0, "fchs", IIC_FSIGN>; 315defm ABS : FPUnary<fabs, MRM_E1, "fabs", IIC_FSIGN>; 316} 317 318let SchedRW = [WriteFSqrt] in 319defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt", IIC_FSQRT>; 320 321let SchedRW = [WriteMicrocoded] in { 322defm SIN : FPUnary<fsin, MRM_FE, "fsin", IIC_FSINCOS>; 323defm COS : FPUnary<fcos, MRM_FF, "fcos", IIC_FSINCOS>; 324} 325 326let SchedRW = [WriteFAdd] in { 327let hasSideEffects = 0 in { 328def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 329def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 330def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 331} // hasSideEffects 332 333def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst", IIC_FCOMI>; 334} // SchedRW 335} // Defs = [FPSW] 336 337// Versions of FP instructions that take a single memory operand. Added for the 338// disassembler; remove as they are included with patterns elsewhere. 339let SchedRW = [WriteFAddLd] in { 340def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 341def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 342 343def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 344def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 345 346def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 347def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 348 349def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 350def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 351} // SchedRW 352 353let SchedRW = [WriteMicrocoded] in { 354def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 355def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; 356 357def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; 358def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; 359def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 360 361def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 362def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 363} // SchedRW 364 365// Floating point cmovs. 366class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern, 367 InstrItinClass itin> : 368 FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf32, HasCMov]>; 369class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern, 370 InstrItinClass itin> : 371 FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf64, HasCMov]>; 372 373multiclass FPCMov<PatLeaf cc> { 374 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 375 CondMovFP, 376 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 377 cc, EFLAGS))], IIC_FCMOV>; 378 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 379 CondMovFP, 380 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 381 cc, EFLAGS))], IIC_FCMOV>; 382 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 383 CondMovFP, 384 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 385 cc, EFLAGS))], IIC_FCMOV>, 386 Requires<[HasCMov]>; 387} 388 389let Defs = [FPSW] in { 390let SchedRW = [WriteFAdd] in { 391let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 392defm CMOVB : FPCMov<X86_COND_B>; 393defm CMOVBE : FPCMov<X86_COND_BE>; 394defm CMOVE : FPCMov<X86_COND_E>; 395defm CMOVP : FPCMov<X86_COND_P>; 396defm CMOVNB : FPCMov<X86_COND_AE>; 397defm CMOVNBE: FPCMov<X86_COND_A>; 398defm CMOVNE : FPCMov<X86_COND_NE>; 399defm CMOVNP : FPCMov<X86_COND_NP>; 400} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 401 402let Predicates = [HasCMov] in { 403// These are not factored because there's no clean way to pass DA/DB. 404def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op), 405 "fcmovb\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>; 406def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op), 407 "fcmovbe\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>; 408def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op), 409 "fcmove\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>; 410def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op), 411 "fcmovu\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>; 412def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op), 413 "fcmovnb\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>; 414def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op), 415 "fcmovnbe\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>; 416def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op), 417 "fcmovne\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>; 418def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op), 419 "fcmovnu\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>; 420} // Predicates = [HasCMov] 421} // SchedRW 422 423// Floating point loads & stores. 424let SchedRW = [WriteLoad] in { 425let canFoldAsLoad = 1 in { 426def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 427 [(set RFP32:$dst, (loadf32 addr:$src))]>; 428let isReMaterializable = 1 in 429 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 430 [(set RFP64:$dst, (loadf64 addr:$src))]>; 431def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 432 [(set RFP80:$dst, (loadf80 addr:$src))]>; 433} // canFoldAsLoad 434def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 435 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 436def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 437 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 438def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 439 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 440def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 441 [(set RFP32:$dst, (X86fild addr:$src, i16))]>; 442def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 443 [(set RFP32:$dst, (X86fild addr:$src, i32))]>; 444def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 445 [(set RFP32:$dst, (X86fild addr:$src, i64))]>; 446def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 447 [(set RFP64:$dst, (X86fild addr:$src, i16))]>; 448def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 449 [(set RFP64:$dst, (X86fild addr:$src, i32))]>; 450def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 451 [(set RFP64:$dst, (X86fild addr:$src, i64))]>; 452def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 453 [(set RFP80:$dst, (X86fild addr:$src, i16))]>; 454def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 455 [(set RFP80:$dst, (X86fild addr:$src, i32))]>; 456def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 457 [(set RFP80:$dst, (X86fild addr:$src, i64))]>; 458} // SchedRW 459 460let SchedRW = [WriteStore] in { 461def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 462 [(store RFP32:$src, addr:$op)]>; 463def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 464 [(truncstoref32 RFP64:$src, addr:$op)]>; 465def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 466 [(store RFP64:$src, addr:$op)]>; 467def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 468 [(truncstoref32 RFP80:$src, addr:$op)]>; 469def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 470 [(truncstoref64 RFP80:$src, addr:$op)]>; 471// FST does not support 80-bit memory target; FSTP must be used. 472 473let mayStore = 1, hasSideEffects = 0 in { 474def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 475def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 476def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 477def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 478def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 479} // mayStore 480 481def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 482 [(store RFP80:$src, addr:$op)]>; 483 484let mayStore = 1, hasSideEffects = 0 in { 485def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 486def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 487def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 488def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 489def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 490def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 491def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 492def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 493def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 494} // mayStore 495} // SchedRW 496 497let mayLoad = 1, SchedRW = [WriteLoad] in { 498def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src", 499 IIC_FLD>; 500def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src", 501 IIC_FLD>; 502def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src", 503 IIC_FLD80>; 504def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src", 505 IIC_FILD>; 506def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src", 507 IIC_FILD>; 508def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src", 509 IIC_FILD>; 510} 511let mayStore = 1, SchedRW = [WriteStore] in { 512def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst", 513 IIC_FST>; 514def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst", 515 IIC_FST>; 516def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst", 517 IIC_FST>; 518def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst", 519 IIC_FST>; 520def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst", 521 IIC_FST80>; 522def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst", 523 IIC_FIST>; 524def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst", 525 IIC_FIST>; 526def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst", 527 IIC_FIST>; 528def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst", 529 IIC_FIST>; 530def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst", 531 IIC_FIST>; 532} 533 534// FISTTP requires SSE3 even though it's a FPStack op. 535let Predicates = [HasSSE3], SchedRW = [WriteStore] in { 536def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 537 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 538def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 539 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 540def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 541 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 542def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 543 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 544def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 545 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 546def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 547 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 548def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 549 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 550def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 551 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 552def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 553 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 554} // Predicates = [HasSSE3] 555 556let mayStore = 1, SchedRW = [WriteStore] in { 557def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst", 558 IIC_FST>; 559def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst", 560 IIC_FST>; 561def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), 562 "fisttp{ll}\t$dst", IIC_FST>; 563} 564 565// FP Stack manipulation instructions. 566let SchedRW = [WriteMove] in { 567def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>; 568def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>; 569def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>; 570def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>; 571} 572 573// Floating point constant loads. 574let isReMaterializable = 1, SchedRW = [WriteZero] in { 575def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 576 [(set RFP32:$dst, fpimm0)]>; 577def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 578 [(set RFP32:$dst, fpimm1)]>; 579def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 580 [(set RFP64:$dst, fpimm0)]>; 581def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 582 [(set RFP64:$dst, fpimm1)]>; 583def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 584 [(set RFP80:$dst, fpimm0)]>; 585def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 586 [(set RFP80:$dst, fpimm1)]>; 587} 588 589let SchedRW = [WriteZero] in { 590def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz", IIC_FLDZ>; 591def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1", IIC_FIST>; 592} 593 594// Floating point compares. 595let SchedRW = [WriteFAdd] in { 596def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 597 [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; 598def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 599 [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; 600def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 601 [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; 602} // SchedRW 603} // Defs = [FPSW] 604 605let SchedRW = [WriteFAdd] in { 606// CC = ST(0) cmp ST(i) 607let Defs = [EFLAGS, FPSW] in { 608def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 609 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; 610def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 611 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; 612def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 613 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; 614} 615 616let Defs = [FPSW], Uses = [ST0] in { 617def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 618 (outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>; 619def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 620 (outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>; 621def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 622 (outs), (ins), "fucompp", IIC_FUCOM>; 623} 624 625let Defs = [EFLAGS, FPSW], Uses = [ST0] in { 626def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 627 (outs), (ins RST:$reg), "fucomi\t$reg", IIC_FUCOMI>; 628def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 629 (outs), (ins RST:$reg), "fucompi\t$reg", IIC_FUCOMI>; 630} 631 632let Defs = [EFLAGS, FPSW] in { 633def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), 634 "fcomi\t$reg", IIC_FCOMI>; 635def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), 636 "fcompi\t$reg", IIC_FCOMI>; 637} 638} // SchedRW 639 640// Floating point flag ops. 641let SchedRW = [WriteALU] in { 642let Defs = [AX], Uses = [FPSW] in 643def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 644 (outs), (ins), "fnstsw\t{%ax|ax}", 645 [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>; 646let Defs = [FPSW] in 647def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 648 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 649 [(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>; 650} // SchedRW 651let Defs = [FPSW], mayLoad = 1 in 652def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 653 (outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>, 654 Sched<[WriteLoad]>; 655 656// FPU control instructions 657let SchedRW = [WriteMicrocoded] in { 658let Defs = [FPSW] in { 659def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>; 660def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), 661 "ffree\t$reg", IIC_FFREE>; 662def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg), 663 "ffreep\t$reg", IIC_FFREE>; 664 665// Clear exceptions 666def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; 667} // Defs = [FPSW] 668} // SchedRW 669 670// Operandless floating-point instructions for the disassembler. 671let SchedRW = [WriteMicrocoded] in { 672def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>; 673 674let Defs = [FPSW] in { 675def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>; 676def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>; 677def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>; 678def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>; 679def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>; 680def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>; 681def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>; 682def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>; 683def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>; 684def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>; 685def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>; 686def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>; 687def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>; 688def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>; 689def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>; 690def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>; 691def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>; 692def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>; 693def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>; 694def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>; 695def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>; 696} // Defs = [FPSW] 697 698def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaque512mem:$dst), 699 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)], IIC_FXSAVE>, TB, 700 Requires<[HasFXSR]>; 701def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaque512mem:$dst), 702 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)], 703 IIC_FXSAVE>, TB, Requires<[HasFXSR, In64BitMode]>; 704def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 705 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)], IIC_FXRSTOR>, 706 TB, Requires<[HasFXSR]>; 707def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 708 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)], 709 IIC_FXRSTOR>, TB, Requires<[HasFXSR, In64BitMode]>; 710} // SchedRW 711 712//===----------------------------------------------------------------------===// 713// Non-Instruction Patterns 714//===----------------------------------------------------------------------===// 715 716// Required for RET of f32 / f64 / f80 values. 717def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; 718def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; 719def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; 720 721// Required for CALL which return f32 / f64 / f80 values. 722def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; 723def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, 724 RFP64:$src)>; 725def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; 726def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, 727 RFP80:$src)>; 728def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, 729 RFP80:$src)>; 730def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, 731 RFP80:$src)>; 732 733// Floating point constant -0.0 and -1.0 734def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 735def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 736def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 737def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 738def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 739def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 740 741// Used to conv. i64 to f64 since there isn't a SSE version. 742def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; 743 744// FP extensions map onto simple pseudo-value conversions if they are to/from 745// the FP stack. 746def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 747 Requires<[FPStackf32]>; 748def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 749 Requires<[FPStackf32]>; 750def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 751 Requires<[FPStackf64]>; 752 753// FP truncations map onto simple pseudo-value conversions if they are to/from 754// the FP stack. We have validated that only value-preserving truncations make 755// it through isel. 756def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 757 Requires<[FPStackf32]>; 758def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 759 Requires<[FPStackf32]>; 760def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 761 Requires<[FPStackf64]>; 762