1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86InstComments.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "llvm/CodeGen/MachineValueType.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/raw_ostream.h"
21 
22 using namespace llvm;
23 
24 #define CASE_SSE_INS_COMMON(Inst, src)            \
25   case X86::Inst##src:
26 
27 #define CASE_AVX_INS_COMMON(Inst, Suffix, src)    \
28   case X86::V##Inst##Suffix##src:
29 
30 #define CASE_MASK_INS_COMMON(Inst, Suffix, src)   \
31   case X86::V##Inst##Suffix##src##k:
32 
33 #define CASE_MASKZ_INS_COMMON(Inst, Suffix, src)  \
34   case X86::V##Inst##Suffix##src##kz:
35 
36 #define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
37   CASE_AVX_INS_COMMON(Inst, Suffix, src)          \
38   CASE_MASK_INS_COMMON(Inst, Suffix, src)         \
39   CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
40 
41 #define CASE_MOVDUP(Inst, src)                    \
42   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
43   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
44   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
45   CASE_AVX_INS_COMMON(Inst, , r##src)             \
46   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
47   CASE_SSE_INS_COMMON(Inst, r##src)
48 
49 #define CASE_MASK_MOVDUP(Inst, src)               \
50   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
51   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
52   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
53 
54 #define CASE_MASKZ_MOVDUP(Inst, src)              \
55   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
56   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
57   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
58 
59 #define CASE_PMOVZX(Inst, src)                    \
60   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
61   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
62   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
63   CASE_AVX_INS_COMMON(Inst, , r##src)             \
64   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
65   CASE_SSE_INS_COMMON(Inst, r##src)
66 
67 #define CASE_MASK_PMOVZX(Inst, src)               \
68   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
69   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
70   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
71 
72 #define CASE_MASKZ_PMOVZX(Inst, src)              \
73   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
74   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
75   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
76 
77 #define CASE_UNPCK(Inst, src)                     \
78   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
79   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
80   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
81   CASE_AVX_INS_COMMON(Inst, , r##src)             \
82   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
83   CASE_SSE_INS_COMMON(Inst, r##src)
84 
85 #define CASE_MASK_UNPCK(Inst, src)                \
86   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
87   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
88   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
89 
90 #define CASE_MASKZ_UNPCK(Inst, src)               \
91   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
92   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
93   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
94 
95 #define CASE_SHUF(Inst, suf)                      \
96   CASE_AVX512_INS_COMMON(Inst, Z, suf)            \
97   CASE_AVX512_INS_COMMON(Inst, Z256, suf)         \
98   CASE_AVX512_INS_COMMON(Inst, Z128, suf)         \
99   CASE_AVX_INS_COMMON(Inst, , suf)                \
100   CASE_AVX_INS_COMMON(Inst, Y, suf)               \
101   CASE_SSE_INS_COMMON(Inst, suf)
102 
103 #define CASE_MASK_SHUF(Inst, src)                 \
104   CASE_MASK_INS_COMMON(Inst, Z, r##src##i)        \
105   CASE_MASK_INS_COMMON(Inst, Z256, r##src##i)     \
106   CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
107 
108 #define CASE_MASKZ_SHUF(Inst, src)                \
109   CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i)       \
110   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i)    \
111   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
112 
113 #define CASE_VPERMILPI(Inst, src)                 \
114   CASE_AVX512_INS_COMMON(Inst, Z, src##i)         \
115   CASE_AVX512_INS_COMMON(Inst, Z256, src##i)      \
116   CASE_AVX512_INS_COMMON(Inst, Z128, src##i)      \
117   CASE_AVX_INS_COMMON(Inst, , src##i)             \
118   CASE_AVX_INS_COMMON(Inst, Y, src##i)
119 
120 #define CASE_MASK_VPERMILPI(Inst, src)            \
121   CASE_MASK_INS_COMMON(Inst, Z, src##i)           \
122   CASE_MASK_INS_COMMON(Inst, Z256, src##i)        \
123   CASE_MASK_INS_COMMON(Inst, Z128, src##i)
124 
125 #define CASE_MASKZ_VPERMILPI(Inst, src)           \
126   CASE_MASKZ_INS_COMMON(Inst, Z, src##i)          \
127   CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)       \
128   CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
129 
130 #define CASE_VPERM(Inst, src)                     \
131   CASE_AVX512_INS_COMMON(Inst, Z, src##i)         \
132   CASE_AVX512_INS_COMMON(Inst, Z256, src##i)      \
133   CASE_AVX_INS_COMMON(Inst, Y, src##i)
134 
135 #define CASE_MASK_VPERM(Inst, src)                \
136   CASE_MASK_INS_COMMON(Inst, Z, src##i)           \
137   CASE_MASK_INS_COMMON(Inst, Z256, src##i)
138 
139 #define CASE_MASKZ_VPERM(Inst, src)               \
140   CASE_MASKZ_INS_COMMON(Inst, Z, src##i)          \
141   CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
142 
143 #define CASE_VSHUF(Inst, src)                          \
144   CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i)    \
145   CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i)    \
146   CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
147   CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
148 
149 #define CASE_MASK_VSHUF(Inst, src)                    \
150   CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i)     \
151   CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i)     \
152   CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i)  \
153   CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
154 
155 #define CASE_MASKZ_VSHUF(Inst, src)                   \
156   CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i)    \
157   CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i)    \
158   CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
159   CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
160 
161 static unsigned getVectorRegSize(unsigned RegNo) {
162   if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
163     return 512;
164   if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
165     return 256;
166   if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
167     return 128;
168   if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
169     return 64;
170 
171   llvm_unreachable("Unknown vector reg!");
172 }
173 
174 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
175                                  unsigned OperandIndex) {
176   unsigned OpReg = MI->getOperand(OperandIndex).getReg();
177   return MVT::getVectorVT(ScalarVT,
178                           getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
179 }
180 
181 /// \brief Extracts the dst type for a given zero extension instruction.
182 static MVT getZeroExtensionResultType(const MCInst *MI) {
183   switch (MI->getOpcode()) {
184   default:
185     llvm_unreachable("Unknown zero extension instruction");
186   // zero extension to i16
187   CASE_PMOVZX(PMOVZXBW, m)
188   CASE_PMOVZX(PMOVZXBW, r)
189     return getRegOperandVectorVT(MI, MVT::i16, 0);
190   // zero extension to i32
191   CASE_PMOVZX(PMOVZXBD, m)
192   CASE_PMOVZX(PMOVZXBD, r)
193   CASE_PMOVZX(PMOVZXWD, m)
194   CASE_PMOVZX(PMOVZXWD, r)
195     return getRegOperandVectorVT(MI, MVT::i32, 0);
196   // zero extension to i64
197   CASE_PMOVZX(PMOVZXBQ, m)
198   CASE_PMOVZX(PMOVZXBQ, r)
199   CASE_PMOVZX(PMOVZXWQ, m)
200   CASE_PMOVZX(PMOVZXWQ, r)
201   CASE_PMOVZX(PMOVZXDQ, m)
202   CASE_PMOVZX(PMOVZXDQ, r)
203     return getRegOperandVectorVT(MI, MVT::i64, 0);
204   }
205 }
206 
207 /// Wraps the destination register name with AVX512 mask/maskz filtering.
208 static void printMasking(raw_ostream &OS, const MCInst *MI,
209                          const char *(*getRegName)(unsigned)) {
210   bool MaskWithZero = false;
211   const char *MaskRegName = nullptr;
212 
213   switch (MI->getOpcode()) {
214   default:
215     return;
216   CASE_MASKZ_MOVDUP(MOVDDUP, m)
217   CASE_MASKZ_MOVDUP(MOVDDUP, r)
218   CASE_MASKZ_MOVDUP(MOVSHDUP, m)
219   CASE_MASKZ_MOVDUP(MOVSHDUP, r)
220   CASE_MASKZ_MOVDUP(MOVSLDUP, m)
221   CASE_MASKZ_MOVDUP(MOVSLDUP, r)
222   CASE_MASKZ_PMOVZX(PMOVZXBD, m)
223   CASE_MASKZ_PMOVZX(PMOVZXBD, r)
224   CASE_MASKZ_PMOVZX(PMOVZXBQ, m)
225   CASE_MASKZ_PMOVZX(PMOVZXBQ, r)
226   CASE_MASKZ_PMOVZX(PMOVZXBW, m)
227   CASE_MASKZ_PMOVZX(PMOVZXBW, r)
228   CASE_MASKZ_PMOVZX(PMOVZXDQ, m)
229   CASE_MASKZ_PMOVZX(PMOVZXDQ, r)
230   CASE_MASKZ_PMOVZX(PMOVZXWD, m)
231   CASE_MASKZ_PMOVZX(PMOVZXWD, r)
232   CASE_MASKZ_PMOVZX(PMOVZXWQ, m)
233   CASE_MASKZ_PMOVZX(PMOVZXWQ, r)
234   CASE_MASKZ_UNPCK(PUNPCKHBW, m)
235   CASE_MASKZ_UNPCK(PUNPCKHBW, r)
236   CASE_MASKZ_UNPCK(PUNPCKHWD, m)
237   CASE_MASKZ_UNPCK(PUNPCKHWD, r)
238   CASE_MASKZ_UNPCK(PUNPCKHDQ, m)
239   CASE_MASKZ_UNPCK(PUNPCKHDQ, r)
240   CASE_MASKZ_UNPCK(PUNPCKLBW, m)
241   CASE_MASKZ_UNPCK(PUNPCKLBW, r)
242   CASE_MASKZ_UNPCK(PUNPCKLWD, m)
243   CASE_MASKZ_UNPCK(PUNPCKLWD, r)
244   CASE_MASKZ_UNPCK(PUNPCKLDQ, m)
245   CASE_MASKZ_UNPCK(PUNPCKLDQ, r)
246   CASE_MASKZ_UNPCK(UNPCKHPD, m)
247   CASE_MASKZ_UNPCK(UNPCKHPD, r)
248   CASE_MASKZ_UNPCK(UNPCKHPS, m)
249   CASE_MASKZ_UNPCK(UNPCKHPS, r)
250   CASE_MASKZ_UNPCK(UNPCKLPD, m)
251   CASE_MASKZ_UNPCK(UNPCKLPD, r)
252   CASE_MASKZ_UNPCK(UNPCKLPS, m)
253   CASE_MASKZ_UNPCK(UNPCKLPS, r)
254   CASE_MASKZ_SHUF(PALIGNR, r)
255   CASE_MASKZ_SHUF(PALIGNR, m)
256   CASE_MASKZ_SHUF(ALIGNQ, r)
257   CASE_MASKZ_SHUF(ALIGNQ, m)
258   CASE_MASKZ_SHUF(ALIGND, r)
259   CASE_MASKZ_SHUF(ALIGND, m)
260   CASE_MASKZ_SHUF(SHUFPD, m)
261   CASE_MASKZ_SHUF(SHUFPD, r)
262   CASE_MASKZ_SHUF(SHUFPS, m)
263   CASE_MASKZ_SHUF(SHUFPS, r)
264   CASE_MASKZ_VPERMILPI(PERMILPD, m)
265   CASE_MASKZ_VPERMILPI(PERMILPD, r)
266   CASE_MASKZ_VPERMILPI(PERMILPS, m)
267   CASE_MASKZ_VPERMILPI(PERMILPS, r)
268   CASE_MASKZ_VPERMILPI(PSHUFD, m)
269   CASE_MASKZ_VPERMILPI(PSHUFD, r)
270   CASE_MASKZ_VPERMILPI(PSHUFHW, m)
271   CASE_MASKZ_VPERMILPI(PSHUFHW, r)
272   CASE_MASKZ_VPERMILPI(PSHUFLW, m)
273   CASE_MASKZ_VPERMILPI(PSHUFLW, r)
274   CASE_MASKZ_VPERM(PERMPD, m)
275   CASE_MASKZ_VPERM(PERMPD, r)
276   CASE_MASKZ_VPERM(PERMQ, m)
277   CASE_MASKZ_VPERM(PERMQ, r)
278   CASE_MASKZ_VSHUF(64X2, m)
279   CASE_MASKZ_VSHUF(64X2, r)
280   CASE_MASKZ_VSHUF(32X4, m)
281   CASE_MASKZ_VSHUF(32X4, r)
282   CASE_MASKZ_INS_COMMON(BROADCASTF64X2, Z128, rm)
283   CASE_MASKZ_INS_COMMON(BROADCASTI64X2, Z128, rm)
284   CASE_MASKZ_INS_COMMON(BROADCASTF64X2, , rm)
285   CASE_MASKZ_INS_COMMON(BROADCASTI64X2, , rm)
286   CASE_MASKZ_INS_COMMON(BROADCASTF64X4, , rm)
287   CASE_MASKZ_INS_COMMON(BROADCASTI64X4, , rm)
288   CASE_MASKZ_INS_COMMON(BROADCASTF32X4, Z256, rm)
289   CASE_MASKZ_INS_COMMON(BROADCASTI32X4, Z256, rm)
290   CASE_MASKZ_INS_COMMON(BROADCASTF32X4, , rm)
291   CASE_MASKZ_INS_COMMON(BROADCASTI32X4, , rm)
292   CASE_MASKZ_INS_COMMON(BROADCASTF32X8, , rm)
293   CASE_MASKZ_INS_COMMON(BROADCASTI32X8, , rm)
294   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z128, r)
295   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z128, m)
296   CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, r)
297   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, r)
298   CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, m)
299   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, m)
300   CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, r)
301   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, r)
302   CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, m)
303   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, m)
304     MaskWithZero = true;
305     MaskRegName = getRegName(MI->getOperand(1).getReg());
306     break;
307   CASE_MASK_MOVDUP(MOVDDUP, m)
308   CASE_MASK_MOVDUP(MOVDDUP, r)
309   CASE_MASK_MOVDUP(MOVSHDUP, m)
310   CASE_MASK_MOVDUP(MOVSHDUP, r)
311   CASE_MASK_MOVDUP(MOVSLDUP, m)
312   CASE_MASK_MOVDUP(MOVSLDUP, r)
313   CASE_MASK_PMOVZX(PMOVZXBD, m)
314   CASE_MASK_PMOVZX(PMOVZXBD, r)
315   CASE_MASK_PMOVZX(PMOVZXBQ, m)
316   CASE_MASK_PMOVZX(PMOVZXBQ, r)
317   CASE_MASK_PMOVZX(PMOVZXBW, m)
318   CASE_MASK_PMOVZX(PMOVZXBW, r)
319   CASE_MASK_PMOVZX(PMOVZXDQ, m)
320   CASE_MASK_PMOVZX(PMOVZXDQ, r)
321   CASE_MASK_PMOVZX(PMOVZXWD, m)
322   CASE_MASK_PMOVZX(PMOVZXWD, r)
323   CASE_MASK_PMOVZX(PMOVZXWQ, m)
324   CASE_MASK_PMOVZX(PMOVZXWQ, r)
325   CASE_MASK_UNPCK(PUNPCKHBW, m)
326   CASE_MASK_UNPCK(PUNPCKHBW, r)
327   CASE_MASK_UNPCK(PUNPCKHWD, m)
328   CASE_MASK_UNPCK(PUNPCKHWD, r)
329   CASE_MASK_UNPCK(PUNPCKHDQ, m)
330   CASE_MASK_UNPCK(PUNPCKHDQ, r)
331   CASE_MASK_UNPCK(PUNPCKLBW, m)
332   CASE_MASK_UNPCK(PUNPCKLBW, r)
333   CASE_MASK_UNPCK(PUNPCKLWD, m)
334   CASE_MASK_UNPCK(PUNPCKLWD, r)
335   CASE_MASK_UNPCK(PUNPCKLDQ, m)
336   CASE_MASK_UNPCK(PUNPCKLDQ, r)
337   CASE_MASK_UNPCK(UNPCKHPD, m)
338   CASE_MASK_UNPCK(UNPCKHPD, r)
339   CASE_MASK_UNPCK(UNPCKHPS, m)
340   CASE_MASK_UNPCK(UNPCKHPS, r)
341   CASE_MASK_UNPCK(UNPCKLPD, m)
342   CASE_MASK_UNPCK(UNPCKLPD, r)
343   CASE_MASK_UNPCK(UNPCKLPS, m)
344   CASE_MASK_UNPCK(UNPCKLPS, r)
345   CASE_MASK_SHUF(PALIGNR, r)
346   CASE_MASK_SHUF(PALIGNR, m)
347   CASE_MASK_SHUF(ALIGNQ, r)
348   CASE_MASK_SHUF(ALIGNQ, m)
349   CASE_MASK_SHUF(ALIGND, r)
350   CASE_MASK_SHUF(ALIGND, m)
351   CASE_MASK_SHUF(SHUFPD, m)
352   CASE_MASK_SHUF(SHUFPD, r)
353   CASE_MASK_SHUF(SHUFPS, m)
354   CASE_MASK_SHUF(SHUFPS, r)
355   CASE_MASK_VPERMILPI(PERMILPD, m)
356   CASE_MASK_VPERMILPI(PERMILPD, r)
357   CASE_MASK_VPERMILPI(PERMILPS, m)
358   CASE_MASK_VPERMILPI(PERMILPS, r)
359   CASE_MASK_VPERMILPI(PSHUFD, m)
360   CASE_MASK_VPERMILPI(PSHUFD, r)
361   CASE_MASK_VPERMILPI(PSHUFHW, m)
362   CASE_MASK_VPERMILPI(PSHUFHW, r)
363   CASE_MASK_VPERMILPI(PSHUFLW, m)
364   CASE_MASK_VPERMILPI(PSHUFLW, r)
365   CASE_MASK_VPERM(PERMPD, m)
366   CASE_MASK_VPERM(PERMPD, r)
367   CASE_MASK_VPERM(PERMQ, m)
368   CASE_MASK_VPERM(PERMQ, r)
369   CASE_MASK_VSHUF(64X2, m)
370   CASE_MASK_VSHUF(64X2, r)
371   CASE_MASK_VSHUF(32X4, m)
372   CASE_MASK_VSHUF(32X4, r)
373   CASE_MASK_INS_COMMON(BROADCASTF64X2, Z128, rm)
374   CASE_MASK_INS_COMMON(BROADCASTI64X2, Z128, rm)
375   CASE_MASK_INS_COMMON(BROADCASTF64X2, , rm)
376   CASE_MASK_INS_COMMON(BROADCASTI64X2, , rm)
377   CASE_MASK_INS_COMMON(BROADCASTF64X4, , rm)
378   CASE_MASK_INS_COMMON(BROADCASTI64X4, , rm)
379   CASE_MASK_INS_COMMON(BROADCASTF32X4, Z256, rm)
380   CASE_MASK_INS_COMMON(BROADCASTI32X4, Z256, rm)
381   CASE_MASK_INS_COMMON(BROADCASTF32X4, , rm)
382   CASE_MASK_INS_COMMON(BROADCASTI32X4, , rm)
383   CASE_MASK_INS_COMMON(BROADCASTF32X8, , rm)
384   CASE_MASK_INS_COMMON(BROADCASTI32X8, , rm)
385   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z128, r)
386   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z128, m)
387   CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, r)
388   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, r)
389   CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, m)
390   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, m)
391   CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, r)
392   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, r)
393   CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, m)
394   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, m)
395     MaskRegName = getRegName(MI->getOperand(2).getReg());
396     break;
397   }
398 
399   // MASK: zmmX {%kY}
400   OS << " {%" << MaskRegName << "}";
401 
402   // MASKZ: zmmX {%kY} {z}
403   if (MaskWithZero)
404     OS << " {z}";
405 }
406 
407 //===----------------------------------------------------------------------===//
408 // Top Level Entrypoint
409 //===----------------------------------------------------------------------===//
410 
411 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
412 /// newline terminated strings to the specified string if desired.  This
413 /// information is shown in disassembly dumps when verbose assembly is enabled.
414 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
415                                   const char *(*getRegName)(unsigned)) {
416   // If this is a shuffle operation, the switch should fill in this state.
417   SmallVector<int, 8> ShuffleMask;
418   const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
419   unsigned NumOperands = MI->getNumOperands();
420   bool RegForm = false;
421 
422   switch (MI->getOpcode()) {
423   default:
424     // Not an instruction for which we can decode comments.
425     return false;
426 
427   case X86::BLENDPDrri:
428   case X86::VBLENDPDrri:
429   case X86::VBLENDPDYrri:
430     Src2Name = getRegName(MI->getOperand(2).getReg());
431     LLVM_FALLTHROUGH;
432   case X86::BLENDPDrmi:
433   case X86::VBLENDPDrmi:
434   case X86::VBLENDPDYrmi:
435     if (MI->getOperand(NumOperands - 1).isImm())
436       DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
437                       MI->getOperand(NumOperands - 1).getImm(),
438                       ShuffleMask);
439     Src1Name = getRegName(MI->getOperand(1).getReg());
440     DestName = getRegName(MI->getOperand(0).getReg());
441     break;
442 
443   case X86::BLENDPSrri:
444   case X86::VBLENDPSrri:
445   case X86::VBLENDPSYrri:
446     Src2Name = getRegName(MI->getOperand(2).getReg());
447     LLVM_FALLTHROUGH;
448   case X86::BLENDPSrmi:
449   case X86::VBLENDPSrmi:
450   case X86::VBLENDPSYrmi:
451     if (MI->getOperand(NumOperands - 1).isImm())
452       DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
453                       MI->getOperand(NumOperands - 1).getImm(),
454                       ShuffleMask);
455     Src1Name = getRegName(MI->getOperand(1).getReg());
456     DestName = getRegName(MI->getOperand(0).getReg());
457     break;
458 
459   case X86::PBLENDWrri:
460   case X86::VPBLENDWrri:
461   case X86::VPBLENDWYrri:
462     Src2Name = getRegName(MI->getOperand(2).getReg());
463     LLVM_FALLTHROUGH;
464   case X86::PBLENDWrmi:
465   case X86::VPBLENDWrmi:
466   case X86::VPBLENDWYrmi:
467     if (MI->getOperand(NumOperands - 1).isImm())
468       DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
469                       MI->getOperand(NumOperands - 1).getImm(),
470                       ShuffleMask);
471     Src1Name = getRegName(MI->getOperand(1).getReg());
472     DestName = getRegName(MI->getOperand(0).getReg());
473     break;
474 
475   case X86::VPBLENDDrri:
476   case X86::VPBLENDDYrri:
477     Src2Name = getRegName(MI->getOperand(2).getReg());
478     LLVM_FALLTHROUGH;
479   case X86::VPBLENDDrmi:
480   case X86::VPBLENDDYrmi:
481     if (MI->getOperand(NumOperands - 1).isImm())
482       DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
483                       MI->getOperand(NumOperands - 1).getImm(),
484                       ShuffleMask);
485     Src1Name = getRegName(MI->getOperand(1).getReg());
486     DestName = getRegName(MI->getOperand(0).getReg());
487     break;
488 
489   case X86::INSERTPSrr:
490   case X86::VINSERTPSrr:
491   case X86::VINSERTPSZrr:
492     Src2Name = getRegName(MI->getOperand(2).getReg());
493     LLVM_FALLTHROUGH;
494   case X86::INSERTPSrm:
495   case X86::VINSERTPSrm:
496   case X86::VINSERTPSZrm:
497     DestName = getRegName(MI->getOperand(0).getReg());
498     Src1Name = getRegName(MI->getOperand(1).getReg());
499     if (MI->getOperand(NumOperands - 1).isImm())
500       DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
501                          ShuffleMask);
502     break;
503 
504   case X86::MOVLHPSrr:
505   case X86::VMOVLHPSrr:
506   case X86::VMOVLHPSZrr:
507     Src2Name = getRegName(MI->getOperand(2).getReg());
508     Src1Name = getRegName(MI->getOperand(1).getReg());
509     DestName = getRegName(MI->getOperand(0).getReg());
510     DecodeMOVLHPSMask(2, ShuffleMask);
511     break;
512 
513   case X86::MOVHLPSrr:
514   case X86::VMOVHLPSrr:
515   case X86::VMOVHLPSZrr:
516     Src2Name = getRegName(MI->getOperand(2).getReg());
517     Src1Name = getRegName(MI->getOperand(1).getReg());
518     DestName = getRegName(MI->getOperand(0).getReg());
519     DecodeMOVHLPSMask(2, ShuffleMask);
520     break;
521 
522   case X86::MOVHPDrm:
523   case X86::VMOVHPDrm:
524   case X86::VMOVHPDZ128rm:
525     Src1Name = getRegName(MI->getOperand(1).getReg());
526     DestName = getRegName(MI->getOperand(0).getReg());
527     DecodeInsertElementMask(MVT::v2f64, 1, 1, ShuffleMask);
528     break;
529 
530   case X86::MOVHPSrm:
531   case X86::VMOVHPSrm:
532   case X86::VMOVHPSZ128rm:
533     Src1Name = getRegName(MI->getOperand(1).getReg());
534     DestName = getRegName(MI->getOperand(0).getReg());
535     DecodeInsertElementMask(MVT::v4f32, 2, 2, ShuffleMask);
536     break;
537 
538   case X86::MOVLPDrm:
539   case X86::VMOVLPDrm:
540   case X86::VMOVLPDZ128rm:
541     Src1Name = getRegName(MI->getOperand(1).getReg());
542     DestName = getRegName(MI->getOperand(0).getReg());
543     DecodeInsertElementMask(MVT::v2f64, 0, 1, ShuffleMask);
544     break;
545 
546   case X86::MOVLPSrm:
547   case X86::VMOVLPSrm:
548   case X86::VMOVLPSZ128rm:
549     Src1Name = getRegName(MI->getOperand(1).getReg());
550     DestName = getRegName(MI->getOperand(0).getReg());
551     DecodeInsertElementMask(MVT::v4f32, 0, 2, ShuffleMask);
552     break;
553 
554   CASE_MOVDUP(MOVSLDUP, r)
555     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
556     LLVM_FALLTHROUGH;
557 
558   CASE_MOVDUP(MOVSLDUP, m)
559     DestName = getRegName(MI->getOperand(0).getReg());
560     DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
561     break;
562 
563   CASE_MOVDUP(MOVSHDUP, r)
564     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
565     LLVM_FALLTHROUGH;
566 
567   CASE_MOVDUP(MOVSHDUP, m)
568     DestName = getRegName(MI->getOperand(0).getReg());
569     DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
570     break;
571 
572   CASE_MOVDUP(MOVDDUP, r)
573     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
574     LLVM_FALLTHROUGH;
575 
576   CASE_MOVDUP(MOVDDUP, m)
577     DestName = getRegName(MI->getOperand(0).getReg());
578     DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
579     break;
580 
581   case X86::PSLLDQri:
582   case X86::VPSLLDQri:
583   case X86::VPSLLDQYri:
584   case X86::VPSLLDQZ128rr:
585   case X86::VPSLLDQZ256rr:
586   case X86::VPSLLDQZrr:
587     Src1Name = getRegName(MI->getOperand(1).getReg());
588     LLVM_FALLTHROUGH;
589   case X86::VPSLLDQZ128rm:
590   case X86::VPSLLDQZ256rm:
591   case X86::VPSLLDQZrm:
592     DestName = getRegName(MI->getOperand(0).getReg());
593     if (MI->getOperand(NumOperands - 1).isImm())
594       DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
595                        MI->getOperand(NumOperands - 1).getImm(),
596                        ShuffleMask);
597     break;
598 
599   case X86::PSRLDQri:
600   case X86::VPSRLDQri:
601   case X86::VPSRLDQYri:
602   case X86::VPSRLDQZ128rr:
603   case X86::VPSRLDQZ256rr:
604   case X86::VPSRLDQZrr:
605     Src1Name = getRegName(MI->getOperand(1).getReg());
606     LLVM_FALLTHROUGH;
607   case X86::VPSRLDQZ128rm:
608   case X86::VPSRLDQZ256rm:
609   case X86::VPSRLDQZrm:
610     DestName = getRegName(MI->getOperand(0).getReg());
611     if (MI->getOperand(NumOperands - 1).isImm())
612       DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
613                        MI->getOperand(NumOperands - 1).getImm(),
614                        ShuffleMask);
615     break;
616 
617   CASE_SHUF(PALIGNR, rri)
618     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
619     RegForm = true;
620     LLVM_FALLTHROUGH;
621 
622   CASE_SHUF(PALIGNR, rmi)
623     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
624     DestName = getRegName(MI->getOperand(0).getReg());
625     if (MI->getOperand(NumOperands - 1).isImm())
626       DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
627                         MI->getOperand(NumOperands - 1).getImm(),
628                         ShuffleMask);
629     break;
630 
631   CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
632   CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
633   CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
634     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
635     RegForm = true;
636     LLVM_FALLTHROUGH;
637 
638   CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
639   CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
640   CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
641     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
642     DestName = getRegName(MI->getOperand(0).getReg());
643     if (MI->getOperand(NumOperands - 1).isImm())
644       DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i64, 0),
645                        MI->getOperand(NumOperands - 1).getImm(),
646                        ShuffleMask);
647     break;
648 
649   CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
650   CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
651   CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
652     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
653     RegForm = true;
654     LLVM_FALLTHROUGH;
655 
656   CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
657   CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
658   CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
659     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
660     DestName = getRegName(MI->getOperand(0).getReg());
661     if (MI->getOperand(NumOperands - 1).isImm())
662       DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i32, 0),
663                        MI->getOperand(NumOperands - 1).getImm(),
664                        ShuffleMask);
665     break;
666 
667   CASE_SHUF(PSHUFD, ri)
668     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
669     LLVM_FALLTHROUGH;
670 
671   CASE_SHUF(PSHUFD, mi)
672     DestName = getRegName(MI->getOperand(0).getReg());
673     if (MI->getOperand(NumOperands - 1).isImm())
674       DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
675                       MI->getOperand(NumOperands - 1).getImm(),
676                       ShuffleMask);
677     break;
678 
679   CASE_SHUF(PSHUFHW, ri)
680     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
681     LLVM_FALLTHROUGH;
682 
683   CASE_SHUF(PSHUFHW, mi)
684     DestName = getRegName(MI->getOperand(0).getReg());
685     if (MI->getOperand(NumOperands - 1).isImm())
686       DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
687                         MI->getOperand(NumOperands - 1).getImm(),
688                         ShuffleMask);
689     break;
690 
691   CASE_SHUF(PSHUFLW, ri)
692     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
693     LLVM_FALLTHROUGH;
694 
695   CASE_SHUF(PSHUFLW, mi)
696     DestName = getRegName(MI->getOperand(0).getReg());
697     if (MI->getOperand(NumOperands - 1).isImm())
698       DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
699                         MI->getOperand(NumOperands - 1).getImm(),
700                         ShuffleMask);
701     break;
702 
703   case X86::MMX_PSHUFWri:
704     Src1Name = getRegName(MI->getOperand(1).getReg());
705     LLVM_FALLTHROUGH;
706 
707   case X86::MMX_PSHUFWmi:
708     DestName = getRegName(MI->getOperand(0).getReg());
709     if (MI->getOperand(NumOperands - 1).isImm())
710       DecodePSHUFMask(MVT::v4i16,
711                       MI->getOperand(NumOperands - 1).getImm(),
712                       ShuffleMask);
713     break;
714 
715   case X86::PSWAPDrr:
716     Src1Name = getRegName(MI->getOperand(1).getReg());
717     LLVM_FALLTHROUGH;
718 
719   case X86::PSWAPDrm:
720     DestName = getRegName(MI->getOperand(0).getReg());
721     DecodePSWAPMask(MVT::v2i32, ShuffleMask);
722     break;
723 
724   CASE_UNPCK(PUNPCKHBW, r)
725   case X86::MMX_PUNPCKHBWirr:
726     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
727     RegForm = true;
728     LLVM_FALLTHROUGH;
729 
730   CASE_UNPCK(PUNPCKHBW, m)
731   case X86::MMX_PUNPCKHBWirm:
732     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
733     DestName = getRegName(MI->getOperand(0).getReg());
734     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
735     break;
736 
737   CASE_UNPCK(PUNPCKHWD, r)
738   case X86::MMX_PUNPCKHWDirr:
739     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
740     RegForm = true;
741     LLVM_FALLTHROUGH;
742 
743   CASE_UNPCK(PUNPCKHWD, m)
744   case X86::MMX_PUNPCKHWDirm:
745     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
746     DestName = getRegName(MI->getOperand(0).getReg());
747     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
748     break;
749 
750   CASE_UNPCK(PUNPCKHDQ, r)
751   case X86::MMX_PUNPCKHDQirr:
752     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
753     RegForm = true;
754     LLVM_FALLTHROUGH;
755 
756   CASE_UNPCK(PUNPCKHDQ, m)
757   case X86::MMX_PUNPCKHDQirm:
758     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
759     DestName = getRegName(MI->getOperand(0).getReg());
760     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
761     break;
762 
763   CASE_UNPCK(PUNPCKHQDQ, r)
764     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
765     RegForm = true;
766     LLVM_FALLTHROUGH;
767 
768   CASE_UNPCK(PUNPCKHQDQ, m)
769     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
770     DestName = getRegName(MI->getOperand(0).getReg());
771     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
772     break;
773 
774   CASE_UNPCK(PUNPCKLBW, r)
775   case X86::MMX_PUNPCKLBWirr:
776     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
777     RegForm = true;
778     LLVM_FALLTHROUGH;
779 
780   CASE_UNPCK(PUNPCKLBW, m)
781   case X86::MMX_PUNPCKLBWirm:
782     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
783     DestName = getRegName(MI->getOperand(0).getReg());
784     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
785     break;
786 
787   CASE_UNPCK(PUNPCKLWD, r)
788   case X86::MMX_PUNPCKLWDirr:
789     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
790     RegForm = true;
791     LLVM_FALLTHROUGH;
792 
793   CASE_UNPCK(PUNPCKLWD, m)
794   case X86::MMX_PUNPCKLWDirm:
795     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
796     DestName = getRegName(MI->getOperand(0).getReg());
797     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
798     break;
799 
800   CASE_UNPCK(PUNPCKLDQ, r)
801   case X86::MMX_PUNPCKLDQirr:
802     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
803     RegForm = true;
804     LLVM_FALLTHROUGH;
805 
806   CASE_UNPCK(PUNPCKLDQ, m)
807   case X86::MMX_PUNPCKLDQirm:
808     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
809     DestName = getRegName(MI->getOperand(0).getReg());
810     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
811     break;
812 
813   CASE_UNPCK(PUNPCKLQDQ, r)
814     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
815     RegForm = true;
816     LLVM_FALLTHROUGH;
817 
818   CASE_UNPCK(PUNPCKLQDQ, m)
819     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
820     DestName = getRegName(MI->getOperand(0).getReg());
821     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
822     break;
823 
824   CASE_SHUF(SHUFPD, rri)
825     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
826     RegForm = true;
827     LLVM_FALLTHROUGH;
828 
829   CASE_SHUF(SHUFPD, rmi)
830     if (MI->getOperand(NumOperands - 1).isImm())
831       DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
832                       MI->getOperand(NumOperands - 1).getImm(),
833                       ShuffleMask);
834     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
835     DestName = getRegName(MI->getOperand(0).getReg());
836     break;
837 
838   CASE_SHUF(SHUFPS, rri)
839     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
840     RegForm = true;
841     LLVM_FALLTHROUGH;
842 
843   CASE_SHUF(SHUFPS, rmi)
844     if (MI->getOperand(NumOperands - 1).isImm())
845       DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
846                       MI->getOperand(NumOperands - 1).getImm(),
847                       ShuffleMask);
848     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
849     DestName = getRegName(MI->getOperand(0).getReg());
850     break;
851 
852   CASE_VSHUF(64X2, r)
853     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
854     RegForm = true;
855     LLVM_FALLTHROUGH;
856 
857   CASE_VSHUF(64X2, m)
858     decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0),
859                               MI->getOperand(NumOperands - 1).getImm(),
860                               ShuffleMask);
861     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
862     DestName = getRegName(MI->getOperand(0).getReg());
863     break;
864 
865   CASE_VSHUF(32X4, r)
866     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
867     RegForm = true;
868     LLVM_FALLTHROUGH;
869 
870   CASE_VSHUF(32X4, m)
871     decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0),
872                               MI->getOperand(NumOperands - 1).getImm(),
873                               ShuffleMask);
874     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
875     DestName = getRegName(MI->getOperand(0).getReg());
876     break;
877 
878   CASE_UNPCK(UNPCKLPD, r)
879     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
880     RegForm = true;
881     LLVM_FALLTHROUGH;
882 
883   CASE_UNPCK(UNPCKLPD, m)
884     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
885     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
886     DestName = getRegName(MI->getOperand(0).getReg());
887     break;
888 
889   CASE_UNPCK(UNPCKLPS, r)
890     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
891     RegForm = true;
892     LLVM_FALLTHROUGH;
893 
894   CASE_UNPCK(UNPCKLPS, m)
895     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
896     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
897     DestName = getRegName(MI->getOperand(0).getReg());
898     break;
899 
900   CASE_UNPCK(UNPCKHPD, r)
901     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
902     RegForm = true;
903     LLVM_FALLTHROUGH;
904 
905   CASE_UNPCK(UNPCKHPD, m)
906     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
907     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
908     DestName = getRegName(MI->getOperand(0).getReg());
909     break;
910 
911   CASE_UNPCK(UNPCKHPS, r)
912     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
913     RegForm = true;
914     LLVM_FALLTHROUGH;
915 
916   CASE_UNPCK(UNPCKHPS, m)
917     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
918     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
919     DestName = getRegName(MI->getOperand(0).getReg());
920     break;
921 
922   CASE_VPERMILPI(PERMILPS, r)
923     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
924     LLVM_FALLTHROUGH;
925 
926   CASE_VPERMILPI(PERMILPS, m)
927     if (MI->getOperand(NumOperands - 1).isImm())
928       DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
929                       MI->getOperand(NumOperands - 1).getImm(),
930                       ShuffleMask);
931     DestName = getRegName(MI->getOperand(0).getReg());
932     break;
933 
934   CASE_VPERMILPI(PERMILPD, r)
935     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
936     LLVM_FALLTHROUGH;
937 
938   CASE_VPERMILPI(PERMILPD, m)
939     if (MI->getOperand(NumOperands - 1).isImm())
940       DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
941                       MI->getOperand(NumOperands - 1).getImm(),
942                       ShuffleMask);
943     DestName = getRegName(MI->getOperand(0).getReg());
944     break;
945 
946   case X86::VPERM2F128rr:
947   case X86::VPERM2I128rr:
948     Src2Name = getRegName(MI->getOperand(2).getReg());
949     LLVM_FALLTHROUGH;
950 
951   case X86::VPERM2F128rm:
952   case X86::VPERM2I128rm:
953     // For instruction comments purpose, assume the 256-bit vector is v4i64.
954     if (MI->getOperand(NumOperands - 1).isImm())
955       DecodeVPERM2X128Mask(MVT::v4i64,
956                            MI->getOperand(NumOperands - 1).getImm(),
957                            ShuffleMask);
958     Src1Name = getRegName(MI->getOperand(1).getReg());
959     DestName = getRegName(MI->getOperand(0).getReg());
960     break;
961 
962   CASE_VPERM(PERMPD, r)
963     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
964     LLVM_FALLTHROUGH;
965 
966   CASE_VPERM(PERMPD, m)
967     if (MI->getOperand(NumOperands - 1).isImm())
968       DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0),
969                       MI->getOperand(NumOperands - 1).getImm(),
970                       ShuffleMask);
971     DestName = getRegName(MI->getOperand(0).getReg());
972     break;
973 
974   CASE_VPERM(PERMQ, r)
975     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
976     LLVM_FALLTHROUGH;
977 
978   CASE_VPERM(PERMQ, m)
979     if (MI->getOperand(NumOperands - 1).isImm())
980       DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0),
981                       MI->getOperand(NumOperands - 1).getImm(),
982                       ShuffleMask);
983     DestName = getRegName(MI->getOperand(0).getReg());
984     break;
985 
986   case X86::MOVSDrr:
987   case X86::VMOVSDrr:
988   case X86::VMOVSDZrr:
989     Src2Name = getRegName(MI->getOperand(2).getReg());
990     Src1Name = getRegName(MI->getOperand(1).getReg());
991     LLVM_FALLTHROUGH;
992 
993   case X86::MOVSDrm:
994   case X86::VMOVSDrm:
995   case X86::VMOVSDZrm:
996     DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
997     DestName = getRegName(MI->getOperand(0).getReg());
998     break;
999 
1000   case X86::MOVSSrr:
1001   case X86::VMOVSSrr:
1002   case X86::VMOVSSZrr:
1003     Src2Name = getRegName(MI->getOperand(2).getReg());
1004     Src1Name = getRegName(MI->getOperand(1).getReg());
1005     LLVM_FALLTHROUGH;
1006 
1007   case X86::MOVSSrm:
1008   case X86::VMOVSSrm:
1009   case X86::VMOVSSZrm:
1010     DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
1011     DestName = getRegName(MI->getOperand(0).getReg());
1012     break;
1013 
1014   case X86::MOVPQI2QIrr:
1015   case X86::MOVZPQILo2PQIrr:
1016   case X86::VMOVPQI2QIrr:
1017   case X86::VMOVZPQILo2PQIrr:
1018   case X86::VMOVZPQILo2PQIZrr:
1019     Src1Name = getRegName(MI->getOperand(1).getReg());
1020     LLVM_FALLTHROUGH;
1021 
1022   case X86::MOVQI2PQIrm:
1023   case X86::VMOVQI2PQIrm:
1024   case X86::VMOVQI2PQIZrm:
1025     DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
1026     DestName = getRegName(MI->getOperand(0).getReg());
1027     break;
1028 
1029   case X86::MOVDI2PDIrm:
1030   case X86::VMOVDI2PDIrm:
1031   case X86::VMOVDI2PDIZrm:
1032     DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
1033     DestName = getRegName(MI->getOperand(0).getReg());
1034     break;
1035 
1036   case X86::EXTRQI:
1037     if (MI->getOperand(2).isImm() &&
1038         MI->getOperand(3).isImm())
1039       DecodeEXTRQIMask(MVT::v16i8, MI->getOperand(2).getImm(),
1040                        MI->getOperand(3).getImm(),
1041                        ShuffleMask);
1042 
1043     DestName = getRegName(MI->getOperand(0).getReg());
1044     Src1Name = getRegName(MI->getOperand(1).getReg());
1045     break;
1046 
1047   case X86::INSERTQI:
1048     if (MI->getOperand(3).isImm() &&
1049         MI->getOperand(4).isImm())
1050       DecodeINSERTQIMask(MVT::v16i8, MI->getOperand(3).getImm(),
1051                          MI->getOperand(4).getImm(),
1052                          ShuffleMask);
1053 
1054     DestName = getRegName(MI->getOperand(0).getReg());
1055     Src1Name = getRegName(MI->getOperand(1).getReg());
1056     Src2Name = getRegName(MI->getOperand(2).getReg());
1057     break;
1058 
1059   case X86::VBROADCASTF128:
1060   case X86::VBROADCASTI128:
1061   CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
1062   CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
1063     DecodeSubVectorBroadcast(MVT::v4f64, MVT::v2f64, ShuffleMask);
1064     DestName = getRegName(MI->getOperand(0).getReg());
1065     break;
1066   CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm)
1067   CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm)
1068     DecodeSubVectorBroadcast(MVT::v8f64, MVT::v2f64, ShuffleMask);
1069     DestName = getRegName(MI->getOperand(0).getReg());
1070     break;
1071   CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm)
1072   CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm)
1073     DecodeSubVectorBroadcast(MVT::v8f64, MVT::v4f64, ShuffleMask);
1074     DestName = getRegName(MI->getOperand(0).getReg());
1075     break;
1076   CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1077   CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1078     DecodeSubVectorBroadcast(MVT::v8f32, MVT::v4f32, ShuffleMask);
1079     DestName = getRegName(MI->getOperand(0).getReg());
1080     break;
1081   CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm)
1082   CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm)
1083     DecodeSubVectorBroadcast(MVT::v16f32, MVT::v4f32, ShuffleMask);
1084     DestName = getRegName(MI->getOperand(0).getReg());
1085     break;
1086   CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm)
1087   CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm)
1088     DecodeSubVectorBroadcast(MVT::v16f32, MVT::v8f32, ShuffleMask);
1089     DestName = getRegName(MI->getOperand(0).getReg());
1090     break;
1091   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, r)
1092     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1093     LLVM_FALLTHROUGH;
1094   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, m)
1095     DecodeSubVectorBroadcast(MVT::v4f32, MVT::v2f32, ShuffleMask);
1096     DestName = getRegName(MI->getOperand(0).getReg());
1097     break;
1098   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r)
1099   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r)
1100     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1101     LLVM_FALLTHROUGH;
1102   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m)
1103   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m)
1104     DecodeSubVectorBroadcast(MVT::v8f32, MVT::v2f32, ShuffleMask);
1105     DestName = getRegName(MI->getOperand(0).getReg());
1106     break;
1107   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r)
1108   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r)
1109     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1110     LLVM_FALLTHROUGH;
1111   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m)
1112   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m)
1113     DecodeSubVectorBroadcast(MVT::v16f32, MVT::v2f32, ShuffleMask);
1114     DestName = getRegName(MI->getOperand(0).getReg());
1115     break;
1116 
1117   CASE_PMOVZX(PMOVZXBW, r)
1118   CASE_PMOVZX(PMOVZXBD, r)
1119   CASE_PMOVZX(PMOVZXBQ, r)
1120     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1121     LLVM_FALLTHROUGH;
1122 
1123   CASE_PMOVZX(PMOVZXBW, m)
1124   CASE_PMOVZX(PMOVZXBD, m)
1125   CASE_PMOVZX(PMOVZXBQ, m)
1126     DecodeZeroExtendMask(MVT::i8, getZeroExtensionResultType(MI), ShuffleMask);
1127     DestName = getRegName(MI->getOperand(0).getReg());
1128     break;
1129 
1130   CASE_PMOVZX(PMOVZXWD, r)
1131   CASE_PMOVZX(PMOVZXWQ, r)
1132     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1133     LLVM_FALLTHROUGH;
1134 
1135   CASE_PMOVZX(PMOVZXWD, m)
1136   CASE_PMOVZX(PMOVZXWQ, m)
1137     DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask);
1138     DestName = getRegName(MI->getOperand(0).getReg());
1139     break;
1140 
1141   CASE_PMOVZX(PMOVZXDQ, r)
1142     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1143     LLVM_FALLTHROUGH;
1144 
1145   CASE_PMOVZX(PMOVZXDQ, m)
1146     DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask);
1147     DestName = getRegName(MI->getOperand(0).getReg());
1148     break;
1149   }
1150 
1151   // The only comments we decode are shuffles, so give up if we were unable to
1152   // decode a shuffle mask.
1153   if (ShuffleMask.empty())
1154     return false;
1155 
1156   if (!DestName) DestName = Src1Name;
1157   if (DestName) {
1158     OS << DestName;
1159     printMasking(OS, MI, getRegName);
1160   } else
1161     OS << "mem";
1162 
1163   OS << " = ";
1164 
1165   // If the two sources are the same, canonicalize the input elements to be
1166   // from the first src so that we get larger element spans.
1167   if (Src1Name == Src2Name) {
1168     for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1169       if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
1170           ShuffleMask[i] >= (int)e)   // From second mask.
1171         ShuffleMask[i] -= e;
1172     }
1173   }
1174 
1175   // The shuffle mask specifies which elements of the src1/src2 fill in the
1176   // destination, with a few sentinel values.  Loop through and print them
1177   // out.
1178   for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1179     if (i != 0)
1180       OS << ',';
1181     if (ShuffleMask[i] == SM_SentinelZero) {
1182       OS << "zero";
1183       continue;
1184     }
1185 
1186     // Otherwise, it must come from src1 or src2.  Print the span of elements
1187     // that comes from this src.
1188     bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1189     const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1190     OS << (SrcName ? SrcName : "mem") << '[';
1191     bool IsFirst = true;
1192     while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1193            (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1194       if (!IsFirst)
1195         OS << ',';
1196       else
1197         IsFirst = false;
1198       if (ShuffleMask[i] == SM_SentinelUndef)
1199         OS << "u";
1200       else
1201         OS << ShuffleMask[i] % ShuffleMask.size();
1202       ++i;
1203     }
1204     OS << ']';
1205     --i; // For loop increments element #.
1206   }
1207 
1208   // We successfully added a comment to this instruction.
1209   return true;
1210 }
1211