1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This defines functionality used to emit comments about X86 instructions to 11 // an output stream for -fverbose-asm. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86InstComments.h" 16 #include "MCTargetDesc/X86MCTargetDesc.h" 17 #include "Utils/X86ShuffleDecode.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/CodeGen/MachineValueType.h" 20 #include "llvm/Support/raw_ostream.h" 21 22 using namespace llvm; 23 24 static unsigned getVectorRegSize(unsigned RegNo) { 25 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31) 26 return 512; 27 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31) 28 return 256; 29 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31) 30 return 128; 31 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) 32 return 64; 33 34 llvm_unreachable("Unknown vector reg!"); 35 } 36 37 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT, 38 unsigned OperandIndex) { 39 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); 40 return MVT::getVectorVT(ScalarVT, 41 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits()); 42 } 43 44 /// \brief Extracts the src/dst types for a given zero extension instruction. 45 /// \note While the number of elements in DstVT type correct, the 46 /// number in the SrcVT type is expanded to fill the src xmm register and the 47 /// upper elements may not be included in the dst xmm/ymm register. 48 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { 49 switch (MI->getOpcode()) { 50 default: 51 llvm_unreachable("Unknown zero extension instruction"); 52 // i8 zero extension 53 case X86::PMOVZXBWrm: 54 case X86::PMOVZXBWrr: 55 case X86::VPMOVZXBWrm: 56 case X86::VPMOVZXBWrr: 57 SrcVT = MVT::v16i8; 58 DstVT = MVT::v8i16; 59 break; 60 case X86::VPMOVZXBWYrm: 61 case X86::VPMOVZXBWYrr: 62 SrcVT = MVT::v16i8; 63 DstVT = MVT::v16i16; 64 break; 65 case X86::PMOVZXBDrm: 66 case X86::PMOVZXBDrr: 67 case X86::VPMOVZXBDrm: 68 case X86::VPMOVZXBDrr: 69 SrcVT = MVT::v16i8; 70 DstVT = MVT::v4i32; 71 break; 72 case X86::VPMOVZXBDYrm: 73 case X86::VPMOVZXBDYrr: 74 SrcVT = MVT::v16i8; 75 DstVT = MVT::v8i32; 76 break; 77 case X86::PMOVZXBQrm: 78 case X86::PMOVZXBQrr: 79 case X86::VPMOVZXBQrm: 80 case X86::VPMOVZXBQrr: 81 SrcVT = MVT::v16i8; 82 DstVT = MVT::v2i64; 83 break; 84 case X86::VPMOVZXBQYrm: 85 case X86::VPMOVZXBQYrr: 86 SrcVT = MVT::v16i8; 87 DstVT = MVT::v4i64; 88 break; 89 // i16 zero extension 90 case X86::PMOVZXWDrm: 91 case X86::PMOVZXWDrr: 92 case X86::VPMOVZXWDrm: 93 case X86::VPMOVZXWDrr: 94 SrcVT = MVT::v8i16; 95 DstVT = MVT::v4i32; 96 break; 97 case X86::VPMOVZXWDYrm: 98 case X86::VPMOVZXWDYrr: 99 SrcVT = MVT::v8i16; 100 DstVT = MVT::v8i32; 101 break; 102 case X86::PMOVZXWQrm: 103 case X86::PMOVZXWQrr: 104 case X86::VPMOVZXWQrm: 105 case X86::VPMOVZXWQrr: 106 SrcVT = MVT::v8i16; 107 DstVT = MVT::v2i64; 108 break; 109 case X86::VPMOVZXWQYrm: 110 case X86::VPMOVZXWQYrr: 111 SrcVT = MVT::v8i16; 112 DstVT = MVT::v4i64; 113 break; 114 // i32 zero extension 115 case X86::PMOVZXDQrm: 116 case X86::PMOVZXDQrr: 117 case X86::VPMOVZXDQrm: 118 case X86::VPMOVZXDQrr: 119 SrcVT = MVT::v4i32; 120 DstVT = MVT::v2i64; 121 break; 122 case X86::VPMOVZXDQYrm: 123 case X86::VPMOVZXDQYrr: 124 SrcVT = MVT::v4i32; 125 DstVT = MVT::v4i64; 126 break; 127 } 128 } 129 130 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \ 131 case X86::V##Inst##Suffix##src: \ 132 case X86::V##Inst##Suffix##src##k: \ 133 case X86::V##Inst##Suffix##src##kz: 134 135 #define CASE_SSE_INS_COMMON(Inst, src) \ 136 case X86::Inst##src: 137 138 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \ 139 case X86::V##Inst##Suffix##src: 140 141 #define CASE_MOVDUP(Inst, src) \ 142 CASE_MASK_INS_COMMON(Inst, Z, r##src) \ 143 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ 144 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \ 145 CASE_AVX_INS_COMMON(Inst, , r##src) \ 146 CASE_AVX_INS_COMMON(Inst, Y, r##src) \ 147 CASE_SSE_INS_COMMON(Inst, r##src) \ 148 149 #define CASE_UNPCK(Inst, src) \ 150 CASE_MASK_INS_COMMON(Inst, Z, r##src) \ 151 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \ 152 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \ 153 CASE_AVX_INS_COMMON(Inst, , r##src) \ 154 CASE_AVX_INS_COMMON(Inst, Y, r##src) \ 155 CASE_SSE_INS_COMMON(Inst, r##src) \ 156 157 #define CASE_SHUF(Inst, src) \ 158 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \ 159 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \ 160 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) \ 161 CASE_AVX_INS_COMMON(Inst, , r##src##i) \ 162 CASE_AVX_INS_COMMON(Inst, Y, r##src##i) \ 163 CASE_SSE_INS_COMMON(Inst, r##src##i) \ 164 165 #define CASE_VPERM(Inst, src) \ 166 CASE_MASK_INS_COMMON(Inst, Z, src##i) \ 167 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \ 168 CASE_MASK_INS_COMMON(Inst, Z128, src##i) \ 169 CASE_AVX_INS_COMMON(Inst, , src##i) \ 170 CASE_AVX_INS_COMMON(Inst, Y, src##i) \ 171 172 #define CASE_VSHUF(Inst, src) \ 173 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \ 174 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \ 175 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \ 176 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \ 177 178 /// \brief Extracts the types and if it has memory operand for a given 179 /// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction. 180 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) { 181 HasMemOp = false; 182 switch (MI->getOpcode()) { 183 default: 184 llvm_unreachable("Unknown VSHUF64x2 family instructions."); 185 break; 186 CASE_VSHUF(64X2, m) 187 HasMemOp = true; // FALL THROUGH. 188 CASE_VSHUF(64X2, r) 189 VT = getRegOperandVectorVT(MI, MVT::i64, 0); 190 break; 191 CASE_VSHUF(32X4, m) 192 HasMemOp = true; // FALL THROUGH. 193 CASE_VSHUF(32X4, r) 194 VT = getRegOperandVectorVT(MI, MVT::i32, 0); 195 break; 196 } 197 } 198 199 //===----------------------------------------------------------------------===// 200 // Top Level Entrypoint 201 //===----------------------------------------------------------------------===// 202 203 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints 204 /// newline terminated strings to the specified string if desired. This 205 /// information is shown in disassembly dumps when verbose assembly is enabled. 206 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, 207 const char *(*getRegName)(unsigned)) { 208 // If this is a shuffle operation, the switch should fill in this state. 209 SmallVector<int, 8> ShuffleMask; 210 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr; 211 212 switch (MI->getOpcode()) { 213 default: 214 // Not an instruction for which we can decode comments. 215 return false; 216 217 case X86::BLENDPDrri: 218 case X86::VBLENDPDrri: 219 case X86::VBLENDPDYrri: 220 Src2Name = getRegName(MI->getOperand(2).getReg()); 221 // FALL THROUGH. 222 case X86::BLENDPDrmi: 223 case X86::VBLENDPDrmi: 224 case X86::VBLENDPDYrmi: 225 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 226 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0), 227 MI->getOperand(MI->getNumOperands() - 1).getImm(), 228 ShuffleMask); 229 Src1Name = getRegName(MI->getOperand(1).getReg()); 230 DestName = getRegName(MI->getOperand(0).getReg()); 231 break; 232 233 case X86::BLENDPSrri: 234 case X86::VBLENDPSrri: 235 case X86::VBLENDPSYrri: 236 Src2Name = getRegName(MI->getOperand(2).getReg()); 237 // FALL THROUGH. 238 case X86::BLENDPSrmi: 239 case X86::VBLENDPSrmi: 240 case X86::VBLENDPSYrmi: 241 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 242 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0), 243 MI->getOperand(MI->getNumOperands() - 1).getImm(), 244 ShuffleMask); 245 Src1Name = getRegName(MI->getOperand(1).getReg()); 246 DestName = getRegName(MI->getOperand(0).getReg()); 247 break; 248 249 case X86::PBLENDWrri: 250 case X86::VPBLENDWrri: 251 case X86::VPBLENDWYrri: 252 Src2Name = getRegName(MI->getOperand(2).getReg()); 253 // FALL THROUGH. 254 case X86::PBLENDWrmi: 255 case X86::VPBLENDWrmi: 256 case X86::VPBLENDWYrmi: 257 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 258 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0), 259 MI->getOperand(MI->getNumOperands() - 1).getImm(), 260 ShuffleMask); 261 Src1Name = getRegName(MI->getOperand(1).getReg()); 262 DestName = getRegName(MI->getOperand(0).getReg()); 263 break; 264 265 case X86::VPBLENDDrri: 266 case X86::VPBLENDDYrri: 267 Src2Name = getRegName(MI->getOperand(2).getReg()); 268 // FALL THROUGH. 269 case X86::VPBLENDDrmi: 270 case X86::VPBLENDDYrmi: 271 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 272 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0), 273 MI->getOperand(MI->getNumOperands() - 1).getImm(), 274 ShuffleMask); 275 Src1Name = getRegName(MI->getOperand(1).getReg()); 276 DestName = getRegName(MI->getOperand(0).getReg()); 277 break; 278 279 case X86::INSERTPSrr: 280 case X86::VINSERTPSrr: 281 Src2Name = getRegName(MI->getOperand(2).getReg()); 282 // FALL THROUGH. 283 case X86::INSERTPSrm: 284 case X86::VINSERTPSrm: 285 DestName = getRegName(MI->getOperand(0).getReg()); 286 Src1Name = getRegName(MI->getOperand(1).getReg()); 287 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 288 DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(), 289 ShuffleMask); 290 break; 291 292 case X86::MOVLHPSrr: 293 case X86::VMOVLHPSrr: 294 case X86::VMOVLHPSZrr: 295 Src2Name = getRegName(MI->getOperand(2).getReg()); 296 Src1Name = getRegName(MI->getOperand(1).getReg()); 297 DestName = getRegName(MI->getOperand(0).getReg()); 298 DecodeMOVLHPSMask(2, ShuffleMask); 299 break; 300 301 case X86::MOVHLPSrr: 302 case X86::VMOVHLPSrr: 303 case X86::VMOVHLPSZrr: 304 Src2Name = getRegName(MI->getOperand(2).getReg()); 305 Src1Name = getRegName(MI->getOperand(1).getReg()); 306 DestName = getRegName(MI->getOperand(0).getReg()); 307 DecodeMOVHLPSMask(2, ShuffleMask); 308 break; 309 310 CASE_MOVDUP(MOVSLDUP, r) 311 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg()); 312 // FALL THROUGH. 313 CASE_MOVDUP(MOVSLDUP, m) 314 DestName = getRegName(MI->getOperand(0).getReg()); 315 DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); 316 break; 317 318 CASE_MOVDUP(MOVSHDUP, r) 319 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg()); 320 // FALL THROUGH. 321 CASE_MOVDUP(MOVSHDUP, m) 322 DestName = getRegName(MI->getOperand(0).getReg()); 323 DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); 324 break; 325 326 CASE_MOVDUP(MOVDDUP, r) 327 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg()); 328 // FALL THROUGH. 329 CASE_MOVDUP(MOVDDUP, m) 330 DestName = getRegName(MI->getOperand(0).getReg()); 331 DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); 332 break; 333 334 case X86::PSLLDQri: 335 case X86::VPSLLDQri: 336 case X86::VPSLLDQYri: 337 Src1Name = getRegName(MI->getOperand(1).getReg()); 338 DestName = getRegName(MI->getOperand(0).getReg()); 339 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 340 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0), 341 MI->getOperand(MI->getNumOperands() - 1).getImm(), 342 ShuffleMask); 343 break; 344 345 case X86::PSRLDQri: 346 case X86::VPSRLDQri: 347 case X86::VPSRLDQYri: 348 Src1Name = getRegName(MI->getOperand(1).getReg()); 349 DestName = getRegName(MI->getOperand(0).getReg()); 350 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 351 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0), 352 MI->getOperand(MI->getNumOperands() - 1).getImm(), 353 ShuffleMask); 354 break; 355 356 case X86::PALIGNR128rr: 357 case X86::VPALIGNR128rr: 358 case X86::VPALIGNR256rr: 359 Src1Name = getRegName(MI->getOperand(2).getReg()); 360 // FALL THROUGH. 361 case X86::PALIGNR128rm: 362 case X86::VPALIGNR128rm: 363 case X86::VPALIGNR256rm: 364 Src2Name = getRegName(MI->getOperand(1).getReg()); 365 DestName = getRegName(MI->getOperand(0).getReg()); 366 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 367 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0), 368 MI->getOperand(MI->getNumOperands() - 1).getImm(), 369 ShuffleMask); 370 break; 371 372 case X86::PSHUFDri: 373 case X86::VPSHUFDri: 374 case X86::VPSHUFDYri: 375 Src1Name = getRegName(MI->getOperand(1).getReg()); 376 // FALL THROUGH. 377 case X86::PSHUFDmi: 378 case X86::VPSHUFDmi: 379 case X86::VPSHUFDYmi: 380 DestName = getRegName(MI->getOperand(0).getReg()); 381 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 382 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0), 383 MI->getOperand(MI->getNumOperands() - 1).getImm(), 384 ShuffleMask); 385 break; 386 387 case X86::PSHUFHWri: 388 case X86::VPSHUFHWri: 389 case X86::VPSHUFHWYri: 390 Src1Name = getRegName(MI->getOperand(1).getReg()); 391 // FALL THROUGH. 392 case X86::PSHUFHWmi: 393 case X86::VPSHUFHWmi: 394 case X86::VPSHUFHWYmi: 395 DestName = getRegName(MI->getOperand(0).getReg()); 396 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 397 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0), 398 MI->getOperand(MI->getNumOperands() - 1).getImm(), 399 ShuffleMask); 400 break; 401 402 case X86::PSHUFLWri: 403 case X86::VPSHUFLWri: 404 case X86::VPSHUFLWYri: 405 Src1Name = getRegName(MI->getOperand(1).getReg()); 406 // FALL THROUGH. 407 case X86::PSHUFLWmi: 408 case X86::VPSHUFLWmi: 409 case X86::VPSHUFLWYmi: 410 DestName = getRegName(MI->getOperand(0).getReg()); 411 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 412 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0), 413 MI->getOperand(MI->getNumOperands() - 1).getImm(), 414 ShuffleMask); 415 break; 416 417 case X86::MMX_PSHUFWri: 418 Src1Name = getRegName(MI->getOperand(1).getReg()); 419 // FALL THROUGH. 420 case X86::MMX_PSHUFWmi: 421 DestName = getRegName(MI->getOperand(0).getReg()); 422 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 423 DecodePSHUFMask(MVT::v4i16, 424 MI->getOperand(MI->getNumOperands() - 1).getImm(), 425 ShuffleMask); 426 break; 427 428 case X86::PSWAPDrr: 429 Src1Name = getRegName(MI->getOperand(1).getReg()); 430 // FALL THROUGH. 431 case X86::PSWAPDrm: 432 DestName = getRegName(MI->getOperand(0).getReg()); 433 DecodePSWAPMask(MVT::v2i32, ShuffleMask); 434 break; 435 436 CASE_UNPCK(PUNPCKHBW, r) 437 case X86::MMX_PUNPCKHBWirr: 438 Src2Name = getRegName(MI->getOperand(2).getReg()); 439 // FALL THROUGH. 440 CASE_UNPCK(PUNPCKHBW, m) 441 case X86::MMX_PUNPCKHBWirm: 442 Src1Name = getRegName(MI->getOperand(1).getReg()); 443 DestName = getRegName(MI->getOperand(0).getReg()); 444 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask); 445 break; 446 447 CASE_UNPCK(PUNPCKHWD, r) 448 case X86::MMX_PUNPCKHWDirr: 449 Src2Name = getRegName(MI->getOperand(2).getReg()); 450 // FALL THROUGH. 451 CASE_UNPCK(PUNPCKHWD, m) 452 case X86::MMX_PUNPCKHWDirm: 453 Src1Name = getRegName(MI->getOperand(1).getReg()); 454 DestName = getRegName(MI->getOperand(0).getReg()); 455 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask); 456 break; 457 458 CASE_UNPCK(PUNPCKHDQ, r) 459 case X86::MMX_PUNPCKHDQirr: 460 Src2Name = getRegName(MI->getOperand(2).getReg()); 461 // FALL THROUGH. 462 CASE_UNPCK(PUNPCKHDQ, m) 463 case X86::MMX_PUNPCKHDQirm: 464 Src1Name = getRegName(MI->getOperand(1).getReg()); 465 DestName = getRegName(MI->getOperand(0).getReg()); 466 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask); 467 break; 468 469 CASE_UNPCK(PUNPCKHQDQ, r) 470 Src2Name = getRegName(MI->getOperand(2).getReg()); 471 // FALL THROUGH. 472 CASE_UNPCK(PUNPCKHQDQ, m) 473 Src1Name = getRegName(MI->getOperand(1).getReg()); 474 DestName = getRegName(MI->getOperand(0).getReg()); 475 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask); 476 break; 477 478 CASE_UNPCK(PUNPCKLBW, r) 479 case X86::MMX_PUNPCKLBWirr: 480 Src2Name = getRegName(MI->getOperand(2).getReg()); 481 // FALL THROUGH. 482 CASE_UNPCK(PUNPCKLBW, m) 483 case X86::MMX_PUNPCKLBWirm: 484 Src1Name = getRegName(MI->getOperand(1).getReg()); 485 DestName = getRegName(MI->getOperand(0).getReg()); 486 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask); 487 break; 488 489 CASE_UNPCK(PUNPCKLWD, r) 490 case X86::MMX_PUNPCKLWDirr: 491 Src2Name = getRegName(MI->getOperand(2).getReg()); 492 // FALL THROUGH. 493 CASE_UNPCK(PUNPCKLWD, m) 494 case X86::MMX_PUNPCKLWDirm: 495 Src1Name = getRegName(MI->getOperand(1).getReg()); 496 DestName = getRegName(MI->getOperand(0).getReg()); 497 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask); 498 break; 499 500 CASE_UNPCK(PUNPCKLDQ, r) 501 case X86::MMX_PUNPCKLDQirr: 502 Src2Name = getRegName(MI->getOperand(2).getReg()); 503 // FALL THROUGH. 504 CASE_UNPCK(PUNPCKLDQ, m) 505 case X86::MMX_PUNPCKLDQirm: 506 Src1Name = getRegName(MI->getOperand(1).getReg()); 507 DestName = getRegName(MI->getOperand(0).getReg()); 508 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask); 509 break; 510 511 CASE_UNPCK(PUNPCKLQDQ, r) 512 Src2Name = getRegName(MI->getOperand(2).getReg()); 513 // FALL THROUGH. 514 CASE_UNPCK(PUNPCKLQDQ, m) 515 Src1Name = getRegName(MI->getOperand(1).getReg()); 516 DestName = getRegName(MI->getOperand(0).getReg()); 517 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask); 518 break; 519 520 CASE_SHUF(SHUFPD, r) 521 Src2Name = getRegName(MI->getOperand(2).getReg()); 522 // FALL THROUGH. 523 CASE_SHUF(SHUFPD, m) 524 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 525 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0), 526 MI->getOperand(MI->getNumOperands() - 1).getImm(), 527 ShuffleMask); 528 Src1Name = getRegName(MI->getOperand(1).getReg()); 529 DestName = getRegName(MI->getOperand(0).getReg()); 530 break; 531 532 CASE_SHUF(SHUFPS, r) 533 Src2Name = getRegName(MI->getOperand(2).getReg()); 534 // FALL THROUGH. 535 CASE_SHUF(SHUFPS, m) 536 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 537 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0), 538 MI->getOperand(MI->getNumOperands() - 1).getImm(), 539 ShuffleMask); 540 Src1Name = getRegName(MI->getOperand(1).getReg()); 541 DestName = getRegName(MI->getOperand(0).getReg()); 542 break; 543 544 CASE_VSHUF(64X2, r) 545 CASE_VSHUF(64X2, m) 546 CASE_VSHUF(32X4, r) 547 CASE_VSHUF(32X4, m) { 548 MVT VT; 549 bool HasMemOp; 550 unsigned NumOp = MI->getNumOperands(); 551 getVSHUF64x2FamilyInfo(MI, VT, HasMemOp); 552 decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(), 553 ShuffleMask); 554 DestName = getRegName(MI->getOperand(0).getReg()); 555 if (HasMemOp) { 556 assert((NumOp >= 8) && "Expected at least 8 operands!"); 557 Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg()); 558 } else { 559 assert((NumOp >= 4) && "Expected at least 4 operands!"); 560 Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg()); 561 Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg()); 562 } 563 break; 564 } 565 566 CASE_UNPCK(UNPCKLPD, r) 567 Src2Name = getRegName(MI->getOperand(2).getReg()); 568 // FALL THROUGH. 569 CASE_UNPCK(UNPCKLPD, m) 570 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); 571 Src1Name = getRegName(MI->getOperand(1).getReg()); 572 DestName = getRegName(MI->getOperand(0).getReg()); 573 break; 574 575 CASE_UNPCK(UNPCKLPS, r) 576 Src2Name = getRegName(MI->getOperand(2).getReg()); 577 // FALL THROUGH. 578 CASE_UNPCK(UNPCKLPS, m) 579 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); 580 Src1Name = getRegName(MI->getOperand(1).getReg()); 581 DestName = getRegName(MI->getOperand(0).getReg()); 582 break; 583 584 CASE_UNPCK(UNPCKHPD, r) 585 Src2Name = getRegName(MI->getOperand(2).getReg()); 586 // FALL THROUGH. 587 CASE_UNPCK(UNPCKHPD, m) 588 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); 589 Src1Name = getRegName(MI->getOperand(1).getReg()); 590 DestName = getRegName(MI->getOperand(0).getReg()); 591 break; 592 593 CASE_UNPCK(UNPCKHPS, r) 594 Src2Name = getRegName(MI->getOperand(2).getReg()); 595 // FALL THROUGH. 596 CASE_UNPCK(UNPCKHPS, m) 597 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); 598 Src1Name = getRegName(MI->getOperand(1).getReg()); 599 DestName = getRegName(MI->getOperand(0).getReg()); 600 break; 601 602 CASE_VPERM(PERMILPS, r) 603 Src1Name = getRegName(MI->getOperand(1).getReg()); 604 // FALL THROUGH. 605 CASE_VPERM(PERMILPS, m) 606 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 607 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0), 608 MI->getOperand(MI->getNumOperands() - 1).getImm(), 609 ShuffleMask); 610 DestName = getRegName(MI->getOperand(0).getReg()); 611 break; 612 613 CASE_VPERM(PERMILPD, r) 614 Src1Name = getRegName(MI->getOperand(1).getReg()); 615 // FALL THROUGH. 616 CASE_VPERM(PERMILPD, m) 617 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 618 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0), 619 MI->getOperand(MI->getNumOperands() - 1).getImm(), 620 ShuffleMask); 621 DestName = getRegName(MI->getOperand(0).getReg()); 622 break; 623 624 case X86::VPERM2F128rr: 625 case X86::VPERM2I128rr: 626 Src2Name = getRegName(MI->getOperand(2).getReg()); 627 // FALL THROUGH. 628 case X86::VPERM2F128rm: 629 case X86::VPERM2I128rm: 630 // For instruction comments purpose, assume the 256-bit vector is v4i64. 631 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 632 DecodeVPERM2X128Mask(MVT::v4i64, 633 MI->getOperand(MI->getNumOperands() - 1).getImm(), 634 ShuffleMask); 635 Src1Name = getRegName(MI->getOperand(1).getReg()); 636 DestName = getRegName(MI->getOperand(0).getReg()); 637 break; 638 639 case X86::VPERMQYri: 640 case X86::VPERMPDYri: 641 Src1Name = getRegName(MI->getOperand(1).getReg()); 642 // FALL THROUGH. 643 case X86::VPERMQYmi: 644 case X86::VPERMPDYmi: 645 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) 646 DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(), 647 ShuffleMask); 648 DestName = getRegName(MI->getOperand(0).getReg()); 649 break; 650 651 case X86::MOVSDrr: 652 case X86::VMOVSDrr: 653 Src2Name = getRegName(MI->getOperand(2).getReg()); 654 Src1Name = getRegName(MI->getOperand(1).getReg()); 655 // FALL THROUGH. 656 case X86::MOVSDrm: 657 case X86::VMOVSDrm: 658 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask); 659 DestName = getRegName(MI->getOperand(0).getReg()); 660 break; 661 662 case X86::MOVSSrr: 663 case X86::VMOVSSrr: 664 Src2Name = getRegName(MI->getOperand(2).getReg()); 665 Src1Name = getRegName(MI->getOperand(1).getReg()); 666 // FALL THROUGH. 667 case X86::MOVSSrm: 668 case X86::VMOVSSrm: 669 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask); 670 DestName = getRegName(MI->getOperand(0).getReg()); 671 break; 672 673 case X86::MOVPQI2QIrr: 674 case X86::MOVZPQILo2PQIrr: 675 case X86::VMOVPQI2QIrr: 676 case X86::VMOVZPQILo2PQIrr: 677 case X86::VMOVZPQILo2PQIZrr: 678 Src1Name = getRegName(MI->getOperand(1).getReg()); 679 // FALL THROUGH. 680 case X86::MOVQI2PQIrm: 681 case X86::MOVZQI2PQIrm: 682 case X86::MOVZPQILo2PQIrm: 683 case X86::VMOVQI2PQIrm: 684 case X86::VMOVZQI2PQIrm: 685 case X86::VMOVZPQILo2PQIrm: 686 case X86::VMOVZPQILo2PQIZrm: 687 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask); 688 DestName = getRegName(MI->getOperand(0).getReg()); 689 break; 690 691 case X86::MOVDI2PDIrm: 692 case X86::VMOVDI2PDIrm: 693 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask); 694 DestName = getRegName(MI->getOperand(0).getReg()); 695 break; 696 697 case X86::EXTRQI: 698 if (MI->getOperand(2).isImm() && 699 MI->getOperand(3).isImm()) 700 DecodeEXTRQIMask(MI->getOperand(2).getImm(), 701 MI->getOperand(3).getImm(), 702 ShuffleMask); 703 704 DestName = getRegName(MI->getOperand(0).getReg()); 705 Src1Name = getRegName(MI->getOperand(1).getReg()); 706 break; 707 708 case X86::INSERTQI: 709 if (MI->getOperand(3).isImm() && 710 MI->getOperand(4).isImm()) 711 DecodeINSERTQIMask(MI->getOperand(3).getImm(), 712 MI->getOperand(4).getImm(), 713 ShuffleMask); 714 715 DestName = getRegName(MI->getOperand(0).getReg()); 716 Src1Name = getRegName(MI->getOperand(1).getReg()); 717 Src2Name = getRegName(MI->getOperand(2).getReg()); 718 break; 719 720 case X86::PMOVZXBWrr: 721 case X86::PMOVZXBDrr: 722 case X86::PMOVZXBQrr: 723 case X86::PMOVZXWDrr: 724 case X86::PMOVZXWQrr: 725 case X86::PMOVZXDQrr: 726 case X86::VPMOVZXBWrr: 727 case X86::VPMOVZXBDrr: 728 case X86::VPMOVZXBQrr: 729 case X86::VPMOVZXWDrr: 730 case X86::VPMOVZXWQrr: 731 case X86::VPMOVZXDQrr: 732 case X86::VPMOVZXBWYrr: 733 case X86::VPMOVZXBDYrr: 734 case X86::VPMOVZXBQYrr: 735 case X86::VPMOVZXWDYrr: 736 case X86::VPMOVZXWQYrr: 737 case X86::VPMOVZXDQYrr: 738 Src1Name = getRegName(MI->getOperand(1).getReg()); 739 // FALL THROUGH. 740 case X86::PMOVZXBWrm: 741 case X86::PMOVZXBDrm: 742 case X86::PMOVZXBQrm: 743 case X86::PMOVZXWDrm: 744 case X86::PMOVZXWQrm: 745 case X86::PMOVZXDQrm: 746 case X86::VPMOVZXBWrm: 747 case X86::VPMOVZXBDrm: 748 case X86::VPMOVZXBQrm: 749 case X86::VPMOVZXWDrm: 750 case X86::VPMOVZXWQrm: 751 case X86::VPMOVZXDQrm: 752 case X86::VPMOVZXBWYrm: 753 case X86::VPMOVZXBDYrm: 754 case X86::VPMOVZXBQYrm: 755 case X86::VPMOVZXWDYrm: 756 case X86::VPMOVZXWQYrm: 757 case X86::VPMOVZXDQYrm: { 758 MVT SrcVT, DstVT; 759 getZeroExtensionTypes(MI, SrcVT, DstVT); 760 DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask); 761 DestName = getRegName(MI->getOperand(0).getReg()); 762 } break; 763 } 764 765 // The only comments we decode are shuffles, so give up if we were unable to 766 // decode a shuffle mask. 767 if (ShuffleMask.empty()) 768 return false; 769 770 if (!DestName) DestName = Src1Name; 771 OS << (DestName ? DestName : "mem") << " = "; 772 773 // If the two sources are the same, canonicalize the input elements to be 774 // from the first src so that we get larger element spans. 775 if (Src1Name == Src2Name) { 776 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) { 777 if ((int)ShuffleMask[i] >= 0 && // Not sentinel. 778 ShuffleMask[i] >= (int)e) // From second mask. 779 ShuffleMask[i] -= e; 780 } 781 } 782 783 // The shuffle mask specifies which elements of the src1/src2 fill in the 784 // destination, with a few sentinel values. Loop through and print them 785 // out. 786 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) { 787 if (i != 0) 788 OS << ','; 789 if (ShuffleMask[i] == SM_SentinelZero) { 790 OS << "zero"; 791 continue; 792 } 793 794 // Otherwise, it must come from src1 or src2. Print the span of elements 795 // that comes from this src. 796 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size(); 797 const char *SrcName = isSrc1 ? Src1Name : Src2Name; 798 OS << (SrcName ? SrcName : "mem") << '['; 799 bool IsFirst = true; 800 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero && 801 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) { 802 if (!IsFirst) 803 OS << ','; 804 else 805 IsFirst = false; 806 if (ShuffleMask[i] == SM_SentinelUndef) 807 OS << "u"; 808 else 809 OS << ShuffleMask[i] % ShuffleMask.size(); 810 ++i; 811 } 812 OS << ']'; 813 --i; // For loop increments element #. 814 } 815 //MI->print(OS, 0); 816 OS << "\n"; 817 818 // We successfully added a comment to this instruction. 819 return true; 820 } 821