1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86InstComments.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "llvm/CodeGen/MachineValueType.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/raw_ostream.h"
21 
22 using namespace llvm;
23 
24 #define CASE_SSE_INS_COMMON(Inst, src)            \
25   case X86::Inst##src:
26 
27 #define CASE_AVX_INS_COMMON(Inst, Suffix, src)    \
28   case X86::V##Inst##Suffix##src:
29 
30 #define CASE_MASK_INS_COMMON(Inst, Suffix, src)   \
31   case X86::V##Inst##Suffix##src##k:
32 
33 #define CASE_MASKZ_INS_COMMON(Inst, Suffix, src)  \
34   case X86::V##Inst##Suffix##src##kz:
35 
36 #define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
37   CASE_AVX_INS_COMMON(Inst, Suffix, src)          \
38   CASE_MASK_INS_COMMON(Inst, Suffix, src)         \
39   CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
40 
41 #define CASE_MOVDUP(Inst, src)                    \
42   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
43   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
44   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
45   CASE_AVX_INS_COMMON(Inst, , r##src)             \
46   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
47   CASE_SSE_INS_COMMON(Inst, r##src)
48 
49 #define CASE_MASK_MOVDUP(Inst, src)               \
50   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
51   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
52   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
53 
54 #define CASE_MASKZ_MOVDUP(Inst, src)              \
55   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
56   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
57   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
58 
59 #define CASE_PMOVZX(Inst, src)                    \
60   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
61   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
62   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
63   CASE_AVX_INS_COMMON(Inst, , r##src)             \
64   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
65   CASE_SSE_INS_COMMON(Inst, r##src)
66 
67 #define CASE_MASK_PMOVZX(Inst, src)               \
68   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
69   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
70   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
71 
72 #define CASE_MASKZ_PMOVZX(Inst, src)              \
73   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
74   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
75   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
76 
77 #define CASE_UNPCK(Inst, src)                     \
78   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
79   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
80   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
81   CASE_AVX_INS_COMMON(Inst, , r##src)             \
82   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
83   CASE_SSE_INS_COMMON(Inst, r##src)
84 
85 #define CASE_MASK_UNPCK(Inst, src)                \
86   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
87   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
88   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
89 
90 #define CASE_MASKZ_UNPCK(Inst, src)               \
91   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
92   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
93   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
94 
95 #define CASE_SHUF(Inst, suf)                      \
96   CASE_AVX512_INS_COMMON(Inst, Z, suf)            \
97   CASE_AVX512_INS_COMMON(Inst, Z256, suf)         \
98   CASE_AVX512_INS_COMMON(Inst, Z128, suf)         \
99   CASE_AVX_INS_COMMON(Inst, , suf)                \
100   CASE_AVX_INS_COMMON(Inst, Y, suf)               \
101   CASE_SSE_INS_COMMON(Inst, suf)
102 
103 #define CASE_MASK_SHUF(Inst, src)                 \
104   CASE_MASK_INS_COMMON(Inst, Z, r##src##i)        \
105   CASE_MASK_INS_COMMON(Inst, Z256, r##src##i)     \
106   CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
107 
108 #define CASE_MASKZ_SHUF(Inst, src)                \
109   CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i)       \
110   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i)    \
111   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
112 
113 #define CASE_VPERMILPI(Inst, src)                 \
114   CASE_AVX512_INS_COMMON(Inst, Z, src##i)         \
115   CASE_AVX512_INS_COMMON(Inst, Z256, src##i)      \
116   CASE_AVX512_INS_COMMON(Inst, Z128, src##i)      \
117   CASE_AVX_INS_COMMON(Inst, , src##i)             \
118   CASE_AVX_INS_COMMON(Inst, Y, src##i)
119 
120 #define CASE_MASK_VPERMILPI(Inst, src)            \
121   CASE_MASK_INS_COMMON(Inst, Z, src##i)           \
122   CASE_MASK_INS_COMMON(Inst, Z256, src##i)        \
123   CASE_MASK_INS_COMMON(Inst, Z128, src##i)
124 
125 #define CASE_MASKZ_VPERMILPI(Inst, src)           \
126   CASE_MASKZ_INS_COMMON(Inst, Z, src##i)          \
127   CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)       \
128   CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
129 
130 #define CASE_VPERM(Inst, src)                     \
131   CASE_AVX512_INS_COMMON(Inst, Z, src##i)         \
132   CASE_AVX512_INS_COMMON(Inst, Z256, src##i)      \
133   CASE_AVX_INS_COMMON(Inst, Y, src##i)
134 
135 #define CASE_MASK_VPERM(Inst, src)                \
136   CASE_MASK_INS_COMMON(Inst, Z, src##i)           \
137   CASE_MASK_INS_COMMON(Inst, Z256, src##i)
138 
139 #define CASE_MASKZ_VPERM(Inst, src)               \
140   CASE_MASKZ_INS_COMMON(Inst, Z, src##i)          \
141   CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
142 
143 #define CASE_VSHUF(Inst, src)                          \
144   CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i)    \
145   CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i)    \
146   CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
147   CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
148 
149 #define CASE_MASK_VSHUF(Inst, src)                    \
150   CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i)     \
151   CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i)     \
152   CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i)  \
153   CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
154 
155 #define CASE_MASKZ_VSHUF(Inst, src)                   \
156   CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i)    \
157   CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i)    \
158   CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
159   CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
160 
161 static unsigned getVectorRegSize(unsigned RegNo) {
162   if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
163     return 512;
164   if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
165     return 256;
166   if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
167     return 128;
168   if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
169     return 64;
170 
171   llvm_unreachable("Unknown vector reg!");
172 }
173 
174 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
175                                  unsigned OperandIndex) {
176   unsigned OpReg = MI->getOperand(OperandIndex).getReg();
177   return MVT::getVectorVT(ScalarVT,
178                           getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
179 }
180 
181 /// \brief Extracts the dst type for a given zero extension instruction.
182 static MVT getZeroExtensionResultType(const MCInst *MI) {
183   switch (MI->getOpcode()) {
184   default:
185     llvm_unreachable("Unknown zero extension instruction");
186   // zero extension to i16
187   CASE_PMOVZX(PMOVZXBW, m)
188   CASE_PMOVZX(PMOVZXBW, r)
189     return getRegOperandVectorVT(MI, MVT::i16, 0);
190   // zero extension to i32
191   CASE_PMOVZX(PMOVZXBD, m)
192   CASE_PMOVZX(PMOVZXBD, r)
193   CASE_PMOVZX(PMOVZXWD, m)
194   CASE_PMOVZX(PMOVZXWD, r)
195     return getRegOperandVectorVT(MI, MVT::i32, 0);
196   // zero extension to i64
197   CASE_PMOVZX(PMOVZXBQ, m)
198   CASE_PMOVZX(PMOVZXBQ, r)
199   CASE_PMOVZX(PMOVZXWQ, m)
200   CASE_PMOVZX(PMOVZXWQ, r)
201   CASE_PMOVZX(PMOVZXDQ, m)
202   CASE_PMOVZX(PMOVZXDQ, r)
203     return getRegOperandVectorVT(MI, MVT::i64, 0);
204   }
205 }
206 
207 /// Wraps the destination register name with AVX512 mask/maskz filtering.
208 static std::string getMaskName(const MCInst *MI, const char *DestName,
209                                const char *(*getRegName)(unsigned)) {
210   std::string OpMaskName(DestName);
211 
212   bool MaskWithZero = false;
213   const char *MaskRegName = nullptr;
214 
215   switch (MI->getOpcode()) {
216   default:
217     return OpMaskName;
218   CASE_MASKZ_MOVDUP(MOVDDUP, m)
219   CASE_MASKZ_MOVDUP(MOVDDUP, r)
220   CASE_MASKZ_MOVDUP(MOVSHDUP, m)
221   CASE_MASKZ_MOVDUP(MOVSHDUP, r)
222   CASE_MASKZ_MOVDUP(MOVSLDUP, m)
223   CASE_MASKZ_MOVDUP(MOVSLDUP, r)
224   CASE_MASKZ_PMOVZX(PMOVZXBD, m)
225   CASE_MASKZ_PMOVZX(PMOVZXBD, r)
226   CASE_MASKZ_PMOVZX(PMOVZXBQ, m)
227   CASE_MASKZ_PMOVZX(PMOVZXBQ, r)
228   CASE_MASKZ_PMOVZX(PMOVZXBW, m)
229   CASE_MASKZ_PMOVZX(PMOVZXBW, r)
230   CASE_MASKZ_PMOVZX(PMOVZXDQ, m)
231   CASE_MASKZ_PMOVZX(PMOVZXDQ, r)
232   CASE_MASKZ_PMOVZX(PMOVZXWD, m)
233   CASE_MASKZ_PMOVZX(PMOVZXWD, r)
234   CASE_MASKZ_PMOVZX(PMOVZXWQ, m)
235   CASE_MASKZ_PMOVZX(PMOVZXWQ, r)
236   CASE_MASKZ_UNPCK(PUNPCKHBW, m)
237   CASE_MASKZ_UNPCK(PUNPCKHBW, r)
238   CASE_MASKZ_UNPCK(PUNPCKHWD, m)
239   CASE_MASKZ_UNPCK(PUNPCKHWD, r)
240   CASE_MASKZ_UNPCK(PUNPCKHDQ, m)
241   CASE_MASKZ_UNPCK(PUNPCKHDQ, r)
242   CASE_MASKZ_UNPCK(PUNPCKLBW, m)
243   CASE_MASKZ_UNPCK(PUNPCKLBW, r)
244   CASE_MASKZ_UNPCK(PUNPCKLWD, m)
245   CASE_MASKZ_UNPCK(PUNPCKLWD, r)
246   CASE_MASKZ_UNPCK(PUNPCKLDQ, m)
247   CASE_MASKZ_UNPCK(PUNPCKLDQ, r)
248   CASE_MASKZ_UNPCK(UNPCKHPD, m)
249   CASE_MASKZ_UNPCK(UNPCKHPD, r)
250   CASE_MASKZ_UNPCK(UNPCKHPS, m)
251   CASE_MASKZ_UNPCK(UNPCKHPS, r)
252   CASE_MASKZ_UNPCK(UNPCKLPD, m)
253   CASE_MASKZ_UNPCK(UNPCKLPD, r)
254   CASE_MASKZ_UNPCK(UNPCKLPS, m)
255   CASE_MASKZ_UNPCK(UNPCKLPS, r)
256   CASE_MASKZ_SHUF(PALIGNR, r)
257   CASE_MASKZ_SHUF(PALIGNR, m)
258   CASE_MASKZ_SHUF(ALIGNQ, r)
259   CASE_MASKZ_SHUF(ALIGNQ, m)
260   CASE_MASKZ_SHUF(ALIGND, r)
261   CASE_MASKZ_SHUF(ALIGND, m)
262   CASE_MASKZ_SHUF(SHUFPD, m)
263   CASE_MASKZ_SHUF(SHUFPD, r)
264   CASE_MASKZ_SHUF(SHUFPS, m)
265   CASE_MASKZ_SHUF(SHUFPS, r)
266   CASE_MASKZ_VPERMILPI(PERMILPD, m)
267   CASE_MASKZ_VPERMILPI(PERMILPD, r)
268   CASE_MASKZ_VPERMILPI(PERMILPS, m)
269   CASE_MASKZ_VPERMILPI(PERMILPS, r)
270   CASE_MASKZ_VPERMILPI(PSHUFD, m)
271   CASE_MASKZ_VPERMILPI(PSHUFD, r)
272   CASE_MASKZ_VPERMILPI(PSHUFHW, m)
273   CASE_MASKZ_VPERMILPI(PSHUFHW, r)
274   CASE_MASKZ_VPERMILPI(PSHUFLW, m)
275   CASE_MASKZ_VPERMILPI(PSHUFLW, r)
276   CASE_MASKZ_VPERM(PERMPD, m)
277   CASE_MASKZ_VPERM(PERMPD, r)
278   CASE_MASKZ_VPERM(PERMQ, m)
279   CASE_MASKZ_VPERM(PERMQ, r)
280   CASE_MASKZ_VSHUF(64X2, m)
281   CASE_MASKZ_VSHUF(64X2, r)
282   CASE_MASKZ_VSHUF(32X4, m)
283   CASE_MASKZ_VSHUF(32X4, r)
284   CASE_MASKZ_INS_COMMON(BROADCASTF64X2, Z128, rm)
285   CASE_MASKZ_INS_COMMON(BROADCASTI64X2, Z128, rm)
286   CASE_MASKZ_INS_COMMON(BROADCASTF64X2, , rm)
287   CASE_MASKZ_INS_COMMON(BROADCASTI64X2, , rm)
288   CASE_MASKZ_INS_COMMON(BROADCASTF64X4, , rm)
289   CASE_MASKZ_INS_COMMON(BROADCASTI64X4, , rm)
290   CASE_MASKZ_INS_COMMON(BROADCASTF32X4, Z256, rm)
291   CASE_MASKZ_INS_COMMON(BROADCASTI32X4, Z256, rm)
292   CASE_MASKZ_INS_COMMON(BROADCASTF32X4, , rm)
293   CASE_MASKZ_INS_COMMON(BROADCASTI32X4, , rm)
294   CASE_MASKZ_INS_COMMON(BROADCASTF32X8, , rm)
295   CASE_MASKZ_INS_COMMON(BROADCASTI32X8, , rm)
296   CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, r)
297   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, r)
298   CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, m)
299   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, m)
300   CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, r)
301   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, r)
302   CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, m)
303   CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, m)
304     MaskWithZero = true;
305     MaskRegName = getRegName(MI->getOperand(1).getReg());
306     break;
307   CASE_MASK_MOVDUP(MOVDDUP, m)
308   CASE_MASK_MOVDUP(MOVDDUP, r)
309   CASE_MASK_MOVDUP(MOVSHDUP, m)
310   CASE_MASK_MOVDUP(MOVSHDUP, r)
311   CASE_MASK_MOVDUP(MOVSLDUP, m)
312   CASE_MASK_MOVDUP(MOVSLDUP, r)
313   CASE_MASK_PMOVZX(PMOVZXBD, m)
314   CASE_MASK_PMOVZX(PMOVZXBD, r)
315   CASE_MASK_PMOVZX(PMOVZXBQ, m)
316   CASE_MASK_PMOVZX(PMOVZXBQ, r)
317   CASE_MASK_PMOVZX(PMOVZXBW, m)
318   CASE_MASK_PMOVZX(PMOVZXBW, r)
319   CASE_MASK_PMOVZX(PMOVZXDQ, m)
320   CASE_MASK_PMOVZX(PMOVZXDQ, r)
321   CASE_MASK_PMOVZX(PMOVZXWD, m)
322   CASE_MASK_PMOVZX(PMOVZXWD, r)
323   CASE_MASK_PMOVZX(PMOVZXWQ, m)
324   CASE_MASK_PMOVZX(PMOVZXWQ, r)
325   CASE_MASK_UNPCK(PUNPCKHBW, m)
326   CASE_MASK_UNPCK(PUNPCKHBW, r)
327   CASE_MASK_UNPCK(PUNPCKHWD, m)
328   CASE_MASK_UNPCK(PUNPCKHWD, r)
329   CASE_MASK_UNPCK(PUNPCKHDQ, m)
330   CASE_MASK_UNPCK(PUNPCKHDQ, r)
331   CASE_MASK_UNPCK(PUNPCKLBW, m)
332   CASE_MASK_UNPCK(PUNPCKLBW, r)
333   CASE_MASK_UNPCK(PUNPCKLWD, m)
334   CASE_MASK_UNPCK(PUNPCKLWD, r)
335   CASE_MASK_UNPCK(PUNPCKLDQ, m)
336   CASE_MASK_UNPCK(PUNPCKLDQ, r)
337   CASE_MASK_UNPCK(UNPCKHPD, m)
338   CASE_MASK_UNPCK(UNPCKHPD, r)
339   CASE_MASK_UNPCK(UNPCKHPS, m)
340   CASE_MASK_UNPCK(UNPCKHPS, r)
341   CASE_MASK_UNPCK(UNPCKLPD, m)
342   CASE_MASK_UNPCK(UNPCKLPD, r)
343   CASE_MASK_UNPCK(UNPCKLPS, m)
344   CASE_MASK_UNPCK(UNPCKLPS, r)
345   CASE_MASK_SHUF(PALIGNR, r)
346   CASE_MASK_SHUF(PALIGNR, m)
347   CASE_MASK_SHUF(ALIGNQ, r)
348   CASE_MASK_SHUF(ALIGNQ, m)
349   CASE_MASK_SHUF(ALIGND, r)
350   CASE_MASK_SHUF(ALIGND, m)
351   CASE_MASK_SHUF(SHUFPD, m)
352   CASE_MASK_SHUF(SHUFPD, r)
353   CASE_MASK_SHUF(SHUFPS, m)
354   CASE_MASK_SHUF(SHUFPS, r)
355   CASE_MASK_VPERMILPI(PERMILPD, m)
356   CASE_MASK_VPERMILPI(PERMILPD, r)
357   CASE_MASK_VPERMILPI(PERMILPS, m)
358   CASE_MASK_VPERMILPI(PERMILPS, r)
359   CASE_MASK_VPERMILPI(PSHUFD, m)
360   CASE_MASK_VPERMILPI(PSHUFD, r)
361   CASE_MASK_VPERMILPI(PSHUFHW, m)
362   CASE_MASK_VPERMILPI(PSHUFHW, r)
363   CASE_MASK_VPERMILPI(PSHUFLW, m)
364   CASE_MASK_VPERMILPI(PSHUFLW, r)
365   CASE_MASK_VPERM(PERMPD, m)
366   CASE_MASK_VPERM(PERMPD, r)
367   CASE_MASK_VPERM(PERMQ, m)
368   CASE_MASK_VPERM(PERMQ, r)
369   CASE_MASK_VSHUF(64X2, m)
370   CASE_MASK_VSHUF(64X2, r)
371   CASE_MASK_VSHUF(32X4, m)
372   CASE_MASK_VSHUF(32X4, r)
373   CASE_MASK_INS_COMMON(BROADCASTF64X2, Z128, rm)
374   CASE_MASK_INS_COMMON(BROADCASTI64X2, Z128, rm)
375   CASE_MASK_INS_COMMON(BROADCASTF64X2, , rm)
376   CASE_MASK_INS_COMMON(BROADCASTI64X2, , rm)
377   CASE_MASK_INS_COMMON(BROADCASTF64X4, , rm)
378   CASE_MASK_INS_COMMON(BROADCASTI64X4, , rm)
379   CASE_MASK_INS_COMMON(BROADCASTF32X4, Z256, rm)
380   CASE_MASK_INS_COMMON(BROADCASTI32X4, Z256, rm)
381   CASE_MASK_INS_COMMON(BROADCASTF32X4, , rm)
382   CASE_MASK_INS_COMMON(BROADCASTI32X4, , rm)
383   CASE_MASK_INS_COMMON(BROADCASTF32X8, , rm)
384   CASE_MASK_INS_COMMON(BROADCASTI32X8, , rm)
385   CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, r)
386   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, r)
387   CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, m)
388   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, m)
389   CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, r)
390   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, r)
391   CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, m)
392   CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, m)
393     MaskRegName = getRegName(MI->getOperand(2).getReg());
394     break;
395   }
396 
397   // MASK: zmmX {%kY}
398   OpMaskName += " {%";
399   OpMaskName += MaskRegName;
400   OpMaskName += "}";
401 
402   // MASKZ: zmmX {%kY} {z}
403   if (MaskWithZero)
404     OpMaskName += " {z}";
405 
406   return OpMaskName;
407 }
408 
409 //===----------------------------------------------------------------------===//
410 // Top Level Entrypoint
411 //===----------------------------------------------------------------------===//
412 
413 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
414 /// newline terminated strings to the specified string if desired.  This
415 /// information is shown in disassembly dumps when verbose assembly is enabled.
416 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
417                                   const char *(*getRegName)(unsigned)) {
418   // If this is a shuffle operation, the switch should fill in this state.
419   SmallVector<int, 8> ShuffleMask;
420   const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
421   unsigned NumOperands = MI->getNumOperands();
422   bool RegForm = false;
423 
424   switch (MI->getOpcode()) {
425   default:
426     // Not an instruction for which we can decode comments.
427     return false;
428 
429   case X86::BLENDPDrri:
430   case X86::VBLENDPDrri:
431   case X86::VBLENDPDYrri:
432     Src2Name = getRegName(MI->getOperand(2).getReg());
433     LLVM_FALLTHROUGH;
434   case X86::BLENDPDrmi:
435   case X86::VBLENDPDrmi:
436   case X86::VBLENDPDYrmi:
437     if (MI->getOperand(NumOperands - 1).isImm())
438       DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
439                       MI->getOperand(NumOperands - 1).getImm(),
440                       ShuffleMask);
441     Src1Name = getRegName(MI->getOperand(1).getReg());
442     DestName = getRegName(MI->getOperand(0).getReg());
443     break;
444 
445   case X86::BLENDPSrri:
446   case X86::VBLENDPSrri:
447   case X86::VBLENDPSYrri:
448     Src2Name = getRegName(MI->getOperand(2).getReg());
449     LLVM_FALLTHROUGH;
450   case X86::BLENDPSrmi:
451   case X86::VBLENDPSrmi:
452   case X86::VBLENDPSYrmi:
453     if (MI->getOperand(NumOperands - 1).isImm())
454       DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
455                       MI->getOperand(NumOperands - 1).getImm(),
456                       ShuffleMask);
457     Src1Name = getRegName(MI->getOperand(1).getReg());
458     DestName = getRegName(MI->getOperand(0).getReg());
459     break;
460 
461   case X86::PBLENDWrri:
462   case X86::VPBLENDWrri:
463   case X86::VPBLENDWYrri:
464     Src2Name = getRegName(MI->getOperand(2).getReg());
465     LLVM_FALLTHROUGH;
466   case X86::PBLENDWrmi:
467   case X86::VPBLENDWrmi:
468   case X86::VPBLENDWYrmi:
469     if (MI->getOperand(NumOperands - 1).isImm())
470       DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
471                       MI->getOperand(NumOperands - 1).getImm(),
472                       ShuffleMask);
473     Src1Name = getRegName(MI->getOperand(1).getReg());
474     DestName = getRegName(MI->getOperand(0).getReg());
475     break;
476 
477   case X86::VPBLENDDrri:
478   case X86::VPBLENDDYrri:
479     Src2Name = getRegName(MI->getOperand(2).getReg());
480     LLVM_FALLTHROUGH;
481   case X86::VPBLENDDrmi:
482   case X86::VPBLENDDYrmi:
483     if (MI->getOperand(NumOperands - 1).isImm())
484       DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
485                       MI->getOperand(NumOperands - 1).getImm(),
486                       ShuffleMask);
487     Src1Name = getRegName(MI->getOperand(1).getReg());
488     DestName = getRegName(MI->getOperand(0).getReg());
489     break;
490 
491   case X86::INSERTPSrr:
492   case X86::VINSERTPSrr:
493   case X86::VINSERTPSZrr:
494     Src2Name = getRegName(MI->getOperand(2).getReg());
495     LLVM_FALLTHROUGH;
496   case X86::INSERTPSrm:
497   case X86::VINSERTPSrm:
498   case X86::VINSERTPSZrm:
499     DestName = getRegName(MI->getOperand(0).getReg());
500     Src1Name = getRegName(MI->getOperand(1).getReg());
501     if (MI->getOperand(NumOperands - 1).isImm())
502       DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
503                          ShuffleMask);
504     break;
505 
506   case X86::MOVLHPSrr:
507   case X86::VMOVLHPSrr:
508   case X86::VMOVLHPSZrr:
509     Src2Name = getRegName(MI->getOperand(2).getReg());
510     Src1Name = getRegName(MI->getOperand(1).getReg());
511     DestName = getRegName(MI->getOperand(0).getReg());
512     DecodeMOVLHPSMask(2, ShuffleMask);
513     break;
514 
515   case X86::MOVHLPSrr:
516   case X86::VMOVHLPSrr:
517   case X86::VMOVHLPSZrr:
518     Src2Name = getRegName(MI->getOperand(2).getReg());
519     Src1Name = getRegName(MI->getOperand(1).getReg());
520     DestName = getRegName(MI->getOperand(0).getReg());
521     DecodeMOVHLPSMask(2, ShuffleMask);
522     break;
523 
524   case X86::MOVHPDrm:
525   case X86::VMOVHPDrm:
526   case X86::VMOVHPDZ128rm:
527     Src1Name = getRegName(MI->getOperand(1).getReg());
528     DestName = getRegName(MI->getOperand(0).getReg());
529     DecodeInsertElementMask(MVT::v2f64, 1, 1, ShuffleMask);
530     break;
531 
532   case X86::MOVHPSrm:
533   case X86::VMOVHPSrm:
534   case X86::VMOVHPSZ128rm:
535     Src1Name = getRegName(MI->getOperand(1).getReg());
536     DestName = getRegName(MI->getOperand(0).getReg());
537     DecodeInsertElementMask(MVT::v4f32, 2, 2, ShuffleMask);
538     break;
539 
540   case X86::MOVLPDrm:
541   case X86::VMOVLPDrm:
542   case X86::VMOVLPDZ128rm:
543     Src1Name = getRegName(MI->getOperand(1).getReg());
544     DestName = getRegName(MI->getOperand(0).getReg());
545     DecodeInsertElementMask(MVT::v2f64, 0, 1, ShuffleMask);
546     break;
547 
548   case X86::MOVLPSrm:
549   case X86::VMOVLPSrm:
550   case X86::VMOVLPSZ128rm:
551     Src1Name = getRegName(MI->getOperand(1).getReg());
552     DestName = getRegName(MI->getOperand(0).getReg());
553     DecodeInsertElementMask(MVT::v4f32, 0, 2, ShuffleMask);
554     break;
555 
556   CASE_MOVDUP(MOVSLDUP, r)
557     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
558     LLVM_FALLTHROUGH;
559 
560   CASE_MOVDUP(MOVSLDUP, m)
561     DestName = getRegName(MI->getOperand(0).getReg());
562     DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
563     break;
564 
565   CASE_MOVDUP(MOVSHDUP, r)
566     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
567     LLVM_FALLTHROUGH;
568 
569   CASE_MOVDUP(MOVSHDUP, m)
570     DestName = getRegName(MI->getOperand(0).getReg());
571     DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
572     break;
573 
574   CASE_MOVDUP(MOVDDUP, r)
575     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
576     LLVM_FALLTHROUGH;
577 
578   CASE_MOVDUP(MOVDDUP, m)
579     DestName = getRegName(MI->getOperand(0).getReg());
580     DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
581     break;
582 
583   case X86::PSLLDQri:
584   case X86::VPSLLDQri:
585   case X86::VPSLLDQYri:
586   case X86::VPSLLDQZ128rr:
587   case X86::VPSLLDQZ256rr:
588   case X86::VPSLLDQZ512rr:
589     Src1Name = getRegName(MI->getOperand(1).getReg());
590     LLVM_FALLTHROUGH;
591   case X86::VPSLLDQZ128rm:
592   case X86::VPSLLDQZ256rm:
593   case X86::VPSLLDQZ512rm:
594     DestName = getRegName(MI->getOperand(0).getReg());
595     if (MI->getOperand(NumOperands - 1).isImm())
596       DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
597                        MI->getOperand(NumOperands - 1).getImm(),
598                        ShuffleMask);
599     break;
600 
601   case X86::PSRLDQri:
602   case X86::VPSRLDQri:
603   case X86::VPSRLDQYri:
604   case X86::VPSRLDQZ128rr:
605   case X86::VPSRLDQZ256rr:
606   case X86::VPSRLDQZ512rr:
607     Src1Name = getRegName(MI->getOperand(1).getReg());
608     LLVM_FALLTHROUGH;
609   case X86::VPSRLDQZ128rm:
610   case X86::VPSRLDQZ256rm:
611   case X86::VPSRLDQZ512rm:
612     DestName = getRegName(MI->getOperand(0).getReg());
613     if (MI->getOperand(NumOperands - 1).isImm())
614       DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
615                        MI->getOperand(NumOperands - 1).getImm(),
616                        ShuffleMask);
617     break;
618 
619   CASE_SHUF(PALIGNR, rri)
620     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
621     RegForm = true;
622     LLVM_FALLTHROUGH;
623 
624   CASE_SHUF(PALIGNR, rmi)
625     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
626     DestName = getRegName(MI->getOperand(0).getReg());
627     if (MI->getOperand(NumOperands - 1).isImm())
628       DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
629                         MI->getOperand(NumOperands - 1).getImm(),
630                         ShuffleMask);
631     break;
632 
633   CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
634   CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
635   CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
636     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
637     RegForm = true;
638     LLVM_FALLTHROUGH;
639 
640   CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
641   CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
642   CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
643     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
644     DestName = getRegName(MI->getOperand(0).getReg());
645     if (MI->getOperand(NumOperands - 1).isImm())
646       DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i64, 0),
647                        MI->getOperand(NumOperands - 1).getImm(),
648                        ShuffleMask);
649     break;
650 
651   CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
652   CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
653   CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
654     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
655     RegForm = true;
656     LLVM_FALLTHROUGH;
657 
658   CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
659   CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
660   CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
661     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
662     DestName = getRegName(MI->getOperand(0).getReg());
663     if (MI->getOperand(NumOperands - 1).isImm())
664       DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i32, 0),
665                        MI->getOperand(NumOperands - 1).getImm(),
666                        ShuffleMask);
667     break;
668 
669   CASE_SHUF(PSHUFD, ri)
670     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
671     LLVM_FALLTHROUGH;
672 
673   CASE_SHUF(PSHUFD, mi)
674     DestName = getRegName(MI->getOperand(0).getReg());
675     if (MI->getOperand(NumOperands - 1).isImm())
676       DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
677                       MI->getOperand(NumOperands - 1).getImm(),
678                       ShuffleMask);
679     break;
680 
681   CASE_SHUF(PSHUFHW, ri)
682     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
683     LLVM_FALLTHROUGH;
684 
685   CASE_SHUF(PSHUFHW, mi)
686     DestName = getRegName(MI->getOperand(0).getReg());
687     if (MI->getOperand(NumOperands - 1).isImm())
688       DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
689                         MI->getOperand(NumOperands - 1).getImm(),
690                         ShuffleMask);
691     break;
692 
693   CASE_SHUF(PSHUFLW, ri)
694     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
695     LLVM_FALLTHROUGH;
696 
697   CASE_SHUF(PSHUFLW, mi)
698     DestName = getRegName(MI->getOperand(0).getReg());
699     if (MI->getOperand(NumOperands - 1).isImm())
700       DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
701                         MI->getOperand(NumOperands - 1).getImm(),
702                         ShuffleMask);
703     break;
704 
705   case X86::MMX_PSHUFWri:
706     Src1Name = getRegName(MI->getOperand(1).getReg());
707     LLVM_FALLTHROUGH;
708 
709   case X86::MMX_PSHUFWmi:
710     DestName = getRegName(MI->getOperand(0).getReg());
711     if (MI->getOperand(NumOperands - 1).isImm())
712       DecodePSHUFMask(MVT::v4i16,
713                       MI->getOperand(NumOperands - 1).getImm(),
714                       ShuffleMask);
715     break;
716 
717   case X86::PSWAPDrr:
718     Src1Name = getRegName(MI->getOperand(1).getReg());
719     LLVM_FALLTHROUGH;
720 
721   case X86::PSWAPDrm:
722     DestName = getRegName(MI->getOperand(0).getReg());
723     DecodePSWAPMask(MVT::v2i32, ShuffleMask);
724     break;
725 
726   CASE_UNPCK(PUNPCKHBW, r)
727   case X86::MMX_PUNPCKHBWirr:
728     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
729     RegForm = true;
730     LLVM_FALLTHROUGH;
731 
732   CASE_UNPCK(PUNPCKHBW, m)
733   case X86::MMX_PUNPCKHBWirm:
734     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
735     DestName = getRegName(MI->getOperand(0).getReg());
736     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
737     break;
738 
739   CASE_UNPCK(PUNPCKHWD, r)
740   case X86::MMX_PUNPCKHWDirr:
741     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
742     RegForm = true;
743     LLVM_FALLTHROUGH;
744 
745   CASE_UNPCK(PUNPCKHWD, m)
746   case X86::MMX_PUNPCKHWDirm:
747     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
748     DestName = getRegName(MI->getOperand(0).getReg());
749     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
750     break;
751 
752   CASE_UNPCK(PUNPCKHDQ, r)
753   case X86::MMX_PUNPCKHDQirr:
754     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
755     RegForm = true;
756     LLVM_FALLTHROUGH;
757 
758   CASE_UNPCK(PUNPCKHDQ, m)
759   case X86::MMX_PUNPCKHDQirm:
760     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
761     DestName = getRegName(MI->getOperand(0).getReg());
762     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
763     break;
764 
765   CASE_UNPCK(PUNPCKHQDQ, r)
766     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
767     RegForm = true;
768     LLVM_FALLTHROUGH;
769 
770   CASE_UNPCK(PUNPCKHQDQ, m)
771     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
772     DestName = getRegName(MI->getOperand(0).getReg());
773     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
774     break;
775 
776   CASE_UNPCK(PUNPCKLBW, r)
777   case X86::MMX_PUNPCKLBWirr:
778     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
779     RegForm = true;
780     LLVM_FALLTHROUGH;
781 
782   CASE_UNPCK(PUNPCKLBW, m)
783   case X86::MMX_PUNPCKLBWirm:
784     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
785     DestName = getRegName(MI->getOperand(0).getReg());
786     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
787     break;
788 
789   CASE_UNPCK(PUNPCKLWD, r)
790   case X86::MMX_PUNPCKLWDirr:
791     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
792     RegForm = true;
793     LLVM_FALLTHROUGH;
794 
795   CASE_UNPCK(PUNPCKLWD, m)
796   case X86::MMX_PUNPCKLWDirm:
797     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
798     DestName = getRegName(MI->getOperand(0).getReg());
799     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
800     break;
801 
802   CASE_UNPCK(PUNPCKLDQ, r)
803   case X86::MMX_PUNPCKLDQirr:
804     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
805     RegForm = true;
806     LLVM_FALLTHROUGH;
807 
808   CASE_UNPCK(PUNPCKLDQ, m)
809   case X86::MMX_PUNPCKLDQirm:
810     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
811     DestName = getRegName(MI->getOperand(0).getReg());
812     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
813     break;
814 
815   CASE_UNPCK(PUNPCKLQDQ, r)
816     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
817     RegForm = true;
818     LLVM_FALLTHROUGH;
819 
820   CASE_UNPCK(PUNPCKLQDQ, m)
821     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
822     DestName = getRegName(MI->getOperand(0).getReg());
823     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
824     break;
825 
826   CASE_SHUF(SHUFPD, rri)
827     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
828     RegForm = true;
829     LLVM_FALLTHROUGH;
830 
831   CASE_SHUF(SHUFPD, rmi)
832     if (MI->getOperand(NumOperands - 1).isImm())
833       DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
834                       MI->getOperand(NumOperands - 1).getImm(),
835                       ShuffleMask);
836     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
837     DestName = getRegName(MI->getOperand(0).getReg());
838     break;
839 
840   CASE_SHUF(SHUFPS, rri)
841     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
842     RegForm = true;
843     LLVM_FALLTHROUGH;
844 
845   CASE_SHUF(SHUFPS, rmi)
846     if (MI->getOperand(NumOperands - 1).isImm())
847       DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
848                       MI->getOperand(NumOperands - 1).getImm(),
849                       ShuffleMask);
850     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
851     DestName = getRegName(MI->getOperand(0).getReg());
852     break;
853 
854   CASE_VSHUF(64X2, r)
855     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
856     RegForm = true;
857     LLVM_FALLTHROUGH;
858 
859   CASE_VSHUF(64X2, m)
860     decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0),
861                               MI->getOperand(NumOperands - 1).getImm(),
862                               ShuffleMask);
863     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
864     DestName = getRegName(MI->getOperand(0).getReg());
865     break;
866 
867   CASE_VSHUF(32X4, r)
868     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
869     RegForm = true;
870     LLVM_FALLTHROUGH;
871 
872   CASE_VSHUF(32X4, m)
873     decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0),
874                               MI->getOperand(NumOperands - 1).getImm(),
875                               ShuffleMask);
876     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
877     DestName = getRegName(MI->getOperand(0).getReg());
878     break;
879 
880   CASE_UNPCK(UNPCKLPD, r)
881     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
882     RegForm = true;
883     LLVM_FALLTHROUGH;
884 
885   CASE_UNPCK(UNPCKLPD, m)
886     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
887     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
888     DestName = getRegName(MI->getOperand(0).getReg());
889     break;
890 
891   CASE_UNPCK(UNPCKLPS, r)
892     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
893     RegForm = true;
894     LLVM_FALLTHROUGH;
895 
896   CASE_UNPCK(UNPCKLPS, m)
897     DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
898     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
899     DestName = getRegName(MI->getOperand(0).getReg());
900     break;
901 
902   CASE_UNPCK(UNPCKHPD, r)
903     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
904     RegForm = true;
905     LLVM_FALLTHROUGH;
906 
907   CASE_UNPCK(UNPCKHPD, m)
908     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
909     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
910     DestName = getRegName(MI->getOperand(0).getReg());
911     break;
912 
913   CASE_UNPCK(UNPCKHPS, r)
914     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
915     RegForm = true;
916     LLVM_FALLTHROUGH;
917 
918   CASE_UNPCK(UNPCKHPS, m)
919     DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
920     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
921     DestName = getRegName(MI->getOperand(0).getReg());
922     break;
923 
924   CASE_VPERMILPI(PERMILPS, r)
925     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
926     LLVM_FALLTHROUGH;
927 
928   CASE_VPERMILPI(PERMILPS, m)
929     if (MI->getOperand(NumOperands - 1).isImm())
930       DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
931                       MI->getOperand(NumOperands - 1).getImm(),
932                       ShuffleMask);
933     DestName = getRegName(MI->getOperand(0).getReg());
934     break;
935 
936   CASE_VPERMILPI(PERMILPD, r)
937     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
938     LLVM_FALLTHROUGH;
939 
940   CASE_VPERMILPI(PERMILPD, m)
941     if (MI->getOperand(NumOperands - 1).isImm())
942       DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
943                       MI->getOperand(NumOperands - 1).getImm(),
944                       ShuffleMask);
945     DestName = getRegName(MI->getOperand(0).getReg());
946     break;
947 
948   case X86::VPERM2F128rr:
949   case X86::VPERM2I128rr:
950     Src2Name = getRegName(MI->getOperand(2).getReg());
951     LLVM_FALLTHROUGH;
952 
953   case X86::VPERM2F128rm:
954   case X86::VPERM2I128rm:
955     // For instruction comments purpose, assume the 256-bit vector is v4i64.
956     if (MI->getOperand(NumOperands - 1).isImm())
957       DecodeVPERM2X128Mask(MVT::v4i64,
958                            MI->getOperand(NumOperands - 1).getImm(),
959                            ShuffleMask);
960     Src1Name = getRegName(MI->getOperand(1).getReg());
961     DestName = getRegName(MI->getOperand(0).getReg());
962     break;
963 
964   CASE_VPERM(PERMPD, r)
965     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
966     LLVM_FALLTHROUGH;
967 
968   CASE_VPERM(PERMPD, m)
969     if (MI->getOperand(NumOperands - 1).isImm())
970       DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0),
971                       MI->getOperand(NumOperands - 1).getImm(),
972                       ShuffleMask);
973     DestName = getRegName(MI->getOperand(0).getReg());
974     break;
975 
976   CASE_VPERM(PERMQ, r)
977     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
978     LLVM_FALLTHROUGH;
979 
980   CASE_VPERM(PERMQ, m)
981     if (MI->getOperand(NumOperands - 1).isImm())
982       DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0),
983                       MI->getOperand(NumOperands - 1).getImm(),
984                       ShuffleMask);
985     DestName = getRegName(MI->getOperand(0).getReg());
986     break;
987 
988   case X86::MOVSDrr:
989   case X86::VMOVSDrr:
990   case X86::VMOVSDZrr:
991     Src2Name = getRegName(MI->getOperand(2).getReg());
992     Src1Name = getRegName(MI->getOperand(1).getReg());
993     LLVM_FALLTHROUGH;
994 
995   case X86::MOVSDrm:
996   case X86::VMOVSDrm:
997   case X86::VMOVSDZrm:
998     DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
999     DestName = getRegName(MI->getOperand(0).getReg());
1000     break;
1001 
1002   case X86::MOVSSrr:
1003   case X86::VMOVSSrr:
1004   case X86::VMOVSSZrr:
1005     Src2Name = getRegName(MI->getOperand(2).getReg());
1006     Src1Name = getRegName(MI->getOperand(1).getReg());
1007     LLVM_FALLTHROUGH;
1008 
1009   case X86::MOVSSrm:
1010   case X86::VMOVSSrm:
1011   case X86::VMOVSSZrm:
1012     DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
1013     DestName = getRegName(MI->getOperand(0).getReg());
1014     break;
1015 
1016   case X86::MOVPQI2QIrr:
1017   case X86::MOVZPQILo2PQIrr:
1018   case X86::VMOVPQI2QIrr:
1019   case X86::VMOVZPQILo2PQIrr:
1020   case X86::VMOVZPQILo2PQIZrr:
1021     Src1Name = getRegName(MI->getOperand(1).getReg());
1022     LLVM_FALLTHROUGH;
1023 
1024   case X86::MOVQI2PQIrm:
1025   case X86::VMOVQI2PQIrm:
1026   case X86::VMOVQI2PQIZrm:
1027     DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
1028     DestName = getRegName(MI->getOperand(0).getReg());
1029     break;
1030 
1031   case X86::MOVDI2PDIrm:
1032   case X86::VMOVDI2PDIrm:
1033   case X86::VMOVDI2PDIZrm:
1034     DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
1035     DestName = getRegName(MI->getOperand(0).getReg());
1036     break;
1037 
1038   case X86::EXTRQI:
1039     if (MI->getOperand(2).isImm() &&
1040         MI->getOperand(3).isImm())
1041       DecodeEXTRQIMask(MVT::v16i8, MI->getOperand(2).getImm(),
1042                        MI->getOperand(3).getImm(),
1043                        ShuffleMask);
1044 
1045     DestName = getRegName(MI->getOperand(0).getReg());
1046     Src1Name = getRegName(MI->getOperand(1).getReg());
1047     break;
1048 
1049   case X86::INSERTQI:
1050     if (MI->getOperand(3).isImm() &&
1051         MI->getOperand(4).isImm())
1052       DecodeINSERTQIMask(MVT::v16i8, MI->getOperand(3).getImm(),
1053                          MI->getOperand(4).getImm(),
1054                          ShuffleMask);
1055 
1056     DestName = getRegName(MI->getOperand(0).getReg());
1057     Src1Name = getRegName(MI->getOperand(1).getReg());
1058     Src2Name = getRegName(MI->getOperand(2).getReg());
1059     break;
1060 
1061   case X86::VBROADCASTF128:
1062   case X86::VBROADCASTI128:
1063   CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
1064   CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
1065     DecodeSubVectorBroadcast(MVT::v4f64, MVT::v2f64, ShuffleMask);
1066     DestName = getRegName(MI->getOperand(0).getReg());
1067     break;
1068   CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm)
1069   CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm)
1070     DecodeSubVectorBroadcast(MVT::v8f64, MVT::v2f64, ShuffleMask);
1071     DestName = getRegName(MI->getOperand(0).getReg());
1072     break;
1073   CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm)
1074   CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm)
1075     DecodeSubVectorBroadcast(MVT::v8f64, MVT::v4f64, ShuffleMask);
1076     DestName = getRegName(MI->getOperand(0).getReg());
1077     break;
1078   CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1079   CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1080     DecodeSubVectorBroadcast(MVT::v8f32, MVT::v4f32, ShuffleMask);
1081     DestName = getRegName(MI->getOperand(0).getReg());
1082     break;
1083   CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm)
1084   CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm)
1085     DecodeSubVectorBroadcast(MVT::v16f32, MVT::v4f32, ShuffleMask);
1086     DestName = getRegName(MI->getOperand(0).getReg());
1087     break;
1088   CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm)
1089   CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm)
1090     DecodeSubVectorBroadcast(MVT::v16f32, MVT::v8f32, ShuffleMask);
1091     DestName = getRegName(MI->getOperand(0).getReg());
1092     break;
1093   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r)
1094   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r)
1095     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1096     LLVM_FALLTHROUGH;
1097   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m)
1098   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m)
1099     DecodeSubVectorBroadcast(MVT::v8f32, MVT::v2f32, ShuffleMask);
1100     DestName = getRegName(MI->getOperand(0).getReg());
1101     break;
1102   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r)
1103   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r)
1104     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1105     LLVM_FALLTHROUGH;
1106   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m)
1107   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m)
1108     DecodeSubVectorBroadcast(MVT::v16f32, MVT::v2f32, ShuffleMask);
1109     DestName = getRegName(MI->getOperand(0).getReg());
1110     break;
1111 
1112   CASE_PMOVZX(PMOVZXBW, r)
1113   CASE_PMOVZX(PMOVZXBD, r)
1114   CASE_PMOVZX(PMOVZXBQ, r)
1115     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1116     LLVM_FALLTHROUGH;
1117 
1118   CASE_PMOVZX(PMOVZXBW, m)
1119   CASE_PMOVZX(PMOVZXBD, m)
1120   CASE_PMOVZX(PMOVZXBQ, m)
1121     DecodeZeroExtendMask(MVT::i8, getZeroExtensionResultType(MI), ShuffleMask);
1122     DestName = getRegName(MI->getOperand(0).getReg());
1123     break;
1124 
1125   CASE_PMOVZX(PMOVZXWD, r)
1126   CASE_PMOVZX(PMOVZXWQ, r)
1127     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1128     LLVM_FALLTHROUGH;
1129 
1130   CASE_PMOVZX(PMOVZXWD, m)
1131   CASE_PMOVZX(PMOVZXWQ, m)
1132     DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask);
1133     DestName = getRegName(MI->getOperand(0).getReg());
1134     break;
1135 
1136   CASE_PMOVZX(PMOVZXDQ, r)
1137     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1138     LLVM_FALLTHROUGH;
1139 
1140   CASE_PMOVZX(PMOVZXDQ, m)
1141     DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask);
1142     DestName = getRegName(MI->getOperand(0).getReg());
1143     break;
1144   }
1145 
1146   // The only comments we decode are shuffles, so give up if we were unable to
1147   // decode a shuffle mask.
1148   if (ShuffleMask.empty())
1149     return false;
1150 
1151   if (!DestName) DestName = Src1Name;
1152   OS << (DestName ? getMaskName(MI, DestName, getRegName) : "mem") << " = ";
1153 
1154   // If the two sources are the same, canonicalize the input elements to be
1155   // from the first src so that we get larger element spans.
1156   if (Src1Name == Src2Name) {
1157     for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1158       if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
1159           ShuffleMask[i] >= (int)e)   // From second mask.
1160         ShuffleMask[i] -= e;
1161     }
1162   }
1163 
1164   // The shuffle mask specifies which elements of the src1/src2 fill in the
1165   // destination, with a few sentinel values.  Loop through and print them
1166   // out.
1167   for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1168     if (i != 0)
1169       OS << ',';
1170     if (ShuffleMask[i] == SM_SentinelZero) {
1171       OS << "zero";
1172       continue;
1173     }
1174 
1175     // Otherwise, it must come from src1 or src2.  Print the span of elements
1176     // that comes from this src.
1177     bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1178     const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1179     OS << (SrcName ? SrcName : "mem") << '[';
1180     bool IsFirst = true;
1181     while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1182            (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1183       if (!IsFirst)
1184         OS << ',';
1185       else
1186         IsFirst = false;
1187       if (ShuffleMask[i] == SM_SentinelUndef)
1188         OS << "u";
1189       else
1190         OS << ShuffleMask[i] % ShuffleMask.size();
1191       ++i;
1192     }
1193     OS << ']';
1194     --i; // For loop increments element #.
1195   }
1196 
1197   // We successfully added a comment to this instruction.
1198   return true;
1199 }
1200