1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86InstComments.h"
16 #include "X86ATTInstPrinter.h"
17 #include "MCTargetDesc/X86BaseInfo.h"
18 #include "MCTargetDesc/X86MCTargetDesc.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/raw_ostream.h"
23 
24 using namespace llvm;
25 
26 #define CASE_SSE_INS_COMMON(Inst, src)            \
27   case X86::Inst##src:
28 
29 #define CASE_AVX_INS_COMMON(Inst, Suffix, src)    \
30   case X86::V##Inst##Suffix##src:
31 
32 #define CASE_MASK_INS_COMMON(Inst, Suffix, src)   \
33   case X86::V##Inst##Suffix##src##k:
34 
35 #define CASE_MASKZ_INS_COMMON(Inst, Suffix, src)  \
36   case X86::V##Inst##Suffix##src##kz:
37 
38 #define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
39   CASE_AVX_INS_COMMON(Inst, Suffix, src)          \
40   CASE_MASK_INS_COMMON(Inst, Suffix, src)         \
41   CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
42 
43 #define CASE_MOVDUP(Inst, src)                    \
44   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
45   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
46   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
47   CASE_AVX_INS_COMMON(Inst, , r##src)             \
48   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
49   CASE_SSE_INS_COMMON(Inst, r##src)
50 
51 #define CASE_MASK_MOVDUP(Inst, src)               \
52   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
53   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
54   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
55 
56 #define CASE_MASKZ_MOVDUP(Inst, src)              \
57   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
58   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
59   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
60 
61 #define CASE_PMOVZX(Inst, src)                    \
62   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
63   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
64   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
65   CASE_AVX_INS_COMMON(Inst, , r##src)             \
66   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
67   CASE_SSE_INS_COMMON(Inst, r##src)
68 
69 #define CASE_MASK_PMOVZX(Inst, src)               \
70   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
71   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
72   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
73 
74 #define CASE_MASKZ_PMOVZX(Inst, src)              \
75   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
76   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
77   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
78 
79 #define CASE_UNPCK(Inst, src)                     \
80   CASE_AVX512_INS_COMMON(Inst, Z, r##src)         \
81   CASE_AVX512_INS_COMMON(Inst, Z256, r##src)      \
82   CASE_AVX512_INS_COMMON(Inst, Z128, r##src)      \
83   CASE_AVX_INS_COMMON(Inst, , r##src)             \
84   CASE_AVX_INS_COMMON(Inst, Y, r##src)            \
85   CASE_SSE_INS_COMMON(Inst, r##src)
86 
87 #define CASE_MASK_UNPCK(Inst, src)                \
88   CASE_MASK_INS_COMMON(Inst, Z, r##src)           \
89   CASE_MASK_INS_COMMON(Inst, Z256, r##src)        \
90   CASE_MASK_INS_COMMON(Inst, Z128, r##src)
91 
92 #define CASE_MASKZ_UNPCK(Inst, src)               \
93   CASE_MASKZ_INS_COMMON(Inst, Z, r##src)          \
94   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src)       \
95   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
96 
97 #define CASE_SHUF(Inst, suf)                      \
98   CASE_AVX512_INS_COMMON(Inst, Z, suf)            \
99   CASE_AVX512_INS_COMMON(Inst, Z256, suf)         \
100   CASE_AVX512_INS_COMMON(Inst, Z128, suf)         \
101   CASE_AVX_INS_COMMON(Inst, , suf)                \
102   CASE_AVX_INS_COMMON(Inst, Y, suf)               \
103   CASE_SSE_INS_COMMON(Inst, suf)
104 
105 #define CASE_MASK_SHUF(Inst, src)                 \
106   CASE_MASK_INS_COMMON(Inst, Z, r##src##i)        \
107   CASE_MASK_INS_COMMON(Inst, Z256, r##src##i)     \
108   CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
109 
110 #define CASE_MASKZ_SHUF(Inst, src)                \
111   CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i)       \
112   CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i)    \
113   CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
114 
115 #define CASE_VPERMILPI(Inst, src)                 \
116   CASE_AVX512_INS_COMMON(Inst, Z, src##i)         \
117   CASE_AVX512_INS_COMMON(Inst, Z256, src##i)      \
118   CASE_AVX512_INS_COMMON(Inst, Z128, src##i)      \
119   CASE_AVX_INS_COMMON(Inst, , src##i)             \
120   CASE_AVX_INS_COMMON(Inst, Y, src##i)
121 
122 #define CASE_MASK_VPERMILPI(Inst, src)            \
123   CASE_MASK_INS_COMMON(Inst, Z, src##i)           \
124   CASE_MASK_INS_COMMON(Inst, Z256, src##i)        \
125   CASE_MASK_INS_COMMON(Inst, Z128, src##i)
126 
127 #define CASE_MASKZ_VPERMILPI(Inst, src)           \
128   CASE_MASKZ_INS_COMMON(Inst, Z, src##i)          \
129   CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)       \
130   CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
131 
132 #define CASE_VPERM(Inst, src)                     \
133   CASE_AVX512_INS_COMMON(Inst, Z, src##i)         \
134   CASE_AVX512_INS_COMMON(Inst, Z256, src##i)      \
135   CASE_AVX_INS_COMMON(Inst, Y, src##i)
136 
137 #define CASE_MASK_VPERM(Inst, src)                \
138   CASE_MASK_INS_COMMON(Inst, Z, src##i)           \
139   CASE_MASK_INS_COMMON(Inst, Z256, src##i)
140 
141 #define CASE_MASKZ_VPERM(Inst, src)               \
142   CASE_MASKZ_INS_COMMON(Inst, Z, src##i)          \
143   CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
144 
145 #define CASE_VSHUF(Inst, src)                          \
146   CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i)    \
147   CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i)    \
148   CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
149   CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
150 
151 #define CASE_MASK_VSHUF(Inst, src)                    \
152   CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i)     \
153   CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i)     \
154   CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i)  \
155   CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
156 
157 #define CASE_MASKZ_VSHUF(Inst, src)                   \
158   CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i)    \
159   CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i)    \
160   CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
161   CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
162 
163 #define CASE_AVX512_FMA(Inst, suf)                \
164   CASE_AVX512_INS_COMMON(Inst, Z, suf)            \
165   CASE_AVX512_INS_COMMON(Inst, Z256, suf)         \
166   CASE_AVX512_INS_COMMON(Inst, Z128, suf)
167 
168 #define CASE_FMA(Inst, suf)                       \
169   CASE_AVX512_FMA(Inst, suf)                      \
170   CASE_AVX_INS_COMMON(Inst, , suf)                \
171   CASE_AVX_INS_COMMON(Inst, Y, suf)
172 
173 #define CASE_FMA_PACKED_REG(Inst)                 \
174   CASE_FMA(Inst##PD, r)                           \
175   CASE_FMA(Inst##PS, r)
176 
177 #define CASE_FMA_PACKED_MEM(Inst)                 \
178   CASE_FMA(Inst##PD, m)                           \
179   CASE_FMA(Inst##PS, m)                           \
180   CASE_AVX512_FMA(Inst##PD, mb)                   \
181   CASE_AVX512_FMA(Inst##PS, mb)
182 
183 #define CASE_FMA_SCALAR_REG(Inst)                 \
184   CASE_AVX_INS_COMMON(Inst##SD, , r)              \
185   CASE_AVX_INS_COMMON(Inst##SS, , r)              \
186   CASE_AVX_INS_COMMON(Inst##SD, , r_Int)          \
187   CASE_AVX_INS_COMMON(Inst##SS, , r_Int)          \
188   CASE_AVX_INS_COMMON(Inst##SD, Z, r)             \
189   CASE_AVX_INS_COMMON(Inst##SS, Z, r)             \
190   CASE_AVX512_INS_COMMON(Inst##SD, Z, r_Int)      \
191   CASE_AVX512_INS_COMMON(Inst##SS, Z, r_Int)
192 
193 #define CASE_FMA_SCALAR_MEM(Inst)                 \
194   CASE_AVX_INS_COMMON(Inst##SD, , m)              \
195   CASE_AVX_INS_COMMON(Inst##SS, , m)              \
196   CASE_AVX_INS_COMMON(Inst##SD, , m_Int)          \
197   CASE_AVX_INS_COMMON(Inst##SS, , m_Int)          \
198   CASE_AVX_INS_COMMON(Inst##SD, Z, m)             \
199   CASE_AVX_INS_COMMON(Inst##SS, Z, m)             \
200   CASE_AVX512_INS_COMMON(Inst##SD, Z, m_Int)      \
201   CASE_AVX512_INS_COMMON(Inst##SS, Z, m_Int)
202 
203 static unsigned getVectorRegSize(unsigned RegNo) {
204   if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
205     return 512;
206   if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
207     return 256;
208   if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
209     return 128;
210   if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
211     return 64;
212 
213   llvm_unreachable("Unknown vector reg!");
214 }
215 
216 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
217                                      unsigned OperandIndex) {
218   unsigned OpReg = MI->getOperand(OperandIndex).getReg();
219   return getVectorRegSize(OpReg) / ScalarSize;
220 }
221 
222 static const char *getRegName(unsigned Reg) {
223   return X86ATTInstPrinter::getRegisterName(Reg);
224 }
225 
226 /// Wraps the destination register name with AVX512 mask/maskz filtering.
227 static void printMasking(raw_ostream &OS, const MCInst *MI,
228                          const MCInstrInfo &MCII) {
229   const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
230   uint64_t TSFlags = Desc.TSFlags;
231 
232   if (!(TSFlags & X86II::EVEX_K))
233     return;
234 
235   bool MaskWithZero = (TSFlags & X86II::EVEX_Z);
236   unsigned MaskOp = Desc.getNumDefs();
237 
238   if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1)
239     ++MaskOp;
240 
241   const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
242 
243   // MASK: zmmX {%kY}
244   OS << " {%" << MaskRegName << "}";
245 
246   // MASKZ: zmmX {%kY} {z}
247   if (MaskWithZero)
248     OS << " {z}";
249 }
250 
251 static bool printFMA3Comments(const MCInst *MI, raw_ostream &OS) {
252   const char *Mul1Name = nullptr, *Mul2Name = nullptr, *AccName = nullptr;
253   unsigned NumOperands = MI->getNumOperands();
254   bool RegForm = false;
255   bool Negate = false;
256   StringRef AccStr = "+";
257 
258   // The operands for FMA instructions without rounding fall into two forms.
259   //  dest, src1, src2, src3
260   //  dest, src1, mask, src2, src3
261   // Where src3 is either a register or 5 memory address operands. So to find
262   // dest and src1 we can index from the front. To find src2 and src3 we can
263   // index from the end by taking into account memory vs register form when
264   // finding src2.
265 
266   switch (MI->getOpcode()) {
267   default:
268     return false;
269   CASE_FMA_PACKED_REG(FMADD132)
270   CASE_FMA_SCALAR_REG(FMADD132)
271     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
272     RegForm = true;
273     LLVM_FALLTHROUGH;
274   CASE_FMA_PACKED_MEM(FMADD132)
275   CASE_FMA_SCALAR_MEM(FMADD132)
276     AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
277     Mul1Name = getRegName(MI->getOperand(1).getReg());
278     break;
279 
280   CASE_FMA_PACKED_REG(FMADD213)
281   CASE_FMA_SCALAR_REG(FMADD213)
282     AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
283     RegForm = true;
284     LLVM_FALLTHROUGH;
285   CASE_FMA_PACKED_MEM(FMADD213)
286   CASE_FMA_SCALAR_MEM(FMADD213)
287     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
288     Mul2Name = getRegName(MI->getOperand(1).getReg());
289     break;
290 
291   CASE_FMA_PACKED_REG(FMADD231)
292   CASE_FMA_SCALAR_REG(FMADD231)
293     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
294     RegForm = true;
295     LLVM_FALLTHROUGH;
296   CASE_FMA_PACKED_MEM(FMADD231)
297   CASE_FMA_SCALAR_MEM(FMADD231)
298     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
299     AccName = getRegName(MI->getOperand(1).getReg());
300     break;
301 
302   CASE_FMA_PACKED_REG(FMSUB132)
303   CASE_FMA_SCALAR_REG(FMSUB132)
304     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
305     RegForm = true;
306     LLVM_FALLTHROUGH;
307   CASE_FMA_PACKED_MEM(FMSUB132)
308   CASE_FMA_SCALAR_MEM(FMSUB132)
309     AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
310     Mul1Name = getRegName(MI->getOperand(1).getReg());
311     AccStr = "-";
312     break;
313 
314   CASE_FMA_PACKED_REG(FMSUB213)
315   CASE_FMA_SCALAR_REG(FMSUB213)
316     AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
317     RegForm = true;
318     LLVM_FALLTHROUGH;
319   CASE_FMA_PACKED_MEM(FMSUB213)
320   CASE_FMA_SCALAR_MEM(FMSUB213)
321     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
322     Mul2Name = getRegName(MI->getOperand(1).getReg());
323     AccStr = "-";
324     break;
325 
326   CASE_FMA_PACKED_REG(FMSUB231)
327   CASE_FMA_SCALAR_REG(FMSUB231)
328     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
329     RegForm = true;
330     LLVM_FALLTHROUGH;
331   CASE_FMA_PACKED_MEM(FMSUB231)
332   CASE_FMA_SCALAR_MEM(FMSUB231)
333     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
334     AccName = getRegName(MI->getOperand(1).getReg());
335     AccStr = "-";
336     break;
337 
338   CASE_FMA_PACKED_REG(FNMADD132)
339   CASE_FMA_SCALAR_REG(FNMADD132)
340     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
341     RegForm = true;
342     LLVM_FALLTHROUGH;
343   CASE_FMA_PACKED_MEM(FNMADD132)
344   CASE_FMA_SCALAR_MEM(FNMADD132)
345     AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
346     Mul1Name = getRegName(MI->getOperand(1).getReg());
347     Negate = true;
348     break;
349 
350   CASE_FMA_PACKED_REG(FNMADD213)
351   CASE_FMA_SCALAR_REG(FNMADD213)
352     AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
353     RegForm = true;
354     LLVM_FALLTHROUGH;
355   CASE_FMA_PACKED_MEM(FNMADD213)
356   CASE_FMA_SCALAR_MEM(FNMADD213)
357     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
358     Mul2Name = getRegName(MI->getOperand(1).getReg());
359     Negate = true;
360     break;
361 
362   CASE_FMA_PACKED_REG(FNMADD231)
363   CASE_FMA_SCALAR_REG(FNMADD231)
364     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
365     RegForm = true;
366     LLVM_FALLTHROUGH;
367   CASE_FMA_PACKED_MEM(FNMADD231)
368   CASE_FMA_SCALAR_MEM(FNMADD231)
369     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
370     AccName = getRegName(MI->getOperand(1).getReg());
371     Negate = true;
372     break;
373 
374   CASE_FMA_PACKED_REG(FNMSUB132)
375   CASE_FMA_SCALAR_REG(FNMSUB132)
376     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
377     RegForm = true;
378     LLVM_FALLTHROUGH;
379   CASE_FMA_PACKED_MEM(FNMSUB132)
380   CASE_FMA_SCALAR_MEM(FNMSUB132)
381     AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
382     Mul1Name = getRegName(MI->getOperand(1).getReg());
383     AccStr = "-";
384     Negate = true;
385     break;
386 
387   CASE_FMA_PACKED_REG(FNMSUB213)
388   CASE_FMA_SCALAR_REG(FNMSUB213)
389     AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
390     RegForm = true;
391     LLVM_FALLTHROUGH;
392   CASE_FMA_PACKED_MEM(FNMSUB213)
393   CASE_FMA_SCALAR_MEM(FNMSUB213)
394     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
395     Mul2Name = getRegName(MI->getOperand(1).getReg());
396     AccStr = "-";
397     Negate = true;
398     break;
399 
400   CASE_FMA_PACKED_REG(FNMSUB231)
401   CASE_FMA_SCALAR_REG(FNMSUB231)
402     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
403     RegForm = true;
404     LLVM_FALLTHROUGH;
405   CASE_FMA_PACKED_MEM(FNMSUB231)
406   CASE_FMA_SCALAR_MEM(FNMSUB231)
407     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
408     AccName = getRegName(MI->getOperand(1).getReg());
409     AccStr = "-";
410     Negate = true;
411     break;
412 
413   CASE_FMA_PACKED_REG(FMADDSUB132)
414     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
415     RegForm = true;
416     LLVM_FALLTHROUGH;
417   CASE_FMA_PACKED_MEM(FMADDSUB132)
418     AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
419     Mul1Name = getRegName(MI->getOperand(1).getReg());
420     AccStr = "+/-";
421     break;
422 
423   CASE_FMA_PACKED_REG(FMADDSUB213)
424     AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
425     RegForm = true;
426     LLVM_FALLTHROUGH;
427   CASE_FMA_PACKED_MEM(FMADDSUB213)
428     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
429     Mul2Name = getRegName(MI->getOperand(1).getReg());
430     AccStr = "+/-";
431     break;
432 
433   CASE_FMA_PACKED_REG(FMADDSUB231)
434     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
435     RegForm = true;
436     LLVM_FALLTHROUGH;
437   CASE_FMA_PACKED_MEM(FMADDSUB231)
438     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
439     AccName = getRegName(MI->getOperand(1).getReg());
440     AccStr = "+/-";
441     break;
442 
443   CASE_FMA_PACKED_REG(FMSUBADD132)
444     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
445     RegForm = true;
446     LLVM_FALLTHROUGH;
447   CASE_FMA_PACKED_MEM(FMSUBADD132)
448     AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
449     Mul1Name = getRegName(MI->getOperand(1).getReg());
450     AccStr = "-/+";
451     break;
452 
453   CASE_FMA_PACKED_REG(FMSUBADD213)
454     AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
455     RegForm = true;
456     LLVM_FALLTHROUGH;
457   CASE_FMA_PACKED_MEM(FMSUBADD213)
458     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
459     Mul2Name = getRegName(MI->getOperand(1).getReg());
460     AccStr = "-/+";
461     break;
462 
463   CASE_FMA_PACKED_REG(FMSUBADD231)
464     Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
465     RegForm = true;
466     LLVM_FALLTHROUGH;
467   CASE_FMA_PACKED_MEM(FMSUBADD231)
468     Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
469     AccName = getRegName(MI->getOperand(1).getReg());
470     AccStr = "-/+";
471     break;
472   }
473 
474   const char *DestName = getRegName(MI->getOperand(0).getReg());
475 
476   if (!Mul1Name) Mul1Name = "mem";
477   if (!Mul2Name) Mul2Name = "mem";
478   if (!AccName)  AccName = "mem";
479 
480   OS << DestName << " = ";
481   // TODO: Print masking information?
482 
483   if (Negate)
484     OS << '-';
485 
486   OS << '(' << Mul1Name << " * " << Mul2Name << ") " << AccStr << ' '
487      << AccName;
488 
489   return true;
490 }
491 
492 
493 //===----------------------------------------------------------------------===//
494 // Top Level Entrypoint
495 //===----------------------------------------------------------------------===//
496 
497 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
498 /// newline terminated strings to the specified string if desired.  This
499 /// information is shown in disassembly dumps when verbose assembly is enabled.
500 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
501                                   const MCInstrInfo &MCII) {
502   // If this is a shuffle operation, the switch should fill in this state.
503   SmallVector<int, 8> ShuffleMask;
504   const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
505   unsigned NumOperands = MI->getNumOperands();
506   bool RegForm = false;
507 
508   if (printFMA3Comments(MI, OS))
509     return true;
510 
511   switch (MI->getOpcode()) {
512   default:
513     // Not an instruction for which we can decode comments.
514     return false;
515 
516   case X86::BLENDPDrri:
517   case X86::VBLENDPDrri:
518   case X86::VBLENDPDYrri:
519     Src2Name = getRegName(MI->getOperand(2).getReg());
520     LLVM_FALLTHROUGH;
521   case X86::BLENDPDrmi:
522   case X86::VBLENDPDrmi:
523   case X86::VBLENDPDYrmi:
524     if (MI->getOperand(NumOperands - 1).isImm())
525       DecodeBLENDMask(getRegOperandNumElts(MI, 64, 0),
526                       MI->getOperand(NumOperands - 1).getImm(),
527                       ShuffleMask);
528     Src1Name = getRegName(MI->getOperand(1).getReg());
529     DestName = getRegName(MI->getOperand(0).getReg());
530     break;
531 
532   case X86::BLENDPSrri:
533   case X86::VBLENDPSrri:
534   case X86::VBLENDPSYrri:
535     Src2Name = getRegName(MI->getOperand(2).getReg());
536     LLVM_FALLTHROUGH;
537   case X86::BLENDPSrmi:
538   case X86::VBLENDPSrmi:
539   case X86::VBLENDPSYrmi:
540     if (MI->getOperand(NumOperands - 1).isImm())
541       DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
542                       MI->getOperand(NumOperands - 1).getImm(),
543                       ShuffleMask);
544     Src1Name = getRegName(MI->getOperand(1).getReg());
545     DestName = getRegName(MI->getOperand(0).getReg());
546     break;
547 
548   case X86::PBLENDWrri:
549   case X86::VPBLENDWrri:
550   case X86::VPBLENDWYrri:
551     Src2Name = getRegName(MI->getOperand(2).getReg());
552     LLVM_FALLTHROUGH;
553   case X86::PBLENDWrmi:
554   case X86::VPBLENDWrmi:
555   case X86::VPBLENDWYrmi:
556     if (MI->getOperand(NumOperands - 1).isImm())
557       DecodeBLENDMask(getRegOperandNumElts(MI, 16, 0),
558                       MI->getOperand(NumOperands - 1).getImm(),
559                       ShuffleMask);
560     Src1Name = getRegName(MI->getOperand(1).getReg());
561     DestName = getRegName(MI->getOperand(0).getReg());
562     break;
563 
564   case X86::VPBLENDDrri:
565   case X86::VPBLENDDYrri:
566     Src2Name = getRegName(MI->getOperand(2).getReg());
567     LLVM_FALLTHROUGH;
568   case X86::VPBLENDDrmi:
569   case X86::VPBLENDDYrmi:
570     if (MI->getOperand(NumOperands - 1).isImm())
571       DecodeBLENDMask(getRegOperandNumElts(MI, 32, 0),
572                       MI->getOperand(NumOperands - 1).getImm(),
573                       ShuffleMask);
574     Src1Name = getRegName(MI->getOperand(1).getReg());
575     DestName = getRegName(MI->getOperand(0).getReg());
576     break;
577 
578   case X86::INSERTPSrr:
579   case X86::VINSERTPSrr:
580   case X86::VINSERTPSZrr:
581     Src2Name = getRegName(MI->getOperand(2).getReg());
582     LLVM_FALLTHROUGH;
583   case X86::INSERTPSrm:
584   case X86::VINSERTPSrm:
585   case X86::VINSERTPSZrm:
586     DestName = getRegName(MI->getOperand(0).getReg());
587     Src1Name = getRegName(MI->getOperand(1).getReg());
588     if (MI->getOperand(NumOperands - 1).isImm())
589       DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
590                          ShuffleMask);
591     break;
592 
593   case X86::MOVLHPSrr:
594   case X86::VMOVLHPSrr:
595   case X86::VMOVLHPSZrr:
596     Src2Name = getRegName(MI->getOperand(2).getReg());
597     Src1Name = getRegName(MI->getOperand(1).getReg());
598     DestName = getRegName(MI->getOperand(0).getReg());
599     DecodeMOVLHPSMask(2, ShuffleMask);
600     break;
601 
602   case X86::MOVHLPSrr:
603   case X86::VMOVHLPSrr:
604   case X86::VMOVHLPSZrr:
605     Src2Name = getRegName(MI->getOperand(2).getReg());
606     Src1Name = getRegName(MI->getOperand(1).getReg());
607     DestName = getRegName(MI->getOperand(0).getReg());
608     DecodeMOVHLPSMask(2, ShuffleMask);
609     break;
610 
611   case X86::MOVHPDrm:
612   case X86::VMOVHPDrm:
613   case X86::VMOVHPDZ128rm:
614     Src1Name = getRegName(MI->getOperand(1).getReg());
615     DestName = getRegName(MI->getOperand(0).getReg());
616     DecodeInsertElementMask(2, 1, 1, ShuffleMask);
617     break;
618 
619   case X86::MOVHPSrm:
620   case X86::VMOVHPSrm:
621   case X86::VMOVHPSZ128rm:
622     Src1Name = getRegName(MI->getOperand(1).getReg());
623     DestName = getRegName(MI->getOperand(0).getReg());
624     DecodeInsertElementMask(4, 2, 2, ShuffleMask);
625     break;
626 
627   case X86::MOVLPDrm:
628   case X86::VMOVLPDrm:
629   case X86::VMOVLPDZ128rm:
630     Src1Name = getRegName(MI->getOperand(1).getReg());
631     DestName = getRegName(MI->getOperand(0).getReg());
632     DecodeInsertElementMask(2, 0, 1, ShuffleMask);
633     break;
634 
635   case X86::MOVLPSrm:
636   case X86::VMOVLPSrm:
637   case X86::VMOVLPSZ128rm:
638     Src1Name = getRegName(MI->getOperand(1).getReg());
639     DestName = getRegName(MI->getOperand(0).getReg());
640     DecodeInsertElementMask(4, 0, 2, ShuffleMask);
641     break;
642 
643   CASE_MOVDUP(MOVSLDUP, r)
644     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
645     LLVM_FALLTHROUGH;
646 
647   CASE_MOVDUP(MOVSLDUP, m)
648     DestName = getRegName(MI->getOperand(0).getReg());
649     DecodeMOVSLDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
650     break;
651 
652   CASE_MOVDUP(MOVSHDUP, r)
653     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
654     LLVM_FALLTHROUGH;
655 
656   CASE_MOVDUP(MOVSHDUP, m)
657     DestName = getRegName(MI->getOperand(0).getReg());
658     DecodeMOVSHDUPMask(getRegOperandNumElts(MI, 32, 0), ShuffleMask);
659     break;
660 
661   CASE_MOVDUP(MOVDDUP, r)
662     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
663     LLVM_FALLTHROUGH;
664 
665   CASE_MOVDUP(MOVDDUP, m)
666     DestName = getRegName(MI->getOperand(0).getReg());
667     DecodeMOVDDUPMask(getRegOperandNumElts(MI, 64, 0), ShuffleMask);
668     break;
669 
670   case X86::PSLLDQri:
671   case X86::VPSLLDQri:
672   case X86::VPSLLDQYri:
673   case X86::VPSLLDQZ128rr:
674   case X86::VPSLLDQZ256rr:
675   case X86::VPSLLDQZrr:
676     Src1Name = getRegName(MI->getOperand(1).getReg());
677     LLVM_FALLTHROUGH;
678   case X86::VPSLLDQZ128rm:
679   case X86::VPSLLDQZ256rm:
680   case X86::VPSLLDQZrm:
681     DestName = getRegName(MI->getOperand(0).getReg());
682     if (MI->getOperand(NumOperands - 1).isImm())
683       DecodePSLLDQMask(getRegOperandNumElts(MI, 8, 0),
684                        MI->getOperand(NumOperands - 1).getImm(),
685                        ShuffleMask);
686     break;
687 
688   case X86::PSRLDQri:
689   case X86::VPSRLDQri:
690   case X86::VPSRLDQYri:
691   case X86::VPSRLDQZ128rr:
692   case X86::VPSRLDQZ256rr:
693   case X86::VPSRLDQZrr:
694     Src1Name = getRegName(MI->getOperand(1).getReg());
695     LLVM_FALLTHROUGH;
696   case X86::VPSRLDQZ128rm:
697   case X86::VPSRLDQZ256rm:
698   case X86::VPSRLDQZrm:
699     DestName = getRegName(MI->getOperand(0).getReg());
700     if (MI->getOperand(NumOperands - 1).isImm())
701       DecodePSRLDQMask(getRegOperandNumElts(MI, 8, 0),
702                        MI->getOperand(NumOperands - 1).getImm(),
703                        ShuffleMask);
704     break;
705 
706   CASE_SHUF(PALIGNR, rri)
707     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
708     RegForm = true;
709     LLVM_FALLTHROUGH;
710 
711   CASE_SHUF(PALIGNR, rmi)
712     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
713     DestName = getRegName(MI->getOperand(0).getReg());
714     if (MI->getOperand(NumOperands - 1).isImm())
715       DecodePALIGNRMask(getRegOperandNumElts(MI, 8, 0),
716                         MI->getOperand(NumOperands - 1).getImm(),
717                         ShuffleMask);
718     break;
719 
720   CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
721   CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
722   CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
723     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
724     RegForm = true;
725     LLVM_FALLTHROUGH;
726 
727   CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
728   CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
729   CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
730     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
731     DestName = getRegName(MI->getOperand(0).getReg());
732     if (MI->getOperand(NumOperands - 1).isImm())
733       DecodeVALIGNMask(getRegOperandNumElts(MI, 64, 0),
734                        MI->getOperand(NumOperands - 1).getImm(),
735                        ShuffleMask);
736     break;
737 
738   CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
739   CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
740   CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
741     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
742     RegForm = true;
743     LLVM_FALLTHROUGH;
744 
745   CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
746   CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
747   CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
748     Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
749     DestName = getRegName(MI->getOperand(0).getReg());
750     if (MI->getOperand(NumOperands - 1).isImm())
751       DecodeVALIGNMask(getRegOperandNumElts(MI, 32, 0),
752                        MI->getOperand(NumOperands - 1).getImm(),
753                        ShuffleMask);
754     break;
755 
756   CASE_SHUF(PSHUFD, ri)
757     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
758     LLVM_FALLTHROUGH;
759 
760   CASE_SHUF(PSHUFD, mi)
761     DestName = getRegName(MI->getOperand(0).getReg());
762     if (MI->getOperand(NumOperands - 1).isImm())
763       DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
764                       MI->getOperand(NumOperands - 1).getImm(),
765                       ShuffleMask);
766     break;
767 
768   CASE_SHUF(PSHUFHW, ri)
769     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
770     LLVM_FALLTHROUGH;
771 
772   CASE_SHUF(PSHUFHW, mi)
773     DestName = getRegName(MI->getOperand(0).getReg());
774     if (MI->getOperand(NumOperands - 1).isImm())
775       DecodePSHUFHWMask(getRegOperandNumElts(MI, 16, 0),
776                         MI->getOperand(NumOperands - 1).getImm(),
777                         ShuffleMask);
778     break;
779 
780   CASE_SHUF(PSHUFLW, ri)
781     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
782     LLVM_FALLTHROUGH;
783 
784   CASE_SHUF(PSHUFLW, mi)
785     DestName = getRegName(MI->getOperand(0).getReg());
786     if (MI->getOperand(NumOperands - 1).isImm())
787       DecodePSHUFLWMask(getRegOperandNumElts(MI, 16, 0),
788                         MI->getOperand(NumOperands - 1).getImm(),
789                         ShuffleMask);
790     break;
791 
792   case X86::MMX_PSHUFWri:
793     Src1Name = getRegName(MI->getOperand(1).getReg());
794     LLVM_FALLTHROUGH;
795 
796   case X86::MMX_PSHUFWmi:
797     DestName = getRegName(MI->getOperand(0).getReg());
798     if (MI->getOperand(NumOperands - 1).isImm())
799       DecodePSHUFMask(4, 16, MI->getOperand(NumOperands - 1).getImm(),
800                       ShuffleMask);
801     break;
802 
803   case X86::PSWAPDrr:
804     Src1Name = getRegName(MI->getOperand(1).getReg());
805     LLVM_FALLTHROUGH;
806 
807   case X86::PSWAPDrm:
808     DestName = getRegName(MI->getOperand(0).getReg());
809     DecodePSWAPMask(2, ShuffleMask);
810     break;
811 
812   CASE_UNPCK(PUNPCKHBW, r)
813   case X86::MMX_PUNPCKHBWirr:
814     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
815     RegForm = true;
816     LLVM_FALLTHROUGH;
817 
818   CASE_UNPCK(PUNPCKHBW, m)
819   case X86::MMX_PUNPCKHBWirm:
820     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
821     DestName = getRegName(MI->getOperand(0).getReg());
822     DecodeUNPCKHMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
823     break;
824 
825   CASE_UNPCK(PUNPCKHWD, r)
826   case X86::MMX_PUNPCKHWDirr:
827     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
828     RegForm = true;
829     LLVM_FALLTHROUGH;
830 
831   CASE_UNPCK(PUNPCKHWD, m)
832   case X86::MMX_PUNPCKHWDirm:
833     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
834     DestName = getRegName(MI->getOperand(0).getReg());
835     DecodeUNPCKHMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
836     break;
837 
838   CASE_UNPCK(PUNPCKHDQ, r)
839   case X86::MMX_PUNPCKHDQirr:
840     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
841     RegForm = true;
842     LLVM_FALLTHROUGH;
843 
844   CASE_UNPCK(PUNPCKHDQ, m)
845   case X86::MMX_PUNPCKHDQirm:
846     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
847     DestName = getRegName(MI->getOperand(0).getReg());
848     DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
849     break;
850 
851   CASE_UNPCK(PUNPCKHQDQ, r)
852     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
853     RegForm = true;
854     LLVM_FALLTHROUGH;
855 
856   CASE_UNPCK(PUNPCKHQDQ, m)
857     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
858     DestName = getRegName(MI->getOperand(0).getReg());
859     DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
860     break;
861 
862   CASE_UNPCK(PUNPCKLBW, r)
863   case X86::MMX_PUNPCKLBWirr:
864     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
865     RegForm = true;
866     LLVM_FALLTHROUGH;
867 
868   CASE_UNPCK(PUNPCKLBW, m)
869   case X86::MMX_PUNPCKLBWirm:
870     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
871     DestName = getRegName(MI->getOperand(0).getReg());
872     DecodeUNPCKLMask(getRegOperandNumElts(MI, 8, 0), 8, ShuffleMask);
873     break;
874 
875   CASE_UNPCK(PUNPCKLWD, r)
876   case X86::MMX_PUNPCKLWDirr:
877     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
878     RegForm = true;
879     LLVM_FALLTHROUGH;
880 
881   CASE_UNPCK(PUNPCKLWD, m)
882   case X86::MMX_PUNPCKLWDirm:
883     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
884     DestName = getRegName(MI->getOperand(0).getReg());
885     DecodeUNPCKLMask(getRegOperandNumElts(MI, 16, 0), 16, ShuffleMask);
886     break;
887 
888   CASE_UNPCK(PUNPCKLDQ, r)
889   case X86::MMX_PUNPCKLDQirr:
890     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
891     RegForm = true;
892     LLVM_FALLTHROUGH;
893 
894   CASE_UNPCK(PUNPCKLDQ, m)
895   case X86::MMX_PUNPCKLDQirm:
896     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
897     DestName = getRegName(MI->getOperand(0).getReg());
898     DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
899     break;
900 
901   CASE_UNPCK(PUNPCKLQDQ, r)
902     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
903     RegForm = true;
904     LLVM_FALLTHROUGH;
905 
906   CASE_UNPCK(PUNPCKLQDQ, m)
907     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
908     DestName = getRegName(MI->getOperand(0).getReg());
909     DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
910     break;
911 
912   CASE_SHUF(SHUFPD, rri)
913     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
914     RegForm = true;
915     LLVM_FALLTHROUGH;
916 
917   CASE_SHUF(SHUFPD, rmi)
918     if (MI->getOperand(NumOperands - 1).isImm())
919       DecodeSHUFPMask(getRegOperandNumElts(MI, 64, 0), 64,
920                       MI->getOperand(NumOperands - 1).getImm(), ShuffleMask);
921     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
922     DestName = getRegName(MI->getOperand(0).getReg());
923     break;
924 
925   CASE_SHUF(SHUFPS, rri)
926     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
927     RegForm = true;
928     LLVM_FALLTHROUGH;
929 
930   CASE_SHUF(SHUFPS, rmi)
931     if (MI->getOperand(NumOperands - 1).isImm())
932       DecodeSHUFPMask(getRegOperandNumElts(MI, 32, 0), 32,
933                       MI->getOperand(NumOperands - 1).getImm(),
934                       ShuffleMask);
935     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
936     DestName = getRegName(MI->getOperand(0).getReg());
937     break;
938 
939   CASE_VSHUF(64X2, r)
940     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
941     RegForm = true;
942     LLVM_FALLTHROUGH;
943 
944   CASE_VSHUF(64X2, m)
945     decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 64, 0), 64,
946                               MI->getOperand(NumOperands - 1).getImm(),
947                               ShuffleMask);
948     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
949     DestName = getRegName(MI->getOperand(0).getReg());
950     break;
951 
952   CASE_VSHUF(32X4, r)
953     Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
954     RegForm = true;
955     LLVM_FALLTHROUGH;
956 
957   CASE_VSHUF(32X4, m)
958     decodeVSHUF64x2FamilyMask(getRegOperandNumElts(MI, 32, 0), 32,
959                               MI->getOperand(NumOperands - 1).getImm(),
960                               ShuffleMask);
961     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
962     DestName = getRegName(MI->getOperand(0).getReg());
963     break;
964 
965   CASE_UNPCK(UNPCKLPD, r)
966     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
967     RegForm = true;
968     LLVM_FALLTHROUGH;
969 
970   CASE_UNPCK(UNPCKLPD, m)
971     DecodeUNPCKLMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
972     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
973     DestName = getRegName(MI->getOperand(0).getReg());
974     break;
975 
976   CASE_UNPCK(UNPCKLPS, r)
977     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
978     RegForm = true;
979     LLVM_FALLTHROUGH;
980 
981   CASE_UNPCK(UNPCKLPS, m)
982     DecodeUNPCKLMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
983     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
984     DestName = getRegName(MI->getOperand(0).getReg());
985     break;
986 
987   CASE_UNPCK(UNPCKHPD, r)
988     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
989     RegForm = true;
990     LLVM_FALLTHROUGH;
991 
992   CASE_UNPCK(UNPCKHPD, m)
993     DecodeUNPCKHMask(getRegOperandNumElts(MI, 64, 0), 64, ShuffleMask);
994     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
995     DestName = getRegName(MI->getOperand(0).getReg());
996     break;
997 
998   CASE_UNPCK(UNPCKHPS, r)
999     Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1000     RegForm = true;
1001     LLVM_FALLTHROUGH;
1002 
1003   CASE_UNPCK(UNPCKHPS, m)
1004     DecodeUNPCKHMask(getRegOperandNumElts(MI, 32, 0), 32, ShuffleMask);
1005     Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
1006     DestName = getRegName(MI->getOperand(0).getReg());
1007     break;
1008 
1009   CASE_VPERMILPI(PERMILPS, r)
1010     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1011     LLVM_FALLTHROUGH;
1012 
1013   CASE_VPERMILPI(PERMILPS, m)
1014     if (MI->getOperand(NumOperands - 1).isImm())
1015       DecodePSHUFMask(getRegOperandNumElts(MI, 32, 0), 32,
1016                       MI->getOperand(NumOperands - 1).getImm(),
1017                       ShuffleMask);
1018     DestName = getRegName(MI->getOperand(0).getReg());
1019     break;
1020 
1021   CASE_VPERMILPI(PERMILPD, r)
1022     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1023     LLVM_FALLTHROUGH;
1024 
1025   CASE_VPERMILPI(PERMILPD, m)
1026     if (MI->getOperand(NumOperands - 1).isImm())
1027       DecodePSHUFMask(getRegOperandNumElts(MI, 64, 0), 64,
1028                       MI->getOperand(NumOperands - 1).getImm(),
1029                       ShuffleMask);
1030     DestName = getRegName(MI->getOperand(0).getReg());
1031     break;
1032 
1033   case X86::VPERM2F128rr:
1034   case X86::VPERM2I128rr:
1035     Src2Name = getRegName(MI->getOperand(2).getReg());
1036     LLVM_FALLTHROUGH;
1037 
1038   case X86::VPERM2F128rm:
1039   case X86::VPERM2I128rm:
1040     // For instruction comments purpose, assume the 256-bit vector is v4i64.
1041     if (MI->getOperand(NumOperands - 1).isImm())
1042       DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),
1043                            ShuffleMask);
1044     Src1Name = getRegName(MI->getOperand(1).getReg());
1045     DestName = getRegName(MI->getOperand(0).getReg());
1046     break;
1047 
1048   CASE_VPERM(PERMPD, r)
1049     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1050     LLVM_FALLTHROUGH;
1051 
1052   CASE_VPERM(PERMPD, m)
1053     if (MI->getOperand(NumOperands - 1).isImm())
1054       DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1055                       MI->getOperand(NumOperands - 1).getImm(),
1056                       ShuffleMask);
1057     DestName = getRegName(MI->getOperand(0).getReg());
1058     break;
1059 
1060   CASE_VPERM(PERMQ, r)
1061     Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
1062     LLVM_FALLTHROUGH;
1063 
1064   CASE_VPERM(PERMQ, m)
1065     if (MI->getOperand(NumOperands - 1).isImm())
1066       DecodeVPERMMask(getRegOperandNumElts(MI, 64, 0),
1067                       MI->getOperand(NumOperands - 1).getImm(),
1068                       ShuffleMask);
1069     DestName = getRegName(MI->getOperand(0).getReg());
1070     break;
1071 
1072   case X86::MOVSDrr:
1073   case X86::VMOVSDrr:
1074   case X86::VMOVSDZrr:
1075     Src2Name = getRegName(MI->getOperand(2).getReg());
1076     Src1Name = getRegName(MI->getOperand(1).getReg());
1077     LLVM_FALLTHROUGH;
1078 
1079   case X86::MOVSDrm:
1080   case X86::VMOVSDrm:
1081   case X86::VMOVSDZrm:
1082     DecodeScalarMoveMask(2, nullptr == Src2Name, ShuffleMask);
1083     DestName = getRegName(MI->getOperand(0).getReg());
1084     break;
1085 
1086   case X86::MOVSSrr:
1087   case X86::VMOVSSrr:
1088   case X86::VMOVSSZrr:
1089     Src2Name = getRegName(MI->getOperand(2).getReg());
1090     Src1Name = getRegName(MI->getOperand(1).getReg());
1091     LLVM_FALLTHROUGH;
1092 
1093   case X86::MOVSSrm:
1094   case X86::VMOVSSrm:
1095   case X86::VMOVSSZrm:
1096     DecodeScalarMoveMask(4, nullptr == Src2Name, ShuffleMask);
1097     DestName = getRegName(MI->getOperand(0).getReg());
1098     break;
1099 
1100   case X86::MOVPQI2QIrr:
1101   case X86::MOVZPQILo2PQIrr:
1102   case X86::VMOVPQI2QIrr:
1103   case X86::VMOVPQI2QIZrr:
1104   case X86::VMOVZPQILo2PQIrr:
1105   case X86::VMOVZPQILo2PQIZrr:
1106     Src1Name = getRegName(MI->getOperand(1).getReg());
1107     LLVM_FALLTHROUGH;
1108 
1109   case X86::MOVQI2PQIrm:
1110   case X86::VMOVQI2PQIrm:
1111   case X86::VMOVQI2PQIZrm:
1112     DecodeZeroMoveLowMask(2, ShuffleMask);
1113     DestName = getRegName(MI->getOperand(0).getReg());
1114     break;
1115 
1116   case X86::MOVDI2PDIrm:
1117   case X86::VMOVDI2PDIrm:
1118   case X86::VMOVDI2PDIZrm:
1119     DecodeZeroMoveLowMask(4, ShuffleMask);
1120     DestName = getRegName(MI->getOperand(0).getReg());
1121     break;
1122 
1123   case X86::EXTRQI:
1124     if (MI->getOperand(2).isImm() &&
1125         MI->getOperand(3).isImm())
1126       DecodeEXTRQIMask(16, 8, MI->getOperand(2).getImm(),
1127                        MI->getOperand(3).getImm(), ShuffleMask);
1128 
1129     DestName = getRegName(MI->getOperand(0).getReg());
1130     Src1Name = getRegName(MI->getOperand(1).getReg());
1131     break;
1132 
1133   case X86::INSERTQI:
1134     if (MI->getOperand(3).isImm() &&
1135         MI->getOperand(4).isImm())
1136       DecodeINSERTQIMask(16, 8, MI->getOperand(3).getImm(),
1137                          MI->getOperand(4).getImm(), ShuffleMask);
1138 
1139     DestName = getRegName(MI->getOperand(0).getReg());
1140     Src1Name = getRegName(MI->getOperand(1).getReg());
1141     Src2Name = getRegName(MI->getOperand(2).getReg());
1142     break;
1143 
1144   case X86::VBROADCASTF128:
1145   case X86::VBROADCASTI128:
1146   CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
1147   CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
1148     DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1149     DestName = getRegName(MI->getOperand(0).getReg());
1150     break;
1151   CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm)
1152   CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm)
1153     DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1154     DestName = getRegName(MI->getOperand(0).getReg());
1155     break;
1156   CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm)
1157   CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm)
1158     DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1159     DestName = getRegName(MI->getOperand(0).getReg());
1160     break;
1161   CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1162   CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1163     DecodeSubVectorBroadcast(8, 4, ShuffleMask);
1164     DestName = getRegName(MI->getOperand(0).getReg());
1165     break;
1166   CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm)
1167   CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm)
1168     DecodeSubVectorBroadcast(16, 4, ShuffleMask);
1169     DestName = getRegName(MI->getOperand(0).getReg());
1170     break;
1171   CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm)
1172   CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm)
1173     DecodeSubVectorBroadcast(16, 8, ShuffleMask);
1174     DestName = getRegName(MI->getOperand(0).getReg());
1175     break;
1176   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, r)
1177     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1178     LLVM_FALLTHROUGH;
1179   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, m)
1180     DecodeSubVectorBroadcast(4, 2, ShuffleMask);
1181     DestName = getRegName(MI->getOperand(0).getReg());
1182     break;
1183   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r)
1184   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r)
1185     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1186     LLVM_FALLTHROUGH;
1187   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m)
1188   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m)
1189     DecodeSubVectorBroadcast(8, 2, ShuffleMask);
1190     DestName = getRegName(MI->getOperand(0).getReg());
1191     break;
1192   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r)
1193   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r)
1194     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1195     LLVM_FALLTHROUGH;
1196   CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m)
1197   CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m)
1198     DecodeSubVectorBroadcast(16, 2, ShuffleMask);
1199     DestName = getRegName(MI->getOperand(0).getReg());
1200     break;
1201 
1202   CASE_PMOVZX(PMOVZXBW, r)
1203     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1204     LLVM_FALLTHROUGH;
1205   CASE_PMOVZX(PMOVZXBW, m)
1206     DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), ShuffleMask);
1207     DestName = getRegName(MI->getOperand(0).getReg());
1208     break;
1209 
1210   CASE_PMOVZX(PMOVZXBD, r)
1211     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1212     LLVM_FALLTHROUGH;
1213   CASE_PMOVZX(PMOVZXBD, m)
1214     DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask);
1215     DestName = getRegName(MI->getOperand(0).getReg());
1216     break;
1217 
1218   CASE_PMOVZX(PMOVZXBQ, r)
1219     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1220     LLVM_FALLTHROUGH;
1221   CASE_PMOVZX(PMOVZXBQ, m)
1222     DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
1223     DestName = getRegName(MI->getOperand(0).getReg());
1224     break;
1225 
1226   CASE_PMOVZX(PMOVZXWD, r)
1227     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1228     LLVM_FALLTHROUGH;
1229   CASE_PMOVZX(PMOVZXWD, m)
1230     DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask);
1231     DestName = getRegName(MI->getOperand(0).getReg());
1232     break;
1233 
1234   CASE_PMOVZX(PMOVZXWQ, r)
1235     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1236     LLVM_FALLTHROUGH;
1237   CASE_PMOVZX(PMOVZXWQ, m)
1238     DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
1239     DestName = getRegName(MI->getOperand(0).getReg());
1240     break;
1241 
1242   CASE_PMOVZX(PMOVZXDQ, r)
1243     Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1244     LLVM_FALLTHROUGH;
1245   CASE_PMOVZX(PMOVZXDQ, m)
1246     DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
1247     DestName = getRegName(MI->getOperand(0).getReg());
1248     break;
1249   }
1250 
1251   // The only comments we decode are shuffles, so give up if we were unable to
1252   // decode a shuffle mask.
1253   if (ShuffleMask.empty())
1254     return false;
1255 
1256   if (!DestName) DestName = Src1Name;
1257   if (DestName) {
1258     OS << DestName;
1259     printMasking(OS, MI, MCII);
1260   } else
1261     OS << "mem";
1262 
1263   OS << " = ";
1264 
1265   // If the two sources are the same, canonicalize the input elements to be
1266   // from the first src so that we get larger element spans.
1267   if (Src1Name == Src2Name) {
1268     for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1269       if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
1270           ShuffleMask[i] >= (int)e)   // From second mask.
1271         ShuffleMask[i] -= e;
1272     }
1273   }
1274 
1275   // The shuffle mask specifies which elements of the src1/src2 fill in the
1276   // destination, with a few sentinel values.  Loop through and print them
1277   // out.
1278   for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1279     if (i != 0)
1280       OS << ',';
1281     if (ShuffleMask[i] == SM_SentinelZero) {
1282       OS << "zero";
1283       continue;
1284     }
1285 
1286     // Otherwise, it must come from src1 or src2.  Print the span of elements
1287     // that comes from this src.
1288     bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1289     const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1290     OS << (SrcName ? SrcName : "mem") << '[';
1291     bool IsFirst = true;
1292     while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1293            (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1294       if (!IsFirst)
1295         OS << ',';
1296       else
1297         IsFirst = false;
1298       if (ShuffleMask[i] == SM_SentinelUndef)
1299         OS << "u";
1300       else
1301         OS << ShuffleMask[i] % ShuffleMask.size();
1302       ++i;
1303     }
1304     OS << ']';
1305     --i; // For loop increments element #.
1306   }
1307 
1308   // We successfully added a comment to this instruction.
1309   return true;
1310 }
1311