1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as AT&T-style
11 // assembly.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86ATTInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "X86InstComments.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/Casting.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/Format.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <cassert>
28 #include <cinttypes>
29 #include <cstdint>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "asm-printer"
34 
35 // Include the auto-generated portion of the assembly writer.
36 #define PRINT_ALIAS_INSTR
37 #include "X86GenAsmWriter.inc"
38 
39 void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
40   OS << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
41 }
42 
43 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
44                                   StringRef Annot, const MCSubtargetInfo &STI) {
45   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
46   uint64_t TSFlags = Desc.TSFlags;
47 
48   // If verbose assembly is enabled, we can print some informative comments.
49   if (CommentStream)
50     HasCustomInstComment =
51         EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
52 
53   if (TSFlags & X86II::LOCK)
54     OS << "\tlock\t";
55 
56   // Output CALLpcrel32 as "callq" in 64-bit mode.
57   // In Intel annotation it's always emitted as "call".
58   //
59   // TODO: Probably this hack should be redesigned via InstAlias in
60   // InstrInfo.td as soon as Requires clause is supported properly
61   // for InstAlias.
62   if (MI->getOpcode() == X86::CALLpcrel32 &&
63       (STI.getFeatureBits()[X86::Mode64Bit])) {
64     OS << "\tcallq\t";
65     printPCRelImm(MI, 0, OS);
66   }
67   // data16 and data32 both have the same encoding of 0x66. While data32 is
68   // valid only in 16 bit systems, data16 is valid in the rest.
69   // There seems to be some lack of support of the Requires clause that causes
70   // 0x66 to be interpreted as "data16" by the asm printer.
71   // Thus we add an adjustment here in order to print the "right" instruction.
72   else if (MI->getOpcode() == X86::DATA16_PREFIX &&
73     (STI.getFeatureBits()[X86::Mode16Bit])) {
74     MCInst Data32MI(*MI);
75     Data32MI.setOpcode(X86::DATA32_PREFIX);
76     printInstruction(&Data32MI, OS);
77   }
78   // Try to print any aliases first.
79   else if (!printAliasInstr(MI, OS))
80     printInstruction(MI, OS);
81 
82   // Next always print the annotation.
83   printAnnotation(OS, Annot);
84 }
85 
86 void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
87                                       raw_ostream &O) {
88   int64_t Imm = MI->getOperand(Op).getImm();
89   switch (Imm) {
90   default: llvm_unreachable("Invalid ssecc/avxcc argument!");
91   case    0: O << "eq"; break;
92   case    1: O << "lt"; break;
93   case    2: O << "le"; break;
94   case    3: O << "unord"; break;
95   case    4: O << "neq"; break;
96   case    5: O << "nlt"; break;
97   case    6: O << "nle"; break;
98   case    7: O << "ord"; break;
99   case    8: O << "eq_uq"; break;
100   case    9: O << "nge"; break;
101   case  0xa: O << "ngt"; break;
102   case  0xb: O << "false"; break;
103   case  0xc: O << "neq_oq"; break;
104   case  0xd: O << "ge"; break;
105   case  0xe: O << "gt"; break;
106   case  0xf: O << "true"; break;
107   case 0x10: O << "eq_os"; break;
108   case 0x11: O << "lt_oq"; break;
109   case 0x12: O << "le_oq"; break;
110   case 0x13: O << "unord_s"; break;
111   case 0x14: O << "neq_us"; break;
112   case 0x15: O << "nlt_uq"; break;
113   case 0x16: O << "nle_uq"; break;
114   case 0x17: O << "ord_s"; break;
115   case 0x18: O << "eq_us"; break;
116   case 0x19: O << "nge_uq"; break;
117   case 0x1a: O << "ngt_uq"; break;
118   case 0x1b: O << "false_os"; break;
119   case 0x1c: O << "neq_os"; break;
120   case 0x1d: O << "ge_oq"; break;
121   case 0x1e: O << "gt_oq"; break;
122   case 0x1f: O << "true_us"; break;
123   }
124 }
125 
126 void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
127                                    raw_ostream &O) {
128   int64_t Imm = MI->getOperand(Op).getImm();
129   switch (Imm) {
130   default: llvm_unreachable("Invalid xopcc argument!");
131   case 0: O << "lt"; break;
132   case 1: O << "le"; break;
133   case 2: O << "gt"; break;
134   case 3: O << "ge"; break;
135   case 4: O << "eq"; break;
136   case 5: O << "neq"; break;
137   case 6: O << "false"; break;
138   case 7: O << "true"; break;
139   }
140 }
141 
142 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
143                                             raw_ostream &O) {
144   int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
145   switch (Imm) {
146   case 0: O << "{rn-sae}"; break;
147   case 1: O << "{rd-sae}"; break;
148   case 2: O << "{ru-sae}"; break;
149   case 3: O << "{rz-sae}"; break;
150   }
151 }
152 
153 /// printPCRelImm - This is used to print an immediate value that ends up
154 /// being encoded as a pc-relative value (e.g. for jumps and calls).  These
155 /// print slightly differently than normal immediates.  For example, a $ is not
156 /// emitted.
157 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
158                                       raw_ostream &O) {
159   const MCOperand &Op = MI->getOperand(OpNo);
160   if (Op.isImm())
161     O << formatImm(Op.getImm());
162   else {
163     assert(Op.isExpr() && "unknown pcrel immediate operand");
164     // If a symbolic branch target was added as a constant expression then print
165     // that address in hex.
166     const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
167     int64_t Address;
168     if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
169       O << formatHex((uint64_t)Address);
170     } else {
171       // Otherwise, just print the expression.
172       Op.getExpr()->print(O, &MAI);
173     }
174   }
175 }
176 
177 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
178                                      raw_ostream &O) {
179   const MCOperand &Op = MI->getOperand(OpNo);
180   if (Op.isReg()) {
181     printRegName(O, Op.getReg());
182   } else if (Op.isImm()) {
183     // Print immediates as signed values.
184     int64_t Imm = Op.getImm();
185     O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
186 
187     // TODO: This should be in a helper function in the base class, so it can
188     // be used by other printers.
189 
190     // If there are no instruction-specific comments, add a comment clarifying
191     // the hex value of the immediate operand when it isn't in the range
192     // [-256,255].
193     if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
194       // Don't print unnecessary hex sign bits.
195       if (Imm == (int16_t)(Imm))
196         *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
197       else if (Imm == (int32_t)(Imm))
198         *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
199       else
200         *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
201     }
202   } else {
203     assert(Op.isExpr() && "unknown operand kind in printOperand");
204     O << markup("<imm:") << '$';
205     Op.getExpr()->print(O, &MAI);
206     O << markup(">");
207   }
208 }
209 
210 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
211                                           raw_ostream &O) {
212   const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
213   const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
214   const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
215   const MCOperand &SegReg = MI->getOperand(Op + X86::AddrSegmentReg);
216 
217   O << markup("<mem:");
218 
219   // If this has a segment register, print it.
220   if (SegReg.getReg()) {
221     printOperand(MI, Op + X86::AddrSegmentReg, O);
222     O << ':';
223   }
224 
225   if (DispSpec.isImm()) {
226     int64_t DispVal = DispSpec.getImm();
227     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
228       O << formatImm(DispVal);
229   } else {
230     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
231     DispSpec.getExpr()->print(O, &MAI);
232   }
233 
234   if (IndexReg.getReg() || BaseReg.getReg()) {
235     O << '(';
236     if (BaseReg.getReg())
237       printOperand(MI, Op + X86::AddrBaseReg, O);
238 
239     if (IndexReg.getReg()) {
240       O << ',';
241       printOperand(MI, Op + X86::AddrIndexReg, O);
242       unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
243       if (ScaleVal != 1) {
244         O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
245           << markup(">");
246       }
247     }
248     O << ')';
249   }
250 
251   O << markup(">");
252 }
253 
254 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
255                                     raw_ostream &O) {
256   const MCOperand &SegReg = MI->getOperand(Op + 1);
257 
258   O << markup("<mem:");
259 
260   // If this has a segment register, print it.
261   if (SegReg.getReg()) {
262     printOperand(MI, Op + 1, O);
263     O << ':';
264   }
265 
266   O << "(";
267   printOperand(MI, Op, O);
268   O << ")";
269 
270   O << markup(">");
271 }
272 
273 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
274                                     raw_ostream &O) {
275   O << markup("<mem:");
276 
277   O << "%es:(";
278   printOperand(MI, Op, O);
279   O << ")";
280 
281   O << markup(">");
282 }
283 
284 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
285                                        raw_ostream &O) {
286   const MCOperand &DispSpec = MI->getOperand(Op);
287   const MCOperand &SegReg = MI->getOperand(Op + 1);
288 
289   O << markup("<mem:");
290 
291   // If this has a segment register, print it.
292   if (SegReg.getReg()) {
293     printOperand(MI, Op + 1, O);
294     O << ':';
295   }
296 
297   if (DispSpec.isImm()) {
298     O << formatImm(DispSpec.getImm());
299   } else {
300     assert(DispSpec.isExpr() && "non-immediate displacement?");
301     DispSpec.getExpr()->print(O, &MAI);
302   }
303 
304   O << markup(">");
305 }
306 
307 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
308                                    raw_ostream &O) {
309   if (MI->getOperand(Op).isExpr())
310     return printOperand(MI, Op, O);
311 
312   O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
313     << markup(">");
314 }
315