1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as AT&T-style
11 // assembly.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86ATTInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86MCTargetDesc.h"
18 #include "X86InstComments.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/Format.h"
27 #include "llvm/Support/FormattedStream.h"
28 #include <map>
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "asm-printer"
32 
33 // Include the auto-generated portion of the assembly writer.
34 #define PRINT_ALIAS_INSTR
35 #include "X86GenAsmWriter.inc"
36 
37 void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
38   OS << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
39 }
40 
41 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
42                                   StringRef Annot, const MCSubtargetInfo &STI) {
43   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
44   uint64_t TSFlags = Desc.TSFlags;
45 
46   // If verbose assembly is enabled, we can print some informative comments.
47   if (CommentStream)
48     HasCustomInstComment =
49         EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
50 
51   if (TSFlags & X86II::LOCK)
52     OS << "\tlock\t";
53 
54   // Output CALLpcrel32 as "callq" in 64-bit mode.
55   // In Intel annotation it's always emitted as "call".
56   //
57   // TODO: Probably this hack should be redesigned via InstAlias in
58   // InstrInfo.td as soon as Requires clause is supported properly
59   // for InstAlias.
60   if (MI->getOpcode() == X86::CALLpcrel32 &&
61       (STI.getFeatureBits()[X86::Mode64Bit])) {
62     OS << "\tcallq\t";
63     printPCRelImm(MI, 0, OS);
64   }
65   // Try to print any aliases first.
66   else if (!printAliasInstr(MI, OS))
67     printInstruction(MI, OS);
68 
69   // Next always print the annotation.
70   printAnnotation(OS, Annot);
71 }
72 
73 void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
74                                       raw_ostream &O) {
75   int64_t Imm = MI->getOperand(Op).getImm();
76   switch (Imm) {
77   default: llvm_unreachable("Invalid ssecc/avxcc argument!");
78   case    0: O << "eq"; break;
79   case    1: O << "lt"; break;
80   case    2: O << "le"; break;
81   case    3: O << "unord"; break;
82   case    4: O << "neq"; break;
83   case    5: O << "nlt"; break;
84   case    6: O << "nle"; break;
85   case    7: O << "ord"; break;
86   case    8: O << "eq_uq"; break;
87   case    9: O << "nge"; break;
88   case  0xa: O << "ngt"; break;
89   case  0xb: O << "false"; break;
90   case  0xc: O << "neq_oq"; break;
91   case  0xd: O << "ge"; break;
92   case  0xe: O << "gt"; break;
93   case  0xf: O << "true"; break;
94   case 0x10: O << "eq_os"; break;
95   case 0x11: O << "lt_oq"; break;
96   case 0x12: O << "le_oq"; break;
97   case 0x13: O << "unord_s"; break;
98   case 0x14: O << "neq_us"; break;
99   case 0x15: O << "nlt_uq"; break;
100   case 0x16: O << "nle_uq"; break;
101   case 0x17: O << "ord_s"; break;
102   case 0x18: O << "eq_us"; break;
103   case 0x19: O << "nge_uq"; break;
104   case 0x1a: O << "ngt_uq"; break;
105   case 0x1b: O << "false_os"; break;
106   case 0x1c: O << "neq_os"; break;
107   case 0x1d: O << "ge_oq"; break;
108   case 0x1e: O << "gt_oq"; break;
109   case 0x1f: O << "true_us"; break;
110   }
111 }
112 
113 void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
114                                    raw_ostream &O) {
115   int64_t Imm = MI->getOperand(Op).getImm();
116   switch (Imm) {
117   default: llvm_unreachable("Invalid xopcc argument!");
118   case 0: O << "lt"; break;
119   case 1: O << "le"; break;
120   case 2: O << "gt"; break;
121   case 3: O << "ge"; break;
122   case 4: O << "eq"; break;
123   case 5: O << "neq"; break;
124   case 6: O << "false"; break;
125   case 7: O << "true"; break;
126   }
127 }
128 
129 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
130                                             raw_ostream &O) {
131   int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
132   switch (Imm) {
133   case 0: O << "{rn-sae}"; break;
134   case 1: O << "{rd-sae}"; break;
135   case 2: O << "{ru-sae}"; break;
136   case 3: O << "{rz-sae}"; break;
137   }
138 }
139 /// printPCRelImm - This is used to print an immediate value that ends up
140 /// being encoded as a pc-relative value (e.g. for jumps and calls).  These
141 /// print slightly differently than normal immediates.  For example, a $ is not
142 /// emitted.
143 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
144                                       raw_ostream &O) {
145   const MCOperand &Op = MI->getOperand(OpNo);
146   if (Op.isImm())
147     O << formatImm(Op.getImm());
148   else {
149     assert(Op.isExpr() && "unknown pcrel immediate operand");
150     // If a symbolic branch target was added as a constant expression then print
151     // that address in hex.
152     const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
153     int64_t Address;
154     if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
155       O << formatHex((uint64_t)Address);
156     } else {
157       // Otherwise, just print the expression.
158       Op.getExpr()->print(O, &MAI);
159     }
160   }
161 }
162 
163 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
164                                      raw_ostream &O) {
165   const MCOperand &Op = MI->getOperand(OpNo);
166   if (Op.isReg()) {
167     printRegName(O, Op.getReg());
168   } else if (Op.isImm()) {
169     // Print X86 immediates as signed values.
170     O << markup("<imm:") << '$' << formatImm((int64_t)Op.getImm())
171       << markup(">");
172 
173     // If there are no instruction-specific comments, add a comment clarifying
174     // the hex value of the immediate operand when it isn't in the range
175     // [-256,255].
176     if (CommentStream && !HasCustomInstComment &&
177         (Op.getImm() > 255 || Op.getImm() < -256))
178       *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
179 
180   } else {
181     assert(Op.isExpr() && "unknown operand kind in printOperand");
182     O << markup("<imm:") << '$';
183     Op.getExpr()->print(O, &MAI);
184     O << markup(">");
185   }
186 }
187 
188 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
189                                           raw_ostream &O) {
190   const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
191   const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
192   const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
193   const MCOperand &SegReg = MI->getOperand(Op + X86::AddrSegmentReg);
194 
195   O << markup("<mem:");
196 
197   // If this has a segment register, print it.
198   if (SegReg.getReg()) {
199     printOperand(MI, Op + X86::AddrSegmentReg, O);
200     O << ':';
201   }
202 
203   if (DispSpec.isImm()) {
204     int64_t DispVal = DispSpec.getImm();
205     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
206       O << formatImm(DispVal);
207   } else {
208     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
209     DispSpec.getExpr()->print(O, &MAI);
210   }
211 
212   if (IndexReg.getReg() || BaseReg.getReg()) {
213     O << '(';
214     if (BaseReg.getReg())
215       printOperand(MI, Op + X86::AddrBaseReg, O);
216 
217     if (IndexReg.getReg()) {
218       O << ',';
219       printOperand(MI, Op + X86::AddrIndexReg, O);
220       unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
221       if (ScaleVal != 1) {
222         O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
223           << markup(">");
224       }
225     }
226     O << ')';
227   }
228 
229   O << markup(">");
230 }
231 
232 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
233                                     raw_ostream &O) {
234   const MCOperand &SegReg = MI->getOperand(Op + 1);
235 
236   O << markup("<mem:");
237 
238   // If this has a segment register, print it.
239   if (SegReg.getReg()) {
240     printOperand(MI, Op + 1, O);
241     O << ':';
242   }
243 
244   O << "(";
245   printOperand(MI, Op, O);
246   O << ")";
247 
248   O << markup(">");
249 }
250 
251 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
252                                     raw_ostream &O) {
253   O << markup("<mem:");
254 
255   O << "%es:(";
256   printOperand(MI, Op, O);
257   O << ")";
258 
259   O << markup(">");
260 }
261 
262 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
263                                        raw_ostream &O) {
264   const MCOperand &DispSpec = MI->getOperand(Op);
265   const MCOperand &SegReg = MI->getOperand(Op + 1);
266 
267   O << markup("<mem:");
268 
269   // If this has a segment register, print it.
270   if (SegReg.getReg()) {
271     printOperand(MI, Op + 1, O);
272     O << ':';
273   }
274 
275   if (DispSpec.isImm()) {
276     O << formatImm(DispSpec.getImm());
277   } else {
278     assert(DispSpec.isExpr() && "non-immediate displacement?");
279     DispSpec.getExpr()->print(O, &MAI);
280   }
281 
282   O << markup(">");
283 }
284 
285 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
286                                    raw_ostream &O) {
287   O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
288     << markup(">");
289 }
290