1 //===-- WebAssemblyUtilities.cpp - WebAssembly Utility Functions ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file implements several utility functions for WebAssembly.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyUtilities.h"
16 #include "WebAssemblyMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineLoopInfo.h"
19 using namespace llvm;
20 
21 bool WebAssembly::isArgument(const MachineInstr &MI) {
22   switch (MI.getOpcode()) {
23   case WebAssembly::ARGUMENT_I32:
24   case WebAssembly::ARGUMENT_I64:
25   case WebAssembly::ARGUMENT_F32:
26   case WebAssembly::ARGUMENT_F64:
27   case WebAssembly::ARGUMENT_v16i8:
28   case WebAssembly::ARGUMENT_v8i16:
29   case WebAssembly::ARGUMENT_v4i32:
30   case WebAssembly::ARGUMENT_v4f32:
31     return true;
32   default:
33     return false;
34   }
35 }
36 
37 bool WebAssembly::isCopy(const MachineInstr &MI) {
38   switch (MI.getOpcode()) {
39   case WebAssembly::COPY_I32:
40   case WebAssembly::COPY_I64:
41   case WebAssembly::COPY_F32:
42   case WebAssembly::COPY_F64:
43     return true;
44   default:
45     return false;
46   }
47 }
48 
49 bool WebAssembly::isTee(const MachineInstr &MI) {
50   switch (MI.getOpcode()) {
51   case WebAssembly::TEE_I32:
52   case WebAssembly::TEE_I64:
53   case WebAssembly::TEE_F32:
54   case WebAssembly::TEE_F64:
55     return true;
56   default:
57     return false;
58   }
59 }
60 
61 /// Test whether MI is a child of some other node in an expression tree.
62 bool WebAssembly::isChild(const MachineInstr &MI,
63                           const WebAssemblyFunctionInfo &MFI) {
64   if (MI.getNumOperands() == 0)
65     return false;
66   const MachineOperand &MO = MI.getOperand(0);
67   if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
68     return false;
69   unsigned Reg = MO.getReg();
70   return TargetRegisterInfo::isVirtualRegister(Reg) &&
71          MFI.isVRegStackified(Reg);
72 }
73 
74 bool WebAssembly::isCallIndirect(const MachineInstr &MI) {
75   switch (MI.getOpcode()) {
76   case WebAssembly::CALL_INDIRECT_VOID:
77   case WebAssembly::CALL_INDIRECT_I32:
78   case WebAssembly::CALL_INDIRECT_I64:
79   case WebAssembly::CALL_INDIRECT_F32:
80   case WebAssembly::CALL_INDIRECT_F64:
81   case WebAssembly::CALL_INDIRECT_v16i8:
82   case WebAssembly::CALL_INDIRECT_v8i16:
83   case WebAssembly::CALL_INDIRECT_v4i32:
84   case WebAssembly::CALL_INDIRECT_v4f32:
85     return true;
86   default:
87     return false;
88   }
89 }
90 
91 MachineBasicBlock *llvm::LoopBottom(const MachineLoop *Loop) {
92   MachineBasicBlock *Bottom = Loop->getHeader();
93   for (MachineBasicBlock *MBB : Loop->blocks())
94     if (MBB->getNumber() > Bottom->getNumber())
95       Bottom = MBB;
96   return Bottom;
97 }
98