13ca95b02SDimitry Andric //===--- WebAssemblyOptimizeLiveIntervals.cpp - LiveInterval processing ---===//
23ca95b02SDimitry Andric //
33ca95b02SDimitry Andric //                     The LLVM Compiler Infrastructure
43ca95b02SDimitry Andric //
53ca95b02SDimitry Andric // This file is distributed under the University of Illinois Open Source
63ca95b02SDimitry Andric // License. See LICENSE.TXT for details.
73ca95b02SDimitry Andric //
83ca95b02SDimitry Andric //===----------------------------------------------------------------------===//
93ca95b02SDimitry Andric ///
103ca95b02SDimitry Andric /// \file
114ba319b5SDimitry Andric /// Optimize LiveIntervals for use in a post-RA context.
123ca95b02SDimitry Andric //
133ca95b02SDimitry Andric /// LiveIntervals normally runs before register allocation when the code is
143ca95b02SDimitry Andric /// only recently lowered out of SSA form, so it's uncommon for registers to
154ba319b5SDimitry Andric /// have multiple defs, and when they do, the defs are usually closely related.
163ca95b02SDimitry Andric /// Later, after coalescing, tail duplication, and other optimizations, it's
173ca95b02SDimitry Andric /// more common to see registers with multiple unrelated defs. This pass
182cab237bSDimitry Andric /// updates LiveIntervals to distribute the value numbers across separate
193ca95b02SDimitry Andric /// LiveIntervals.
203ca95b02SDimitry Andric ///
213ca95b02SDimitry Andric //===----------------------------------------------------------------------===//
223ca95b02SDimitry Andric 
233ca95b02SDimitry Andric #include "WebAssembly.h"
243ca95b02SDimitry Andric #include "WebAssemblySubtarget.h"
252cab237bSDimitry Andric #include "llvm/CodeGen/LiveIntervals.h"
263ca95b02SDimitry Andric #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
273ca95b02SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
283ca95b02SDimitry Andric #include "llvm/CodeGen/Passes.h"
293ca95b02SDimitry Andric #include "llvm/Support/Debug.h"
303ca95b02SDimitry Andric #include "llvm/Support/raw_ostream.h"
313ca95b02SDimitry Andric using namespace llvm;
323ca95b02SDimitry Andric 
333ca95b02SDimitry Andric #define DEBUG_TYPE "wasm-optimize-live-intervals"
343ca95b02SDimitry Andric 
353ca95b02SDimitry Andric namespace {
363ca95b02SDimitry Andric class WebAssemblyOptimizeLiveIntervals final : public MachineFunctionPass {
getPassName() const37d88c1a5aSDimitry Andric   StringRef getPassName() const override {
383ca95b02SDimitry Andric     return "WebAssembly Optimize Live Intervals";
393ca95b02SDimitry Andric   }
403ca95b02SDimitry Andric 
getAnalysisUsage(AnalysisUsage & AU) const413ca95b02SDimitry Andric   void getAnalysisUsage(AnalysisUsage &AU) const override {
423ca95b02SDimitry Andric     AU.setPreservesCFG();
433ca95b02SDimitry Andric     AU.addRequired<LiveIntervals>();
443ca95b02SDimitry Andric     AU.addPreserved<MachineBlockFrequencyInfo>();
453ca95b02SDimitry Andric     AU.addPreserved<SlotIndexes>();
463ca95b02SDimitry Andric     AU.addPreserved<LiveIntervals>();
473ca95b02SDimitry Andric     AU.addPreservedID(LiveVariablesID);
483ca95b02SDimitry Andric     AU.addPreservedID(MachineDominatorsID);
493ca95b02SDimitry Andric     MachineFunctionPass::getAnalysisUsage(AU);
503ca95b02SDimitry Andric   }
513ca95b02SDimitry Andric 
523ca95b02SDimitry Andric   bool runOnMachineFunction(MachineFunction &MF) override;
533ca95b02SDimitry Andric 
543ca95b02SDimitry Andric public:
553ca95b02SDimitry Andric   static char ID; // Pass identification, replacement for typeid
WebAssemblyOptimizeLiveIntervals()563ca95b02SDimitry Andric   WebAssemblyOptimizeLiveIntervals() : MachineFunctionPass(ID) {}
573ca95b02SDimitry Andric };
583ca95b02SDimitry Andric } // end anonymous namespace
593ca95b02SDimitry Andric 
603ca95b02SDimitry Andric char WebAssemblyOptimizeLiveIntervals::ID = 0;
614ba319b5SDimitry Andric INITIALIZE_PASS(WebAssemblyOptimizeLiveIntervals, DEBUG_TYPE,
624ba319b5SDimitry Andric                 "Optimize LiveIntervals for WebAssembly", false, false)
634ba319b5SDimitry Andric 
createWebAssemblyOptimizeLiveIntervals()643ca95b02SDimitry Andric FunctionPass *llvm::createWebAssemblyOptimizeLiveIntervals() {
653ca95b02SDimitry Andric   return new WebAssemblyOptimizeLiveIntervals();
663ca95b02SDimitry Andric }
673ca95b02SDimitry Andric 
runOnMachineFunction(MachineFunction & MF)68*b5893f02SDimitry Andric bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(
69*b5893f02SDimitry Andric     MachineFunction &MF) {
704ba319b5SDimitry Andric   LLVM_DEBUG(dbgs() << "********** Optimize LiveIntervals **********\n"
713ca95b02SDimitry Andric                        "********** Function: "
723ca95b02SDimitry Andric                     << MF.getName() << '\n');
733ca95b02SDimitry Andric 
743ca95b02SDimitry Andric   MachineRegisterInfo &MRI = MF.getRegInfo();
753ca95b02SDimitry Andric   LiveIntervals &LIS = getAnalysis<LiveIntervals>();
763ca95b02SDimitry Andric 
773ca95b02SDimitry Andric   // We don't preserve SSA form.
783ca95b02SDimitry Andric   MRI.leaveSSA();
793ca95b02SDimitry Andric 
80*b5893f02SDimitry Andric   assert(MRI.tracksLiveness() && "OptimizeLiveIntervals expects liveness");
813ca95b02SDimitry Andric 
823ca95b02SDimitry Andric   // Split multiple-VN LiveIntervals into multiple LiveIntervals.
833ca95b02SDimitry Andric   SmallVector<LiveInterval *, 4> SplitLIs;
843ca95b02SDimitry Andric   for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) {
853ca95b02SDimitry Andric     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
863ca95b02SDimitry Andric     if (MRI.reg_nodbg_empty(Reg))
873ca95b02SDimitry Andric       continue;
883ca95b02SDimitry Andric 
893ca95b02SDimitry Andric     LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs);
903ca95b02SDimitry Andric     SplitLIs.clear();
913ca95b02SDimitry Andric   }
923ca95b02SDimitry Andric 
933ca95b02SDimitry Andric   // In PrepareForLiveIntervals, we conservatively inserted IMPLICIT_DEF
943ca95b02SDimitry Andric   // instructions to satisfy LiveIntervals' requirement that all uses be
953ca95b02SDimitry Andric   // dominated by defs. Now that LiveIntervals has computed which of these
963ca95b02SDimitry Andric   // defs are actually needed and which are dead, remove the dead ones.
973ca95b02SDimitry Andric   for (auto MII = MF.begin()->begin(), MIE = MF.begin()->end(); MII != MIE;) {
983ca95b02SDimitry Andric     MachineInstr *MI = &*MII++;
993ca95b02SDimitry Andric     if (MI->isImplicitDef() && MI->getOperand(0).isDead()) {
1003ca95b02SDimitry Andric       LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
1013ca95b02SDimitry Andric       LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
1023ca95b02SDimitry Andric       LIS.RemoveMachineInstrFromMaps(*MI);
1033ca95b02SDimitry Andric       MI->eraseFromParent();
1043ca95b02SDimitry Andric     }
1053ca95b02SDimitry Andric   }
1063ca95b02SDimitry Andric 
1073ca95b02SDimitry Andric   return false;
1083ca95b02SDimitry Andric }
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