1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZTargetMachine.h"
11 #include "SystemZTargetTransformInfo.h"
12 #include "SystemZMachineScheduler.h"
13 #include "llvm/CodeGen/Passes.h"
14 #include "llvm/CodeGen/TargetPassConfig.h"
15 #include "llvm/Support/TargetRegistry.h"
16 #include "llvm/Transforms/Scalar.h"
17 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
18 
19 using namespace llvm;
20 
21 extern "C" void LLVMInitializeSystemZTarget() {
22   // Register the target.
23   RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
24 }
25 
26 // Determine whether we use the vector ABI.
27 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
28   // We use the vector ABI whenever the vector facility is avaiable.
29   // This is the case by default if CPU is z13 or later, and can be
30   // overridden via "[+-]vector" feature string elements.
31   bool VectorABI = true;
32   if (CPU.empty() || CPU == "generic" ||
33       CPU == "z10" || CPU == "z196" || CPU == "zEC12")
34     VectorABI = false;
35 
36   SmallVector<StringRef, 3> Features;
37   FS.split(Features, ',', -1, false /* KeepEmpty */);
38   for (auto &Feature : Features) {
39     if (Feature == "vector" || Feature == "+vector")
40       VectorABI = true;
41     if (Feature == "-vector")
42       VectorABI = false;
43   }
44 
45   return VectorABI;
46 }
47 
48 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
49                                      StringRef FS) {
50   bool VectorABI = UsesVectorABI(CPU, FS);
51   std::string Ret = "";
52 
53   // Big endian.
54   Ret += "E";
55 
56   // Data mangling.
57   Ret += DataLayout::getManglingComponent(TT);
58 
59   // Make sure that global data has at least 16 bits of alignment by
60   // default, so that we can refer to it using LARL.  We don't have any
61   // special requirements for stack variables though.
62   Ret += "-i1:8:16-i8:8:16";
63 
64   // 64-bit integers are naturally aligned.
65   Ret += "-i64:64";
66 
67   // 128-bit floats are aligned only to 64 bits.
68   Ret += "-f128:64";
69 
70   // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
71   if (VectorABI)
72     Ret += "-v128:64";
73 
74   // We prefer 16 bits of aligned for all globals; see above.
75   Ret += "-a:8:16";
76 
77   // Integer registers are 32 or 64 bits.
78   Ret += "-n32:64";
79 
80   return Ret;
81 }
82 
83 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
84   // Static code is suitable for use in a dynamic executable; there is no
85   // separate DynamicNoPIC model.
86   if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
87     return Reloc::Static;
88   return *RM;
89 }
90 
91 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
92                                            StringRef CPU, StringRef FS,
93                                            const TargetOptions &Options,
94                                            Optional<Reloc::Model> RM,
95                                            CodeModel::Model CM,
96                                            CodeGenOpt::Level OL)
97     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
98                         getEffectiveRelocModel(RM), CM, OL),
99       TLOF(make_unique<TargetLoweringObjectFileELF>()),
100       Subtarget(TT, CPU, FS, *this) {
101   initAsmInfo();
102 }
103 
104 SystemZTargetMachine::~SystemZTargetMachine() {}
105 
106 namespace {
107 /// SystemZ Code Generator Pass Configuration Options.
108 class SystemZPassConfig : public TargetPassConfig {
109 public:
110   SystemZPassConfig(SystemZTargetMachine *TM, PassManagerBase &PM)
111     : TargetPassConfig(TM, PM) {}
112 
113   SystemZTargetMachine &getSystemZTargetMachine() const {
114     return getTM<SystemZTargetMachine>();
115   }
116 
117   ScheduleDAGInstrs *
118   createPostMachineScheduler(MachineSchedContext *C) const override {
119     return new ScheduleDAGMI(C, make_unique<SystemZPostRASchedStrategy>(C),
120                              /*RemoveKillFlags=*/true);
121   }
122 
123   void addIRPasses() override;
124   bool addInstSelector() override;
125   bool addILPOpts() override;
126   void addPreSched2() override;
127   void addPreEmitPass() override;
128 };
129 } // end anonymous namespace
130 
131 void SystemZPassConfig::addIRPasses() {
132   if (getOptLevel() != CodeGenOpt::None)
133     addPass(createSystemZTDCPass());
134 
135   TargetPassConfig::addIRPasses();
136 }
137 
138 bool SystemZPassConfig::addInstSelector() {
139   addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
140 
141  if (getOptLevel() != CodeGenOpt::None)
142     addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
143 
144   return false;
145 }
146 
147 bool SystemZPassConfig::addILPOpts() {
148   addPass(&EarlyIfConverterID);
149   return true;
150 }
151 
152 void SystemZPassConfig::addPreSched2() {
153   addPass(createSystemZExpandPseudoPass(getSystemZTargetMachine()));
154 
155   if (getOptLevel() != CodeGenOpt::None)
156     addPass(&IfConverterID);
157 }
158 
159 void SystemZPassConfig::addPreEmitPass() {
160 
161   // Do instruction shortening before compare elimination because some
162   // vector instructions will be shortened into opcodes that compare
163   // elimination recognizes.
164   if (getOptLevel() != CodeGenOpt::None)
165     addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
166 
167   // We eliminate comparisons here rather than earlier because some
168   // transformations can change the set of available CC values and we
169   // generally want those transformations to have priority.  This is
170   // especially true in the commonest case where the result of the comparison
171   // is used by a single in-range branch instruction, since we will then
172   // be able to fuse the compare and the branch instead.
173   //
174   // For example, two-address NILF can sometimes be converted into
175   // three-address RISBLG.  NILF produces a CC value that indicates whether
176   // the low word is zero, but RISBLG does not modify CC at all.  On the
177   // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
178   // The CC value produced by NILL isn't useful for our purposes, but the
179   // value produced by RISBG can be used for any comparison with zero
180   // (not just equality).  So there are some transformations that lose
181   // CC values (while still being worthwhile) and others that happen to make
182   // the CC result more useful than it was originally.
183   //
184   // Another reason is that we only want to use BRANCH ON COUNT in cases
185   // where we know that the count register is not going to be spilled.
186   //
187   // Doing it so late makes it more likely that a register will be reused
188   // between the comparison and the branch, but it isn't clear whether
189   // preventing that would be a win or not.
190   if (getOptLevel() != CodeGenOpt::None)
191     addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
192   addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
193 
194   // Do final scheduling after all other optimizations, to get an
195   // optimal input for the decoder (branch relaxation must happen
196   // after block placement).
197   if (getOptLevel() != CodeGenOpt::None)
198     addPass(&PostMachineSchedulerID);
199 }
200 
201 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
202   return new SystemZPassConfig(this, PM);
203 }
204 
205 TargetIRAnalysis SystemZTargetMachine::getTargetIRAnalysis() {
206   return TargetIRAnalysis([this](const Function &F) {
207     return TargetTransformInfo(SystemZTTIImpl(this, F));
208   });
209 }
210