1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass tries to replace instructions with shorter forms.  For example,
11 // IILF can be replaced with LLILL or LLILH if the constant fits and if the
12 // other 32 bits of the GR64 destination are not live.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/LivePhysRegs.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "systemz-shorten-inst"
25 
26 namespace {
27 class SystemZShortenInst : public MachineFunctionPass {
28 public:
29   static char ID;
30   SystemZShortenInst(const SystemZTargetMachine &tm);
31 
32   const char *getPassName() const override {
33     return "SystemZ Instruction Shortening";
34   }
35 
36   bool processBlock(MachineBasicBlock &MBB);
37   bool runOnMachineFunction(MachineFunction &F) override;
38   MachineFunctionProperties getRequiredProperties() const override {
39     return MachineFunctionProperties().set(
40         MachineFunctionProperties::Property::AllVRegsAllocated);
41   }
42 
43 private:
44   bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
45   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
46   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
47   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
48   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
49   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
50 
51   const SystemZInstrInfo *TII;
52   const TargetRegisterInfo *TRI;
53   LivePhysRegs LiveRegs;
54 };
55 
56 char SystemZShortenInst::ID = 0;
57 } // end anonymous namespace
58 
59 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
60   return new SystemZShortenInst(TM);
61 }
62 
63 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
64   : MachineFunctionPass(ID), TII(nullptr) {}
65 
66 // Tie operands if MI has become a two-address instruction.
67 static void tieOpsIfNeeded(MachineInstr &MI) {
68   if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
69       !MI.getOperand(0).isTied())
70     MI.tieOperands(0, 1);
71 }
72 
73 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
74 // are the halfword immediate loads for the same word.  Try to use one of them
75 // instead of IIxF.
76 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
77                                     unsigned LLIxH) {
78   unsigned Reg = MI.getOperand(0).getReg();
79   // The new opcode will clear the other half of the GR64 reg, so
80   // cancel if that is live.
81   unsigned thisSubRegIdx =
82       (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
83                                                : SystemZ::subreg_l32);
84   unsigned otherSubRegIdx =
85       (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
86                                             : SystemZ::subreg_l32);
87   unsigned GR64BitReg =
88       TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
89   unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
90   if (LiveRegs.contains(OtherReg))
91     return false;
92 
93   uint64_t Imm = MI.getOperand(1).getImm();
94   if (SystemZ::isImmLL(Imm)) {
95     MI.setDesc(TII->get(LLIxL));
96     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
97     return true;
98   }
99   if (SystemZ::isImmLH(Imm)) {
100     MI.setDesc(TII->get(LLIxH));
101     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
102     MI.getOperand(1).setImm(Imm >> 16);
103     return true;
104   }
105   return false;
106 }
107 
108 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
110   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
111     MI.setDesc(TII->get(Opcode));
112     return true;
113   }
114   return false;
115 }
116 
117 // Change MI's opcode to Opcode if register operands 0 and 1 have a
118 // 4-bit encoding.
119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
120   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
121       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
122     MI.setDesc(TII->get(Opcode));
123     return true;
124   }
125   return false;
126 }
127 
128 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
129 // 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
130 // with op 1, if MI becomes 2-address.
131 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
132   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
133       MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
134       SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
135     MI.setDesc(TII->get(Opcode));
136     tieOpsIfNeeded(MI);
137     return true;
138   }
139   return false;
140 }
141 
142 // Calls shortenOn001 if CCLive is false. CC def operand is added in
143 // case of success.
144 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
145   if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
146     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
147       .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
148     return true;
149   }
150   return false;
151 }
152 
153 // MI is a vector-style conversion instruction with the operand order:
154 // destination, source, exact-suppress, rounding-mode.  If both registers
155 // have a 4-bit encoding then change it to Opcode, which has operand order:
156 // destination, rouding-mode, source, exact-suppress.
157 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
158   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
159       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
160     MachineOperand Dest(MI.getOperand(0));
161     MachineOperand Src(MI.getOperand(1));
162     MachineOperand Suppress(MI.getOperand(2));
163     MachineOperand Mode(MI.getOperand(3));
164     MI.RemoveOperand(3);
165     MI.RemoveOperand(2);
166     MI.RemoveOperand(1);
167     MI.RemoveOperand(0);
168     MI.setDesc(TII->get(Opcode));
169     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
170       .addOperand(Dest)
171       .addOperand(Mode)
172       .addOperand(Src)
173       .addOperand(Suppress);
174     return true;
175   }
176   return false;
177 }
178 
179 // Process all instructions in MBB.  Return true if something changed.
180 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
181   bool Changed = false;
182 
183   // Set up the set of live registers at the end of MBB (live out)
184   LiveRegs.clear();
185   LiveRegs.addLiveOuts(MBB);
186 
187   // Iterate backwards through the block looking for instructions to change.
188   for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
189     MachineInstr &MI = *MBBI;
190     switch (MI.getOpcode()) {
191     case SystemZ::IILF:
192       Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
193       break;
194 
195     case SystemZ::IIHF:
196       Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
197       break;
198 
199     case SystemZ::WFADB:
200       Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
201       break;
202 
203     case SystemZ::WFDDB:
204       Changed |= shortenOn001(MI, SystemZ::DDBR);
205       break;
206 
207     case SystemZ::WFIDB:
208       Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
209       break;
210 
211     case SystemZ::WLDEB:
212       Changed |= shortenOn01(MI, SystemZ::LDEBR);
213       break;
214 
215     case SystemZ::WLEDB:
216       Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
217       break;
218 
219     case SystemZ::WFMDB:
220       Changed |= shortenOn001(MI, SystemZ::MDBR);
221       break;
222 
223     case SystemZ::WFLCDB:
224       Changed |= shortenOn01(MI, SystemZ::LCDFR);
225       break;
226 
227     case SystemZ::WFLNDB:
228       Changed |= shortenOn01(MI, SystemZ::LNDFR);
229       break;
230 
231     case SystemZ::WFLPDB:
232       Changed |= shortenOn01(MI, SystemZ::LPDFR);
233       break;
234 
235     case SystemZ::WFSQDB:
236       Changed |= shortenOn01(MI, SystemZ::SQDBR);
237       break;
238 
239     case SystemZ::WFSDB:
240       Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
241       break;
242 
243     case SystemZ::WFCDB:
244       Changed |= shortenOn01(MI, SystemZ::CDBR);
245       break;
246 
247     case SystemZ::VL32:
248       // For z13 we prefer LDE over LE to avoid partial register dependencies.
249       Changed |= shortenOn0(MI, SystemZ::LDE32);
250       break;
251 
252     case SystemZ::VST32:
253       Changed |= shortenOn0(MI, SystemZ::STE);
254       break;
255 
256     case SystemZ::VL64:
257       Changed |= shortenOn0(MI, SystemZ::LD);
258       break;
259 
260     case SystemZ::VST64:
261       Changed |= shortenOn0(MI, SystemZ::STD);
262       break;
263     }
264 
265     LiveRegs.stepBackward(MI);
266   }
267 
268   return Changed;
269 }
270 
271 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
272   if (skipFunction(*F.getFunction()))
273     return false;
274 
275   const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
276   TII = ST.getInstrInfo();
277   TRI = ST.getRegisterInfo();
278   LiveRegs.init(TRI);
279 
280   bool Changed = false;
281   for (auto &MBB : F)
282     Changed |= processBlock(MBB);
283 
284   return Changed;
285 }
286