1//=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for ZEC12 to support instruction
11// scheduling and other instruction cost heuristics.
12//
13// Pseudos expanded right after isel do not need to be modelled here.
14//
15//===----------------------------------------------------------------------===//
16
17def ZEC12Model : SchedMachineModel {
18
19    let UnsupportedFeatures = Arch10UnsupportedFeatures.List;
20
21    let IssueWidth = 3;
22    let MicroOpBufferSize = 40;     // Issue queues
23    let LoadLatency = 1;            // Optimistic load latency.
24
25    let PostRAScheduler = 1;
26
27    // Extra cycles for a mispredicted branch.
28    let MispredictPenalty = 16;
29}
30
31let SchedModel = ZEC12Model in {
32// These definitions need the SchedModel value. They could be put in a
33// subtarget common include file, but it seems the include system in Tablegen
34// currently (2016) rejects multiple includes of same file.
35
36// Decoder grouping rules
37let NumMicroOps = 1 in {
38  def : WriteRes<NormalGr, []>;
39  def : WriteRes<BeginGroup, []> { let BeginGroup  = 1; }
40  def : WriteRes<EndGroup, []>   { let EndGroup    = 1; }
41}
42def : WriteRes<GroupAlone, []> {
43  let NumMicroOps = 3;
44  let BeginGroup  = 1;
45  let EndGroup    = 1;
46}
47def : WriteRes<GroupAlone2, []> {
48  let NumMicroOps = 6;
49  let BeginGroup  = 1;
50  let EndGroup    = 1;
51}
52def : WriteRes<GroupAlone3, []> {
53  let NumMicroOps = 9;
54  let BeginGroup  = 1;
55  let EndGroup    = 1;
56}
57
58// Incoming latency removed from the register operand which is used together
59// with a memory operand by the instruction.
60def : ReadAdvance<RegReadAdv, 4>;
61
62// LoadLatency (above) is not used for instructions in this file. This is
63// instead the role of LSULatency, which is the latency value added to the
64// result of loads and instructions with folded memory operands.
65def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
66
67let NumMicroOps = 0 in {
68  foreach L = 1-30 in {
69    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
70  }
71}
72
73// Execution units.
74def ZEC12_FXUnit : ProcResource<2>;
75def ZEC12_LSUnit : ProcResource<2>;
76def ZEC12_FPUnit : ProcResource<1>;
77def ZEC12_DFUnit : ProcResource<1>;
78def ZEC12_VBUnit : ProcResource<1>;
79def ZEC12_MCD    : ProcResource<1>;
80
81// Subtarget specific definitions of scheduling resources.
82let NumMicroOps = 0 in {
83  def : WriteRes<FXU, [ZEC12_FXUnit]>;
84  def : WriteRes<LSU, [ZEC12_LSUnit]>;
85  def : WriteRes<FPU, [ZEC12_FPUnit]>;
86  def : WriteRes<DFU, [ZEC12_DFUnit]>;
87  foreach Num = 2-6 in { let ResourceCycles = [Num] in {
88    def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
89    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
90    def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
91    def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
92  }}
93
94  def : WriteRes<VBU,  [ZEC12_VBUnit]>; // Virtual Branching Unit
95}
96
97def : WriteRes<MCD, [ZEC12_MCD]> { let NumMicroOps = 3;
98                                   let BeginGroup  = 1;
99                                   let EndGroup    = 1; }
100
101// -------------------------- INSTRUCTIONS ---------------------------------- //
102
103// InstRW constructs have been used in order to preserve the
104// readability of the InstrInfo files.
105
106// For each instruction, as matched by a regexp, provide a list of
107// resources that it needs. These will be combined into a SchedClass.
108
109//===----------------------------------------------------------------------===//
110// Stack allocation
111//===----------------------------------------------------------------------===//
112
113// Pseudo -> LA / LAY
114def : InstRW<[WLat1, FXU, NormalGr], (instregex "ADJDYNALLOC$")>;
115
116//===----------------------------------------------------------------------===//
117// Branch instructions
118//===----------------------------------------------------------------------===//
119
120// Branch
121def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
122def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?J(G)?(Asm.*)?$")>;
123def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
124def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
125def : InstRW<[WLat1, FXU, EndGroup], (instregex "BRCT(G)?$")>;
126def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCTH$")>;
127def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
128def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
129             (instregex "B(R)?X(H|L).*$")>;
130
131// Compare and branch
132def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
133def : InstRW<[WLat1, FXU, LSU, GroupAlone],
134             (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
135
136//===----------------------------------------------------------------------===//
137// Trap instructions
138//===----------------------------------------------------------------------===//
139
140// Trap
141def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Cond)?Trap$")>;
142
143// Compare and trap
144def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
145def : InstRW<[WLat1, FXU, NormalGr], (instregex "CL(G)?RT(Asm.*)?$")>;
146def : InstRW<[WLat1, FXU, NormalGr], (instregex "CL(F|G)IT(Asm.*)?$")>;
147def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
148
149//===----------------------------------------------------------------------===//
150// Call and return instructions
151//===----------------------------------------------------------------------===//
152
153// Call
154def : InstRW<[WLat1, FXU2, VBU, GroupAlone], (instregex "(Call)?BRAS$")>;
155def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BRASL$")>;
156def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
157def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
158
159// Return
160def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return$")>;
161def : InstRW<[WLat1, LSU, NormalGr], (instregex "CondReturn$")>;
162
163//===----------------------------------------------------------------------===//
164// Move instructions
165//===----------------------------------------------------------------------===//
166
167// Moves
168def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
169def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "MVI(Y)?$")>;
170
171// Move character
172def : InstRW<[WLat1, FXU, LSU3, GroupAlone], (instregex "MVC$")>;
173def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVCL(E|U)?$")>;
174
175// Pseudo -> reg move
176def : InstRW<[WLat1, FXU, NormalGr], (instregex "COPY(_TO_REGCLASS)?$")>;
177def : InstRW<[WLat1, FXU, NormalGr], (instregex "EXTRACT_SUBREG$")>;
178def : InstRW<[WLat1, FXU, NormalGr], (instregex "INSERT_SUBREG$")>;
179def : InstRW<[WLat1, FXU, NormalGr], (instregex "REG_SEQUENCE$")>;
180
181// Loads
182def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
183def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
184def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
185
186def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIH(F|H|L)$")>;
187def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIL(F|H|L)$")>;
188
189def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>;
190def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;
191def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>;
192
193// Load and trap
194def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "L(FH|G)?AT$")>;
195
196// Load and test
197def : InstRW<[WLat1LSU, WLat1LSU, LSU, FXU, NormalGr], (instregex "LT(G)?$")>;
198def : InstRW<[WLat1, FXU, NormalGr], (instregex "LT(G)?R$")>;
199
200// Stores
201def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
202def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST128$")>;
203def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
204
205// String moves.
206def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVST$")>;
207
208//===----------------------------------------------------------------------===//
209// Conditional move instructions
210//===----------------------------------------------------------------------===//
211
212def : InstRW<[WLat2, FXU, NormalGr], (instregex "LOC(G)?R(Asm.*)?$")>;
213def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
214             (instregex "LOC(G)?(Asm.*)?$")>;
215def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STOC(G)?(Asm.*)?$")>;
216
217//===----------------------------------------------------------------------===//
218// Sign extensions
219//===----------------------------------------------------------------------===//
220
221def : InstRW<[WLat1, FXU, NormalGr], (instregex "L(B|H|G)R$")>;
222def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(B|H|F)R$")>;
223
224def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LTGF$")>;
225def : InstRW<[WLat1, FXU, NormalGr], (instregex "LTGFR$")>;
226
227def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
228def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(Y)?$")>;
229def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
230def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(B|H|F)$")>;
231def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
232
233//===----------------------------------------------------------------------===//
234// Zero extensions
235//===----------------------------------------------------------------------===//
236
237def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;
238def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;
239def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLG(C|H|F|T)R$")>;
240def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;
241def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;
242def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LL(C|H)H$")>;
243def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;
244def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
245
246// Load and trap
247def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LLG(F|T)?AT$")>;
248
249//===----------------------------------------------------------------------===//
250// Truncations
251//===----------------------------------------------------------------------===//
252
253def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STC(H|Y|Mux)?$")>;
254def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
255def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STCM(H|Y)?$")>;
256
257//===----------------------------------------------------------------------===//
258// Multi-register moves
259//===----------------------------------------------------------------------===//
260
261// Load multiple (estimated average of 5 ops)
262def : InstRW<[WLat10, WLat10, LSU5, GroupAlone], (instregex "LM(H|Y|G)?$")>;
263
264// Load multiple disjoint
265def : InstRW<[WLat30, WLat30, MCD], (instregex "LMD$")>;
266
267// Store multiple (estimated average of 3 ops)
268def : InstRW<[WLat1, LSU2, FXU5, GroupAlone], (instregex "STM(H|Y|G)?$")>;
269
270//===----------------------------------------------------------------------===//
271// Byte swaps
272//===----------------------------------------------------------------------===//
273
274def : InstRW<[WLat1, FXU, NormalGr], (instregex "LRV(G)?R$")>;
275def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LRV(G|H)?$")>;
276def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STRV(G|H)?$")>;
277def : InstRW<[WLat30, MCD], (instregex "MVCIN$")>;
278
279//===----------------------------------------------------------------------===//
280// Load address instructions
281//===----------------------------------------------------------------------===//
282
283def : InstRW<[WLat1, FXU, NormalGr], (instregex "LA(Y|RL)?$")>;
284
285// Load the Global Offset Table address
286def : InstRW<[WLat1, FXU, NormalGr], (instregex "GOT$")>;
287
288//===----------------------------------------------------------------------===//
289// Absolute and Negation
290//===----------------------------------------------------------------------===//
291
292def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "LP(G)?R$")>;
293def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "L(N|P)GFR$")>;
294def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "LN(R|GR)$")>;
295def : InstRW<[WLat1, FXU, NormalGr], (instregex "LC(R|GR)$")>;
296def : InstRW<[WLat2, WLat2, FXU2, GroupAlone], (instregex "LCGFR$")>;
297
298//===----------------------------------------------------------------------===//
299// Insertion
300//===----------------------------------------------------------------------===//
301
302def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "IC(Y)?$")>;
303def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
304             (instregex "IC32(Y)?$")>;
305def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
306             (instregex "ICM(H|Y)?$")>;
307def : InstRW<[WLat1, FXU, NormalGr], (instregex "II(F|H|L)Mux$")>;
308def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHF(64)?$")>;
309def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHH(64)?$")>;
310def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHL(64)?$")>;
311def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILF(64)?$")>;
312def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILH(64)?$")>;
313def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILL(64)?$")>;
314
315//===----------------------------------------------------------------------===//
316// Addition
317//===----------------------------------------------------------------------===//
318
319def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
320             (instregex "A(L)?(Y)?$")>;
321def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "A(L)?SI$")>;
322def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
323             (instregex "AH(Y)?$")>;
324def : InstRW<[WLat1, FXU, NormalGr], (instregex "AIH$")>;
325def : InstRW<[WLat1, FXU, NormalGr], (instregex "AFI(Mux)?$")>;
326def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGFI$")>;
327def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGHI(K)?$")>;
328def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGR(K)?$")>;
329def : InstRW<[WLat1, FXU, NormalGr], (instregex "AHI(K)?$")>;
330def : InstRW<[WLat1, FXU, NormalGr], (instregex "AHIMux(K)?$")>;
331def : InstRW<[WLat1, FXU, NormalGr], (instregex "AL(FI|HSIK)$")>;
332def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
333             (instregex "ALGF$")>;
334def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGHSIK$")>;
335def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGF(I|R)$")>;
336def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGR(K)?$")>;
337def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALR(K)?$")>;
338def : InstRW<[WLat1, FXU, NormalGr], (instregex "AR(K)?$")>;
339def : InstRW<[WLat1, FXU, NormalGr], (instregex "A(L)?HHHR$")>;
340def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "A(L)?HHLR$")>;
341def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALSIH(N)?$")>;
342def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
343             (instregex "A(L)?G$")>;
344def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "A(L)?GSI$")>;
345
346// Logical addition with carry
347def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, GroupAlone],
348             (instregex "ALC(G)?$")>;
349def : InstRW<[WLat2, WLat2, FXU, GroupAlone], (instregex "ALC(G)?R$")>;
350
351// Add with sign extension (32 -> 64)
352def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
353             (instregex "AGF$")>;
354def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "AGFR$")>;
355
356//===----------------------------------------------------------------------===//
357// Subtraction
358//===----------------------------------------------------------------------===//
359
360def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
361             (instregex "S(G|Y)?$")>;
362def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
363             (instregex "SH(Y)?$")>;
364def : InstRW<[WLat1, FXU, NormalGr], (instregex "SGR(K)?$")>;
365def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLFI$")>;
366def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
367             (instregex "SL(G|GF|Y)?$")>;
368def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLGF(I|R)$")>;
369def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLGR(K)?$")>;
370def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLR(K)?$")>;
371def : InstRW<[WLat1, FXU, NormalGr], (instregex "SR(K)?$")>;
372def : InstRW<[WLat1, FXU, NormalGr], (instregex "S(L)?HHHR$")>;
373def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "S(L)?HHLR$")>;
374
375// Subtraction with borrow
376def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, GroupAlone],
377             (instregex "SLB(G)?$")>;
378def : InstRW<[WLat2, WLat2, FXU, GroupAlone], (instregex "SLB(G)?R$")>;
379
380// Subtraction with sign extension (32 -> 64)
381def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
382             (instregex "SGF$")>;
383def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "SGFR$")>;
384
385//===----------------------------------------------------------------------===//
386// AND
387//===----------------------------------------------------------------------===//
388
389def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
390             (instregex "N(G|Y)?$")>;
391def : InstRW<[WLat1, FXU, NormalGr], (instregex "NGR(K)?$")>;
392def : InstRW<[WLat1, FXU, NormalGr], (instregex "NI(FMux|HMux|LMux)$")>;
393def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "NI(Y)?$")>;
394def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHF(64)?$")>;
395def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHH(64)?$")>;
396def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHL(64)?$")>;
397def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILF(64)?$")>;
398def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILH(64)?$")>;
399def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILL(64)?$")>;
400def : InstRW<[WLat1, FXU, NormalGr], (instregex "NR(K)?$")>;
401def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "NC$")>;
402
403//===----------------------------------------------------------------------===//
404// OR
405//===----------------------------------------------------------------------===//
406
407def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
408             (instregex "O(G|Y)?$")>;
409def : InstRW<[WLat1, FXU, NormalGr], (instregex "OGR(K)?$")>;
410def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "OI(Y)?$")>;
411def : InstRW<[WLat1, FXU, NormalGr], (instregex "OI(FMux|HMux|LMux)$")>;
412def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHF(64)?$")>;
413def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHH(64)?$")>;
414def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHL(64)?$")>;
415def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILF(64)?$")>;
416def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILH(64)?$")>;
417def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILL(64)?$")>;
418def : InstRW<[WLat1, FXU, NormalGr], (instregex "OR(K)?$")>;
419def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "OC$")>;
420
421//===----------------------------------------------------------------------===//
422// XOR
423//===----------------------------------------------------------------------===//
424
425def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
426             (instregex "X(G|Y)?$")>;
427def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "XI(Y)?$")>;
428def : InstRW<[WLat1, FXU, NormalGr], (instregex "XIFMux$")>;
429def : InstRW<[WLat1, FXU, NormalGr], (instregex "XGR(K)?$")>;
430def : InstRW<[WLat1, FXU, NormalGr], (instregex "XIHF(64)?$")>;
431def : InstRW<[WLat1, FXU, NormalGr], (instregex "XILF(64)?$")>;
432def : InstRW<[WLat1, FXU, NormalGr], (instregex "XR(K)?$")>;
433def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "XC$")>;
434
435//===----------------------------------------------------------------------===//
436// Multiplication
437//===----------------------------------------------------------------------===//
438
439def : InstRW<[WLat6LSU, RegReadAdv, FXU, LSU, NormalGr],
440             (instregex "MS(GF|Y)?$")>;
441def : InstRW<[WLat6, FXU, NormalGr], (instregex "MS(R|FI)$")>;
442def : InstRW<[WLat8LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "MSG$")>;
443def : InstRW<[WLat8, FXU, NormalGr], (instregex "MSGR$")>;
444def : InstRW<[WLat6, FXU, NormalGr], (instregex "MSGF(I|R)$")>;
445def : InstRW<[WLat11LSU, RegReadAdv, FXU2, LSU, GroupAlone],
446             (instregex "MLG$")>;
447def : InstRW<[WLat9, FXU2, GroupAlone], (instregex "MLGR$")>;
448def : InstRW<[WLat5, FXU, NormalGr], (instregex "MGHI$")>;
449def : InstRW<[WLat5, FXU, NormalGr], (instregex "MHI$")>;
450def : InstRW<[WLat5LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "MH(Y)?$")>;
451def : InstRW<[WLat7, FXU2, GroupAlone], (instregex "M(L)?R$")>;
452def : InstRW<[WLat7LSU, RegReadAdv, FXU2, LSU, GroupAlone],
453             (instregex "M(FY|L)?$")>;
454
455//===----------------------------------------------------------------------===//
456// Division and remainder
457//===----------------------------------------------------------------------===//
458
459def : InstRW<[WLat30, FPU4, FXU5, GroupAlone3], (instregex "DR$")>;
460def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU4, GroupAlone3],
461             (instregex "D$")>;
462def : InstRW<[WLat30, FPU4, FXU4, GroupAlone3], (instregex "DSG(F)?R$")>;
463def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU3, GroupAlone3],
464             (instregex "DSG(F)?$")>;
465def : InstRW<[WLat30, FPU4, FXU5, GroupAlone3], (instregex "DL(G)?R$")>;
466def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU4, GroupAlone3],
467             (instregex "DL(G)?$")>;
468
469//===----------------------------------------------------------------------===//
470// Shifts
471//===----------------------------------------------------------------------===//
472
473def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLL(G|K)?$")>;
474def : InstRW<[WLat1, FXU, NormalGr], (instregex "SRL(G|K)?$")>;
475def : InstRW<[WLat1, FXU, NormalGr], (instregex "SRA(G|K)?$")>;
476def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLA(G|K)?$")>;
477def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
478             (instregex "S(L|R)D(A|L)$")>;
479
480// Rotate
481def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
482
483// Rotate and insert
484def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?$")>;
485def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
486def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
487def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
488
489// Rotate and Select
490def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
491
492//===----------------------------------------------------------------------===//
493// Comparison
494//===----------------------------------------------------------------------===//
495
496def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "C(G|Y|Mux|RL)?$")>;
497def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(F|H)I(Mux)?$")>;
498def : InstRW<[WLat1, FXU, NormalGr], (instregex "CG(F|H)I$")>;
499def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
500def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(G)?R$")>;
501def : InstRW<[WLat1, FXU, NormalGr], (instregex "CIH$")>;
502def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CHF$")>;
503def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CHSI$")>;
504def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
505             (instregex "CL(Y|Mux)?$")>;
506def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLFHSI$")>;
507def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLFI(Mux)?$")>;
508def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLG$")>;
509def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLG(HRL|HSI)$")>;
510def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLGF$")>;
511def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLGFRL$")>;
512def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLGF(I|R)$")>;
513def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLGR$")>;
514def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLGRL$")>;
515def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLHF$")>;
516def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
517def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLIH$")>;
518def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLI(Y)?$")>;
519def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLR$")>;
520def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLRL$")>;
521def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(L)?HHR$")>;
522def : InstRW<[WLat2, FXU, NormalGr], (instregex "C(L)?HLR$")>;
523
524// Compare halfword
525def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CH(Y)?$")>;
526def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CHRL$")>;
527def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CGH$")>;
528def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CGHRL$")>;
529def : InstRW<[WLat2LSU, FXU2, LSU, GroupAlone], (instregex "CHHSI$")>;
530
531// Compare with sign extension (32 -> 64)
532def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CGF$")>;
533def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CGFRL$")>;
534def : InstRW<[WLat2, FXU, NormalGr], (instregex "CGFR$")>;
535
536// Compare logical character
537def : InstRW<[WLat9, FXU, LSU2, GroupAlone], (instregex "CLC$")>;
538def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLCL(E|U)?$")>;
539def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLST$")>;
540
541// Test under mask
542def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "TM(Y)?$")>;
543def : InstRW<[WLat1, FXU, NormalGr], (instregex "TM(H|L)Mux$")>;
544def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMHH(64)?$")>;
545def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMHL(64)?$")>;
546def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMLH(64)?$")>;
547def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMLL(64)?$")>;
548
549// Compare logical characters under mask
550def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
551             (instregex "CLM(H|Y)?$")>;
552
553//===----------------------------------------------------------------------===//
554// Prefetch and execution hint
555//===----------------------------------------------------------------------===//
556
557def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;
558def : InstRW<[WLat1, LSU, NormalGr], (instregex "BP(R)?P$")>;
559def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIAI$")>;
560
561//===----------------------------------------------------------------------===//
562// Atomic operations
563//===----------------------------------------------------------------------===//
564
565def : InstRW<[WLat1, LSU, EndGroup], (instregex "Serialize$")>;
566
567def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAA(G)?$")>;
568def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAAL(G)?$")>;
569def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAN(G)?$")>;
570def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAO(G)?$")>;
571def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAX(G)?$")>;
572
573// Test and set
574def : InstRW<[WLat1LSU, FXU, LSU, EndGroup], (instregex "TS$")>;
575
576// Compare and swap
577def : InstRW<[WLat2LSU, WLat2LSU, FXU2, LSU, GroupAlone],
578             (instregex "CS(G|Y)?$")>;
579
580// Compare double and swap
581def : InstRW<[WLat5LSU, WLat5LSU, FXU5, LSU, GroupAlone2],
582             (instregex "CDS(Y)?$")>;
583def : InstRW<[WLat12, WLat12, FXU6, LSU2, GroupAlone],
584             (instregex "CDSG$")>;
585
586// Compare and swap and store
587def : InstRW<[WLat30, MCD], (instregex "CSST$")>;
588
589// Perform locked operation
590def : InstRW<[WLat30, MCD], (instregex "PLO$")>;
591
592// Load/store pair from/to quadword
593def : InstRW<[WLat4LSU, LSU2, GroupAlone], (instregex "LPQ$")>;
594def : InstRW<[WLat1, FXU2, LSU2, GroupAlone], (instregex "STPQ$")>;
595
596// Load pair disjoint
597def : InstRW<[WLat2LSU, WLat2LSU, LSU2, GroupAlone], (instregex "LPD(G)?$")>;
598
599//===----------------------------------------------------------------------===//
600// Translate and convert
601//===----------------------------------------------------------------------===//
602
603def : InstRW<[WLat1, LSU, GroupAlone], (instregex "TR$")>;
604def : InstRW<[WLat30, WLat30, WLat30, FXU3, LSU2, GroupAlone2],
605             (instregex "TRT$")>;
606def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRTR$")>;
607def : InstRW<[WLat30, WLat30, MCD], (instregex "TRE$")>;
608def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRT(R)?E(Opt)?$")>;
609def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TR(T|O)(T|O)(Opt)?$")>;
610def : InstRW<[WLat30, WLat30, WLat30, MCD],
611             (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
612def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
613
614//===----------------------------------------------------------------------===//
615// Message-security assist
616//===----------------------------------------------------------------------===//
617
618def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD],
619             (instregex "KM(C|F|O|CTR)?$")>;
620def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "(KIMD|KLMD|KMAC|PCC)$")>;
621
622//===----------------------------------------------------------------------===//
623// Decimal arithmetic
624//===----------------------------------------------------------------------===//
625
626def : InstRW<[WLat30, RegReadAdv, FXU, DFU2, LSU2, GroupAlone2],
627             (instregex "CVBG$")>;
628def : InstRW<[WLat20, RegReadAdv, FXU, DFU, LSU, GroupAlone],
629             (instregex "CVB(Y)?$")>;
630def : InstRW<[WLat1, FXU3, DFU4, LSU, GroupAlone3], (instregex "CVDG$")>;
631def : InstRW<[WLat1, FXU2, DFU, LSU, GroupAlone], (instregex "CVD(Y)?$")>;
632def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "MV(N|O|Z)$")>;
633def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "(PACK|PKA|PKU)$")>;
634def : InstRW<[WLat10, LSU5, GroupAlone], (instregex "UNPK(A|U)$")>;
635def : InstRW<[WLat1, FXU, LSU2, GroupAlone], (instregex "UNPK$")>;
636
637def : InstRW<[WLat11LSU, FXU, DFU4, LSU2, GroupAlone],
638             (instregex "(A|S|ZA)P$")>;
639def : InstRW<[WLat1, FXU, DFU4, LSU2, GroupAlone], (instregex "(M|D)P$")>;
640def : InstRW<[WLat15, FXU2, DFU4, LSU3, GroupAlone], (instregex "SRP$")>;
641def : InstRW<[WLat11, DFU4, LSU2, GroupAlone], (instregex "CP$")>;
642def : InstRW<[WLat5LSU, DFU2, LSU2, GroupAlone], (instregex "TP$")>;
643def : InstRW<[WLat30, MCD], (instregex "ED(MK)?$")>;
644
645//===----------------------------------------------------------------------===//
646// Access registers
647//===----------------------------------------------------------------------===//
648
649// Extract/set/copy access register
650def : InstRW<[WLat3, LSU, NormalGr], (instregex "(EAR|SAR|CPYA)$")>;
651
652// Load address extended
653def : InstRW<[WLat5, LSU, FXU, GroupAlone], (instregex "LAE(Y)?$")>;
654
655// Load/store access multiple (not modeled precisely)
656def : InstRW<[WLat10, WLat10, LSU5, GroupAlone], (instregex "LAM(Y)?$")>;
657def : InstRW<[WLat1, FXU5, LSU5, GroupAlone], (instregex "STAM(Y)?$")>;
658
659//===----------------------------------------------------------------------===//
660// Program mask and addressing mode
661//===----------------------------------------------------------------------===//
662
663// Insert Program Mask
664def : InstRW<[WLat3, FXU, EndGroup], (instregex "IPM$")>;
665
666// Set Program Mask
667def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
668
669// Branch and link
670def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "BAL(R)?$")>;
671
672// Test addressing mode
673def : InstRW<[WLat1, FXU, NormalGr], (instregex "TAM$")>;
674
675// Set addressing mode
676def : InstRW<[WLat1, LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
677
678// Branch (and save) and set mode.
679def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BSM$")>;
680def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "BASSM$")>;
681
682//===----------------------------------------------------------------------===//
683// Transactional execution
684//===----------------------------------------------------------------------===//
685
686// Transaction begin
687def : InstRW<[WLat9, LSU2, FXU5, GroupAlone], (instregex "TBEGIN(C)?$")>;
688
689// Transaction end
690def : InstRW<[WLat4, LSU, GroupAlone], (instregex "TEND$")>;
691
692// Transaction abort
693def : InstRW<[WLat30, MCD], (instregex "TABORT$")>;
694
695// Extract Transaction Nesting Depth
696def : InstRW<[WLat30, MCD], (instregex "ETND$")>;
697
698// Nontransactional store
699def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "NTSTG$")>;
700
701//===----------------------------------------------------------------------===//
702// Processor assist
703//===----------------------------------------------------------------------===//
704
705def : InstRW<[WLat30, MCD], (instregex "PPA$")>;
706
707//===----------------------------------------------------------------------===//
708// Miscellaneous Instructions.
709//===----------------------------------------------------------------------===//
710
711// Find leftmost one
712def : InstRW<[WLat7, WLat7, FXU2, GroupAlone], (instregex "FLOGR$")>;
713
714// Population count
715def : InstRW<[WLat3, WLat3, FXU, NormalGr], (instregex "POPCNT$")>;
716
717// String instructions
718def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "SRST(U)?$")>;
719def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CUSE$")>;
720
721// Various complex instructions
722def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CFC$")>;
723def : InstRW<[WLat30, WLat30, WLat30, WLat30, WLat30, WLat30, MCD],
724             (instregex "UPT$")>;
725def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CKSM$")>;
726def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CMPSC$")>;
727
728// Execute
729def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
730
731//===----------------------------------------------------------------------===//
732// .insn directive instructions
733//===----------------------------------------------------------------------===//
734
735// An "empty" sched-class will be assigned instead of the "invalid sched-class".
736// getNumDecoderSlots() will then return 1 instead of 0.
737def : InstRW<[], (instregex "Insn.*")>;
738
739
740// ----------------------------- Floating point ----------------------------- //
741
742//===----------------------------------------------------------------------===//
743// FP: Move instructions
744//===----------------------------------------------------------------------===//
745
746// Load zero
747def : InstRW<[WLat1, FXU, NormalGr], (instregex "LZ(DR|ER)$")>;
748def : InstRW<[WLat2, FXU2, GroupAlone], (instregex "LZXR$")>;
749
750// Load
751def : InstRW<[WLat1, FXU, NormalGr], (instregex "LER$")>;
752def : InstRW<[WLat1, FXU, NormalGr], (instregex "LD(R|R32|GR)$")>;
753def : InstRW<[WLat3, FXU, NormalGr], (instregex "LGDR$")>;
754def : InstRW<[WLat2, FXU2, GroupAlone], (instregex "LXR$")>;
755
756// Load and Test
757def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
758def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
759def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "LTXBR(Compare)?$")>;
760
761// Copy sign
762def : InstRW<[WLat5, FXU2, GroupAlone], (instregex "CPSDR(d|s)(d|s)$")>;
763
764//===----------------------------------------------------------------------===//
765// FP: Load instructions
766//===----------------------------------------------------------------------===//
767
768def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(E|D)(Y|E32)?$")>;
769def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;
770
771//===----------------------------------------------------------------------===//
772// FP: Store instructions
773//===----------------------------------------------------------------------===//
774
775def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
776def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STX$")>;
777
778//===----------------------------------------------------------------------===//
779// FP: Conversion instructions
780//===----------------------------------------------------------------------===//
781
782// Load rounded
783def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
784def : InstRW<[WLat9, FPU2, NormalGr], (instregex "L(E|D)XBR(A)?$")>;
785
786// Load lengthened
787def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
788def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
789def : InstRW<[WLat11LSU, FPU4, LSU, GroupAlone], (instregex "LX(E|D)B$")>;
790def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "LX(E|D)BR$")>;
791
792// Convert from fixed / logical
793def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
794def : InstRW<[WLat11, FXU, FPU4, GroupAlone2], (instregex "CX(F|G)BR(A?)$")>;
795def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
796def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
797def : InstRW<[WLat11, FXU, FPU4, GroupAlone2], (instregex "CXL(F|G)BR$")>;
798
799// Convert to fixed / logical
800def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
801             (instregex "C(F|G)(E|D)BR(A?)$")>;
802def : InstRW<[WLat12, WLat12, FXU, FPU2, GroupAlone],
803             (instregex "C(F|G)XBR(A?)$")>;
804def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
805             (instregex "CL(F|G)(E|D)BR$")>;
806def : InstRW<[WLat12, WLat12, FXU, FPU2, GroupAlone], (instregex "CL(F|G)XBR$")>;
807
808//===----------------------------------------------------------------------===//
809// FP: Unary arithmetic
810//===----------------------------------------------------------------------===//
811
812// Load Complement / Negative / Positive
813def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "L(C|N|P)(E|D)BR$")>;
814def : InstRW<[WLat1, FXU, NormalGr], (instregex "L(C|N|P)DFR(_32)?$")>;
815def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "L(C|N|P)XBR$")>;
816
817// Square root
818def : InstRW<[WLat30, FPU, LSU, NormalGr], (instregex "SQ(E|D)B$")>;
819def : InstRW<[WLat30, FPU, NormalGr], (instregex "SQ(E|D)BR$")>;
820def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "SQXBR$")>;
821
822// Load FP integer
823def : InstRW<[WLat7, FPU, NormalGr], (instregex "FI(E|D)BR(A)?$")>;
824def : InstRW<[WLat15, FPU4, GroupAlone], (instregex "FIXBR(A)?$")>;
825
826//===----------------------------------------------------------------------===//
827// FP: Binary arithmetic
828//===----------------------------------------------------------------------===//
829
830// Addition
831def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
832             (instregex "A(E|D)B$")>;
833def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "A(E|D)BR$")>;
834def : InstRW<[WLat20, WLat20, FPU4, GroupAlone], (instregex "AXBR$")>;
835
836// Subtraction
837def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
838             (instregex "S(E|D)B$")>;
839def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "S(E|D)BR$")>;
840def : InstRW<[WLat20, WLat20, FPU4, GroupAlone], (instregex "SXBR$")>;
841
842// Multiply
843def : InstRW<[WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
844             (instregex "M(D|DE|EE)B$")>;
845def : InstRW<[WLat7, FPU, NormalGr], (instregex "M(D|DE|EE)BR$")>;
846def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone],
847             (instregex "MXDB$")>;
848def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MXDBR$")>;
849def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "MXBR$")>;
850
851// Multiply and add / subtract
852def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],
853             (instregex "M(A|S)EB$")>;
854def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
855def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],
856             (instregex "M(A|S)DB$")>;
857def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
858
859// Division
860def : InstRW<[WLat30, RegReadAdv, FPU, LSU, NormalGr], (instregex "D(E|D)B$")>;
861def : InstRW<[WLat30, FPU, NormalGr], (instregex "D(E|D)BR$")>;
862def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "DXBR$")>;
863
864// Divide to integer
865def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "DI(E|D)BR$")>;
866
867//===----------------------------------------------------------------------===//
868// FP: Comparisons
869//===----------------------------------------------------------------------===//
870
871// Compare
872def : InstRW<[WLat11LSU, RegReadAdv, FPU, LSU, NormalGr],
873             (instregex "(K|C)(E|D)B$")>;
874def : InstRW<[WLat9, FPU, NormalGr], (instregex "(K|C)(E|D)BR$")>;
875def : InstRW<[WLat30, FPU2, NormalGr], (instregex "(K|C)XBR$")>;
876
877// Test Data Class
878def : InstRW<[WLat15, FPU, LSU, NormalGr], (instregex "TC(E|D)B$")>;
879def : InstRW<[WLat15, FPU4, LSU, GroupAlone], (instregex "TCXB$")>;
880
881//===----------------------------------------------------------------------===//
882// FP: Floating-point control register instructions
883//===----------------------------------------------------------------------===//
884
885def : InstRW<[WLat4, FXU, LSU, GroupAlone], (instregex "EFPC$")>;
886def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "STFPC$")>;
887def : InstRW<[WLat1, LSU, GroupAlone], (instregex "SFPC$")>;
888def : InstRW<[WLat1, LSU2, GroupAlone], (instregex "LFPC$")>;
889def : InstRW<[WLat30, MCD], (instregex "SFASR$")>;
890def : InstRW<[WLat30, MCD], (instregex "LFAS$")>;
891def : InstRW<[WLat2, FXU, GroupAlone], (instregex "SRNM(B|T)?$")>;
892
893
894// --------------------- Hexadecimal floating point ------------------------- //
895
896//===----------------------------------------------------------------------===//
897// HFP: Move instructions
898//===----------------------------------------------------------------------===//
899
900// Load and Test
901def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)R$")>;
902def : InstRW<[WLat9, WLat9, FPU4, GroupAlone], (instregex "LTXR$")>;
903
904//===----------------------------------------------------------------------===//
905// HFP: Conversion instructions
906//===----------------------------------------------------------------------===//
907
908// Load rounded
909def : InstRW<[WLat7, FPU, NormalGr], (instregex "(LEDR|LRER)$")>;
910def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEXR$")>;
911def : InstRW<[WLat9, FPU, NormalGr], (instregex "(LDXR|LRDR)$")>;
912
913// Load lengthened
914def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LDE$")>;
915def : InstRW<[WLat1, FXU, NormalGr], (instregex "LDER$")>;
916def : InstRW<[WLat11LSU, FPU4, LSU, GroupAlone], (instregex "LX(E|D)$")>;
917def : InstRW<[WLat9, FPU4, GroupAlone], (instregex "LX(E|D)R$")>;
918
919// Convert from fixed
920def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)R$")>;
921def : InstRW<[WLat10, FXU, FPU4, GroupAlone2], (instregex "CX(F|G)R$")>;
922
923// Convert to fixed
924def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
925             (instregex "C(F|G)(E|D)R$")>;
926def : InstRW<[WLat30, WLat30, FXU, FPU2, GroupAlone], (instregex "C(F|G)XR$")>;
927
928// Convert BFP to HFP / HFP to BFP.
929def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "THD(E)?R$")>;
930def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "TB(E)?DR$")>;
931
932//===----------------------------------------------------------------------===//
933// HFP: Unary arithmetic
934//===----------------------------------------------------------------------===//
935
936// Load Complement / Negative / Positive
937def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "L(C|N|P)(E|D)R$")>;
938def : InstRW<[WLat9, WLat9, FPU4, GroupAlone], (instregex "L(C|N|P)XR$")>;
939
940// Halve
941def : InstRW<[WLat7, FPU, NormalGr], (instregex "H(E|D)R$")>;
942
943// Square root
944def : InstRW<[WLat30, FPU, LSU, NormalGr], (instregex "SQ(E|D)$")>;
945def : InstRW<[WLat30, FPU, NormalGr], (instregex "SQ(E|D)R$")>;
946def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "SQXR$")>;
947
948// Load FP integer
949def : InstRW<[WLat7, FPU, NormalGr], (instregex "FI(E|D)R$")>;
950def : InstRW<[WLat15, FPU4, GroupAlone], (instregex "FIXR$")>;
951
952//===----------------------------------------------------------------------===//
953// HFP: Binary arithmetic
954//===----------------------------------------------------------------------===//
955
956// Addition
957def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
958             (instregex "A(E|D|U|W)$")>;
959def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "A(E|D|U|W)R$")>;
960def : InstRW<[WLat15, WLat15, FPU4, GroupAlone], (instregex "AXR$")>;
961
962// Subtraction
963def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
964             (instregex "S(E|D|U|W)$")>;
965def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "S(E|D|U|W)R$")>;
966def : InstRW<[WLat15, WLat15, FPU4, GroupAlone], (instregex "SXR$")>;
967
968// Multiply
969def : InstRW<[WLat7LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "M(D|EE)$")>;
970def : InstRW<[WLat8LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "M(DE|E)$")>;
971def : InstRW<[WLat7, FPU, NormalGr], (instregex "M(D|EE)R$")>;
972def : InstRW<[WLat8, FPU, NormalGr], (instregex "M(DE|E)R$")>;
973def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone], (instregex "MXD$")>;
974def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MXDR$")>;
975def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "MXR$")>;
976def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone], (instregex "MY$")>;
977def : InstRW<[WLat7LSU, RegReadAdv, FPU2, LSU, GroupAlone],
978             (instregex "MY(H|L)$")>;
979def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MYR$")>;
980def : InstRW<[WLat7, FPU, GroupAlone], (instregex "MY(H|L)R$")>;
981
982// Multiply and add / subtract
983def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],
984             (instregex "M(A|S)(E|D)$")>;
985def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)(E|D)R$")>;
986def : InstRW<[WLat11LSU, RegReadAdv, RegReadAdv, FPU4, LSU, GroupAlone],
987             (instregex "MAY$")>;
988def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],
989             (instregex "MAY(H|L)$")>;
990def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MAYR$")>;
991def : InstRW<[WLat7, FPU, GroupAlone], (instregex "MAY(H|L)R$")>;
992
993// Division
994def : InstRW<[WLat30, RegReadAdv, FPU, LSU, NormalGr], (instregex "D(E|D)$")>;
995def : InstRW<[WLat30, FPU, NormalGr], (instregex "D(E|D)R$")>;
996def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "DXR$")>;
997
998//===----------------------------------------------------------------------===//
999// HFP: Comparisons
1000//===----------------------------------------------------------------------===//
1001
1002// Compare
1003def : InstRW<[WLat11LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "C(E|D)$")>;
1004def : InstRW<[WLat9, FPU, NormalGr], (instregex "C(E|D)R$")>;
1005def : InstRW<[WLat15, FPU2, NormalGr], (instregex "CXR$")>;
1006
1007
1008// ------------------------ Decimal floating point -------------------------- //
1009
1010//===----------------------------------------------------------------------===//
1011// DFP: Move instructions
1012//===----------------------------------------------------------------------===//
1013
1014// Load and Test
1015def : InstRW<[WLat4, WLat4, DFU, NormalGr], (instregex "LTDTR$")>;
1016def : InstRW<[WLat6, WLat6, DFU4, GroupAlone], (instregex "LTXTR$")>;
1017
1018//===----------------------------------------------------------------------===//
1019// DFP: Conversion instructions
1020//===----------------------------------------------------------------------===//
1021
1022// Load rounded
1023def : InstRW<[WLat30, DFU, NormalGr], (instregex "LEDTR$")>;
1024def : InstRW<[WLat30, DFU2, NormalGr], (instregex "LDXTR$")>;
1025
1026// Load lengthened
1027def : InstRW<[WLat7, DFU, NormalGr], (instregex "LDETR$")>;
1028def : InstRW<[WLat6, DFU4, GroupAlone], (instregex "LXDTR$")>;
1029
1030// Convert from fixed / logical
1031def : InstRW<[WLat9, FXU, DFU, GroupAlone], (instregex "CDFTR$")>;
1032def : InstRW<[WLat30, FXU, DFU, GroupAlone], (instregex "CDGTR(A)?$")>;
1033def : InstRW<[WLat5, FXU, DFU4, GroupAlone2], (instregex "CXFTR(A)?$")>;
1034def : InstRW<[WLat30, FXU, DFU4, GroupAlone2], (instregex "CXGTR(A)?$")>;
1035def : InstRW<[WLat9, FXU, DFU, GroupAlone], (instregex "CDL(F|G)TR$")>;
1036def : InstRW<[WLat9, FXU, DFU4, GroupAlone2], (instregex "CXLFTR$")>;
1037def : InstRW<[WLat5, FXU, DFU4, GroupAlone2], (instregex "CXLGTR$")>;
1038
1039// Convert to fixed / logical
1040def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "CFDTR(A)?$")>;
1041def : InstRW<[WLat30, WLat30, FXU, DFU, GroupAlone], (instregex "CGDTR(A)?$")>;
1042def : InstRW<[WLat7, WLat7, FXU, DFU2, GroupAlone], (instregex "CFXTR$")>;
1043def : InstRW<[WLat30, WLat30, FXU, DFU2, GroupAlone], (instregex "CGXTR(A)?$")>;
1044def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "CL(F|G)DTR$")>;
1045def : InstRW<[WLat7, WLat7, FXU, DFU2, GroupAlone], (instregex "CL(F|G)XTR$")>;
1046
1047// Convert from / to signed / unsigned packed
1048def : InstRW<[WLat5, FXU, DFU, GroupAlone], (instregex "CD(S|U)TR$")>;
1049def : InstRW<[WLat8, FXU2, DFU4, GroupAlone2], (instregex "CX(S|U)TR$")>;
1050def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "C(S|U)DTR$")>;
1051def : InstRW<[WLat12, FXU2, DFU4, GroupAlone2], (instregex "C(S|U)XTR$")>;
1052
1053// Convert from / to zoned
1054def : InstRW<[WLat4LSU, LSU, DFU2, GroupAlone], (instregex "CDZT$")>;
1055def : InstRW<[WLat11LSU, LSU2, DFU4, GroupAlone3], (instregex "CXZT$")>;
1056def : InstRW<[WLat1, FXU, LSU, DFU2, GroupAlone], (instregex "CZDT$")>;
1057def : InstRW<[WLat1, FXU, LSU, DFU2, GroupAlone], (instregex "CZXT$")>;
1058
1059// Perform floating-point operation
1060def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "PFPO$")>;
1061
1062//===----------------------------------------------------------------------===//
1063// DFP: Unary arithmetic
1064//===----------------------------------------------------------------------===//
1065
1066// Load FP integer
1067def : InstRW<[WLat8, DFU, NormalGr], (instregex "FIDTR$")>;
1068def : InstRW<[WLat10, DFU4, GroupAlone], (instregex "FIXTR$")>;
1069
1070// Extract biased exponent
1071def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "EEDTR$")>;
1072def : InstRW<[WLat8, FXU, DFU2, GroupAlone], (instregex "EEXTR$")>;
1073
1074// Extract significance
1075def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "ESDTR$")>;
1076def : InstRW<[WLat8, FXU, DFU2, GroupAlone], (instregex "ESXTR$")>;
1077
1078//===----------------------------------------------------------------------===//
1079// DFP: Binary arithmetic
1080//===----------------------------------------------------------------------===//
1081
1082// Addition
1083def : InstRW<[WLat9, WLat9, DFU, NormalGr], (instregex "ADTR(A)?$")>;
1084def : InstRW<[WLat30, WLat30, DFU4, GroupAlone], (instregex "AXTR(A)?$")>;
1085
1086// Subtraction
1087def : InstRW<[WLat9, WLat9, DFU, NormalGr], (instregex "SDTR(A)?$")>;
1088def : InstRW<[WLat30, WLat30, DFU4, GroupAlone], (instregex "SXTR(A)?$")>;
1089
1090// Multiply
1091def : InstRW<[WLat30, DFU, NormalGr], (instregex "MDTR(A)?$")>;
1092def : InstRW<[WLat30, DFU4, GroupAlone], (instregex "MXTR(A)?$")>;
1093
1094// Division
1095def : InstRW<[WLat30, DFU, NormalGr], (instregex "DDTR(A)?$")>;
1096def : InstRW<[WLat30, DFU4, GroupAlone], (instregex "DXTR(A)?$")>;
1097
1098// Quantize
1099def : InstRW<[WLat8, WLat8, DFU, NormalGr], (instregex "QADTR$")>;
1100def : InstRW<[WLat10, WLat10, DFU4, GroupAlone], (instregex "QAXTR$")>;
1101
1102// Reround
1103def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "RRDTR$")>;
1104def : InstRW<[WLat30, WLat30, FXU, DFU4, GroupAlone2], (instregex "RRXTR$")>;
1105
1106// Shift significand left/right
1107def : InstRW<[WLat7LSU, LSU, DFU, GroupAlone], (instregex "S(L|R)DT$")>;
1108def : InstRW<[WLat11LSU, LSU, DFU4, GroupAlone], (instregex "S(L|R)XT$")>;
1109
1110// Insert biased exponent
1111def : InstRW<[WLat5, FXU, DFU, GroupAlone], (instregex "IEDTR$")>;
1112def : InstRW<[WLat7, FXU, DFU4, GroupAlone2], (instregex "IEXTR$")>;
1113
1114//===----------------------------------------------------------------------===//
1115// DFP: Comparisons
1116//===----------------------------------------------------------------------===//
1117
1118// Compare
1119def : InstRW<[WLat9, DFU, NormalGr], (instregex "(K|C)DTR$")>;
1120def : InstRW<[WLat10, DFU2, NormalGr], (instregex "(K|C)XTR$")>;
1121
1122// Compare biased exponent
1123def : InstRW<[WLat4, DFU, NormalGr], (instregex "CEDTR$")>;
1124def : InstRW<[WLat5, DFU2, NormalGr], (instregex "CEXTR$")>;
1125
1126// Test Data Class/Group
1127def : InstRW<[WLat9, LSU, DFU, NormalGr], (instregex "TD(C|G)DT$")>;
1128def : InstRW<[WLat10, LSU, DFU, NormalGr], (instregex "TD(C|G)ET$")>;
1129def : InstRW<[WLat10, LSU, DFU2, NormalGr], (instregex "TD(C|G)XT$")>;
1130
1131
1132// -------------------------------- System ---------------------------------- //
1133
1134//===----------------------------------------------------------------------===//
1135// System: Program-Status Word Instructions
1136//===----------------------------------------------------------------------===//
1137
1138def : InstRW<[WLat30, WLat30, MCD], (instregex "EPSW$")>;
1139def : InstRW<[WLat30, MCD], (instregex "LPSW(E)?$")>;
1140def : InstRW<[WLat3, FXU, GroupAlone], (instregex "IPK$")>;
1141def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
1142def : InstRW<[WLat1, LSU, EndGroup], (instregex "SSM$")>;
1143def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "ST(N|O)SM$")>;
1144def : InstRW<[WLat3, FXU, NormalGr], (instregex "IAC$")>;
1145def : InstRW<[WLat1, LSU, EndGroup], (instregex "SAC(F)?$")>;
1146
1147//===----------------------------------------------------------------------===//
1148// System: Control Register Instructions
1149//===----------------------------------------------------------------------===//
1150
1151def : InstRW<[WLat10, WLat10, FXU, LSU, NormalGr], (instregex "LCTL(G)?$")>;
1152def : InstRW<[WLat1, FXU5, LSU5, GroupAlone], (instregex "STCT(L|G)$")>;
1153def : InstRW<[LSULatency, LSU, NormalGr], (instregex "E(P|S)A(I)?R$")>;
1154def : InstRW<[WLat30, MCD], (instregex "SSA(I)?R$")>;
1155def : InstRW<[WLat30, MCD], (instregex "ESEA$")>;
1156
1157//===----------------------------------------------------------------------===//
1158// System: Prefix-Register Instructions
1159//===----------------------------------------------------------------------===//
1160
1161def : InstRW<[WLat30, MCD], (instregex "S(T)?PX$")>;
1162
1163//===----------------------------------------------------------------------===//
1164// System: Storage-Key and Real Memory Instructions
1165//===----------------------------------------------------------------------===//
1166
1167def : InstRW<[WLat30, MCD], (instregex "ISKE$")>;
1168def : InstRW<[WLat30, MCD], (instregex "IVSK$")>;
1169def : InstRW<[WLat30, MCD], (instregex "SSKE(Opt)?$")>;
1170def : InstRW<[WLat30, MCD], (instregex "RRB(E|M)$")>;
1171def : InstRW<[WLat30, MCD], (instregex "PFMF$")>;
1172def : InstRW<[WLat30, WLat30, MCD], (instregex "TB$")>;
1173def : InstRW<[WLat30, MCD], (instregex "PGIN$")>;
1174def : InstRW<[WLat30, MCD], (instregex "PGOUT$")>;
1175
1176//===----------------------------------------------------------------------===//
1177// System: Dynamic-Address-Translation Instructions
1178//===----------------------------------------------------------------------===//
1179
1180def : InstRW<[WLat30, MCD], (instregex "IPTE(Opt)?(Opt)?$")>;
1181def : InstRW<[WLat30, MCD], (instregex "IDTE(Opt)?$")>;
1182def : InstRW<[WLat30, MCD], (instregex "CRDTE(Opt)?$")>;
1183def : InstRW<[WLat30, MCD], (instregex "PTLB$")>;
1184def : InstRW<[WLat30, WLat30, MCD], (instregex "CSP(G)?$")>;
1185def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "LPTEA$")>;
1186def : InstRW<[WLat30, WLat30, MCD], (instregex "LRA(Y|G)?$")>;
1187def : InstRW<[WLat30, MCD], (instregex "STRAG$")>;
1188def : InstRW<[WLat30, MCD], (instregex "LURA(G)?$")>;
1189def : InstRW<[WLat30, MCD], (instregex "STUR(A|G)$")>;
1190def : InstRW<[WLat30, MCD], (instregex "TPROT$")>;
1191
1192//===----------------------------------------------------------------------===//
1193// System: Memory-move Instructions
1194//===----------------------------------------------------------------------===//
1195
1196def : InstRW<[WLat30, MCD], (instregex "MVC(K|P|S)$")>;
1197def : InstRW<[WLat30, MCD], (instregex "MVC(S|D)K$")>;
1198def : InstRW<[WLat30, MCD], (instregex "MVCOS$")>;
1199def : InstRW<[WLat30, MCD], (instregex "MVPG$")>;
1200
1201//===----------------------------------------------------------------------===//
1202// System: Address-Space Instructions
1203//===----------------------------------------------------------------------===//
1204
1205def : InstRW<[WLat30, MCD], (instregex "LASP$")>;
1206def : InstRW<[WLat1, LSU, GroupAlone], (instregex "PALB$")>;
1207def : InstRW<[WLat30, MCD], (instregex "PC$")>;
1208def : InstRW<[WLat30, MCD], (instregex "PR$")>;
1209def : InstRW<[WLat30, MCD], (instregex "PT(I)?$")>;
1210def : InstRW<[WLat30, MCD], (instregex "RP$")>;
1211def : InstRW<[WLat30, MCD], (instregex "BS(G|A)$")>;
1212def : InstRW<[WLat30, MCD], (instregex "TAR$")>;
1213
1214//===----------------------------------------------------------------------===//
1215// System: Linkage-Stack Instructions
1216//===----------------------------------------------------------------------===//
1217
1218def : InstRW<[WLat30, MCD], (instregex "BAKR$")>;
1219def : InstRW<[WLat30, MCD], (instregex "EREG(G)?$")>;
1220def : InstRW<[WLat30, WLat30, MCD], (instregex "(E|M)STA$")>;
1221
1222//===----------------------------------------------------------------------===//
1223// System: Time-Related Instructions
1224//===----------------------------------------------------------------------===//
1225
1226def : InstRW<[WLat30, MCD], (instregex "PTFF$")>;
1227def : InstRW<[WLat30, MCD], (instregex "SCK$")>;
1228def : InstRW<[WLat30, MCD], (instregex "SCKPF$")>;
1229def : InstRW<[WLat30, MCD], (instregex "SCKC$")>;
1230def : InstRW<[WLat30, MCD], (instregex "SPT$")>;
1231def : InstRW<[WLat9, FXU, LSU2, GroupAlone], (instregex "STCK(F)?$")>;
1232def : InstRW<[WLat20, LSU4, FXU2, GroupAlone2], (instregex "STCKE$")>;
1233def : InstRW<[WLat30, MCD], (instregex "STCKC$")>;
1234def : InstRW<[WLat30, MCD], (instregex "STPT$")>;
1235
1236//===----------------------------------------------------------------------===//
1237// System: CPU-Related Instructions
1238//===----------------------------------------------------------------------===//
1239
1240def : InstRW<[WLat30, MCD], (instregex "STAP$")>;
1241def : InstRW<[WLat30, MCD], (instregex "STIDP$")>;
1242def : InstRW<[WLat30, WLat30, MCD], (instregex "STSI$")>;
1243def : InstRW<[WLat30, WLat30, MCD], (instregex "STFL(E)?$")>;
1244def : InstRW<[WLat30, MCD], (instregex "ECAG$")>;
1245def : InstRW<[WLat30, WLat30, MCD], (instregex "ECTG$")>;
1246def : InstRW<[WLat30, MCD], (instregex "PTF$")>;
1247def : InstRW<[WLat30, MCD], (instregex "PCKMO$")>;
1248
1249//===----------------------------------------------------------------------===//
1250// System: Miscellaneous Instructions
1251//===----------------------------------------------------------------------===//
1252
1253def : InstRW<[WLat30, MCD], (instregex "SVC$")>;
1254def : InstRW<[WLat1, FXU, GroupAlone], (instregex "MC$")>;
1255def : InstRW<[WLat30, MCD], (instregex "DIAG$")>;
1256def : InstRW<[WLat1, FXU, NormalGr], (instregex "TRAC(E|G)$")>;
1257def : InstRW<[WLat30, MCD], (instregex "TRAP(2|4)$")>;
1258def : InstRW<[WLat30, MCD], (instregex "SIG(P|A)$")>;
1259def : InstRW<[WLat30, MCD], (instregex "SIE$")>;
1260
1261//===----------------------------------------------------------------------===//
1262// System: CPU-Measurement Facility Instructions
1263//===----------------------------------------------------------------------===//
1264
1265def : InstRW<[WLat1, FXU, NormalGr], (instregex "LPP$")>;
1266def : InstRW<[WLat30, WLat30, MCD], (instregex "ECPGA$")>;
1267def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
1268def : InstRW<[WLat30, MCD], (instregex "LCCTL$")>;
1269def : InstRW<[WLat30, MCD], (instregex "L(P|S)CTL$")>;
1270def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
1271def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
1272
1273//===----------------------------------------------------------------------===//
1274// System: I/O Instructions
1275//===----------------------------------------------------------------------===//
1276
1277def : InstRW<[WLat30, MCD], (instregex "(C|H|R|X)SCH$")>;
1278def : InstRW<[WLat30, MCD], (instregex "(M|S|ST|T)SCH$")>;
1279def : InstRW<[WLat30, MCD], (instregex "RCHP$")>;
1280def : InstRW<[WLat30, MCD], (instregex "SCHM$")>;
1281def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
1282def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
1283def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
1284
1285}
1286
1287