1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14let hasNoSchedulingInfo = 1 in { 15 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 16 [(callseq_start timm:$amt1, timm:$amt2)]>; 17 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 18 [(callseq_end timm:$amt1, timm:$amt2)]>; 19} 20 21let hasSideEffects = 0 in { 22 // Takes as input the value of the stack pointer after a dynamic allocation 23 // has been made. Sets the output to the address of the dynamically- 24 // allocated area itself, skipping the outgoing arguments. 25 // 26 // This expands to an LA or LAY instruction. We restrict the offset 27 // to the range of LA and keep the LAY range in reserve for when 28 // the size of the outgoing arguments is added. 29 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 30 [(set GR64:$dst, dynalloc12only:$src)]>; 31} 32 33//===----------------------------------------------------------------------===// 34// Branch instructions 35//===----------------------------------------------------------------------===// 36 37// Conditional branches. 38let isBranch = 1, isTerminator = 1, Uses = [CC] in { 39 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 40 // with the condition-code mask being the first operand. It seems friendlier 41 // to use mnemonic forms like JE and JLH when writing out the assembly though. 42 let isCodeGenOnly = 1 in { 43 // An assembler extended mnemonic for BRC. 44 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 45 // An assembler extended mnemonic for BRCL. (The extension is "G" 46 // rather than "L" because "JL" is "Jump if Less".) 47 def BRCL : CondBranchRIL<"jg#", 0xC04>; 48 let isIndirectBranch = 1 in { 49 def BC : CondBranchRX<"b#", 0x47>; 50 def BCR : CondBranchRR<"b#r", 0x07>; 51 def BIC : CondBranchRXY<"bi#", 0xe347>, 52 Requires<[FeatureMiscellaneousExtensions2]>; 53 } 54 } 55 56 // Allow using the raw forms directly from the assembler (and occasional 57 // special code generation needs) as well. 58 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 59 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 60 let isIndirectBranch = 1 in { 61 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 62 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 63 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 64 Requires<[FeatureMiscellaneousExtensions2]>; 65 } 66 67 // Define AsmParser extended mnemonics for each general condition-code mask 68 // (integer or floating-point) 69 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 70 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 71 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 72 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 73 let isIndirectBranch = 1 in { 74 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 75 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 76 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 77 Requires<[FeatureMiscellaneousExtensions2]>; 78 } 79 } 80} 81 82// Unconditional branches. These are in fact simply variants of the 83// conditional branches with the condition mask set to "always". 84let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 85 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 86 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 87 let isIndirectBranch = 1 in { 88 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 89 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 90 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 91 Requires<[FeatureMiscellaneousExtensions2]>; 92 } 93} 94 95// NOPs. These are again variants of the conditional branches, 96// with the condition mask set to "never". 97def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 98def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 99 100// Fused compare-and-branch instructions. 101// 102// These instructions do not use or clobber the condition codes. 103// We nevertheless pretend that the relative compare-and-branch 104// instructions clobber CC, so that we can lower them to separate 105// comparisons and BRCLs if the branch ends up being out of range. 106let isBranch = 1, isTerminator = 1 in { 107 // As for normal branches, we handle these instructions internally in 108 // their raw CRJ-like form, but use assembly macros like CRJE when writing 109 // them out. Using the *Pair multiclasses, we also create the raw forms. 110 let Defs = [CC] in { 111 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 112 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 113 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 114 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 115 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 116 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 117 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 118 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 119 } 120 let isIndirectBranch = 1 in { 121 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 122 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 123 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 124 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 125 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 126 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 127 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 128 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 129 } 130 131 // Define AsmParser mnemonics for each integer condition-code mask. 132 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 133 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 134 let Defs = [CC] in { 135 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 136 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 137 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 138 imm32sx8>; 139 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 140 imm64sx8>; 141 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 142 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 143 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 144 imm32zx8>; 145 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 146 imm64zx8>; 147 } 148 let isIndirectBranch = 1 in { 149 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 150 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 151 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 152 imm32sx8>; 153 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 154 imm64sx8>; 155 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 156 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 157 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 158 imm32zx8>; 159 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 160 imm64zx8>; 161 } 162 } 163} 164 165// Decrement a register and branch if it is nonzero. These don't clobber CC, 166// but we might need to split long relative branches into sequences that do. 167let isBranch = 1, isTerminator = 1 in { 168 let Defs = [CC] in { 169 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 170 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 171 } 172 // This doesn't need to clobber CC since we never need to split it. 173 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 174 Requires<[FeatureHighWord]>; 175 176 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 177 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 178 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 179 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 180} 181 182let isBranch = 1, isTerminator = 1 in { 183 let Defs = [CC] in { 184 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 185 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 186 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 187 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 188 } 189 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 190 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 191 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 192 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 193} 194 195//===----------------------------------------------------------------------===// 196// Trap instructions 197//===----------------------------------------------------------------------===// 198 199// Unconditional trap. 200let hasCtrlDep = 1 in 201 def Trap : Alias<4, (outs), (ins), [(trap)]>; 202 203// Conditional trap. 204let hasCtrlDep = 1, Uses = [CC] in 205 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 206 207// Fused compare-and-trap instructions. 208let hasCtrlDep = 1 in { 209 // These patterns work the same way as for compare-and-branch. 210 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 211 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 212 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 213 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 214 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 215 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 216 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 217 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 218 let Predicates = [FeatureMiscellaneousExtensions] in { 219 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 220 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 221 } 222 223 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 224 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 225 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 226 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 227 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 228 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 229 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 230 imm32sx16>; 231 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 232 imm64sx16>; 233 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 234 imm32zx16>; 235 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 236 imm64zx16>; 237 let Predicates = [FeatureMiscellaneousExtensions] in { 238 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 239 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 240 } 241 } 242} 243 244//===----------------------------------------------------------------------===// 245// Call and return instructions 246//===----------------------------------------------------------------------===// 247 248// Define the general form of the call instructions for the asm parser. 249// These instructions don't hard-code %r14 as the return address register. 250let isCall = 1, Defs = [CC] in { 251 def BRAS : CallRI <"bras", 0xA75>; 252 def BRASL : CallRIL<"brasl", 0xC05>; 253 def BAS : CallRX <"bas", 0x4D>; 254 def BASR : CallRR <"basr", 0x0D>; 255} 256 257// Regular calls. 258let isCall = 1, Defs = [R14D, CC] in { 259 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 260 [(z_call pcrel32:$I2)]>; 261 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 262 [(z_call ADDR64:$R2)]>; 263} 264 265// TLS calls. These will be lowered into a call to __tls_get_offset, 266// with an extra relocation specifying the TLS symbol. 267let isCall = 1, Defs = [R14D, CC] in { 268 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 269 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 270 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 271 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 272} 273 274// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 275// are argument registers and since branching to R0 is a no-op. 276let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 277 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 278 [(z_sibcall pcrel32:$I2)]>; 279 let Uses = [R1D] in 280 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 281} 282 283// Conditional sibling calls. 284let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 285 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 286 pcrel32:$I2), []>; 287 let Uses = [R1D] in 288 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 289} 290 291// Fused compare and conditional sibling calls. 292let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 293 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 294 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 295 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 296 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 297 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 298 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 299 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 300 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 301} 302 303// A return instruction (br %r14). 304let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 305 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 306 307// A conditional return instruction (bcr <cond>, %r14). 308let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 309 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 310 311// Fused compare and conditional returns. 312let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 313 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 314 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 315 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 316 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 317 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 318 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 319 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 320 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 321} 322 323//===----------------------------------------------------------------------===// 324// Select instructions 325//===----------------------------------------------------------------------===// 326 327def Select32Mux : SelectWrapper<i32, GRX32>, Requires<[FeatureHighWord]>; 328def Select32 : SelectWrapper<i32, GR32>; 329def Select64 : SelectWrapper<i64, GR64>; 330 331// We don't define 32-bit Mux stores if we don't have STOCFH, because the 332// low-only STOC should then always be used if possible. 333defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 334 nonvolatile_anyextloadi8, bdxaddr20only>, 335 Requires<[FeatureHighWord]>; 336defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 337 nonvolatile_anyextloadi16, bdxaddr20only>, 338 Requires<[FeatureHighWord]>; 339defm CondStore32Mux : CondStores<GRX32, nonvolatile_store, 340 nonvolatile_load, bdxaddr20only>, 341 Requires<[FeatureLoadStoreOnCond2]>; 342defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 343 nonvolatile_anyextloadi8, bdxaddr20only>; 344defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 345 nonvolatile_anyextloadi16, bdxaddr20only>; 346defm CondStore32 : CondStores<GR32, nonvolatile_store, 347 nonvolatile_load, bdxaddr20only>; 348 349defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 350 nonvolatile_anyextloadi8, bdxaddr20only>; 351defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 352 nonvolatile_anyextloadi16, bdxaddr20only>; 353defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 354 nonvolatile_anyextloadi32, bdxaddr20only>; 355defm CondStore64 : CondStores<GR64, nonvolatile_store, 356 nonvolatile_load, bdxaddr20only>; 357 358//===----------------------------------------------------------------------===// 359// Move instructions 360//===----------------------------------------------------------------------===// 361 362// Register moves. 363let hasSideEffects = 0 in { 364 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 365 def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>, 366 Requires<[FeatureHighWord]>; 367 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 368 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 369} 370let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 371 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 372 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 373} 374 375// Immediate moves. 376let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 377 isReMaterializable = 1 in { 378 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 379 // deopending on the choice of register. 380 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 381 Requires<[FeatureHighWord]>; 382 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 383 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 384 385 // Other 16-bit immediates. 386 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 387 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 388 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 389 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 390 391 // 32-bit immediates. 392 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 393 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 394 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 395} 396 397// Register loads. 398let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 399 // Expands to L, LY or LFH, depending on the choice of register. 400 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 401 Requires<[FeatureHighWord]>; 402 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 403 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 404 Requires<[FeatureHighWord]>; 405 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 406 407 // These instructions are split after register allocation, so we don't 408 // want a custom inserter. 409 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 410 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 411 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 412 } 413} 414let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 415 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 416 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 417} 418 419let canFoldAsLoad = 1 in { 420 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 421 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 422} 423 424// Load and zero rightmost byte. 425let Predicates = [FeatureLoadAndZeroRightmostByte] in { 426 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 427 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 428 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 429 (LZRF bdxaddr20only:$src)>; 430 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 431 (LZRG bdxaddr20only:$src)>; 432} 433 434// Load and trap. 435let Predicates = [FeatureLoadAndTrap] in { 436 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 437 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 438 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 439} 440 441// Register stores. 442let SimpleBDXStore = 1 in { 443 // Expands to ST, STY or STFH, depending on the choice of register. 444 def STMux : StoreRXYPseudo<store, GRX32, 4>, 445 Requires<[FeatureHighWord]>; 446 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 447 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 448 Requires<[FeatureHighWord]>; 449 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 450 451 // These instructions are split after register allocation, so we don't 452 // want a custom inserter. 453 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 454 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 455 [(store GR128:$src, bdxaddr20only128:$dst)]>; 456 } 457} 458def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 459def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 460 461// 8-bit immediate stores to 8-bit fields. 462defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 463 464// 16-bit immediate stores to 16-, 32- or 64-bit fields. 465def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 466def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 467def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 468 469// Memory-to-memory moves. 470let mayLoad = 1, mayStore = 1 in 471 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 472let mayLoad = 1, mayStore = 1, Defs = [CC] in { 473 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 474 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 475 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 476} 477 478// String moves. 479let mayLoad = 1, mayStore = 1, Defs = [CC] in 480 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 481 482//===----------------------------------------------------------------------===// 483// Conditional move instructions 484//===----------------------------------------------------------------------===// 485 486let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 487 // Load immediate on condition. Matched via DAG pattern and created 488 // by the PeepholeOptimizer via FoldImmediate. 489 let hasSideEffects = 0 in { 490 // Expands to LOCHI or LOCHHI, depending on the choice of register. 491 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 492 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 493 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 494 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 495 } 496 497 // Move register on condition. Expanded from Select* pseudos and 498 // created by early if-conversion. 499 let hasSideEffects = 0, isCommutable = 1 in { 500 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 501 // depending on the choice of registers. 502 def LOCRMux : CondBinaryRRFPseudo<GRX32, GRX32>; 503 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 504 } 505 506 // Load on condition. Matched via DAG pattern. 507 // Expands to LOC or LOCFH, depending on the choice of register. 508 def LOCMux : CondUnaryRSYPseudo<nonvolatile_load, GRX32, 4>; 509 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, nonvolatile_load, GRH32, 4>; 510 511 // Store on condition. Expanded from CondStore* pseudos. 512 // Expands to STOC or STOCFH, depending on the choice of register. 513 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 514 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 515 516 // Define AsmParser extended mnemonics for each general condition-code mask. 517 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 518 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 519 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 520 imm32sx16>; 521 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 522 imm64sx16>; 523 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 524 imm32sx16>; 525 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 526 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 527 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 528 } 529} 530 531let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 532 // Move register on condition. Expanded from Select* pseudos and 533 // created by early if-conversion. 534 let hasSideEffects = 0, isCommutable = 1 in { 535 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 536 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 537 } 538 539 // Load on condition. Matched via DAG pattern. 540 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 541 defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 542 543 // Store on condition. Expanded from CondStore* pseudos. 544 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 545 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 546 547 // Define AsmParser extended mnemonics for each general condition-code mask. 548 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 549 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 550 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 551 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 552 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 553 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 554 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 555 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 556 } 557} 558//===----------------------------------------------------------------------===// 559// Sign extensions 560//===----------------------------------------------------------------------===// 561// 562// Note that putting these before zero extensions mean that we will prefer 563// them for anyextload*. There's not really much to choose between the two 564// either way, but signed-extending loads have a short LH and a long LHY, 565// while zero-extending loads have only the long LLH. 566// 567//===----------------------------------------------------------------------===// 568 569// 32-bit extensions from registers. 570let hasSideEffects = 0 in { 571 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 572 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 573} 574 575// 64-bit extensions from registers. 576let hasSideEffects = 0 in { 577 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 578 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 579 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 580} 581let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 582 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 583 584// Match 32-to-64-bit sign extensions in which the source is already 585// in a 64-bit register. 586def : Pat<(sext_inreg GR64:$src, i32), 587 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 588 589// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 590// depending on the choice of register. 591def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 592 Requires<[FeatureHighWord]>; 593def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 594def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 595 Requires<[FeatureHighWord]>; 596 597// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 598// depending on the choice of register. 599def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 600 Requires<[FeatureHighWord]>; 601defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 602def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 603 Requires<[FeatureHighWord]>; 604def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 605 606// 64-bit extensions from memory. 607def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 608def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 609def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 610def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 611def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 612let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 613 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 614 615//===----------------------------------------------------------------------===// 616// Zero extensions 617//===----------------------------------------------------------------------===// 618 619// 32-bit extensions from registers. 620let hasSideEffects = 0 in { 621 // Expands to LLCR or RISB[LH]G, depending on the choice of registers. 622 def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 623 Requires<[FeatureHighWord]>; 624 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 625 // Expands to LLHR or RISB[LH]G, depending on the choice of registers. 626 def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 627 Requires<[FeatureHighWord]>; 628 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 629} 630 631// 64-bit extensions from registers. 632let hasSideEffects = 0 in { 633 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 634 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 635 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 636} 637 638// Match 32-to-64-bit zero extensions in which the source is already 639// in a 64-bit register. 640def : Pat<(and GR64:$src, 0xffffffff), 641 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 642 643// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 644// depending on the choice of register. 645def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 646 Requires<[FeatureHighWord]>; 647def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 648def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 649 Requires<[FeatureHighWord]>; 650 651// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 652// depending on the choice of register. 653def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 654 Requires<[FeatureHighWord]>; 655def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 656def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 657 Requires<[FeatureHighWord]>; 658def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 659 660// 64-bit extensions from memory. 661def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 662def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 663def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 664def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 665def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 666 667// 31-to-64-bit zero extensions. 668def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 669def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 670def : Pat<(and GR64:$src, 0x7fffffff), 671 (LLGTR GR64:$src)>; 672def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 673 (LLGT bdxaddr20only:$src)>; 674 675// Load and zero rightmost byte. 676let Predicates = [FeatureLoadAndZeroRightmostByte] in { 677 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 678 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 679 (LLZRGF bdxaddr20only:$src)>; 680} 681 682// Load and trap. 683let Predicates = [FeatureLoadAndTrap] in { 684 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 685 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 686} 687 688// Extend GR64s to GR128s. 689let usesCustomInserter = 1 in 690 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 691 692//===----------------------------------------------------------------------===// 693// "Any" extensions 694//===----------------------------------------------------------------------===// 695 696// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 697def : Pat<(i64 (anyext GR32:$src)), 698 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 699 700// Extend GR64s to GR128s. 701let usesCustomInserter = 1 in 702 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 703 704//===----------------------------------------------------------------------===// 705// Truncations 706//===----------------------------------------------------------------------===// 707 708// Truncations of 64-bit registers to 32-bit registers. 709def : Pat<(i32 (trunc GR64:$src)), 710 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 711 712// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 713// STC, STCY or STCH, depending on the choice of register. 714def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 715 Requires<[FeatureHighWord]>; 716defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 717def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 718 Requires<[FeatureHighWord]>; 719 720// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 721// STH, STHY or STHH, depending on the choice of register. 722def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 723 Requires<[FeatureHighWord]>; 724defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 725def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 726 Requires<[FeatureHighWord]>; 727def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 728 729// Truncations of 64-bit registers to memory. 730defm : StoreGR64Pair<STC, STCY, truncstorei8>; 731defm : StoreGR64Pair<STH, STHY, truncstorei16>; 732def : StoreGR64PC<STHRL, aligned_truncstorei16>; 733defm : StoreGR64Pair<ST, STY, truncstorei32>; 734def : StoreGR64PC<STRL, aligned_truncstorei32>; 735 736// Store characters under mask -- not (yet) used for codegen. 737defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 738def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 739 740//===----------------------------------------------------------------------===// 741// Multi-register moves 742//===----------------------------------------------------------------------===// 743 744// Multi-register loads. 745defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 746def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 747def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 748def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 749 750// Multi-register stores. 751defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 752def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 753def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 754 755//===----------------------------------------------------------------------===// 756// Byte swaps 757//===----------------------------------------------------------------------===// 758 759// Byte-swapping register moves. 760let hasSideEffects = 0 in { 761 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 762 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 763} 764 765// Byte-swapping loads. Unlike normal loads, these instructions are 766// allowed to access storage more than once. 767def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>; 768def LRV : UnaryRXY<"lrv", 0xE31E, z_lrv, GR32, 4>; 769def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>; 770 771// Likewise byte-swapping stores. 772def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>; 773def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>; 774def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>; 775 776// Byte-swapping memory-to-memory moves. 777let mayLoad = 1, mayStore = 1 in 778 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 779 780//===----------------------------------------------------------------------===// 781// Load address instructions 782//===----------------------------------------------------------------------===// 783 784// Load BDX-style addresses. 785let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1 in 786 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 787 788// Load a PC-relative address. There's no version of this instruction 789// with a 16-bit offset, so there's no relaxation. 790let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 791 isReMaterializable = 1 in 792 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 793 794// Load the Global Offset Table address. This will be lowered into a 795// larl $R1, _GLOBAL_OFFSET_TABLE_ 796// instruction. 797def GOT : Alias<6, (outs GR64:$R1), (ins), 798 [(set GR64:$R1, (global_offset_table))]>; 799 800//===----------------------------------------------------------------------===// 801// Absolute and Negation 802//===----------------------------------------------------------------------===// 803 804let Defs = [CC] in { 805 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 806 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>; 807 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>; 808 } 809 let CCValues = 0xE, CompareZeroCCMask = 0xE in 810 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 811} 812def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 813def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 814defm : SXU<z_iabs, LPGFR>; 815defm : SXU<z_iabs64, LPGFR>; 816 817let Defs = [CC] in { 818 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 819 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 820 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 821 } 822 let CCValues = 0xE, CompareZeroCCMask = 0xE in 823 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 824} 825def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 826def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 827defm : SXU<z_inegabs, LNGFR>; 828defm : SXU<z_inegabs64, LNGFR>; 829 830let Defs = [CC] in { 831 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 832 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 833 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 834 } 835 let CCValues = 0xE, CompareZeroCCMask = 0xE in 836 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 837} 838defm : SXU<ineg, LCGFR>; 839 840//===----------------------------------------------------------------------===// 841// Insertion 842//===----------------------------------------------------------------------===// 843 844let isCodeGenOnly = 1 in 845 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 846defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 847 848defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 849defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 850 851defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 852defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 853 854// Insert characters under mask -- not (yet) used for codegen. 855let Defs = [CC] in { 856 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 857 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 858} 859 860// Insertions of a 16-bit immediate, leaving other bits unaffected. 861// We don't have or_as_insert equivalents of these operations because 862// OI is available instead. 863// 864// IIxMux expands to II[LH]x, depending on the choice of register. 865def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 866 Requires<[FeatureHighWord]>; 867def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 868 Requires<[FeatureHighWord]>; 869def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 870def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 871def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 872def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 873def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 874def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 875def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 876def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 877 878// ...likewise for 32-bit immediates. For GR32s this is a general 879// full-width move. (We use IILF rather than something like LLILF 880// for 32-bit moves because IILF leaves the upper 32 bits of the 881// GR64 unchanged.) 882let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 883 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 884 Requires<[FeatureHighWord]>; 885 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 886 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 887} 888def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 889def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 890 891// An alternative model of inserthf, with the first operand being 892// a zero-extended value. 893def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 894 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 895 imm64hf32:$imm)>; 896 897//===----------------------------------------------------------------------===// 898// Addition 899//===----------------------------------------------------------------------===// 900 901// Plain addition. 902let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 903 // Addition of a register. 904 let isCommutable = 1 in { 905 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, add, GR32, GR32>; 906 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, add, GR64, GR64>; 907 } 908 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 909 910 // Addition to a high register. 911 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 912 Requires<[FeatureHighWord]>; 913 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 914 Requires<[FeatureHighWord]>; 915 916 // Addition of signed 16-bit immediates. 917 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>; 918 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 919 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 920 921 // Addition of signed 32-bit immediates. 922 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>, 923 Requires<[FeatureHighWord]>; 924 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 925 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>, 926 Requires<[FeatureHighWord]>; 927 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 928 929 // Addition of memory. 930 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; 931 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 932 def AGH : BinaryRXY<"agh", 0xE338, add, GR64, asextloadi16, 2>, 933 Requires<[FeatureMiscellaneousExtensions2]>; 934 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; 935 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 936 937 // Addition to memory. 938 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 939 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 940} 941defm : SXB<add, GR64, AGFR>; 942 943// Addition producing a carry. 944let Defs = [CC] in { 945 // Addition of a register. 946 let isCommutable = 1 in { 947 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, addc, GR32, GR32>; 948 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, addc, GR64, GR64>; 949 } 950 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 951 952 // Addition to a high register. 953 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 954 Requires<[FeatureHighWord]>; 955 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 956 Requires<[FeatureHighWord]>; 957 958 // Addition of signed 16-bit immediates. 959 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 960 Requires<[FeatureDistinctOps]>; 961 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 962 Requires<[FeatureDistinctOps]>; 963 964 // Addition of unsigned 32-bit immediates. 965 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 966 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 967 968 // Addition of signed 32-bit immediates. 969 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 970 Requires<[FeatureHighWord]>; 971 972 // Addition of memory. 973 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 974 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>; 975 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 976 977 // Addition to memory. 978 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 979 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 980} 981defm : ZXB<addc, GR64, ALGFR>; 982 983// Addition producing and using a carry. 984let Defs = [CC], Uses = [CC] in { 985 // Addition of a register. 986 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>; 987 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>; 988 989 // Addition of memory. 990 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 991 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 992} 993 994// Addition that does not modify the condition code. 995def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 996 Requires<[FeatureHighWord]>; 997 998//===----------------------------------------------------------------------===// 999// Subtraction 1000//===----------------------------------------------------------------------===// 1001 1002// Plain subtraction. Although immediate forms exist, we use the 1003// add-immediate instruction instead. 1004let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 1005 // Subtraction of a register. 1006 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, sub, GR32, GR32>; 1007 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1008 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, sub, GR64, GR64>; 1009 1010 // Subtraction from a high register. 1011 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1012 Requires<[FeatureHighWord]>; 1013 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1014 Requires<[FeatureHighWord]>; 1015 1016 // Subtraction of memory. 1017 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; 1018 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 1019 def SGH : BinaryRXY<"sgh", 0xE339, sub, GR64, asextloadi16, 2>, 1020 Requires<[FeatureMiscellaneousExtensions2]>; 1021 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; 1022 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 1023} 1024defm : SXB<sub, GR64, SGFR>; 1025 1026// Subtraction producing a carry. 1027let Defs = [CC] in { 1028 // Subtraction of a register. 1029 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, subc, GR32, GR32>; 1030 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1031 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, subc, GR64, GR64>; 1032 1033 // Subtraction from a high register. 1034 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1035 Requires<[FeatureHighWord]>; 1036 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1037 Requires<[FeatureHighWord]>; 1038 1039 // Subtraction of unsigned 32-bit immediates. These don't match 1040 // subc because we prefer addc for constants. 1041 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 1042 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 1043 1044 // Subtraction of memory. 1045 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 1046 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>; 1047 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 1048} 1049defm : ZXB<subc, GR64, SLGFR>; 1050 1051// Subtraction producing and using a carry. 1052let Defs = [CC], Uses = [CC] in { 1053 // Subtraction of a register. 1054 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>; 1055 def SLBGR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>; 1056 1057 // Subtraction of memory. 1058 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 1059 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 1060} 1061 1062//===----------------------------------------------------------------------===// 1063// AND 1064//===----------------------------------------------------------------------===// 1065 1066let Defs = [CC] in { 1067 // ANDs of a register. 1068 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1069 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1070 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1071 } 1072 1073 let isConvertibleToThreeAddress = 1 in { 1074 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1075 // The CC result only reflects the 16-bit field, not the full register. 1076 // 1077 // NIxMux expands to NI[LH]x, depending on the choice of register. 1078 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1079 Requires<[FeatureHighWord]>; 1080 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1081 Requires<[FeatureHighWord]>; 1082 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1083 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1084 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1085 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1086 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1087 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1088 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1089 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1090 1091 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1092 // The CC result only reflects the 32-bit field, which means we can 1093 // use it as a zero indicator for i32 operations but not otherwise. 1094 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1095 // Expands to NILF or NIHF, depending on the choice of register. 1096 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1097 Requires<[FeatureHighWord]>; 1098 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1099 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1100 } 1101 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1102 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1103 } 1104 1105 // ANDs of memory. 1106 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1107 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1108 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1109 } 1110 1111 // AND to memory 1112 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1113 1114 // Block AND. 1115 let mayLoad = 1, mayStore = 1 in 1116 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1117} 1118defm : RMWIByte<and, bdaddr12pair, NI>; 1119defm : RMWIByte<and, bdaddr20pair, NIY>; 1120 1121//===----------------------------------------------------------------------===// 1122// OR 1123//===----------------------------------------------------------------------===// 1124 1125let Defs = [CC] in { 1126 // ORs of a register. 1127 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1128 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1129 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1130 } 1131 1132 // ORs of a 16-bit immediate, leaving other bits unaffected. 1133 // The CC result only reflects the 16-bit field, not the full register. 1134 // 1135 // OIxMux expands to OI[LH]x, depending on the choice of register. 1136 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1137 Requires<[FeatureHighWord]>; 1138 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1139 Requires<[FeatureHighWord]>; 1140 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1141 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1142 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1143 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1144 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1145 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1146 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1147 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1148 1149 // ORs of a 32-bit immediate, leaving other bits unaffected. 1150 // The CC result only reflects the 32-bit field, which means we can 1151 // use it as a zero indicator for i32 operations but not otherwise. 1152 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1153 // Expands to OILF or OIHF, depending on the choice of register. 1154 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1155 Requires<[FeatureHighWord]>; 1156 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1157 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1158 } 1159 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1160 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1161 1162 // ORs of memory. 1163 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1164 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1165 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1166 } 1167 1168 // OR to memory 1169 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1170 1171 // Block OR. 1172 let mayLoad = 1, mayStore = 1 in 1173 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1174} 1175defm : RMWIByte<or, bdaddr12pair, OI>; 1176defm : RMWIByte<or, bdaddr20pair, OIY>; 1177 1178//===----------------------------------------------------------------------===// 1179// XOR 1180//===----------------------------------------------------------------------===// 1181 1182let Defs = [CC] in { 1183 // XORs of a register. 1184 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1185 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1186 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1187 } 1188 1189 // XORs of a 32-bit immediate, leaving other bits unaffected. 1190 // The CC result only reflects the 32-bit field, which means we can 1191 // use it as a zero indicator for i32 operations but not otherwise. 1192 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1193 // Expands to XILF or XIHF, depending on the choice of register. 1194 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1195 Requires<[FeatureHighWord]>; 1196 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1197 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1198 } 1199 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1200 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1201 1202 // XORs of memory. 1203 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1204 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1205 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1206 } 1207 1208 // XOR to memory 1209 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1210 1211 // Block XOR. 1212 let mayLoad = 1, mayStore = 1 in 1213 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1214} 1215defm : RMWIByte<xor, bdaddr12pair, XI>; 1216defm : RMWIByte<xor, bdaddr20pair, XIY>; 1217 1218//===----------------------------------------------------------------------===// 1219// Multiplication 1220//===----------------------------------------------------------------------===// 1221 1222// Multiplication of a register, setting the condition code. We prefer these 1223// over MS(G)R if available, even though we cannot use the condition code, 1224// since they are three-operand instructions. 1225let Predicates = [FeatureMiscellaneousExtensions2], 1226 Defs = [CC], isCommutable = 1 in { 1227 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1228 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1229} 1230 1231// Multiplication of a register. 1232let isCommutable = 1 in { 1233 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1234 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1235} 1236def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1237defm : SXB<mul, GR64, MSGFR>; 1238 1239// Multiplication of a signed 16-bit immediate. 1240def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1241def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1242 1243// Multiplication of a signed 32-bit immediate. 1244def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1245def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1246 1247// Multiplication of memory. 1248defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1249defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1250def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1251 Requires<[FeatureMiscellaneousExtensions2]>; 1252def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1253def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1254 1255// Multiplication of memory, setting the condition code. 1256let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1257 def MSC : BinaryRXY<"msc", 0xE353, null_frag, GR32, load, 4>; 1258 def MSGC : BinaryRXY<"msgc", 0xE383, null_frag, GR64, load, 8>; 1259} 1260 1261// Multiplication of a register, producing two results. 1262def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1263def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1264 Requires<[FeatureMiscellaneousExtensions2]>; 1265def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1266def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1267def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1268 (MGRK GR64:$src1, GR64:$src2)>; 1269def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1270 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1271 1272// Multiplication of memory, producing two results. 1273def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1274def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1275def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1276 Requires<[FeatureMiscellaneousExtensions2]>; 1277def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1278def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1279def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1280 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1281def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1282 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1283 1284//===----------------------------------------------------------------------===// 1285// Division and remainder 1286//===----------------------------------------------------------------------===// 1287 1288let hasSideEffects = 1 in { // Do not speculatively execute. 1289 // Division and remainder, from registers. 1290 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1291 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1292 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1293 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1294 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1295 1296 // Division and remainder, from memory. 1297 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1298 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1299 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1300 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1301 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1302} 1303def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1304 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1305def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1306 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1307def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1308 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1309def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1310 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1311 1312def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1313 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1314 subreg_l32)), GR32:$src2)>; 1315def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1316 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1317 subreg_l32)), bdxaddr20only:$src2)>; 1318def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1319 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1320def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1321 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1322 1323//===----------------------------------------------------------------------===// 1324// Shifts 1325//===----------------------------------------------------------------------===// 1326 1327// Logical shift left. 1328let hasSideEffects = 0 in { 1329 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1330 def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1331 def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1332} 1333 1334// Arithmetic shift left. 1335let Defs = [CC] in { 1336 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1337 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1338 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1339} 1340 1341// Logical shift right. 1342let hasSideEffects = 0 in { 1343 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1344 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1345 def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1346} 1347 1348// Arithmetic shift right. 1349let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1350 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1351 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1352 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1353} 1354 1355// Rotate left. 1356let hasSideEffects = 0 in { 1357 def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1358 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1359} 1360 1361// Rotate second operand left and inserted selected bits into first operand. 1362// These can act like 32-bit operands provided that the constant start and 1363// end bits (operands 2 and 3) are in the range [32, 64). 1364let Defs = [CC] in { 1365 let isCodeGenOnly = 1 in 1366 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1367 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1368 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1369} 1370 1371// On zEC12 we have a variant of RISBG that does not set CC. 1372let Predicates = [FeatureMiscellaneousExtensions] in 1373 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1374 1375// Forms of RISBG that only affect one word of the destination register. 1376// They do not set CC. 1377let Predicates = [FeatureHighWord] in { 1378 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1379 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1380 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1381 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1382 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1383 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1384 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1385} 1386 1387// Rotate second operand left and perform a logical operation with selected 1388// bits of the first operand. The CC result only describes the selected bits, 1389// so isn't useful for a full comparison against zero. 1390let Defs = [CC] in { 1391 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1392 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1393 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1394} 1395 1396//===----------------------------------------------------------------------===// 1397// Comparison 1398//===----------------------------------------------------------------------===// 1399 1400// Signed comparisons. We put these before the unsigned comparisons because 1401// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1402// of the unsigned forms do. 1403let Defs = [CC], CCValues = 0xE in { 1404 // Comparison with a register. 1405 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1406 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1407 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1408 1409 // Comparison with a high register. 1410 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1411 Requires<[FeatureHighWord]>; 1412 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1413 Requires<[FeatureHighWord]>; 1414 1415 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1416 // depending on the choice of register. 1417 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1418 Requires<[FeatureHighWord]>; 1419 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1420 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1421 1422 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1423 // depending on the choice of register. 1424 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1425 Requires<[FeatureHighWord]>; 1426 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1427 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1428 Requires<[FeatureHighWord]>; 1429 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1430 1431 // Comparison with memory. 1432 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1433 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1434 Requires<[FeatureHighWord]>; 1435 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1436 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1437 Requires<[FeatureHighWord]>; 1438 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1439 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1440 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1441 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1442 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1443 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1444 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1445 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1446 1447 // Comparison between memory and a signed 16-bit immediate. 1448 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1449 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1450 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1451} 1452defm : SXB<z_scmp, GR64, CGFR>; 1453 1454// Unsigned comparisons. 1455let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1456 // Comparison with a register. 1457 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1458 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1459 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1460 1461 // Comparison with a high register. 1462 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1463 Requires<[FeatureHighWord]>; 1464 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1465 Requires<[FeatureHighWord]>; 1466 1467 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1468 // or CLIH, depending on the choice of register. 1469 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1470 Requires<[FeatureHighWord]>; 1471 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1472 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1473 Requires<[FeatureHighWord]>; 1474 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1475 1476 // Comparison with memory. 1477 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1478 Requires<[FeatureHighWord]>; 1479 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1480 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1481 Requires<[FeatureHighWord]>; 1482 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1483 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1484 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1485 aligned_azextloadi16>; 1486 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1487 aligned_load>; 1488 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1489 aligned_azextloadi16>; 1490 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1491 aligned_azextloadi32>; 1492 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1493 aligned_load>; 1494 1495 // Comparison between memory and an unsigned 8-bit immediate. 1496 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1497 1498 // Comparison between memory and an unsigned 16-bit immediate. 1499 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1500 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1501 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1502} 1503defm : ZXB<z_ucmp, GR64, CLGFR>; 1504 1505// Memory-to-memory comparison. 1506let mayLoad = 1, Defs = [CC] in { 1507 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1508 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1509 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1510 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1511} 1512 1513// String comparison. 1514let mayLoad = 1, Defs = [CC] in 1515 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1516 1517// Test under mask. 1518let Defs = [CC] in { 1519 // TMxMux expands to TM[LH]x, depending on the choice of register. 1520 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1521 Requires<[FeatureHighWord]>; 1522 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1523 Requires<[FeatureHighWord]>; 1524 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1525 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1526 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1527 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1528 1529 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1530 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1531 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1532 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1533 1534 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1535} 1536 1537def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1538def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1539 1540// Compare logical characters under mask -- not (yet) used for codegen. 1541let Defs = [CC] in { 1542 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1543 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1544} 1545 1546//===----------------------------------------------------------------------===// 1547// Prefetch and execution hint 1548//===----------------------------------------------------------------------===// 1549 1550def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1551def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1552 1553let Predicates = [FeatureExecutionHint] in { 1554 // Branch Prediction Preload 1555 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1556 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1557 1558 // Next Instruction Access Intent 1559 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1560} 1561 1562//===----------------------------------------------------------------------===// 1563// Atomic operations 1564//===----------------------------------------------------------------------===// 1565 1566// A serialization instruction that acts as a barrier for all memory 1567// accesses, which expands to "bcr 14, 0". 1568let hasSideEffects = 1 in 1569def Serialize : Alias<2, (outs), (ins), []>; 1570 1571// A pseudo instruction that serves as a compiler barrier. 1572let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1573def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1574 1575let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1576 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1577 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1578 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1579 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1580 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1581 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1582 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1583 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1584 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1585 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1586} 1587 1588def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1589def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1590def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1591 1592def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1593def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1594let Predicates = [FeatureNoInterlockedAccess1] in { 1595 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1596 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1597 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1598 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1599 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1600 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1601} 1602 1603def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1604def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1605def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1606 1607def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1608def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1609let Predicates = [FeatureNoInterlockedAccess1] in { 1610 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1611 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1612 imm32ll16c>; 1613 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1614 imm32lh16c>; 1615 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1616 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1617 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1618 imm64ll16c>; 1619 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1620 imm64lh16c>; 1621 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1622 imm64hl16c>; 1623 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1624 imm64hh16c>; 1625 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1626 imm64lf32c>; 1627 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1628 imm64hf32c>; 1629} 1630 1631def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1632def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1633let Predicates = [FeatureNoInterlockedAccess1] in { 1634 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1635 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1636 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1637 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1638 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1639 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1640 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1641 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1642 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1643 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1644 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1645} 1646 1647def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1648def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1649let Predicates = [FeatureNoInterlockedAccess1] in { 1650 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1651 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1652 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1653 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1654 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1655} 1656 1657def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1658def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1659 imm32lh16c>; 1660def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1661def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1662 imm32ll16c>; 1663def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1664 imm32lh16c>; 1665def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1666def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1667def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1668 imm64ll16c>; 1669def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1670 imm64lh16c>; 1671def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1672 imm64hl16c>; 1673def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1674 imm64hh16c>; 1675def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1676 imm64lf32c>; 1677def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1678 imm64hf32c>; 1679 1680def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1681def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1682def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1683 1684def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1685def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1686def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1687 1688def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1689def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1690def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1691 1692def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1693def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1694def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1695 1696def ATOMIC_CMP_SWAPW 1697 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1698 ADDR32:$bitshift, ADDR32:$negbitshift, 1699 uimm32:$bitsize), 1700 [(set GR32:$dst, 1701 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1702 ADDR32:$bitshift, ADDR32:$negbitshift, 1703 uimm32:$bitsize))]> { 1704 let Defs = [CC]; 1705 let mayLoad = 1; 1706 let mayStore = 1; 1707 let usesCustomInserter = 1; 1708 let hasNoSchedulingInfo = 1; 1709} 1710 1711// Test and set. 1712let mayLoad = 1, Defs = [CC] in 1713 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1714 1715// Compare and swap. 1716let Defs = [CC] in { 1717 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 1718 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 1719} 1720 1721// Compare double and swap. 1722let Defs = [CC] in { 1723 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1724 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, null_frag, GR128>; 1725} 1726 1727// Compare and swap and store. 1728let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1729 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1730 1731// Perform locked operation. 1732let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1733 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1734 1735// Load/store pair from/to quadword. 1736def LPQ : UnaryRXY<"lpq", 0xE38F, null_frag, GR128, 16>; 1737def STPQ : StoreRXY<"stpq", 0xE38E, null_frag, GR128, 16>; 1738 1739// Load pair disjoint. 1740let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1741 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1742 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1743} 1744 1745//===----------------------------------------------------------------------===// 1746// Translate and convert 1747//===----------------------------------------------------------------------===// 1748 1749let mayLoad = 1, mayStore = 1 in 1750 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1751 1752let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1753 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1754 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1755} 1756 1757let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1758 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1759 1760let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1761 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1762 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1763} 1764 1765let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1766 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1767 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1768 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1769 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1770} 1771 1772let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1773 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1774 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1775 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1776 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1777 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1778 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1779 1780 let isAsmParserOnly = 1 in { 1781 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1782 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1783 } 1784} 1785 1786//===----------------------------------------------------------------------===// 1787// Message-security assist 1788//===----------------------------------------------------------------------===// 1789 1790let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1791 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1792 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1793 1794 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1795 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1796 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1797 1798 let Predicates = [FeatureMessageSecurityAssist4] in { 1799 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1800 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1801 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1802 GR128, GR128, GR128>; 1803 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1804 } 1805 1806 let Predicates = [FeatureMessageSecurityAssist5] in 1807 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1808 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1809 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1810 1811 let Predicates = [FeatureMessageSecurityAssist8] in 1812 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1813 GR128, GR128, GR128>; 1814} 1815 1816//===----------------------------------------------------------------------===// 1817// Guarded storage 1818//===----------------------------------------------------------------------===// 1819 1820let Predicates = [FeatureGuardedStorage] in { 1821 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1822 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1823 1824 let mayLoad = 1 in 1825 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1826 let mayStore = 1 in 1827 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1828} 1829 1830//===----------------------------------------------------------------------===// 1831// Decimal arithmetic 1832//===----------------------------------------------------------------------===// 1833 1834defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1835def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1836 1837defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1838def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1839 1840let mayLoad = 1, mayStore = 1 in { 1841 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1842 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1843 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1844 1845 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1846 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1847 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1848 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1849 let Defs = [CC] in { 1850 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1851 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1852 } 1853} 1854 1855let mayLoad = 1, mayStore = 1 in { 1856 let Defs = [CC] in { 1857 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1858 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1859 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1860 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1861 } 1862 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1863 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1864 let Defs = [CC] in { 1865 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1866 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1867 } 1868} 1869 1870let Defs = [CC] in { 1871 def CP : CompareSSb<"cp", 0xF9>; 1872 def TP : TestRSL<"tp", 0xEBC0>; 1873} 1874 1875//===----------------------------------------------------------------------===// 1876// Access registers 1877//===----------------------------------------------------------------------===// 1878 1879// Read a 32-bit access register into a GR32. As with all GR32 operations, 1880// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1881// when a 64-bit address is stored in a pair of access registers. 1882def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1883 1884// Set access register. 1885def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1886 1887// Copy access register. 1888def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1889 1890// Load address extended. 1891defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1892 1893// Load access multiple. 1894defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1895 1896// Load access multiple. 1897defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1898 1899//===----------------------------------------------------------------------===// 1900// Program mask and addressing mode 1901//===----------------------------------------------------------------------===// 1902 1903// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1904let Uses = [CC] in 1905 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 1906 1907// Set CC and program mask from a register. 1908let hasSideEffects = 1, Defs = [CC] in 1909 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 1910 1911// Branch and link - like BAS, but also extracts CC and program mask. 1912let isCall = 1, Uses = [CC], Defs = [CC] in { 1913 def BAL : CallRX<"bal", 0x45>; 1914 def BALR : CallRR<"balr", 0x05>; 1915} 1916 1917// Test addressing mode. 1918let Defs = [CC] in 1919 def TAM : SideEffectInherentE<"tam", 0x010B>; 1920 1921// Set addressing mode. 1922let hasSideEffects = 1 in { 1923 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 1924 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 1925 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 1926} 1927 1928// Branch and set mode. Not really a call, but also sets an output register. 1929let isBranch = 1, isTerminator = 1, isBarrier = 1 in 1930 def BSM : CallRR<"bsm", 0x0B>; 1931 1932// Branch and save and set mode. 1933let isCall = 1, Defs = [CC] in 1934 def BASSM : CallRR<"bassm", 0x0C>; 1935 1936//===----------------------------------------------------------------------===// 1937// Transactional execution 1938//===----------------------------------------------------------------------===// 1939 1940let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 1941 // Transaction Begin 1942 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 1943 def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 1944 def TBEGIN_nofloat : SideEffectBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 1945 1946 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 1947 int_s390_tbeginc, imm32zx16>; 1948 } 1949 1950 // Transaction End 1951 let Defs = [CC] in 1952 def TEND : SideEffectInherentS<"tend", 0xB2F8, z_tend>; 1953 1954 // Transaction Abort 1955 let isTerminator = 1, isBarrier = 1 in 1956 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 1957 1958 // Nontransactional Store 1959 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1960 1961 // Extract Transaction Nesting Depth 1962 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 1963} 1964 1965//===----------------------------------------------------------------------===// 1966// Processor assist 1967//===----------------------------------------------------------------------===// 1968 1969let Predicates = [FeatureProcessorAssist] in { 1970 let hasSideEffects = 1 in 1971 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 1972 def : Pat<(int_s390_ppa_txassist GR32:$src), 1973 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1974 0, 1)>; 1975} 1976 1977//===----------------------------------------------------------------------===// 1978// Miscellaneous Instructions. 1979//===----------------------------------------------------------------------===// 1980 1981// Find leftmost one, AKA count leading zeros. The instruction actually 1982// returns a pair of GR64s, the first giving the number of leading zeros 1983// and the second giving a copy of the source with the leftmost one bit 1984// cleared. We only use the first result here. 1985let Defs = [CC] in 1986 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 1987def : Pat<(ctlz GR64:$src), 1988 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 1989 1990// Population count. Counts bits set per byte. 1991let Predicates = [FeaturePopulationCount], Defs = [CC] in 1992 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 1993 1994// Search a block of memory for a character. 1995let mayLoad = 1, Defs = [CC] in 1996 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 1997let mayLoad = 1, Defs = [CC], Uses = [R0L] in 1998 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 1999 2000// Compare until substring equal. 2001let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2002 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2003 2004// Compare and form codeword. 2005let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2006 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2007 2008// Update tree. 2009let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2010 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2011 def UPT : SideEffectInherentE<"upt", 0x0102>; 2012 2013// Checksum. 2014let mayLoad = 1, Defs = [CC] in 2015 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2016 2017// Compression call. 2018let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2019 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2020 2021// Execute. 2022let hasSideEffects = 1 in { 2023 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2024 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2025} 2026 2027//===----------------------------------------------------------------------===// 2028// .insn directive instructions 2029//===----------------------------------------------------------------------===// 2030 2031let isCodeGenOnly = 1 in { 2032 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2033 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2034 imm32sx16:$I2), 2035 ".insn ri,$enc,$R1,$I2", []>; 2036 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2037 AnyReg:$R3, brtarget16:$I2), 2038 ".insn rie,$enc,$R1,$R3,$I2", []>; 2039 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2040 brtarget32:$I2), 2041 ".insn ril,$enc,$R1,$I2", []>; 2042 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2043 uimm32:$I2), 2044 ".insn rilu,$enc,$R1,$I2", []>; 2045 def InsnRIS : DirectiveInsnRIS<(outs), 2046 (ins imm64zx48:$enc, AnyReg:$R1, 2047 imm32sx8:$I2, imm32zx4:$M3, 2048 bdaddr12only:$BD4), 2049 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2050 def InsnRR : DirectiveInsnRR<(outs), 2051 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2052 ".insn rr,$enc,$R1,$R2", []>; 2053 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2054 AnyReg:$R1, AnyReg:$R2), 2055 ".insn rre,$enc,$R1,$R2", []>; 2056 def InsnRRF : DirectiveInsnRRF<(outs), 2057 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2058 AnyReg:$R3, imm32zx4:$M4), 2059 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2060 def InsnRRS : DirectiveInsnRRS<(outs), 2061 (ins imm64zx48:$enc, AnyReg:$R1, 2062 AnyReg:$R2, imm32zx4:$M3, 2063 bdaddr12only:$BD4), 2064 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2065 def InsnRS : DirectiveInsnRS<(outs), 2066 (ins imm64zx32:$enc, AnyReg:$R1, 2067 AnyReg:$R3, bdaddr12only:$BD2), 2068 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2069 def InsnRSE : DirectiveInsnRSE<(outs), 2070 (ins imm64zx48:$enc, AnyReg:$R1, 2071 AnyReg:$R3, bdaddr12only:$BD2), 2072 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2073 def InsnRSI : DirectiveInsnRSI<(outs), 2074 (ins imm64zx48:$enc, AnyReg:$R1, 2075 AnyReg:$R3, brtarget16:$RI2), 2076 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2077 def InsnRSY : DirectiveInsnRSY<(outs), 2078 (ins imm64zx48:$enc, AnyReg:$R1, 2079 AnyReg:$R3, bdaddr20only:$BD2), 2080 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2081 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2082 bdxaddr12only:$XBD2), 2083 ".insn rx,$enc,$R1,$XBD2", []>; 2084 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2085 bdxaddr12only:$XBD2), 2086 ".insn rxe,$enc,$R1,$XBD2", []>; 2087 def InsnRXF : DirectiveInsnRXF<(outs), 2088 (ins imm64zx48:$enc, AnyReg:$R1, 2089 AnyReg:$R3, bdxaddr12only:$XBD2), 2090 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2091 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2092 bdxaddr20only:$XBD2), 2093 ".insn rxy,$enc,$R1,$XBD2", []>; 2094 def InsnS : DirectiveInsnS<(outs), 2095 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2096 ".insn s,$enc,$BD2", []>; 2097 def InsnSI : DirectiveInsnSI<(outs), 2098 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2099 imm32sx8:$I2), 2100 ".insn si,$enc,$BD1,$I2", []>; 2101 def InsnSIY : DirectiveInsnSIY<(outs), 2102 (ins imm64zx48:$enc, 2103 bdaddr20only:$BD1, imm32zx8:$I2), 2104 ".insn siy,$enc,$BD1,$I2", []>; 2105 def InsnSIL : DirectiveInsnSIL<(outs), 2106 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2107 imm32zx16:$I2), 2108 ".insn sil,$enc,$BD1,$I2", []>; 2109 def InsnSS : DirectiveInsnSS<(outs), 2110 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2111 bdaddr12only:$BD2, AnyReg:$R3), 2112 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2113 def InsnSSE : DirectiveInsnSSE<(outs), 2114 (ins imm64zx48:$enc, 2115 bdaddr12only:$BD1,bdaddr12only:$BD2), 2116 ".insn sse,$enc,$BD1,$BD2", []>; 2117 def InsnSSF : DirectiveInsnSSF<(outs), 2118 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2119 bdaddr12only:$BD2, AnyReg:$R3), 2120 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2121} 2122 2123//===----------------------------------------------------------------------===// 2124// Peepholes. 2125//===----------------------------------------------------------------------===// 2126 2127// Use AL* for GR64 additions of unsigned 32-bit values. 2128defm : ZXB<add, GR64, ALGFR>; 2129def : Pat<(add GR64:$src1, imm64zx32:$src2), 2130 (ALGFI GR64:$src1, imm64zx32:$src2)>; 2131def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 2132 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 2133 2134// Use SL* for GR64 subtractions of unsigned 32-bit values. 2135defm : ZXB<sub, GR64, SLGFR>; 2136def : Pat<(add GR64:$src1, imm64zx32n:$src2), 2137 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 2138def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 2139 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 2140 2141// Optimize sign-extended 1/0 selects to -1/0 selects. This is important 2142// for vector legalization. 2143def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)), 2144 (i32 31)), 2145 (i32 31)), 2146 (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 2147def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, 2148 imm32zx4:$cc)))), 2149 (i32 63)), 2150 (i32 63)), 2151 (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 2152 2153// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2154// equivalent to (and (xor x, -1), y) 2155def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2156 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2157 2158// Shift/rotate instructions only use the last 6 bits of the second operand 2159// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2160// last 16 bits. 2161// Complexity is added so that we match this before we match NILF on the AND 2162// operation alone. 2163let AddedComplexity = 4 in { 2164 def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2165 (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2166 2167 def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)), 2168 (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2169 2170 def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2171 (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2172 2173 def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2174 (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2175 2176 def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)), 2177 (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2178 2179 def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2180 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2181 2182 def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2183 (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2184 2185 def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2186 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2187} 2188 2189// Peepholes for turning scalar operations into block operations. 2190defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2191 XCSequence, 1>; 2192defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2193 XCSequence, 2>; 2194defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2195 XCSequence, 4>; 2196defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2197 OCSequence, XCSequence, 1>; 2198defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2199 XCSequence, 2>; 2200defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2201 XCSequence, 4>; 2202defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2203 XCSequence, 8>; 2204