1 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the SystemZ implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SystemZ.h" 15 #include "SystemZInstrBuilder.h" 16 #include "SystemZInstrInfo.h" 17 #include "SystemZMachineFunctionInfo.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZGenInstrInfo.inc" 20 #include "llvm/Function.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/PseudoSourceValue.h" 25 #include "llvm/Support/ErrorHandling.h" 26 using namespace llvm; 27 28 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) 29 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)), 30 RI(tm, *this), TM(tm) { 31 // Fill the spill offsets map 32 static const unsigned SpillOffsTab[][2] = { 33 { SystemZ::R2D, 0x10 }, 34 { SystemZ::R3D, 0x18 }, 35 { SystemZ::R4D, 0x20 }, 36 { SystemZ::R5D, 0x28 }, 37 { SystemZ::R6D, 0x30 }, 38 { SystemZ::R7D, 0x38 }, 39 { SystemZ::R8D, 0x40 }, 40 { SystemZ::R9D, 0x48 }, 41 { SystemZ::R10D, 0x50 }, 42 { SystemZ::R11D, 0x58 }, 43 { SystemZ::R12D, 0x60 }, 44 { SystemZ::R13D, 0x68 }, 45 { SystemZ::R14D, 0x70 }, 46 { SystemZ::R15D, 0x78 } 47 }; 48 49 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS); 50 51 for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i) 52 RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1]; 53 } 54 55 /// isGVStub - Return true if the GV requires an extra load to get the 56 /// real address. 57 static inline bool isGVStub(GlobalValue *GV, SystemZTargetMachine &TM) { 58 return TM.getSubtarget<SystemZSubtarget>().GVRequiresExtraLoad(GV, TM, false); 59 } 60 61 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MI, 63 unsigned SrcReg, bool isKill, int FrameIdx, 64 const TargetRegisterClass *RC, 65 const TargetRegisterInfo *TRI) const { 66 DebugLoc DL; 67 if (MI != MBB.end()) DL = MI->getDebugLoc(); 68 69 unsigned Opc = 0; 70 if (RC == &SystemZ::GR32RegClass || 71 RC == &SystemZ::ADDR32RegClass) 72 Opc = SystemZ::MOV32mr; 73 else if (RC == &SystemZ::GR64RegClass || 74 RC == &SystemZ::ADDR64RegClass) { 75 Opc = SystemZ::MOV64mr; 76 } else if (RC == &SystemZ::FP32RegClass) { 77 Opc = SystemZ::FMOV32mr; 78 } else if (RC == &SystemZ::FP64RegClass) { 79 Opc = SystemZ::FMOV64mr; 80 } else if (RC == &SystemZ::GR64PRegClass) { 81 Opc = SystemZ::MOV64Pmr; 82 } else if (RC == &SystemZ::GR128RegClass) { 83 Opc = SystemZ::MOV128mr; 84 } else 85 llvm_unreachable("Unsupported regclass to store"); 86 87 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 88 .addReg(SrcReg, getKillRegState(isKill)); 89 } 90 91 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 92 MachineBasicBlock::iterator MI, 93 unsigned DestReg, int FrameIdx, 94 const TargetRegisterClass *RC, 95 const TargetRegisterInfo *TRI) const{ 96 DebugLoc DL; 97 if (MI != MBB.end()) DL = MI->getDebugLoc(); 98 99 unsigned Opc = 0; 100 if (RC == &SystemZ::GR32RegClass || 101 RC == &SystemZ::ADDR32RegClass) 102 Opc = SystemZ::MOV32rm; 103 else if (RC == &SystemZ::GR64RegClass || 104 RC == &SystemZ::ADDR64RegClass) { 105 Opc = SystemZ::MOV64rm; 106 } else if (RC == &SystemZ::FP32RegClass) { 107 Opc = SystemZ::FMOV32rm; 108 } else if (RC == &SystemZ::FP64RegClass) { 109 Opc = SystemZ::FMOV64rm; 110 } else if (RC == &SystemZ::GR64PRegClass) { 111 Opc = SystemZ::MOV64Prm; 112 } else if (RC == &SystemZ::GR128RegClass) { 113 Opc = SystemZ::MOV128rm; 114 } else 115 llvm_unreachable("Unsupported regclass to load"); 116 117 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 118 } 119 120 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 121 MachineBasicBlock::iterator I, DebugLoc DL, 122 unsigned DestReg, unsigned SrcReg, 123 bool KillSrc) const { 124 unsigned Opc; 125 if (SystemZ::GR64RegClass.contains(DestReg, SrcReg)) 126 Opc = SystemZ::MOV64rr; 127 else if (SystemZ::GR32RegClass.contains(DestReg, SrcReg)) 128 Opc = SystemZ::MOV32rr; 129 else if (SystemZ::GR64PRegClass.contains(DestReg, SrcReg)) 130 Opc = SystemZ::MOV64rrP; 131 else if (SystemZ::GR128RegClass.contains(DestReg, SrcReg)) 132 Opc = SystemZ::MOV128rr; 133 else if (SystemZ::FP32RegClass.contains(DestReg, SrcReg)) 134 Opc = SystemZ::FMOV32rr; 135 else if (SystemZ::FP64RegClass.contains(DestReg, SrcReg)) 136 Opc = SystemZ::FMOV64rr; 137 else 138 llvm_unreachable("Impossible reg-to-reg copy"); 139 140 BuildMI(MBB, I, DL, get(Opc), DestReg) 141 .addReg(SrcReg, getKillRegState(KillSrc)); 142 } 143 144 bool 145 SystemZInstrInfo::isMoveInstr(const MachineInstr& MI, 146 unsigned &SrcReg, unsigned &DstReg, 147 unsigned &SrcSubIdx, unsigned &DstSubIdx) const { 148 switch (MI.getOpcode()) { 149 default: 150 return false; 151 case SystemZ::MOV32rr: 152 case SystemZ::MOV64rr: 153 case SystemZ::MOV64rrP: 154 case SystemZ::MOV128rr: 155 case SystemZ::FMOV32rr: 156 case SystemZ::FMOV64rr: 157 assert(MI.getNumOperands() >= 2 && 158 MI.getOperand(0).isReg() && 159 MI.getOperand(1).isReg() && 160 "invalid register-register move instruction"); 161 SrcReg = MI.getOperand(1).getReg(); 162 DstReg = MI.getOperand(0).getReg(); 163 SrcSubIdx = MI.getOperand(1).getSubReg(); 164 DstSubIdx = MI.getOperand(0).getSubReg(); 165 return true; 166 } 167 } 168 169 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 170 int &FrameIndex) const { 171 switch (MI->getOpcode()) { 172 default: break; 173 case SystemZ::MOV32rm: 174 case SystemZ::MOV32rmy: 175 case SystemZ::MOV64rm: 176 case SystemZ::MOVSX32rm8: 177 case SystemZ::MOVSX32rm16y: 178 case SystemZ::MOVSX64rm8: 179 case SystemZ::MOVSX64rm16: 180 case SystemZ::MOVSX64rm32: 181 case SystemZ::MOVZX32rm8: 182 case SystemZ::MOVZX32rm16: 183 case SystemZ::MOVZX64rm8: 184 case SystemZ::MOVZX64rm16: 185 case SystemZ::MOVZX64rm32: 186 case SystemZ::FMOV32rm: 187 case SystemZ::FMOV32rmy: 188 case SystemZ::FMOV64rm: 189 case SystemZ::FMOV64rmy: 190 case SystemZ::MOV64Prm: 191 case SystemZ::MOV64Prmy: 192 case SystemZ::MOV128rm: 193 if (MI->getOperand(1).isFI() && 194 MI->getOperand(2).isImm() && MI->getOperand(3).isReg() && 195 MI->getOperand(2).getImm() == 0 && MI->getOperand(3).getReg() == 0) { 196 FrameIndex = MI->getOperand(1).getIndex(); 197 return MI->getOperand(0).getReg(); 198 } 199 break; 200 } 201 return 0; 202 } 203 204 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 205 int &FrameIndex) const { 206 switch (MI->getOpcode()) { 207 default: break; 208 case SystemZ::MOV32mr: 209 case SystemZ::MOV32mry: 210 case SystemZ::MOV64mr: 211 case SystemZ::MOV32m8r: 212 case SystemZ::MOV32m8ry: 213 case SystemZ::MOV32m16r: 214 case SystemZ::MOV32m16ry: 215 case SystemZ::MOV64m8r: 216 case SystemZ::MOV64m8ry: 217 case SystemZ::MOV64m16r: 218 case SystemZ::MOV64m16ry: 219 case SystemZ::MOV64m32r: 220 case SystemZ::MOV64m32ry: 221 case SystemZ::FMOV32mr: 222 case SystemZ::FMOV32mry: 223 case SystemZ::FMOV64mr: 224 case SystemZ::FMOV64mry: 225 case SystemZ::MOV64Pmr: 226 case SystemZ::MOV64Pmry: 227 case SystemZ::MOV128mr: 228 if (MI->getOperand(0).isFI() && 229 MI->getOperand(1).isImm() && MI->getOperand(2).isReg() && 230 MI->getOperand(1).getImm() == 0 && MI->getOperand(2).getReg() == 0) { 231 FrameIndex = MI->getOperand(0).getIndex(); 232 return MI->getOperand(3).getReg(); 233 } 234 break; 235 } 236 return 0; 237 } 238 239 bool 240 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 241 MachineBasicBlock::iterator MI, 242 const std::vector<CalleeSavedInfo> &CSI, 243 const TargetRegisterInfo *TRI) const { 244 if (CSI.empty()) 245 return false; 246 247 DebugLoc DL; 248 if (MI != MBB.end()) DL = MI->getDebugLoc(); 249 250 MachineFunction &MF = *MBB.getParent(); 251 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); 252 unsigned CalleeFrameSize = 0; 253 254 // Scan the callee-saved and find the bounds of register spill area. 255 unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0; 256 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 257 unsigned Reg = CSI[i].getReg(); 258 if (!SystemZ::FP64RegClass.contains(Reg)) { 259 unsigned Offset = RegSpillOffsets[Reg]; 260 CalleeFrameSize += 8; 261 if (StartOffset > Offset) { 262 LowReg = Reg; StartOffset = Offset; 263 } 264 if (EndOffset < Offset) { 265 HighReg = Reg; EndOffset = RegSpillOffsets[Reg]; 266 } 267 } 268 } 269 270 // Save information for epilogue inserter. 271 MFI->setCalleeSavedFrameSize(CalleeFrameSize); 272 MFI->setLowReg(LowReg); MFI->setHighReg(HighReg); 273 274 // Save GPRs 275 if (StartOffset) { 276 // Build a store instruction. Use STORE MULTIPLE instruction if there are many 277 // registers to store, otherwise - just STORE. 278 MachineInstrBuilder MIB = 279 BuildMI(MBB, MI, DL, get((LowReg == HighReg ? 280 SystemZ::MOV64mr : SystemZ::MOV64mrm))); 281 282 // Add store operands. 283 MIB.addReg(SystemZ::R15D).addImm(StartOffset); 284 if (LowReg == HighReg) 285 MIB.addReg(0); 286 MIB.addReg(LowReg, RegState::Kill); 287 if (LowReg != HighReg) 288 MIB.addReg(HighReg, RegState::Kill); 289 290 // Do a second scan adding regs as being killed by instruction 291 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 292 unsigned Reg = CSI[i].getReg(); 293 // Add the callee-saved register as live-in. It's killed at the spill. 294 MBB.addLiveIn(Reg); 295 if (Reg != LowReg && Reg != HighReg) 296 MIB.addReg(Reg, RegState::ImplicitKill); 297 } 298 } 299 300 // Save FPRs 301 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 302 unsigned Reg = CSI[i].getReg(); 303 if (SystemZ::FP64RegClass.contains(Reg)) { 304 MBB.addLiveIn(Reg); 305 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), 306 &SystemZ::FP64RegClass, &RI); 307 } 308 } 309 310 return true; 311 } 312 313 bool 314 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 315 MachineBasicBlock::iterator MI, 316 const std::vector<CalleeSavedInfo> &CSI, 317 const TargetRegisterInfo *TRI) const { 318 if (CSI.empty()) 319 return false; 320 321 DebugLoc DL; 322 if (MI != MBB.end()) DL = MI->getDebugLoc(); 323 324 MachineFunction &MF = *MBB.getParent(); 325 const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo(); 326 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); 327 328 // Restore FP registers 329 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 330 unsigned Reg = CSI[i].getReg(); 331 if (SystemZ::FP64RegClass.contains(Reg)) 332 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 333 &SystemZ::FP64RegClass, &RI); 334 } 335 336 // Restore GP registers 337 unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg(); 338 unsigned StartOffset = RegSpillOffsets[LowReg]; 339 340 if (StartOffset) { 341 // Build a load instruction. Use LOAD MULTIPLE instruction if there are many 342 // registers to load, otherwise - just LOAD. 343 MachineInstrBuilder MIB = 344 BuildMI(MBB, MI, DL, get((LowReg == HighReg ? 345 SystemZ::MOV64rm : SystemZ::MOV64rmm))); 346 // Add store operands. 347 MIB.addReg(LowReg, RegState::Define); 348 if (LowReg != HighReg) 349 MIB.addReg(HighReg, RegState::Define); 350 351 MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D)); 352 MIB.addImm(StartOffset); 353 if (LowReg == HighReg) 354 MIB.addReg(0); 355 356 // Do a second scan adding regs as being defined by instruction 357 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 358 unsigned Reg = CSI[i].getReg(); 359 if (Reg != LowReg && Reg != HighReg) 360 MIB.addReg(Reg, RegState::ImplicitDefine); 361 } 362 } 363 364 return true; 365 } 366 367 bool SystemZInstrInfo:: 368 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 369 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 370 371 SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm()); 372 Cond[0].setImm(getOppositeCondition(CC)); 373 return false; 374 } 375 376 bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 377 const TargetInstrDesc &TID = MI->getDesc(); 378 if (!TID.isTerminator()) return false; 379 380 // Conditional branch is a special case. 381 if (TID.isBranch() && !TID.isBarrier()) 382 return true; 383 if (!TID.isPredicable()) 384 return true; 385 return !isPredicated(MI); 386 } 387 388 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 389 MachineBasicBlock *&TBB, 390 MachineBasicBlock *&FBB, 391 SmallVectorImpl<MachineOperand> &Cond, 392 bool AllowModify) const { 393 // Start from the bottom of the block and work up, examining the 394 // terminator instructions. 395 MachineBasicBlock::iterator I = MBB.end(); 396 while (I != MBB.begin()) { 397 --I; 398 if (I->isDebugValue()) 399 continue; 400 // Working from the bottom, when we see a non-terminator 401 // instruction, we're done. 402 if (!isUnpredicatedTerminator(I)) 403 break; 404 405 // A terminator that isn't a branch can't easily be handled 406 // by this analysis. 407 if (!I->getDesc().isBranch()) 408 return true; 409 410 // Handle unconditional branches. 411 if (I->getOpcode() == SystemZ::JMP) { 412 if (!AllowModify) { 413 TBB = I->getOperand(0).getMBB(); 414 continue; 415 } 416 417 // If the block has any instructions after a JMP, delete them. 418 while (llvm::next(I) != MBB.end()) 419 llvm::next(I)->eraseFromParent(); 420 Cond.clear(); 421 FBB = 0; 422 423 // Delete the JMP if it's equivalent to a fall-through. 424 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 425 TBB = 0; 426 I->eraseFromParent(); 427 I = MBB.end(); 428 continue; 429 } 430 431 // TBB is used to indicate the unconditinal destination. 432 TBB = I->getOperand(0).getMBB(); 433 continue; 434 } 435 436 // Handle conditional branches. 437 SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); 438 if (BranchCode == SystemZCC::INVALID) 439 return true; // Can't handle indirect branch. 440 441 // Working from the bottom, handle the first conditional branch. 442 if (Cond.empty()) { 443 FBB = TBB; 444 TBB = I->getOperand(0).getMBB(); 445 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 446 continue; 447 } 448 449 // Handle subsequent conditional branches. Only handle the case where all 450 // conditional branches branch to the same destination. 451 assert(Cond.size() == 1); 452 assert(TBB); 453 454 // Only handle the case where all conditional branches branch to 455 // the same destination. 456 if (TBB != I->getOperand(0).getMBB()) 457 return true; 458 459 SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm(); 460 // If the conditions are the same, we can leave them alone. 461 if (OldBranchCode == BranchCode) 462 continue; 463 464 return true; 465 } 466 467 return false; 468 } 469 470 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 471 MachineBasicBlock::iterator I = MBB.end(); 472 unsigned Count = 0; 473 474 while (I != MBB.begin()) { 475 --I; 476 if (I->isDebugValue()) 477 continue; 478 if (I->getOpcode() != SystemZ::JMP && 479 getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID) 480 break; 481 // Remove the branch. 482 I->eraseFromParent(); 483 I = MBB.end(); 484 ++Count; 485 } 486 487 return Count; 488 } 489 490 unsigned 491 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 492 MachineBasicBlock *FBB, 493 const SmallVectorImpl<MachineOperand> &Cond, 494 DebugLoc DL) const { 495 // Shouldn't be a fall through. 496 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 497 assert((Cond.size() == 1 || Cond.size() == 0) && 498 "SystemZ branch conditions have one component!"); 499 500 if (Cond.empty()) { 501 // Unconditional branch? 502 assert(!FBB && "Unconditional branch with multiple successors!"); 503 BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(TBB); 504 return 1; 505 } 506 507 // Conditional branch. 508 unsigned Count = 0; 509 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm(); 510 BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB); 511 ++Count; 512 513 if (FBB) { 514 // Two-way Conditional branch. Insert the second branch. 515 BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(FBB); 516 ++Count; 517 } 518 return Count; 519 } 520 521 const TargetInstrDesc& 522 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const { 523 switch (CC) { 524 default: 525 llvm_unreachable("Unknown condition code!"); 526 case SystemZCC::O: return get(SystemZ::JO); 527 case SystemZCC::H: return get(SystemZ::JH); 528 case SystemZCC::NLE: return get(SystemZ::JNLE); 529 case SystemZCC::L: return get(SystemZ::JL); 530 case SystemZCC::NHE: return get(SystemZ::JNHE); 531 case SystemZCC::LH: return get(SystemZ::JLH); 532 case SystemZCC::NE: return get(SystemZ::JNE); 533 case SystemZCC::E: return get(SystemZ::JE); 534 case SystemZCC::NLH: return get(SystemZ::JNLH); 535 case SystemZCC::HE: return get(SystemZ::JHE); 536 case SystemZCC::NL: return get(SystemZ::JNL); 537 case SystemZCC::LE: return get(SystemZ::JLE); 538 case SystemZCC::NH: return get(SystemZ::JNH); 539 case SystemZCC::NO: return get(SystemZ::JNO); 540 } 541 } 542 543 SystemZCC::CondCodes 544 SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const { 545 switch (Opc) { 546 default: return SystemZCC::INVALID; 547 case SystemZ::JO: return SystemZCC::O; 548 case SystemZ::JH: return SystemZCC::H; 549 case SystemZ::JNLE: return SystemZCC::NLE; 550 case SystemZ::JL: return SystemZCC::L; 551 case SystemZ::JNHE: return SystemZCC::NHE; 552 case SystemZ::JLH: return SystemZCC::LH; 553 case SystemZ::JNE: return SystemZCC::NE; 554 case SystemZ::JE: return SystemZCC::E; 555 case SystemZ::JNLH: return SystemZCC::NLH; 556 case SystemZ::JHE: return SystemZCC::HE; 557 case SystemZ::JNL: return SystemZCC::NL; 558 case SystemZ::JLE: return SystemZCC::LE; 559 case SystemZ::JNH: return SystemZCC::NH; 560 case SystemZ::JNO: return SystemZCC::NO; 561 } 562 } 563 564 SystemZCC::CondCodes 565 SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const { 566 switch (CC) { 567 default: 568 llvm_unreachable("Invalid condition!"); 569 case SystemZCC::O: return SystemZCC::NO; 570 case SystemZCC::H: return SystemZCC::NH; 571 case SystemZCC::NLE: return SystemZCC::LE; 572 case SystemZCC::L: return SystemZCC::NL; 573 case SystemZCC::NHE: return SystemZCC::HE; 574 case SystemZCC::LH: return SystemZCC::NLH; 575 case SystemZCC::NE: return SystemZCC::E; 576 case SystemZCC::E: return SystemZCC::NE; 577 case SystemZCC::NLH: return SystemZCC::LH; 578 case SystemZCC::HE: return SystemZCC::NHE; 579 case SystemZCC::NL: return SystemZCC::L; 580 case SystemZCC::LE: return SystemZCC::NLE; 581 case SystemZCC::NH: return SystemZCC::H; 582 case SystemZCC::NO: return SystemZCC::O; 583 } 584 } 585 586 const TargetInstrDesc& 587 SystemZInstrInfo::getLongDispOpc(unsigned Opc) const { 588 switch (Opc) { 589 default: 590 llvm_unreachable("Don't have long disp version of this instruction"); 591 case SystemZ::MOV32mr: return get(SystemZ::MOV32mry); 592 case SystemZ::MOV32rm: return get(SystemZ::MOV32rmy); 593 case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y); 594 case SystemZ::MOV32m8r: return get(SystemZ::MOV32m8ry); 595 case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry); 596 case SystemZ::MOV64m8r: return get(SystemZ::MOV64m8ry); 597 case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry); 598 case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry); 599 case SystemZ::MOV8mi: return get(SystemZ::MOV8miy); 600 case SystemZ::MUL32rm: return get(SystemZ::MUL32rmy); 601 case SystemZ::CMP32rm: return get(SystemZ::CMP32rmy); 602 case SystemZ::UCMP32rm: return get(SystemZ::UCMP32rmy); 603 case SystemZ::FMOV32mr: return get(SystemZ::FMOV32mry); 604 case SystemZ::FMOV64mr: return get(SystemZ::FMOV64mry); 605 case SystemZ::FMOV32rm: return get(SystemZ::FMOV32rmy); 606 case SystemZ::FMOV64rm: return get(SystemZ::FMOV64rmy); 607 case SystemZ::MOV64Pmr: return get(SystemZ::MOV64Pmry); 608 case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy); 609 } 610 } 611