1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Select instructions 12//===----------------------------------------------------------------------===// 13 14// C's ?: operator for floating-point operands. 15def SelectF32 : SelectWrapper<f32, FP32>; 16def SelectF64 : SelectWrapper<f64, FP64>; 17let Predicates = [FeatureNoVectorEnhancements1] in 18 def SelectF128 : SelectWrapper<f128, FP128>; 19let Predicates = [FeatureVectorEnhancements1] in 20 def SelectVR128 : SelectWrapper<f128, VR128>; 21 22defm CondStoreF32 : CondStores<FP32, nonvolatile_store, 23 nonvolatile_load, bdxaddr20only>; 24defm CondStoreF64 : CondStores<FP64, nonvolatile_store, 25 nonvolatile_load, bdxaddr20only>; 26 27//===----------------------------------------------------------------------===// 28// Move instructions 29//===----------------------------------------------------------------------===// 30 31// Load zero. 32let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in { 33 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>; 34 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>; 35 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>; 36} 37 38// Moves between two floating-point registers. 39let hasSideEffects = 0 in { 40 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>; 41 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>; 42 def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>; 43 44 // For z13 we prefer LDR over LER to avoid partial register dependencies. 45 let isCodeGenOnly = 1 in 46 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>; 47} 48 49// Moves between two floating-point registers that also set the condition 50// codes. 51let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 52 defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>; 53 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>; 54 defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>; 55} 56// Note that LTxBRCompare is not available if we have vector support, 57// since load-and-test instructions will partially clobber the target 58// (vector) register. 59let Predicates = [FeatureNoVector] in { 60 defm : CompareZeroFP<LTEBRCompare, FP32>; 61 defm : CompareZeroFP<LTDBRCompare, FP64>; 62 defm : CompareZeroFP<LTXBRCompare, FP128>; 63} 64 65// Use a normal load-and-test for compare against zero in case of 66// vector support (via a pseudo to simplify instruction selection). 67let Defs = [CC], usesCustomInserter = 1 in { 68 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>; 69 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>; 70 def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>; 71} 72let Predicates = [FeatureVector] in { 73 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>; 74 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>; 75} 76let Predicates = [FeatureVector, FeatureNoVectorEnhancements1] in 77 defm : CompareZeroFP<LTXBRCompare_VecPseudo, FP128>; 78 79// Moves between 64-bit integer and floating-point registers. 80def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>; 81def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>; 82 83// fcopysign with an FP32 result. 84let isCodeGenOnly = 1 in { 85 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>; 86 def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>; 87} 88 89// The sign of an FP128 is in the high register. 90let Predicates = [FeatureNoVectorEnhancements1] in 91 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 FP128:$src2)))), 92 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 93let Predicates = [FeatureVectorEnhancements1] in 94 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))), 95 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_r64))>; 96 97// fcopysign with an FP64 result. 98let isCodeGenOnly = 1 in 99 def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>; 100def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>; 101 102// The sign of an FP128 is in the high register. 103let Predicates = [FeatureNoVectorEnhancements1] in 104 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 FP128:$src2)))), 105 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 106let Predicates = [FeatureVectorEnhancements1] in 107 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))), 108 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_r64))>; 109 110// fcopysign with an FP128 result. Use "upper" as the high half and leave 111// the low half as-is. 112class CopySign128<RegisterOperand cls, dag upper> 113 : Pat<(fcopysign FP128:$src1, cls:$src2), 114 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 115 116let Predicates = [FeatureNoVectorEnhancements1] in { 117 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 118 FP32:$src2)>; 119 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 120 FP64:$src2)>; 121 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 122 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 123} 124 125defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>; 126defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>; 127defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>; 128 129//===----------------------------------------------------------------------===// 130// Load instructions 131//===----------------------------------------------------------------------===// 132 133let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 134 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 135 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 136 137 // For z13 we prefer LDE over LE to avoid partial register dependencies. 138 let isCodeGenOnly = 1 in 139 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>; 140 141 // These instructions are split after register allocation, so we don't 142 // want a custom inserter. 143 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 144 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 145 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 146 } 147} 148 149//===----------------------------------------------------------------------===// 150// Store instructions 151//===----------------------------------------------------------------------===// 152 153let SimpleBDXStore = 1 in { 154 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 155 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 156 157 // These instructions are split after register allocation, so we don't 158 // want a custom inserter. 159 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 160 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 161 [(store FP128:$src, bdxaddr20only128:$dst)]>; 162 } 163} 164 165//===----------------------------------------------------------------------===// 166// Conversion instructions 167//===----------------------------------------------------------------------===// 168 169// Convert floating-point values to narrower representations, rounding 170// according to the current mode. The destination of LEXBR and LDXBR 171// is a 128-bit value, but only the first register of the pair is used. 172def LEDBR : UnaryRRE<"ledbr", 0xB344, fpround, FP32, FP64>; 173def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>; 174def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>; 175 176def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32, FP64>, 177 Requires<[FeatureFPExtension]>; 178def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>, 179 Requires<[FeatureFPExtension]>; 180def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>, 181 Requires<[FeatureFPExtension]>; 182 183let Predicates = [FeatureNoVectorEnhancements1] in { 184 def : Pat<(f32 (fpround FP128:$src)), 185 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>; 186 def : Pat<(f64 (fpround FP128:$src)), 187 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 188} 189 190// Extend register floating-point values to wider representations. 191def LDEBR : UnaryRRE<"ldebr", 0xB304, fpextend, FP64, FP32>; 192def LXEBR : UnaryRRE<"lxebr", 0xB306, null_frag, FP128, FP32>; 193def LXDBR : UnaryRRE<"lxdbr", 0xB305, null_frag, FP128, FP64>; 194let Predicates = [FeatureNoVectorEnhancements1] in { 195 def : Pat<(f128 (fpextend (f32 FP32:$src))), (LXEBR FP32:$src)>; 196 def : Pat<(f128 (fpextend (f64 FP64:$src))), (LXDBR FP64:$src)>; 197} 198 199// Extend memory floating-point values to wider representations. 200def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 201def LXEB : UnaryRXE<"lxeb", 0xED06, null_frag, FP128, 4>; 202def LXDB : UnaryRXE<"lxdb", 0xED05, null_frag, FP128, 8>; 203let Predicates = [FeatureNoVectorEnhancements1] in { 204 def : Pat<(f128 (extloadf32 bdxaddr12only:$src)), 205 (LXEB bdxaddr12only:$src)>; 206 def : Pat<(f128 (extloadf64 bdxaddr12only:$src)), 207 (LXDB bdxaddr12only:$src)>; 208} 209 210// Convert a signed integer register value to a floating-point one. 211def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>; 212def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>; 213def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>; 214 215def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>; 216def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>; 217def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>; 218 219// The FP extension feature provides versions of the above that allow 220// specifying rounding mode and inexact-exception suppression flags. 221let Predicates = [FeatureFPExtension] in { 222 def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32, GR32>; 223 def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64, GR32>; 224 def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>; 225 226 def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32, GR64>; 227 def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64, GR64>; 228 def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>; 229} 230 231// Convert am unsigned integer register value to a floating-point one. 232let Predicates = [FeatureFPExtension] in { 233 def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>; 234 def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64, GR32>; 235 def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>; 236 237 def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32, GR64>; 238 def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64, GR64>; 239 def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>; 240 241 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; 242 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; 243 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; 244 245 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; 246 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; 247 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; 248} 249 250// Convert a floating-point register value to a signed integer value, 251// with the second operand (modifier M3) specifying the rounding mode. 252let Defs = [CC] in { 253 def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>; 254 def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>; 255 def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>; 256 257 def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>; 258 def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>; 259 def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>; 260} 261 262// fp_to_sint always rounds towards zero, which is modifier value 5. 263def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 264def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 265def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 266 267def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 268def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 269def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 270 271// The FP extension feature provides versions of the above that allow 272// also specifying the inexact-exception suppression flag. 273let Predicates = [FeatureFPExtension], Defs = [CC] in { 274 def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>; 275 def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>; 276 def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>; 277 278 def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>; 279 def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>; 280 def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>; 281} 282 283// Convert a floating-point register value to an unsigned integer value. 284let Predicates = [FeatureFPExtension] in { 285 let Defs = [CC] in { 286 def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>; 287 def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>; 288 def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>; 289 290 def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>; 291 def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>; 292 def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>; 293 } 294 295 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; 296 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; 297 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; 298 299 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; 300 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; 301 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; 302} 303 304 305//===----------------------------------------------------------------------===// 306// Unary arithmetic 307//===----------------------------------------------------------------------===// 308 309// We prefer generic instructions during isel, because they do not 310// clobber CC and therefore give the scheduler more freedom. In cases 311// the CC is actually useful, the SystemZElimCompare pass will try to 312// convert generic instructions into opcodes that also set CC. Note 313// that lcdf / lpdf / lndf only affect the sign bit, and can therefore 314// be used with fp32 as well. This could be done for fp128, in which 315// case the operands would have to be tied. 316 317// Negation (Load Complement). 318let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 319 def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32, FP32>; 320 def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64, FP64>; 321 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>; 322} 323// Generic form, which does not set CC. 324def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>; 325let isCodeGenOnly = 1 in 326 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>; 327 328// Absolute value (Load Positive). 329let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 330 def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32, FP32>; 331 def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64, FP64>; 332 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>; 333} 334// Generic form, which does not set CC. 335def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>; 336let isCodeGenOnly = 1 in 337 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>; 338 339// Negative absolute value (Load Negative). 340let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 341 def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32, FP32>; 342 def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64, FP64>; 343 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>; 344} 345// Generic form, which does not set CC. 346def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>; 347let isCodeGenOnly = 1 in 348 def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32, FP32>; 349 350// Square root. 351def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>; 352def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>; 353def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>; 354 355def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 356def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 357 358// Round to an integer, with the second operand (modifier M3) specifying 359// the rounding mode. These forms always check for inexact conditions. 360def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>; 361def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>; 362def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>; 363 364// frint rounds according to the current mode (modifier 0) and detects 365// inexact conditions. 366def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 367def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 368def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 369 370let Predicates = [FeatureFPExtension] in { 371 // Extended forms of the FIxBR instructions. M4 can be set to 4 372 // to suppress detection of inexact conditions. 373 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>; 374 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>; 375 def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>; 376 377 // fnearbyint is like frint but does not detect inexact conditions. 378 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 379 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 380 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 381 382 // floor is no longer allowed to raise an inexact condition, 383 // so restrict it to the cases where the condition can be suppressed. 384 // Mode 7 is round towards -inf. 385 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 386 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 387 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 388 389 // Same idea for ceil, where mode 6 is round towards +inf. 390 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 391 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 392 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 393 394 // Same idea for trunc, where mode 5 is round towards zero. 395 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 396 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 397 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 398 399 // Same idea for round, where mode 1 is round towards nearest with 400 // ties away from zero. 401 def : Pat<(fround FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 402 def : Pat<(fround FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 403 def : Pat<(fround FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 404} 405 406//===----------------------------------------------------------------------===// 407// Binary arithmetic 408//===----------------------------------------------------------------------===// 409 410// Addition. 411let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 412 let isCommutable = 1 in { 413 def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>; 414 def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>; 415 def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>; 416 } 417 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 418 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 419} 420 421// Subtraction. 422let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 423 def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>; 424 def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>; 425 def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>; 426 427 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 428 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 429} 430 431// Multiplication. 432let isCommutable = 1 in { 433 def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>; 434 def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>; 435 def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>; 436} 437def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 438def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 439 440// f64 multiplication of two FP32 registers. 441def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>; 442def : Pat<(fmul (f64 (fpextend FP32:$src1)), (f64 (fpextend FP32:$src2))), 443 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 444 FP32:$src1, subreg_r32), FP32:$src2)>; 445 446// f64 multiplication of an FP32 register and an f32 memory. 447def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 448def : Pat<(fmul (f64 (fpextend FP32:$src1)), 449 (f64 (extloadf32 bdxaddr12only:$addr))), 450 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32), 451 bdxaddr12only:$addr)>; 452 453// f128 multiplication of two FP64 registers. 454def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>; 455let Predicates = [FeatureNoVectorEnhancements1] in 456 def : Pat<(fmul (f128 (fpextend FP64:$src1)), (f128 (fpextend FP64:$src2))), 457 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 458 FP64:$src1, subreg_h64), FP64:$src2)>; 459 460// f128 multiplication of an FP64 register and an f64 memory. 461def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 462let Predicates = [FeatureNoVectorEnhancements1] in 463 def : Pat<(fmul (f128 (fpextend FP64:$src1)), 464 (f128 (extloadf64 bdxaddr12only:$addr))), 465 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 466 bdxaddr12only:$addr)>; 467 468// Fused multiply-add. 469def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32, FP32>; 470def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64, FP64>; 471 472def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, FP32, load, 4>; 473def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, FP64, load, 8>; 474 475// Fused multiply-subtract. 476def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32, FP32>; 477def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64, FP64>; 478 479def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, FP32, load, 4>; 480def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, FP64, load, 8>; 481 482// Division. 483def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>; 484def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>; 485def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>; 486 487def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 488def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 489 490// Divide to integer. 491let Defs = [CC] in { 492 def DIEBR : TernaryRRFb<"diebr", 0xB353, FP32, FP32, FP32>; 493 def DIDBR : TernaryRRFb<"didbr", 0xB35B, FP64, FP64, FP64>; 494} 495 496//===----------------------------------------------------------------------===// 497// Comparisons 498//===----------------------------------------------------------------------===// 499 500let Defs = [CC], CCValues = 0xF in { 501 def CEBR : CompareRRE<"cebr", 0xB309, z_fcmp, FP32, FP32>; 502 def CDBR : CompareRRE<"cdbr", 0xB319, z_fcmp, FP64, FP64>; 503 def CXBR : CompareRRE<"cxbr", 0xB349, z_fcmp, FP128, FP128>; 504 505 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>; 506 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>; 507 508 def KEBR : CompareRRE<"kebr", 0xB308, null_frag, FP32, FP32>; 509 def KDBR : CompareRRE<"kdbr", 0xB318, null_frag, FP64, FP64>; 510 def KXBR : CompareRRE<"kxbr", 0xB348, null_frag, FP128, FP128>; 511 512 def KEB : CompareRXE<"keb", 0xED08, null_frag, FP32, load, 4>; 513 def KDB : CompareRXE<"kdb", 0xED18, null_frag, FP64, load, 8>; 514} 515 516// Test Data Class. 517let Defs = [CC], CCValues = 0xC in { 518 def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>; 519 def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>; 520 def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>; 521} 522 523//===----------------------------------------------------------------------===// 524// Floating-point control register instructions 525//===----------------------------------------------------------------------===// 526 527let hasSideEffects = 1 in { 528 def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>; 529 def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>; 530 531 def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>; 532 def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>; 533 534 def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>; 535 def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>; 536 537 def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>, 538 Requires<[FeatureFPExtension]>; 539 def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>; 540 def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>; 541} 542 543//===----------------------------------------------------------------------===// 544// Peepholes 545//===----------------------------------------------------------------------===// 546 547def : Pat<(f32 fpimmneg0), (LCDFR_32 (LZER))>; 548def : Pat<(f64 fpimmneg0), (LCDFR (LZDR))>; 549def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 550